Fault protection device and photovoltaic power generation system

Abstract

The present application relates to a fault protection device and a photovoltaic power generation system. The photovoltaic power generation system comprises: a capacitor bridge arm, the capacitor bridge arm comprises a positive output port, a negative output port and a reference output port between the positive output port and the negative output port; an inverter bridge arm, the inverter bridge arm comprises a positive input port, a negative input port and a reference input port between the positive input port and the negative input port, the positive input port is connected to the positive output port, and the negative input port is connected to the negative output port; and a fault protection device, wherein the reference input port is connected to the reference output port through the fault protection device, and the fault protection device is turned off according to the magnitude or change of the voltage or the magnitude or change of the current between the positive input port or the negative input port and the reference input port.

Description

Technical Field

[0001] The present application relates to the field of power electronics, and in particular to a fault protection device and a photovoltaic power generation system. Background Art

[0002] Solar power generation, wind power generation, frequency converters, uninterruptible power systems (UPS), motor drives, and new energy vehicles all require power converters, also called inverters, for converting DC to AC. Among them, multi-level circuits that can output three or more voltage levels have been widely used and received attention. Compared with two-level circuits, multi-level circuits that can output three or more voltage levels have the advantages of more output levels, less voltage stress, less ripple current, and better harmonic characteristics, which are conducive to achieving output voltage pulses close to industrial frequency AC voltage, thereby reducing the volume and weight of the filter. Multi-level circuits usually use semiconductor switching devices to achieve the conversion of DC to AC. Taking a typical three-phase bridge inverter circuit as an example, the semiconductor switch tube of each bridge arm is turned on for half a cycle in a sinusoidal cycle, and the bridge arms of the three phases are alternately turned on with a conduction angle difference of 120 degrees, so that the output voltage waveform obtained is approximately a sine wave.

[0003] In the prior art, a three-level circuit including two DC voltage sources is widely used. However, the intermediate nodes of the two DC voltage sources of the three-level circuit are directly electrically connected to the intermediate nodes of the semiconductor switch device. Therefore, when the inverter bridge arm of the semiconductor switch device fails, it is easy to cause overvoltage damage to the half-bus capacitor, and it may further spread and damage the circuit and equipment, greatly reducing the reliability of the circuit.

[0004] Therefore, it is necessary to provide a technical solution for the multi-level circuit so as to protect the capacitor bridge arm when a short circuit fault occurs in the inverter bridge arm, thereby avoiding circuit failure and damage. Summary of the invention

[0005] The purpose of the present application is to provide a fault protection device and a photovoltaic power generation system, so as to protect the capacitor bridge arm when a short circuit fault occurs in the inverter bridge arm, thereby avoiding circuit failure and damage.

[0006] In the first aspect, the embodiment of the present application provides a photovoltaic power generation system. The photovoltaic power generation system includes: a capacitor bridge arm, wherein the capacitor bridge arm includes a positive output port, a negative output port, and a reference output port between the positive output port and the negative output port; an inverter bridge arm, wherein the inverter bridge arm includes a positive input port, a negative input port, and a reference input port between the positive input port and the negative input port, the positive input port is connected to the positive output port, and the negative input port is connected to the negative output port; and a fault protection device, wherein the reference input port is connected to the reference output port through the fault protection device, and the fault protection device is turned off according to the magnitude or change of the voltage or the magnitude or change of the current between the positive input port or the negative input port and the reference input port.

[0007] The technical solution described in the first aspect can adjust the connection relationship between the reference output port and the reference input port by closing and opening the fault protection device, thereby avoiding overvoltage damage to the half-bus capacitor and improving the reliability of the circuit.

[0008] According to the first aspect, in a possible implementation, the fault protection device is shut down according to the size or change of the voltage between the positive input port or the negative input port and the reference input port, including: when the voltage between the negative input port and the reference input port is lower than a first threshold, the fault protection device is disconnected; or when the voltage between the positive input port and the reference input port is lower than a second threshold, the fault protection device is disconnected; or when the voltage drop rate between the negative input port and the reference input port is higher than a third threshold, the fault protection device is disconnected; or when the voltage drop rate between the positive input port and the reference input port is higher than a fourth threshold, the fault protection device is disconnected.

[0009] In this way, the fault protection device is controlled to be disconnected by monitoring the voltage change, thereby adjusting the connection relationship between the reference output port and the reference input port, thereby avoiding overvoltage damage to the half-bus capacitor and improving the reliability of the circuit.

[0010] According to the first aspect, in a possible implementation manner, the fault protection device is further shut down according to a current flowing through the fault protection device.

[0011] In this way, the fault protection device is disconnected by monitoring the current flowing through the fault protection device, thereby adjusting the connection relationship between the reference output port and the reference input port, thereby avoiding overvoltage damage to the half-bus capacitor and improving circuit reliability.

[0012] According to the first aspect, in a possible implementation, the inverter bridge arm also includes at least one semiconductor switching device connected between the positive input port or the negative input port and the reference input port, and the fault protection device is also shut down according to the current flowing through the at least one semiconductor switching device or the voltage applied between the first transmission electrode and the second transmission electrode of the at least one semiconductor switching device.

[0013] In this way, the fault protection device is controlled to disconnect by monitoring the voltage and current of the semiconductor switch device, thereby adjusting the connection relationship between the reference output port and the reference input port, thereby avoiding overvoltage damage to the half-bus capacitor and improving the reliability of the circuit.

[0014] According to the first aspect, in a possible implementation, the fault protection device includes a main circuit breaker, wherein the main circuit breaker includes a first switching transistor and a second switching transistor, the first switching transistor and the second switching transistor are connected in series between the reference output port and the reference input port, and the fault protection device is closed and opened by controlling the conduction and disconnection of the first switching transistor and the second switching transistor.

[0015] In this way, the closing and opening of the circuit breaker switch is controlled by controlling the on and off of the first switch transistor and the second switch transistor.

[0016] According to the first aspect, in a possible implementation manner, the first switch transistor and the second switch transistor are MOSFET, IGBT, GTR, GTO, HEMT, MODFET, 2-DEGFET or SDHT.

[0017] In this way, the use of various types of switching transistors is achieved.

[0018] According to the first aspect, in a possible implementation manner, the fault protection device further includes: a high impedance device, wherein the high impedance device and the main circuit breaker are connected in parallel between the reference output port and the reference input port.

[0019] In this way, the charging and discharging speed of the capacitor bridge arm is slowed down by the high impedance device, which is conducive to the response of other protection mechanisms and improves the stability of the system.

[0020] According to the first aspect, in a possible implementation manner, the high impedance device is a thermistor.

[0021] In this way, the charging and discharging speed of the capacitor bridge arm is slowed down by the thermistor, which is conducive to the response of other protection mechanisms and improves the stability of the system.

[0022] According to the first aspect, in a possible implementation manner, the fault protection device further includes: a varistor, wherein the varistor and the main circuit breaker are connected in parallel between the reference output port and the reference input port.

[0023] In this way, the residual energy of the fault protection device during the circuit breaking process is absorbed by the varistor, which is helpful to prevent overvoltage damage and improve the reliability of the circuit.

[0024] According to the first aspect, in a possible implementation, the fault protection device also includes: a high-speed mechanical switch, wherein the high-speed mechanical switch, the varistor and the main circuit breaker are connected in parallel between the reference output port and the reference input port, the high-speed mechanical switch is closed after the first switching transistor and the second switching transistor of the main circuit breaker are turned on, and the high-speed mechanical switch is opened before the first switching transistor and the second switching transistor of the main circuit breaker are turned off.

[0025] In this way, the main circuit breaker is bypassed by the closed high-speed mechanical switch after the switching transistor of the main circuit breaker is turned on, so that the loss can be reduced by the closed high-speed mechanical switch.

[0026] According to the first aspect, in a possible implementation, the fault protection device further includes: a high-speed mechanical switch, and an auxiliary circuit breaker, wherein the auxiliary circuit breaker includes a third switching transistor and a fourth switching transistor, the third switching transistor and the fourth switching transistor are connected in series with the high-speed mechanical switch between the reference output port and the reference input port after being connected in a pairwise manner, the high-speed mechanical switch and the auxiliary circuit breaker are connected in parallel with the varistor and the main circuit breaker between the reference output port and the reference input port after being connected in series, the third switching transistor and the fourth switching transistor of the auxiliary circuit breaker and the high-speed mechanical switch are closed after the first switching transistor and the second switching transistor of the main circuit breaker are turned on, the high-speed mechanical switch is disconnected before the first switching transistor and the second switching transistor of the main circuit breaker are turned off, and the third switching transistor and the fourth switching transistor of the auxiliary circuit breaker are turned off before the high-speed mechanical switch is disconnected.

[0027] In this way, after the switch transistor of the main circuit breaker is turned on, the high-speed mechanical switch and the auxiliary circuit breaker are closed to form a bypass branch to bypass the main circuit breaker, thereby reducing the loss of the circuit breaker SP.

[0028] According to the first aspect, in a possible implementation manner, the third switch transistor and the fourth switch transistor are MOSFET, IGBT, GTR, GTO, HEMT, MODFET, 2-DEGFET or SDHT.

[0029] In this way, the use of various types of switching transistors is achieved.

[0030] According to the first aspect, in a possible implementation, the inverter bridge arm includes an ANPC three-level bridge arm, and the ANPC three-level bridge arm includes a plurality of semiconductor switching devices connected in series between the positive input port and the reference input port and connected in series between the negative input port and the reference input port, and the fault protection device is also shut down according to the current flowing through the plurality of semiconductor switching devices or the voltage applied between the first transmission electrode and the second transmission electrode of the plurality of semiconductor switching devices.

[0031] In this way, by monitoring the voltage and current conditions of multiple semiconductor switching devices, it is possible to determine whether a short-circuit fault occurs in the ANPC three-level bridge arm, and timely control the fault protection device to disconnect and adjust the connection relationship between the reference output port and the reference input port, thereby avoiding overvoltage damage to the half-bus capacitor and improving the reliability of the circuit.

[0032] According to the first aspect, in a possible implementation, the inverter bridge arm includes an NPC three-level bridge arm, and the NPC three-level bridge arm includes a plurality of semiconductor switching devices connected in series between the positive input port and the reference input port and connected in series between the negative input port and the reference input port, and the fault protection device is also shut down according to the current flowing through the plurality of semiconductor switching devices or the voltage applied between the first transmission electrode and the second transmission electrode of the plurality of semiconductor switching devices.

[0033] In this way, by monitoring the voltage and current conditions of multiple semiconductor switching devices, it is possible to determine whether a short-circuit fault has occurred in the NPC three-level bridge arm, and timely control the fault protection device to disconnect and adjust the connection relationship between the reference output port and the reference input port, thereby avoiding overvoltage damage to the half-bus capacitor and improving the reliability of the circuit.

[0034] According to the first aspect, in a possible implementation, the inverter bridge arm includes a T-type three-level bridge arm, and the T-type three-level bridge arm includes a plurality of semiconductor switching devices connected in series between the positive input port and the negative input port, and the fault protection device is also shut down according to the current flowing through the plurality of semiconductor switching devices or the voltage applied between the first transmission electrode and the second transmission electrode of the plurality of semiconductor switching devices.

[0035] In this way, by monitoring the voltage and current conditions of multiple semiconductor switching devices, it is possible to determine whether a short-circuit fault occurs in the T-type three-level bridge arm, and timely control the fault protection device to disconnect and adjust the connection relationship between the reference output port and the reference input port, thereby avoiding overvoltage damage to the half-bus capacitor and improving the reliability of the circuit.

[0036] According to the first aspect, in a possible implementation, the inverter bridge arm includes a five-level bridge arm, and the five-level bridge arm includes a plurality of semiconductor switching devices connected in series between the positive input port and the reference input port and connected in series between the negative input port and the reference input port, and the fault protection device is also shut down according to the current flowing through the plurality of semiconductor switching devices or the voltage applied between the first transmission electrode and the second transmission electrode of the plurality of semiconductor switching devices.

[0037] In this way, by monitoring the voltage and current conditions of multiple semiconductor switching devices, it is possible to determine whether a short circuit fault occurs in the five-level bridge arm, and timely control the fault protection device to disconnect and adjust the connection relationship between the reference output port and the reference input port, thereby avoiding overvoltage damage to the half-bus capacitor and improving the reliability of the circuit.

[0038] In a second aspect, an embodiment of the present application provides a control method for a fault protection device, which is applied to a photovoltaic power generation system. The photovoltaic power generation system includes a capacitor bridge arm, an inverter bridge arm, and the fault protection device, wherein the capacitor bridge arm includes a positive output port, a negative output port, and a reference output port between the positive output port and the negative output port, the inverter bridge arm includes a positive input port, a negative input port, and a reference input port between the positive input port and the negative input port, the positive input port is connected to the positive output port, the negative input port is connected to the negative output port, and the reference input port is connected to the reference output port through the fault protection device, and the method includes: controlling the fault protection device to shut down according to the magnitude or change of the voltage between the positive input port or the negative input port and the reference input port or the magnitude or change of the current.

[0039] The technical solution described in the second aspect can adjust the connection relationship between the reference output port and the reference input port by closing and opening the fault protection device, thereby avoiding overvoltage damage to the half-bus capacitor and improving the reliability of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to illustrate the technical solutions in the embodiments of the present application or the background technology, the drawings required for use in the embodiments of the present application or the background technology will be described below.

[0041] Figure 1 A principle block diagram of a multi-level circuit with a fault protection device provided in an embodiment of the present application is shown.

[0042] Figure 2 The embodiment of the present application provides Figure 1 The structure block diagram of the first embodiment of the disconnect switch SP of the fault protection device is shown.

[0043] Figure 3 The embodiment of the present application provides Figure 1 The structural block diagram of the second embodiment of the disconnect switch SP of the fault protection device is shown.

[0044] Figure 4 The embodiment of the present application provides Figure 1 The structural block diagram of the third embodiment of the disconnect switch SP of the fault protection device is shown.

[0045] Figure 5 The embodiment of the present application provides Figure 1 The structural block diagram of the fourth embodiment of the circuit breaker SP of the fault protection device is shown.

[0046] Figure 6 The embodiment of the present application provides Figure 1 The structure block diagram of the fifth embodiment of the circuit breaker SP of the fault protection device is shown.

[0047] Figure 7 A principle block diagram of an ANPC three-level circuit with a fault protection device provided in an embodiment of the present application is shown.

[0048] Figure 8 A principle block diagram of an NPC three-level circuit with a fault protection device provided in an embodiment of the present application is shown.

[0049] Fig. 9 A principle block diagram of a T-type three-level circuit with a fault protection device provided in an embodiment of the present application is shown.

[0050] Fig.10 A principle block diagram of a five-level circuit with a fault protection device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0051] The embodiment of the present application provides a photovoltaic power generation system. The photovoltaic power generation system includes: a capacitor bridge arm, wherein the capacitor bridge arm includes a positive output port, a negative output port and a reference output port between the positive output port and the negative output port; an inverter bridge arm, wherein the inverter bridge arm includes a positive input port, a negative input port and a reference input port between the positive input port and the negative input port, the positive input port is connected to the positive output port, and the negative input port is connected to the negative output port; and a fault protection device, wherein the reference input port is connected to the reference output port through the fault protection device, and the fault protection device is turned off according to the magnitude or change of the voltage or the magnitude or change of the current between the positive input port or the negative input port and the reference input port. In this way, the connection relationship between the reference output port and the reference input port can be adjusted by closing and opening the fault protection device, thereby avoiding overvoltage damage to the half-bus capacitor and improving the reliability of the circuit.

[0052] The embodiments of the present application can be used in the following application scenarios: solar power generation, wind power generation, inverter, UPS, motor drive, new energy vehicles or other application scenarios requiring multi-level inverter circuits.

[0053] The embodiments of the present application can be adjusted and improved according to the specific application environment and are not specifically limited here.

[0054] In order to enable those skilled in the art to better understand the present application, the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0055] See also Figure 1 , Figure 1 FIG. 1 shows a principle block diagram of a multi-level circuit with a fault protection device provided in an embodiment of the present application. Figure 1As shown, the multi-level circuit 100 includes a fault protection device 110, a capacitor bridge arm 120 and an inverter multi-level bridge arm 130. The capacitor bridge arm 120 has three output ports, namely a positive output port P, a negative output port N and a reference output port M. Relatively, the inverter multi-level bridge arm 130 has three input ports, namely a positive input port P', a negative input port N' and a reference input port M'. Among them, the positive output port P is connected to the positive input port P', the negative output port N is connected to the negative input port N', one end of the fault protection device 110 is connected to the reference output port M, and the other end is connected to the reference input port M'. In this way, there is a one-to-one corresponding connection relationship between each output port of the capacitor bridge arm 120 and each input port of the inverter multi-level bridge arm 130, and the reference output port M is indirectly connected to the reference input port M' through the fault protection device 110. It should be understood that the positive electrode and negative electrode mentioned in the embodiments of the present application are only relative concepts. One port is designated as the positive electrode and the other port as the negative electrode for the convenience of description, and should not be understood as restrictive.

[0056] Please continue reading Figure 1 , the fault protection device 110 includes a circuit breaker SP and a controller 111. One end of the circuit breaker SP is connected to the reference output port M, and the other end is connected to the reference input port M'. The controller 111 is communicatively connected to the circuit breaker SP and is configured to control the closing and opening of the circuit breaker SP. When the controller 111 controls the circuit breaker SP to close, the reference output port M is connected to the reference input port M' through the circuit breaker SP; when the controller 111 controls the circuit breaker SP to open, the reference output port M is blocked by the circuit breaker SP and cannot be connected to the reference input port M'. In this way, the connection relationship between the reference output port M and the reference input port M' can be adjusted by controlling the closing and opening of the circuit breaker SP through the controller 111. The fault protection device 110 has the following multiple implementation structures, but it can be understood that the present application is not limited to the implementation methods of the following specific circuit breaker structures. The key to this application is to connect a circuit breaker SP protection device between the reference end of the capacitor bridge arm and the reference end of the inverter bridge arm, and the specific structure of the protection device is not critical. It can refer to various circuit breaker protection implementation methods and structures commonly used in the market, which will not be described here one by one.

[0057] See also Figure 2 , Figure 2 The embodiment of the present application provides Figure 1 The structural block diagram of the first embodiment of the circuit breaker SP of the fault protection device shown in FIG. Figure 2As shown, the circuit breaker SP includes a main circuit breaker 212. The main circuit breaker 212 includes two semiconductor switching devices, taking an insulated gate bipolar transistor (IGBT) as an example, which are Q1 and Q2. Q1 and Q2 are connected in series between the reference output port M and the reference input port M'. That is, the emitter of Q1 and the emitter of Q2 are connected to each other, the collector of Q1 is connected to the reference input port M', and the collector of Q2 is connected to the reference output port M. In another embodiment, the collector of Q1 and the collector of Q2 are connected to each other, the emitter of Q1 is connected to the reference input port M', and the emitter of Q2 is connected to the reference output port M. In these two embodiments, the positions of Q1 and Q2 can also be interchanged. The main circuit breaker 212 also includes two diodes T1 and T2, and T1 and T2 are in anti-parallel relationship with Q1 and Q2 respectively. Specifically, the diode T1 corresponds to Q1, the anode of T1 is connected to the emitter of Q1, and the cathode of T1 is connected to the collector of Q1; the diode T2 corresponds to Q2, the anode of T2 is connected to the emitter of Q2, and the cathode of T2 is connected to the collector of Q2. In this way, the control mechanism of the circuit breaker SP is realized by two insulated gate bipolar transistors Q1 and Q2 connected in series, and a pair of diodes T1 and T2 connected in anti-parallel relationship. Specifically, when the circuit breaker SP receives a control signal indicating closing, the gate voltage of the IGBT in the circuit breaker SP can be controlled to turn on the IGBT, thereby realizing the connection between the reference output port M and the reference input port M'; when the circuit breaker SP receives a control signal indicating disconnection, the gate voltage of the IGBT in the circuit breaker SP can be controlled to turn off the IGBT, thereby blocking the connection between the reference output port M and the reference input port M'; using the control mechanism of the IGBT, it is also possible to stop sending a closing control signal to the circuit breaker SP, so that the circuit breaker SP can drive the IGBT to turn off after not receiving the closing control signal. In addition, the reverse current voltage can be suppressed by connecting the diode in anti-parallel with the IGBT to avoid damage caused by excessive reverse current voltage.

[0058] Please continue reading Figure 2 It should be understood that Figure 2The IGBT shown is only exemplary. In some exemplary embodiments, the two semiconductor switching devices included in the main circuit breaker 212 are a first switching transistor and a second switching transistor. The first switching transistor and the second switching transistor are connected in series between the reference output port of the capacitor bridge arm and the reference input port of the inverter multi-level bridge arm. The controller controls the closing and opening of the circuit breaker by controlling the conduction and disconnection of the first switching transistor and the second switching transistor of the main circuit breaker. In some exemplary embodiments, the two semiconductor switch devices included in the main circuit breaker 212 can be implemented by other semiconductor devices with similar functions, such as metal-oxide-semiconductor field-effect transistor (MOSFET), giant transistor (GTR), gate turn-off thyristor (GTO) or other suitable devices, and pairs of diodes are configured accordingly. In some exemplary embodiments, these semiconductor devices can also be high electron mobility transistors (HEMT), also known as modulation-doped FET (MODFET), or two-dimensional electron gas field effect transistors (2-DEGFET), or selectively doped heterojunction transistors (Selectively-Doped Heterojunction Transistors). Transistor, SDHT). These can be adjusted and improved according to the specific application environment and are not specifically limited here. In other words, the first switch transistor and the second switch transistor are MOSFET, IGBT, GTR, GTO, HEMT, MODFET, 2-DEGFET or SDHT.

[0059] See also Figure 3 , Figure 3 The embodiment of the present application provides Figure 1 The structural block diagram of the second embodiment of the circuit breaker SP of the fault protection device is shown in FIG. Figure 3 As shown, the circuit breaker SP includes a main circuit breaker 312 and a varistor 313. The structure and function of the main circuit breaker 312 are similar to those of the circuit breaker 313. Figure 2The main circuit breaker 212 shown is similar and will not be described again. The varistor 313 can be based on a metal oxide material, and the varistor 313 and the main circuit breaker 312 are connected in parallel between the reference output port M and the reference input port M'. The varistor 313 has a nonlinear volt-ampere characteristic and is used to absorb the residual energy of the circuit breaker SP during the circuit breaking process, which is beneficial to prevent the main circuit breaker 312 from being damaged by overvoltage and improve the reliability of the circuit.

[0060] See also Figure 4 , Figure 4 The embodiment of the present application provides Figure 1 FIG. 1 is a block diagram of a third embodiment of a circuit breaker SP of a fault protection device. Figure 4 As shown, the circuit breaker SP includes a main circuit breaker 412, a varistor 413 and a high-speed mechanical switch 414. The main circuit breaker 412, the varistor 413 and the high-speed mechanical switch 414 are all connected in parallel between the reference output port M and the reference input port M'. The structure and function of the main circuit breaker 412 are similar to those of Figure 2 The structure and function of the varistor 413 are similar to those of the main circuit breaker 212 shown in FIG. Figure 3 The high-speed mechanical switch 414 is similar to the varistor 313 shown, and will not be described in detail here. The high-speed mechanical switch 414 is closed only after the IGBT of the main circuit breaker 412 is turned on, that is, after the IGBT of the main circuit breaker 412 is turned on, the main circuit breaker 412 is bypassed by the closed high-speed mechanical switch 414, so that the loss of the circuit breaker SP can be reduced by the closed high-speed mechanical switch 414. The high-speed mechanical switch 414 is disconnected before the IGBT of the main circuit breaker 412 is turned off, thereby ensuring that the IGBT of the main circuit breaker 412 bears the impact of the current circuit breaker, and avoiding the impact of the current circuit breaker by the high-speed mechanical switch 414.

[0061] See also Figure 5 , Figure 5 The embodiment of the present application provides Figure 1 FIG. 4 is a block diagram of a fourth embodiment of a circuit breaker SP of a fault protection device. Figure 5 As shown, the circuit breaker SP includes a main circuit breaker 512, a varistor 513, a high-speed mechanical switch 514, and an auxiliary circuit breaker 515. The high-speed mechanical switch 514 and the auxiliary circuit breaker 515 are connected in series and then connected in parallel with the main circuit breaker 512 and the varistor 513 between the reference output port M and the reference input port M'. The structure and function of the main circuit breaker 512 are similar to those of the auxiliary circuit breaker 515. Figure 2 The structure and function of the varistor 513 are similar to those of the main circuit breaker 212 shown in FIG. Figure 3 The structure and function of the high-speed mechanical switch 514 are similar to those of the varistor 313 shown in FIG. Figure 4 The high-speed mechanical switch 414 shown is similar and will not be described here. Among them, the auxiliary circuit breaker 515 includes two semiconductor switch devices, taking IGBT as an example, Q3 and Q4. Q3 and Q4 are connected between the reference input port M' and the high-speed mechanical switch 514 in a pair-wise series manner. That is, the emitter of Q3 and the emitter of Q4 are connected to each other, the collector of Q3 is connected to the reference input port M', and the collector of Q4 is connected to the reference high-speed mechanical switch 514. In another embodiment, the collector of Q3 and the collector of Q4 are connected to each other, the emitter of Q3 is connected to the reference input port M', and the emitter of Q4 is connected to the high-speed mechanical switch 514. In these two embodiments, the positions of Q3 and Q4 can also be interchanged. In addition, the positions of the high-speed mechanical switch 514 and the auxiliary circuit breaker 515 can also be interchanged. The auxiliary circuit breaker 515 also includes two diodes T3 and T4, and T3 and T4 are in an anti-parallel relationship with Q3 and Q4 respectively. Specifically, diode T3 corresponds to Q3, the anode of T3 is connected to the emitter of Q3, and the cathode of T3 is connected to the collector of Q3; diode T4 corresponds to Q4, the anode of T4 is connected to the emitter of Q4, and the cathode of T4 is connected to the collector of Q4. The auxiliary circuit breaker 515 and the high-speed mechanical switch 514 are closed only after the IGBT of the main circuit breaker 512 is turned on, that is, after the IGBT of the main circuit breaker 512 is turned on, the high-speed mechanical switch 514 and the auxiliary circuit breaker 515 are closed to form a bypass branch to bypass the main circuit breaker 512, thereby reducing the loss of the circuit breaker SP. The high-speed mechanical switch 514 is disconnected before the IGBT of the main circuit breaker 512 is turned off, and the auxiliary circuit breaker 515 is disconnected before the high-speed mechanical switch 514 is disconnected. Therefore, through the disconnection operation of the auxiliary circuit breaker 515, the bypass branch including the high-speed mechanical switch 514 and the auxiliary circuit breaker 515 is disconnected before the IGBT of the main circuit breaker 512 is turned off, thereby avoiding the high-speed mechanical switch 514 from bearing the impact of the current circuit breakers and ensuring that the IGBT of the main circuit breaker 512 bears the impact of the current circuit breakers.

[0062] Please continue reading Figure 5 It should be understood that Figure 5 The IGBT shown is only exemplary. In some exemplary embodiments, the two semiconductor switching devices included in the auxiliary circuit breaker 515 are a third switching transistor and a fourth switching transistor. The third switching transistor and the fourth switching transistor are MOSFET, IGBT, GTR, GTO, HEMT, MODFET, 2-DEGFET or SDHT.

[0063] See also Figure 6 , Figure 6 The embodiment of the present application provides Figure 1FIG. 5 is a block diagram of a fifth embodiment of a circuit breaker SP of a fault protection device. Figure 3 As shown, the circuit breaker SP includes a main circuit breaker 612 and a thermistor 615. The thermistor 615 can also be other types of high impedance devices. Figure 2 The main circuit breaker 212 shown is similar and will not be described in detail here. The thermistor 615 and the main circuit breaker 612 are connected in parallel between the reference output port M and the reference input port M'. The thermistor 615 withstands the short-circuit current and charges and discharges the capacitor bridge arm connected to the circuit breaker SP after the main circuit breaker 612 is disconnected. Because the resistance of the thermistor 615 is large and the resistance is further increased at high temperatures, the charging and discharging speed of the capacitor bridge arm is slowed down, which is conducive to the response of other protection mechanisms and improves the stability of the system. The thermistor 615 can be used in parallel with the second, third, and fourth embodiments of the circuit breaker SP in the same way, which will not be described in detail here.

[0064] See also Figure 7 , Figure 7 FIG. 1 shows a principle block diagram of an ANPC three-level circuit with a fault protection device provided in an embodiment of the present application. Figure 7 As shown, the active neutral point clamped (ANPC) three-level circuit 700 includes a fault protection device 710, a capacitor bridge arm 720 and an ANPC three-level bridge arm 730. The fault protection device 710 includes a disconnect switch SP, Figure 7 The circuit breaker SP shown can correspond to Figures 2 to 5 The circuit breaker SP shown in any embodiment of the present invention or any possible combination or variant of these embodiments. The capacitor bridge arm 720 has three output ports, namely, a positive output port P, a negative output port N and a reference output port M. In contrast, the ANPC three-level bridge arm 730 has three input ports, namely, a positive input port P', a negative input port N' and a reference input port M'. Among them, the ANPC three-level bridge arm 730 also has an external output port O, which is used to provide an output level voltage to the next level load or external network. Among them, the positive output port P is connected to the positive input port P', the negative output port N is connected to the negative input port N', one end of the fault protection device 710 is connected to the reference output port M, and the other end is connected to the reference input port M'. In this way, there is a one-to-one corresponding connection relationship between each output port of the capacitor bridge arm 720 and each input port of the ANPC three-level bridge arm 730, and the reference output port M is indirectly connected to the reference input port M' through the fault protection device 710. It should be understood that the positive electrode and negative electrode mentioned in the embodiments of the present application are only relative concepts. One port is designated as the positive electrode and the other port as the negative electrode for the convenience of description, and should not be understood as restrictive.

[0065] Please continue reading Figure 7 , the capacitor bridge arm 720 includes two capacitors C1 and C2. The capacitors C1 and C2 are connected in series between the positive output port P and the negative output port N, and the intermediate node between the capacitors C1 and C2 is connected to the reference output port M. The ANPC three-level bridge arm 730 includes a total of six semiconductor switching devices, which are marked as S1, S2, S3, S4, S5 and S6 respectively. It should be understood that each of the semiconductor switching devices S1, S2, S3, S4, S5 and S6 included in the ANPC three-level bridge arm 730 is a paired IGBT and a diode connected in an anti-parallel relationship with the IGBT. In some exemplary embodiments, these semiconductor switching devices can also be implemented using other semiconductor devices with similar functions, such as metal oxide semiconductor field effect tubes MOSFET, power transistors GTR, turn-off thyristors GTO or other suitable devices, and pairs of diodes are configured accordingly. In some exemplary embodiments, these semiconductor devices may also use high electron mobility transistors HEMT, also known as modulation doped field effect transistors MODFET, or two-dimensional electron gas field effect transistors 2-DEGFET, or selective doped heterojunction transistors SDHT. These may be adjusted and improved according to specific application environments, and are not specifically limited here.

[0066] Please continue reading Figure 7, semiconductor switch devices S1 and S2 are connected in series between the positive input port P' and the reference input port M', and semiconductor switch devices S3 and S4 are connected in series between the reference input port M' and the negative input port N'. Semiconductor switch devices S2 and S3 are connected, and the intermediate node between semiconductor switch devices S2 and S3 is connected to the reference input port M'. Semiconductor switch devices S5 and S6 are connected in series to respectively connect the intermediate node between semiconductor switch devices S1 and S2 and the intermediate node between semiconductor switch devices S3 and S4. The intermediate node between semiconductor switch devices S5 and S6 is connected to the external output port O of the ANPC three-level bridge arm 730. When semiconductor switch devices S1 and S5 are turned on, the external output port O is connected to the positive input port P' through a branch composed of semiconductor switch devices S1 and S5, and the positive output port P is connected to the positive input port P', so the voltage outputted by the external output port O is the first voltage applied to the positive output port P. When the semiconductor switch devices S4 and S6 are turned on, the external output port O is connected to the negative input port N' through the branch composed of the semiconductor switch devices S4 and S6, and the negative output port N is connected to the negative input port N', so the voltage outputted from the external output port O is the second voltage applied to the negative output port N. When the semiconductor switch devices S2 and S5 are turned on or when the semiconductor switch devices S3 and S6 are turned on, the external output port O is connected to the reference input port M' through the branch composed of the semiconductor switch devices S2 and S5 or the branch composed of the semiconductor switch devices S3 and S6, and the reference output port M is indirectly connected to the reference input port M' through the fault protection device 710, so the voltage outputted from the external output port O is the third voltage applied to the reference output port M. In this way, by controlling the on and off of each semiconductor switching device included in the ANPC three-level bridge arm 730, the voltage output to the external output port O can be switched between a first voltage applied to the positive output port P, a second voltage applied to the negative output port N, and a third voltage applied to the reference output port M, thereby achieving a three-level output.

[0067] Please continue reading Figure 7When the semiconductor switch devices S3 and S4 are short-circuited at the same time, the negative input port N' and the reference input port M' are equivalent to a short-circuit connection, and if the reference output port M is connected to the reference input port M', the capacitor C2 will be bypassed, so that the voltage between the positive output port P and the negative output port N is all applied to the capacitor C1. When the capacitor bridge arm 720 adopts a symmetrical design, the capacitors C1 and C2 bear half of the voltage between the positive output port P and the negative output port N, respectively. Therefore, when the voltage between the positive output port P and the negative output port N is all applied to the capacitor C1, the capacitor C1 may bear twice the voltage of the normal design, thereby causing overvoltage damage, and even spreading to damage the circuit and equipment, greatly reducing the reliability of the circuit. Similarly, when the semiconductor switch devices S1 and S2 are short-circuited at the same time, the positive input port P' and the reference input port M' are equivalent to a short-circuit connection, and if the reference output port M and the reference input port M' remain connected, the capacitor C1 will be bypassed, so that the voltage between the positive output port P and the negative output port N is all applied to the capacitor C2, thereby causing overvoltage damage. To this end, it is necessary to adjust the connection relationship between the reference output port M and the reference input port M' by controlling the closing and opening of the circuit breaker SP. Specifically, it is possible to determine whether a short-circuit fault occurs in the semiconductor switch device by monitoring one of the following situations: monitoring the voltage between the negative input port N' and the reference input port M', and determining that the semiconductor switch devices S3 and S4 have short-circuit faults at the same time when the voltage is lower than a certain threshold; monitoring the voltage between the positive input port P' and the reference input port M', and determining that the semiconductor switch devices S1 and S2 have short-circuit faults at the same time when the voltage is lower than a certain threshold; monitoring the voltage drop rate between the negative input port N' and the reference input port M', and determining that the semiconductor switch devices S3 and S4 have short-circuit faults at the same time when the voltage drop rate is higher than a certain threshold; monitoring the voltage between the positive input port P' and the reference input port M'. ' and the reference input port M', when the voltage drop rate is higher than a certain threshold, it is judged that the semiconductor switch devices S1 and S2 have short-circuit faults at the same time; monitor the current flowing from the positive input port P' to the negative input port N' and passing through the semiconductor switch devices S1, S2, S3 or S4, when the current is higher than a certain threshold, it is judged that the corresponding semiconductor switch device S1, S2, S3 or S4 has a short-circuit fault; monitor the voltage between the collector and the emitter of each semiconductor switch device S1, S2, S3 or S4 when the semiconductor switch device S1, S2, S3 or S4 is closed, when the voltage is higher than a certain threshold, it is judged that the corresponding semiconductor switch device S1, S2, S3 or S4 has a short-circuit fault.In this way, by monitoring the above situation, for example, monitoring the current and voltage of a specific semiconductor switch device, it is possible to determine whether the ANPC three-level bridge arm 730 has a short circuit fault, and timely adjust the connection relationship between the reference output port M and the reference input port M' by controlling the closing and opening of the circuit breaker SP, thereby avoiding overvoltage damage to the half-bus capacitor and improving the reliability of the circuit. In addition, the current flowing through the circuit breaker SP can also be monitored, and when the current is greater than a certain threshold, it is determined that the ANPC three-level bridge arm 730 has a short circuit fault.

[0068] Please continue reading Figure 7 The ANPC three-level circuit 700 may include a plurality of ANPC three-level bridge arms 730, wherein each ANPC three-level bridge arm 730 has Figure 7 The input ports of the multiple ANPC three-level bridge arms 730 are connected in parallel to the corresponding Figure 7 The positive input port P', the negative input port N' and the reference input port M' shown in the figure make the multiple ANPC three-level bridge arms 730 form a parallel relationship. When the multiple ANPC three-level bridge arms 730 are working normally, the circuit breaker SP of the fault protection device 710 is closed; when any one of the multiple ANPC three-level bridge arms 730 has a short circuit fault, the circuit breaker SP of the fault protection device 710 is disconnected, thereby avoiding overvoltage damage to the half-bus capacitor and improving the reliability of the circuit. Among them, judging whether any one of the multiple ANPC three-level bridge arms 730 has a short circuit fault can be achieved by monitoring whether all the ANPC three-level bridge arms 730 have one of the above situations.

[0069] It should be understood that the controller 711 included in the fault protection device 710 is communicatively connected to the circuit breaker SP and is configured to control the closing and opening of the circuit breaker SP. The controller 711 may have corresponding circuits and components to monitor the above-mentioned short-circuit fault, and may also receive instructions from the outside through an interface circuit. In some exemplary embodiments, the controller 711 may be provided separately from the fault protection device 710, that is, as a separate device. In addition to the various situations mentioned above, other technical means may also be used to determine whether a short-circuit fault has occurred in the semiconductor switch device. These can be adjusted and improved according to the specific application environment, and are not specifically limited here.

[0070] It should be understood that Figure 7 The multiple semiconductor switching devices included in the ANPC three-level bridge arm 730 are IGBTs as an example. Figure 7The respective collectors and emitters of these semiconductor switch devices are schematically shown in FIG. When these semiconductor switch devices are other types such as MOSFET, the collectors and emitters are replaced with drains and sources. Figure 7 The collector and emitter shown are to be understood as schematically representing the first transfer electrode and the second transfer electrode, respectively, of these semiconductor switching devices.

[0071] See also Figure 8 , Figure 8 FIG. 1 shows a principle block diagram of an NPC three-level circuit with a fault protection device provided in an embodiment of the present application. Figure 8 As shown, the neutral point clamped (NPC) three-level circuit 800 includes a fault protection device 810, a capacitor bridge arm 820 and an NPC three-level bridge arm 830. The fault protection device 810 includes a disconnect switch SP, Figure 8 The circuit breaker SP shown can correspond to Figures 2 to 5 The circuit breaker SP shown in any embodiment of the present invention or any possible combination or variant of these embodiments. The capacitor bridge arm 820 has three output ports, namely, a positive output port P, a negative output port N and a reference output port M. In contrast, the NPC three-level bridge arm 830 has three input ports, namely, a positive input port P', a negative input port N' and a reference input port M'. Among them, the NPC three-level bridge arm 830 also has an external output port O, which is used to provide an output level voltage to the next level load or external network. Among them, the positive output port P is connected to the positive input port P', the negative output port N is connected to the negative input port N', one end of the fault protection device 810 is connected to the reference output port M, and the other end is connected to the reference input port M'. In this way, there is a one-to-one corresponding connection relationship between each output port of the capacitor bridge arm 820 and each input port of the NPC three-level bridge arm 830, and the reference output port M is indirectly connected to the reference input port M' through the fault protection device 810. It should be understood that the positive electrode and negative electrode mentioned in the embodiments of the present application are only relative concepts. One port is designated as the positive electrode and the other port as the negative electrode for the convenience of description, and should not be understood as restrictive.

[0072] Please continue reading Figure 8, the capacitor bridge arm 820 includes two capacitors C1 and C2. The capacitors C1 and C2 are connected in series between the positive output port P and the negative output port N, and the intermediate node between the capacitors C1 and C2 is connected to the reference output port M. The NPC three-level bridge arm 830 includes a total of six semiconductor devices, which are marked as S1, D2, D3, S4, S5 and S6. Among them, the semiconductor devices S1, S4, S5 and S6 are semiconductor switching devices and the semiconductor devices D2 and D3 are diodes. It should be understood that each of the semiconductor switching devices S1, S4, S5 and S6 included in the NPC three-level bridge arm 830 is a paired IGBT and a diode connected in an anti-parallel relationship with the IGBT. In some exemplary embodiments, these semiconductor switching devices can also be implemented using other semiconductor devices with similar functions, such as MOSFET, GTR, GTO or other suitable devices, and paired diodes are configured accordingly. In some exemplary embodiments, these semiconductor devices may also use HEMT, also known as MODFET, or 2-DEGFET, or SDHT. These may be adjusted and improved according to specific application environments, and are not specifically limited here.

[0073] Please continue reading Figure 8, semiconductor switch devices S1 and D2 are connected in series between the positive input port P' and the reference input port M', and semiconductor switch devices D3 and S4 are connected in series between the reference input port M' and the negative input port N'. Semiconductor switch devices D2 and D3 are connected, and the intermediate node between semiconductor switch devices D2 and D3 is connected to the reference input port M'. Semiconductor switch devices S5 and S6 are connected in series to respectively connect the intermediate node between semiconductor switch devices S1 and D2 and the intermediate node between semiconductor switch devices D3 and S4. The intermediate node between semiconductor switch devices S5 and S6 is connected to the external output port O of the NPC three-level bridge arm 830. Among them, the anode of diode D2 is connected to the reference input port M', and the cathode is connected to the emitter of semiconductor switch device S1. The cathode of diode D3 is connected to the reference input port M', and the anode is connected to the collector of semiconductor switch device S4. The anode of diode D2 is connected to the cathode of diode D3. When the semiconductor switch devices S1 and S5 are turned on, the external output port O is connected to the positive input port P' through the branch composed of the semiconductor switch devices S1 and S5, and the positive output port P is connected to the positive input port P', so the voltage output from the external output port O is the first voltage applied to the positive output port P. When the semiconductor switch devices S4 and S6 are turned on, the external output port O is connected to the negative input port N' through the branch composed of the semiconductor switch devices S4 and S6, and the negative output port N is connected to the negative input port N', so the voltage output from the external output port O is the second voltage applied to the negative output port N. When the semiconductor switch devices D2 and S5 are turned on or when the semiconductor switch devices D3 and S6 are turned on, the external output port O is connected to the reference input port M' through the branch composed of the semiconductor switch devices D2 and S5 or the branch composed of the semiconductor switch devices D3 and S6, and the reference output port M is indirectly connected to the reference input port M' through the fault protection device 810, so the voltage output by the external output port O is the third voltage applied to the reference output port M. In this way, by controlling the conduction and shutdown of each semiconductor switch device included in the NPC three-level bridge arm 830, the voltage output by the external output port O can be switched between the first voltage applied to the positive output port P, the second voltage applied to the negative output port N, and the third voltage applied to the reference output port M, so as to achieve a three-level output.

[0074] Please continue reading Figure 8When the semiconductor switch devices D3 and S4 are short-circuited at the same time, the negative input port N' and the reference input port M' are equivalent to a short-circuit connection, and if the reference output port M is connected to the reference input port M', the capacitor C2 will be bypassed, so that the voltage between the positive output port P and the negative output port N is all applied to the capacitor C1. When the capacitor bridge arm 820 adopts a symmetrical design, the capacitors C1 and C2 bear half of the voltage between the positive output port P and the negative output port N, respectively. Therefore, when the voltage between the positive output port P and the negative output port N is all applied to the capacitor C1, the capacitor C1 may bear twice the voltage of the normal design, thereby causing overvoltage damage, and even spreading to damage the circuit and equipment, greatly reducing the reliability of the circuit. Similarly, when the semiconductor switch devices S1 and D2 are short-circuited at the same time, the positive input port P' and the reference input port M' are equivalent to a short-circuit connection, and if the reference output port M and the reference input port M' remain connected, the capacitor C1 will be bypassed, so that the voltage between the positive output port P and the negative output port N is all applied to the capacitor C2, thereby causing overvoltage damage. To this end, it is necessary to adjust the connection relationship between the reference output port M and the reference input port M' by controlling the closing and opening of the circuit breaker SP. Specifically, it is possible to determine whether a short-circuit fault occurs in a semiconductor switch device by monitoring one of the following situations: monitoring the voltage between the negative input port N' and the reference input port M', and determining that the semiconductor switch devices D3 and S4 have short-circuit faults at the same time when the voltage is lower than a certain threshold; monitoring the voltage between the positive input port P' and the reference input port M', and determining that the semiconductor switch devices S1 and D2 have short-circuit faults at the same time when the voltage is lower than a certain threshold; monitoring the voltage drop rate between the negative input port N' and the reference input port M', and determining that the semiconductor switch devices D3 and S4 have short-circuit faults at the same time when the voltage is higher than a certain threshold; monitoring the positive input port P' and the reference input port M', and determining that the semiconductor switch devices S1 and D2 have short-circuit faults at the same time when the voltage is lower than a certain threshold. The voltage drop rate between the positive input port P' and the reference input port M' is monitored. When the voltage drop rate is higher than a certain threshold, it is determined that the semiconductor switch devices S1 and D2 have short-circuit faults at the same time; the current flowing from the positive input port P' to the negative input port N' and passing through the semiconductor switch devices S1, D2, D3 or S4 is monitored. When the current is higher than a certain threshold, it is determined that the corresponding semiconductor switch device S1, D2, D3 or S4 has a short-circuit fault; the voltage between the collector and the emitter of the semiconductor switch device S1 or S4 is monitored when the semiconductor switch device S1 or S4 is closed. When the voltage is higher than a certain threshold, it is determined that the corresponding semiconductor switch device S1 or S4 has a short-circuit fault.In this way, by monitoring the above situation, for example, monitoring the current and voltage of a specific semiconductor switch device, it is possible to determine whether a short circuit fault occurs in the NPC three-level bridge arm 830, and timely adjust the connection relationship between the reference output port M and the reference input port M' by controlling the closing and opening of the circuit breaker SP, thereby avoiding overvoltage damage to the half-bus capacitor and improving the reliability of the circuit. In addition, the current flowing through the circuit breaker SP can also be monitored, and when the current is greater than a certain threshold, it is determined that a short circuit fault occurs in the NPC three-level bridge arm 830.

[0075] Please continue reading Figure 8 The NPC three-level circuit 800 may include a plurality of NPC three-level bridge arms 830, wherein each NPC three-level bridge arm 830 has Figure 8 The structure shown in FIG. 1 and each of them has three input ports. The input ports of the plurality of NPC three-level bridge arms 830 are connected in parallel to the corresponding Figure 8 The positive input port P', the negative input port N' and the reference input port M' shown in the figure make the multiple NPC three-level bridge arms 830 form a parallel relationship. When the multiple NPC three-level bridge arms 830 are working normally, the circuit breaker SP of the fault protection device 810 is closed; when any one of the multiple NPC three-level bridge arms 830 has a short circuit fault, the circuit breaker SP of the fault protection device 810 is disconnected, thereby avoiding overvoltage damage to the half-bus capacitor and improving the reliability of the circuit. Among them, judging whether any one of the multiple NPC three-level bridge arms 830 has a short circuit fault can be achieved by monitoring whether all the NPC three-level bridge arms 830 have one of the above situations.

[0076] It should be understood that the controller 811 included in the fault protection device 810 is communicatively connected to the circuit breaker SP and is configured to control the closing and opening of the circuit breaker SP. The controller 811 may have corresponding circuits and components to monitor the above-mentioned short-circuit fault, and may also receive instructions from the outside through an interface circuit. In some exemplary embodiments, the controller 811 may be provided separately from the fault protection device 810, that is, as a separate device. In addition to the various situations mentioned above, other technical means may also be used to determine whether a short-circuit fault has occurred in the semiconductor switch device. These can be adjusted and improved according to the specific application environment, and are not specifically limited here.

[0077] It should be understood that Figure 8 The multiple semiconductor switching devices included in the NPC three-level bridge arm 830 are IGBTs as an example. Figure 8 The respective collectors and emitters of these semiconductor switch devices are schematically shown in FIG. When these semiconductor switch devices are other types such as MOSFET, the collectors and emitters are replaced with drains and sources. Figure 8 The collector and emitter shown are to be understood as schematically representing the first transfer electrode and the second transfer electrode, respectively, of these semiconductor switching devices.

[0078] See also Fig. 9 , Fig. 9 FIG. 1 shows a principle block diagram of a T-type three-level circuit with a fault protection device provided in an embodiment of the present application. Fig. 9 As shown, the T-type three-level circuit 900 includes a fault protection device 910, a capacitor bridge arm 920 and a T-type three-level bridge arm 930. The fault protection device 910 includes a disconnect switch SP, Fig. 9 The circuit breaker SP shown can correspond to Figures 2 to 5 The circuit breaker SP shown in any embodiment of the present invention or any possible combination or variant of these embodiments. The capacitor bridge arm 920 has three output ports, namely, a positive output port P, a negative output port N and a reference output port M. In contrast, the T-type three-level bridge arm 930 has three input ports, namely, a positive input port P', a negative input port N' and a reference input port M'. Among them, the T-type three-level bridge arm 930 also has an external output port O, which is used to provide an output level voltage to the next level load or external network. Among them, the positive output port P is connected to the positive input port P', the negative output port N is connected to the negative input port N', one end of the fault protection device 910 is connected to the reference output port M, and the other end is connected to the reference input port M'. In this way, there is a one-to-one corresponding connection relationship between each output port of the capacitor bridge arm 920 and each input port of the T-type three-level bridge arm 930, and the reference output port M is indirectly connected to the reference input port M' through the fault protection device 910. It should be understood that the positive electrode and negative electrode mentioned in the embodiments of the present application are only relative concepts. One port is designated as the positive electrode and the other port as the negative electrode for the convenience of description, and should not be understood as restrictive.

[0079] Please continue reading Fig. 9, the capacitor bridge arm 920 includes two capacitors C1 and C2. The capacitors C1 and C2 are connected in series between the positive output port P and the negative output port N, and the intermediate node between the capacitors C1 and C2 is connected to the reference output port M. The T-type three-level bridge arm 930 includes a total of four semiconductor switching devices, which are marked as S1, S2, S3 and S4 respectively. It should be understood that each of the semiconductor switching devices S1, S2, S3 and S4 included in the T-type three-level bridge arm 930 is a paired IGBT and a diode connected in anti-parallel relationship with the IGBT. In some exemplary embodiments, these semiconductor switching devices can also be implemented using other semiconductor devices with similar functions, such as MOSFET, GTR, GTO or other suitable devices, and paired diodes are configured accordingly. In some exemplary embodiments, these semiconductor devices can also use HEMT, also known as MODFET, or 2-DEGFET, or SDHT. These can be adjusted and improved according to the specific application environment, and are not specifically limited here.

[0080] Please continue reading Fig. 9, semiconductor switch devices S1 and S2 are connected in series between the positive input port P' and the negative input port N', and the intermediate node between the semiconductor switch devices S1 and S2 is connected to the external output port O. Semiconductor switch devices S3 and S4 are connected in series between the reference input port M' and the external output port O. Among them, semiconductor switch devices S3 and S4 are connected between the reference input port M' and the external output port O in a pair-wise series manner. That is, the emitter of S3 and the emitter of S4 are connected to each other, the collector of S3 is connected to the reference input port M', and the collector of S4 is connected to the external output port O. In another embodiment, the positions of S3 and S4 can also be interchanged, as long as the respective emitters are kept connected to each other, the collector of one is connected to the reference input port M', and the collector of the other is connected to the external output port O. When the semiconductor switch device S1 is turned on, the external output port O is connected to the positive input port P' through the branch composed of the semiconductor switch device S1, and the positive output port P is connected to the positive input port P', so the voltage output by the external output port O is the first voltage applied to the positive output port P. When the semiconductor switch device S2 is turned on, the external output port O is connected to the negative input port N' through the branch composed of the semiconductor switch device S2, and the negative output port N is connected to the negative input port N', so the voltage outputted by the external output port O is the second voltage applied to the negative output port N. When the semiconductor switch devices S3 and S4 are turned on, the external output port O is connected to the reference input port M' through the branch composed of the semiconductor switch devices S3 and S4, and the reference output port M is indirectly connected to the reference input port M' through the fault protection device 910, so the voltage outputted by the external output port O is the third voltage applied to the reference output port M. In this way, by controlling the conduction and disconnection of each semiconductor switch device included in the T-type three-level bridge arm 930, the voltage outputted by the external output port O can be switched between the first voltage applied to the positive output port P, the second voltage applied to the negative output port N, and the third voltage applied to the reference output port M, so as to realize the three-level output.

[0081] Please continue reading Fig. 9When the semiconductor switch devices S2, S3 and S4 are short-circuited at the same time, the negative input port N' and the reference input port M' are equivalent to a short-circuit connection, and if the reference output port M is connected to the reference input port M', the capacitor C2 will be bypassed, so that the voltage between the positive output port P and the negative output port N is all applied to the capacitor C1. When the capacitor bridge arm 920 adopts a symmetrical design, the capacitors C1 and C2 bear half of the voltage between the positive output port P and the negative output port N, respectively. Therefore, when the voltage between the positive output port P and the negative output port N is all applied to the capacitor C1, the capacitor C1 may bear twice the voltage of the normal design, thereby causing overvoltage damage, and even spreading to damage the circuit and equipment, greatly reducing the reliability of the circuit. Similarly, when the semiconductor switch devices S1, S3 and S4 are short-circuited at the same time, the positive input port P' and the reference input port M' are equivalent to a short-circuit connection, and if the reference output port M and the reference input port M' remain connected, the capacitor C1 will be bypassed, so that the voltage between the positive output port P and the negative output port N is all applied to the capacitor C2, thereby causing overvoltage damage. To this end, it is necessary to adjust the connection relationship between the reference output port M and the reference input port M' by controlling the closing and opening of the circuit breaker SP. Specifically, it is possible to determine whether a short-circuit fault occurs in a semiconductor switch device by monitoring one of the following situations: monitoring the voltage between the negative input port N' and the reference input port M', and determining that the semiconductor switch devices S2, S3, and S4 have short-circuit faults at the same time when the voltage is lower than a certain threshold; monitoring the voltage between the positive input port P' and the reference input port M', and determining that the semiconductor switch devices S1, S3, and S4 have short-circuit faults at the same time when the voltage is lower than a certain threshold; monitoring the voltage drop rate between the negative input port N' and the reference input port M', and determining that the semiconductor switch devices S2, S3, and S4 have short-circuit faults at the same time when the voltage drop rate is higher than a certain threshold; Monitor the voltage drop rate between the positive input port P' and the reference input port M', and determine that the semiconductor switch devices S1, S3 and S4 have short-circuit faults at the same time when the voltage drop rate is higher than a certain threshold; monitor the current flowing from the positive input port P' to the negative input port N' and passing through the semiconductor switch device S1 or S2, and determine that the corresponding semiconductor switch device S1 or S2 has a short-circuit fault when the current is higher than a certain threshold; monitor the voltage between the collector and the emitter of each semiconductor switch device S1, S2, S3 or S4 when the semiconductor switch device S1, S2, S3 or S4 is closed, and determine that the corresponding semiconductor switch device S1, S2, S3 or S4 has a short-circuit fault when the voltage is higher than a certain threshold.In this way, by monitoring the above situation, for example, monitoring the current and voltage of a specific semiconductor switch device, it is possible to determine whether a short circuit fault occurs in the T-type three-level bridge arm 930, and timely adjust the connection relationship between the reference output port M and the reference input port M' by controlling the closing and opening of the circuit breaker SP, thereby avoiding overvoltage damage to the half-bus capacitor and improving the reliability of the circuit. In addition, the current flowing through the circuit breaker SP can also be monitored, and when the current is greater than a certain threshold, it is determined that a short circuit fault occurs in the T-type three-level bridge arm 930.

[0082] Please continue reading Fig. 9 The T-type three-level bridge arm 930 may include a plurality of T-type three-level bridge arms 930, wherein each T-type three-level bridge arm 930 has Fig. 9 The structure shown in FIG. 1 and each of the plurality of T-type three-level bridge arms 930 has three input ports. The input ports of each of the plurality of T-type three-level bridge arms 930 are connected in parallel to the corresponding Fig. 9 The positive input port P', the negative input port N' and the reference input port M' are shown, so that the multiple T-type three-level bridge arms 930 are connected in parallel. When the multiple T-type three-level bridge arms 930 are working normally, the circuit breaker SP of the fault protection device 910 is closed; when any one of the multiple T-type three-level bridge arms 930 has a short circuit fault, the circuit breaker SP of the fault protection device 910 is disconnected, thereby avoiding overvoltage damage to the half-bus capacitor and improving the reliability of the circuit. Among them, judging whether any one of the multiple T-type three-level bridge arms 930 has a short circuit fault can be achieved by monitoring whether all the T-type three-level bridge arms 930 have one of the above situations.

[0083] It should be understood that the controller 911 included in the fault protection device 910 is communicatively connected to the circuit breaker SP and is configured to control the closing and opening of the circuit breaker SP. The controller 911 may have corresponding circuits and components to monitor the above-mentioned short-circuit fault, and may also receive instructions from the outside through an interface circuit. In some exemplary embodiments, the controller 911 may be provided separately from the fault protection device 910, that is, as a separate device. In addition to the various situations mentioned above, other technical means may also be used to determine whether a short-circuit fault has occurred in the semiconductor switch device. These can be adjusted and improved according to the specific application environment, and are not specifically limited here.

[0084] It should be understood that Fig. 9 The multiple semiconductor switching devices included in the T-type three-level bridge arm 930 shown in the figure take IGBT as an example. Fig. 9 The respective collectors and emitters of these semiconductor switch devices are schematically shown in FIG. When these semiconductor switch devices are other types such as MOSFET, the collectors and emitters are replaced with drains and sources. Fig. 9The collector and emitter shown are to be understood as schematically representing the first transfer electrode and the second transfer electrode, respectively, of these semiconductor switching devices.

[0085] See also Fig.10 , Fig.10 FIG. 1 shows a principle block diagram of a five-level circuit with a fault protection device provided in an embodiment of the present application. Fig.10 As shown, the five-level circuit 1000 includes a fault protection device 1010, a capacitor bridge arm 1020 and a five-level bridge arm 1030. The fault protection device 1010 includes a disconnect switch SP, Fig.10 The circuit breaker SP shown can correspond to Figures 2 to 5 The circuit breaker SP shown in any embodiment of the present invention or any possible combination or variant of these embodiments. The capacitor bridge arm 1020 has three output ports, namely, a positive output port P, a negative output port N and a reference output port M. In contrast, the five-level bridge arm 1030 has three input ports, namely, a positive input port P', a negative input port N' and a reference input port M'. Among them, the five-level bridge arm 1030 also has an external output port O, which is used to provide an output level voltage to the next level load or external network. Among them, the positive output port P is connected to the positive input port P', the negative output port N is connected to the negative input port N', one end of the fault protection device 1010 is connected to the reference output port M, and the other end is connected to the reference input port M'. In this way, there is a one-to-one corresponding connection relationship between each output port of the capacitor bridge arm 1020 and each input port of the five-level bridge arm 1030, and the reference output port M is indirectly connected to the reference input port M' through the fault protection device 1010. It should be understood that the positive electrode and negative electrode mentioned in the embodiments of the present application are only relative concepts. One port is designated as the positive electrode and the other port as the negative electrode for the convenience of description, and should not be understood as restrictive.

[0086] Please continue reading Fig.10, the capacitor bridge arm 1020 includes two capacitors C1 and C2. The capacitors C1 and C2 are connected in series between the positive output port P and the negative output port N, and the intermediate node between the capacitors C1 and C2 is connected to the reference output port M. The five-level bridge arm 1030 includes a total of eight semiconductor switching devices, which are marked as S1, S2, S3, S4, S5, S6, S7 and S8 respectively. It should be understood that each of the semiconductor switching devices S1, S2, S3, S4, S5, S6, S7 and S8 included in the five-level bridge arm 1030 is a paired IGBT and a diode connected in an anti-parallel relationship with the IGBT. In some exemplary embodiments, these semiconductor switching devices can also be implemented using other semiconductor devices with similar functions, such as MOSFET, GTR, GTO or other suitable devices, and paired diodes are configured accordingly. In some exemplary embodiments, these semiconductor devices can also use HEMT, also known as MODFET, or 2-DEGFET, or SDHT. These can be adjusted and improved according to the specific application environment and are not specifically limited here.

[0087] Please continue reading Fig.10, semiconductor switch devices S1 and S2 are connected in series between the positive input port P' and the reference input port M', and semiconductor switch devices S3 and S4 are connected in series between the reference input port M' and the negative input port N'. Semiconductor switch devices S2 and S3 are connected, and the intermediate node between semiconductor switch devices S2 and S3 is connected to the reference input port M'. Semiconductor switch devices S5 and S7 are connected in series and respectively connect the intermediate node between semiconductor switch devices S1 and S2 and the external output port O of the five-level bridge arm 1030. Semiconductor switch devices S6 and S8 are connected in series and respectively connect the intermediate node between semiconductor switch devices S3 and S4 and the external output port O of the five-level bridge arm 1030. Semiconductor switch devices S7 and S9 are connected, and the intermediate node between semiconductor switch devices S7 and S8 is connected to the external output port O of the five-level bridge arm 1030. Semiconductor switch devices S1, S2, S3 and S4 are connected in series between the positive input port P' and the negative input port N'. Semiconductor switch devices S5, S7, S8 and S6 are connected in series between the intermediate node between semiconductor switch devices S1 and S2 and the intermediate node between semiconductor switch devices S3 and S4. The five-level bridge arm 1030 also includes two capacitors Ca and Cb. Among them, one end of capacitor Ca is connected to the intermediate node between semiconductor switch devices S2 and S5, and the other end is connected to the intermediate node between semiconductor switch devices S3 and S6. One end of capacitor Cb is connected to the intermediate node between semiconductor switch devices S5 and S7, and the other end is connected to the intermediate node between semiconductor switch devices S6 and S8. When semiconductor switch devices S1, S5 and S7 are turned on, the external output port O is connected to the positive input port P' through a branch composed of semiconductor switch devices S1, S5 and S7, and the positive output port P is connected to the positive input port P', so the voltage output by the external output port O is the first voltage applied to the positive output port P. When the semiconductor switch devices S4, S6 and S8 are turned on, the external output port O is connected to the negative input port N' through the branch composed of the semiconductor switch devices S4, S6 and S8, and the negative output port N is connected to the negative input port N', so the voltage outputted from the external output port O is the second voltage applied to the negative output port N. When the semiconductor switch devices S2, S5 and S7 are turned on or when the semiconductor switch devices S3, S6 and S8 are turned on, the external output port O is connected to the reference input port M' through the branch composed of the semiconductor switch devices S2, S5 and S7 or the branch composed of the semiconductor switch devices S3, S6 and S8, and the reference output port M is indirectly connected to the reference input port M' through the fault protection device 1010, so the voltage outputted from the external output port O is the third voltage applied to the reference output port M.In this way, by controlling the on and off of each semiconductor switch device included in the five-level bridge arm 1030, the voltage output to the external output port O can be switched between the first voltage applied to the positive output port P, the second voltage applied to the negative output port N, and the third voltage applied to the reference output port M, thereby realizing a three-level output. In addition, by combining the capacitors Ca and Cb, a voltage dividing branch can be formed or combined with a control signal design, thereby further providing a fourth level and a fifth level output, which can be obtained based on conventional technologies and will not be described in detail here.

[0088] Please continue reading Fig.10When the semiconductor switch devices S3 and S4 are short-circuited at the same time, the negative input port N' and the reference input port M' are equivalent to a short-circuit connection, and if the reference output port M is connected to the reference input port M', the capacitor C2 will be bypassed, so that the voltage between the positive output port P and the negative output port N is all applied to the capacitor C1. When the capacitor bridge arm 1020 adopts a symmetrical design, the capacitors C1 and C2 bear half of the voltage between the positive output port P and the negative output port N, respectively. Therefore, when the voltage between the positive output port P and the negative output port N is all applied to the capacitor C1, the capacitor C1 may bear twice the voltage of the normal design, thereby causing overvoltage damage, and even spreading to damage the circuit and equipment, greatly reducing the reliability of the circuit. Similarly, when the semiconductor switch devices S1 and S2 are short-circuited at the same time, the positive input port P' and the reference input port M' are equivalent to a short-circuit connection, and if the reference output port M and the reference input port M' remain connected, the capacitor C1 will be bypassed, so that the voltage between the positive output port P and the negative output port N is all applied to the capacitor C2, thereby causing overvoltage damage. To this end, it is necessary to adjust the connection relationship between the reference output port M and the reference input port M' by controlling the closing and opening of the circuit breaker SP. Specifically, it is possible to determine whether a short-circuit fault occurs in the semiconductor switch device by monitoring one of the following situations: monitoring the voltage between the negative input port N' and the reference input port M', and determining that the semiconductor switch devices S3 and S4 have short-circuit faults at the same time when the voltage is lower than a certain threshold; monitoring the voltage between the positive input port P' and the reference input port M', and determining that the semiconductor switch devices S1 and S2 have short-circuit faults at the same time when the voltage is lower than a certain threshold; monitoring the voltage drop rate between the negative input port N' and the reference input port M', and determining that the semiconductor switch devices S3 and S4 have short-circuit faults at the same time when the voltage drop rate is higher than a certain threshold; monitoring the voltage between the positive input port P' and the reference input port M'. ' and the reference input port M', when the voltage drop rate is higher than a certain threshold, it is judged that the semiconductor switch devices S1 and S2 have short-circuit faults at the same time; monitor the current flowing from the positive input port P' to the negative input port N' and passing through the semiconductor switch devices S1, S2, S3 or S4, when the current is higher than a certain threshold, it is judged that the corresponding semiconductor switch device S1, S2, S3 or S4 has a short-circuit fault; monitor the voltage between the collector and the emitter of each semiconductor switch device S1, S2, S3 or S4 when the semiconductor switch device S1, S2, S3 or S4 is closed, when the voltage is higher than a certain threshold, it is judged that the corresponding semiconductor switch device S1, S2, S3 or S4 has a short-circuit fault.In this way, by monitoring the above situation, for example, monitoring the current and voltage of a specific semiconductor switch device, it is possible to determine whether a short circuit fault occurs in the five-level bridge arm 1030, and timely adjust the connection relationship between the reference output port M and the reference input port M' by controlling the closing and opening of the circuit breaker SP, thereby avoiding overvoltage damage to the half-bus capacitor and improving the reliability of the circuit. In addition, the current flowing through the circuit breaker SP can also be monitored, and when the current is greater than a certain threshold, it is determined that a short circuit fault occurs in the five-level bridge arm 1030.

[0089] It should be understood that the controller 1011 included in the fault protection device 1010 is communicatively connected to the circuit breaker SP and is configured to control the closing and opening of the circuit breaker SP. The controller 1011 may have corresponding circuits and components to monitor the above-mentioned short-circuit fault, and may also receive instructions from the outside through an interface circuit. In some exemplary embodiments, the controller 1011 may be provided separately from the fault protection device 1010, that is, as a separate device. In addition to the various situations mentioned above, other technical means may also be used to determine whether a short-circuit fault has occurred in the semiconductor switch device. These can be adjusted and improved according to the specific application environment, and are not specifically limited here.

[0090] It should be understood that Fig.10 The five-level circuit 1000 shown in the figure includes a plurality of semiconductor switching devices, for example, IGBT. Fig.10 The respective collectors and emitters of these semiconductor switch devices are schematically shown in FIG. When these semiconductor switch devices are other types such as MOSFET, the collectors and emitters are replaced with drains and sources. Fig.10 The collector and emitter shown are to be understood as schematically representing the first transfer electrode and the second transfer electrode, respectively, of these semiconductor switching devices.

[0091] The specific embodiments provided by the present application can be implemented with any one or combination of hardware, software, firmware or solid-state logic circuits, and can be implemented in combination with signal processing, control and / or special circuits. The equipment or device provided by the specific embodiments of the present application may include one or more processors (e.g., microprocessors, controllers, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), etc.), which process various computer-executable instructions to control the operation of the equipment or device. The equipment or device provided by the specific embodiments of the present application may include a system bus or a data transmission system that couples various components together. The system bus may include any one or a combination of different bus structures, such as a memory bus or a memory controller, a peripheral bus, a universal serial bus and / or a processor or local bus utilizing any one of a variety of bus architectures. The equipment or device provided by the specific embodiments of the present application may be provided separately, may be a part of a system, or may be a part of other equipment or devices.

[0092] The specific embodiments provided in this application may include a computer-readable storage medium or be combined with a computer-readable storage medium, such as one or more storage devices capable of providing non-temporary data storage. The computer-readable storage medium / storage device may be configured to store data, programmers and / or instructions, which, when executed by a processor of a device or apparatus provided in a specific embodiment of this application, enable these devices or apparatuses to perform related operations. The computer-readable storage medium / storage device may include one or more of the following features: volatility, non-volatility, dynamic, static, readable / writable, read-only, random access, sequential access, location addressability, file addressability, and content addressability. In one or more exemplary embodiments, the computer-readable storage medium / storage device may be integrated into the device or apparatus provided in a specific embodiment of this application or belong to a common system. Computer-readable storage media / storage devices may include optical storage devices, semiconductor storage devices and / or magnetic storage devices, etc., and may also include random access memory (RAM), flash memory, read-only memory (ROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, removable disks, recordable and / or rewritable compact disks (CDs), digital versatile disks (DVDs), mass storage media devices or any other form of suitable storage media.

[0093] The above is the implementation method of the embodiment of the present application. It should be noted that the steps in the method described in the specific embodiment of the present application can be adjusted in order, merged and deleted according to actual needs. In the above embodiments, the description of each embodiment has its own emphasis. For the part that is not described in detail in a certain embodiment, refer to the relevant description of other embodiments. It is understandable that the structure shown in the embodiment of the present application and the accompanying drawings does not constitute a specific limitation on the relevant device or system. In other embodiments of the present application, the relevant device or system may include more or fewer components than the specific embodiments and the accompanying drawings, or combine certain components, or split certain components, or have different component arrangements. Those skilled in the art will understand that, without departing from the spirit and scope of the specific embodiments of the present application, various modifications or changes can be made to the arrangement, operation and details of the methods and equipment recorded in the specific embodiments; without departing from the principles of the embodiments of the present application, several improvements and modifications can also be made, and these improvements and modifications are also regarded as the scope of protection of the present application.

Claims

1. A photovoltaic power generation system, characterized in that: The photovoltaic power generation system comprises: A capacitor bridge arm, wherein the capacitor bridge arm comprises a positive output port, a negative output port and a reference output port between the positive output port and the negative output port; An inverter bridge arm, wherein the inverter bridge arm comprises a positive input port, a negative input port and a reference input port between the positive input port and the negative input port, the positive input port is connected to the positive output port, and the negative input port is connected to the negative output port; and A fault protection device, the fault protection device comprising a disconnect switch and a controller, wherein the reference input port is connected to the reference output port through the disconnect switch, the controller is communicatively connected to the disconnect switch and configured to control the closing or opening of the disconnect switch to achieve the closing or opening of the fault protection device, and the fault protection device is turned off according to the magnitude or change of the voltage between the positive input port or the negative input port and the reference input port; The fault protection device is shut down according to the magnitude or change of the voltage between the positive input port or the negative input port and the reference input port, including: When the voltage between the negative input port and the reference input port is lower than a first threshold, the fault protection device is disconnected; or When the voltage between the positive input port and the reference input port is lower than a second threshold, the fault protection device is disconnected; or When the voltage drop rate between the negative input port and the reference input port is higher than a third threshold, the fault protection device is disconnected; or When the voltage drop rate between the positive input port and the reference input port is higher than a fourth threshold, the fault protection device is disconnected.

2. The photovoltaic power generation system according to claim 1, characterized in that: The inverter bridge arm also includes at least one switching device connected between the positive input port or the negative input port and the reference input port, and the fault protection device is also shut down according to the voltage applied between the first transmission electrode and the second transmission electrode of the at least one switching device.

3. The photovoltaic power generation system according to any one of claims 1 to 2, characterized in that: The circuit breaker includes a main circuit breaker, wherein the main circuit breaker includes a first switching transistor and a second switching transistor, the first switching transistor and the second switching transistor are connected in series between the reference output port and the reference input port, and the controller controls the closing and opening of the fault protection device by controlling the conduction and disconnection of the first switching transistor and the second switching transistor.

4. The photovoltaic power generation system according to claim 3, characterized in that: The first switching transistor and the second switching transistor are MOSFET, IGBT, GTR, GTO, HEMT, MODFET, 2-DEGFET or SDHT.

5. The photovoltaic power generation system according to claim 3, characterized in that: The circuit breaker also includes: A high impedance device, wherein the high impedance device and the main circuit breaker are connected in parallel between the reference output port and the reference input port.

6. The photovoltaic power generation system according to claim 5, characterized in that: The high impedance device is a thermistor.

7. The photovoltaic power generation system according to claim 3, characterized in that: The circuit breaker also includes: A varistor, wherein the varistor and the main circuit breaker are connected in parallel between the reference output port and the reference input port.

8. The photovoltaic power generation system according to claim 7, characterized in that: The circuit breaker also includes: A high-speed mechanical switch, wherein the high-speed mechanical switch, the varistor and the main circuit breaker are connected in parallel between the reference output port and the reference input port, the high-speed mechanical switch is closed after the first switching transistor and the second switching transistor of the main circuit breaker are turned on, and the high-speed mechanical switch is opened before the first switching transistor and the second switching transistor of the main circuit breaker are turned off.

9. The photovoltaic power generation system according to claim 7, characterized in that: The circuit breaker also includes: High-speed mechanical switches, and The auxiliary circuit breaker comprises a third switch transistor and a fourth switch transistor, wherein the third switch transistor and the fourth switch transistor are connected in series with the high-speed mechanical switch between the reference output port and the reference input port, The high-speed mechanical switch and the auxiliary circuit breaker are connected in series and then connected in parallel with the varistor and the main circuit breaker between the reference output port and the reference input port. The third switching transistor and the fourth switching transistor of the auxiliary circuit breaker and the high-speed mechanical switch are closed after the first switching transistor and the second switching transistor of the main circuit breaker are turned on, the high-speed mechanical switch is opened before the first switching transistor and the second switching transistor of the main circuit breaker are turned off, and the third switching transistor and the fourth switching transistor of the auxiliary circuit breaker are turned off before the high-speed mechanical switch is opened.

10. The photovoltaic power generation system according to claim 9, characterized in that: The third switching transistor and the fourth switching transistor are MOSFET, IGBT, GTR, GTO, HEMT, MODFET, 2-DEGFET or SDHT.

11. The photovoltaic power generation system according to claim 1, characterized in that: The inverter bridge arm includes an ANPC three-level bridge arm, and the ANPC three-level bridge arm includes a plurality of semiconductor switching devices connected in series between the positive input port and the reference input port and connected in series between the negative input port and the reference input port. The fault protection device is also shut down according to the voltage applied between the first transmission electrode and the second transmission electrode of the plurality of semiconductor switching devices.

12. The photovoltaic power generation system according to claim 11, characterized in that: The plurality of semiconductor switching devices are IGBT, MOSFET, GTR, GTO, HEMT, MODFET, 2-DEGFET or SDHT.

13. The photovoltaic power generation system according to claim 1, characterized in that: The inverter bridge arm includes an NPC three-level bridge arm, and the NPC three-level bridge arm includes a plurality of semiconductor switching devices connected in series between the positive input port and the reference input port and connected in series between the negative input port and the reference input port. The fault protection device is also shut down according to the voltage applied between the first transmission electrode and the second transmission electrode of the plurality of semiconductor switching devices.

14. The photovoltaic power generation system according to claim 13, characterized in that: The plurality of semiconductor switching devices are IGBT, MOSFET, GTR, GTO, HEMT, MODFET, 2-DEGFET or SDHT.

15. The photovoltaic power generation system according to any one of claims 1 to 2, characterized in that: The inverter bridge arm includes a T-type three-level bridge arm, and the T-type three-level bridge arm includes a plurality of semiconductor switching devices connected in series between the positive input port and the negative input port. The fault protection device is also shut down according to the voltage applied between the first transmission electrode and the second transmission electrode of the plurality of semiconductor switching devices.

16. The photovoltaic power generation system according to claim 15, characterized in that: The plurality of semiconductor switching devices are IGBT, MOSFET, GTR, GTO, HEMT, MODFET, 2-DEGFET or SDHT.

17. The photovoltaic power generation system according to claim 1, characterized in that: The inverter bridge arm includes a five-level bridge arm, and the five-level bridge arm includes a plurality of semiconductor switching devices connected in series between the positive input port and the reference input port and connected in series between the negative input port and the reference input port. The fault protection device is also shut down according to the voltage applied between the first transmission electrode and the second transmission electrode of the plurality of semiconductor switching devices.

18. A control method for a fault protection device, applied to a photovoltaic power generation system, characterized in that: The photovoltaic power generation system comprises a capacitor bridge arm, an inverter bridge arm and the fault protection device, wherein the fault protection device comprises a disconnect switch and a controller, wherein the capacitor bridge arm comprises a positive output port, a negative output port and a reference output port between the positive output port and the negative output port, the inverter bridge arm comprises a positive input port, a negative input port and a reference input port between the positive input port and the negative input port, the positive input port is connected to the positive output port, the negative input port is connected to the negative output port, the reference input port is connected to the reference output port via the disconnect switch, the controller is communicatively connected to the disconnect switch and is configured to control the closing or opening of the disconnect switch to control the closing or opening of the fault protection device, and the method comprises: Controlling the fault protection device to shut down according to the magnitude or change of the voltage between the positive input port or the negative input port and the reference input port; The method of controlling the fault protection device to shut down according to the magnitude or change of the voltage between the positive input port or the negative input port and the reference input port includes: When the voltage between the negative input port and the reference input port is lower than a first threshold, the fault protection device is disconnected; or When the voltage between the positive input port and the reference input port is lower than a second threshold, the fault protection device is disconnected; or When the voltage drop rate between the negative input port and the reference input port is higher than a third threshold, the fault protection device is disconnected; or When the voltage drop rate between the positive input port and the reference input port is higher than a fourth threshold, the fault protection device is disconnected.

19. The method according to claim 18, characterized in that The inverter bridge arm further includes at least one semiconductor switch device connected between the positive input port or the negative input port and the reference input port, and the method further includes: The fault protection device is controlled to be turned off according to a voltage applied between a first transmission electrode and a second transmission electrode of the at least one semiconductor switching device.

20. The method according to any one of claims 18 to 19, characterized in that The fault protection device comprises a main circuit breaker, wherein the main circuit breaker comprises a first switching transistor and a second switching transistor, the first switching transistor and the second switching transistor are connected in series between the reference output port and the reference input port, and the method further comprises: The fault protection device is controlled to be closed and opened by controlling the on and off of the first switching transistor and the second switching transistor.

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