Constant Level Offset Buffer Amplifier Circuit

Abstract

A push-pull dynamic amplifier is operable in a reset phase and an amplification phase. The amplifier includes a first NMOS input transistor and a first PMOS input transistor electrically coupled to a first input terminal and a first output terminal. A second NMOS input transistor and a second PMOS input transistor are electrically coupled to a second input terminal and a second output terminal. A first reset switch and a second reset switch are electrically coupled to the first output terminal and the second output terminal, respectively. A power switch is electrically coupled to the first PMOS transistor and the second PMOS transistor, and a ground switch is electrically coupled to the first NMOS transistor and the second NMOS transistor. During the reset phase, the reset switch is closed, and the power switch and the ground switch are open. During the amplification phase, the reset switch is open, and the power switch and the ground switch are closed.

Description

Technical Field

[0001] The present application relates generally to buffer amplifier circuits.

[0002] background

[0003] Buffer amplifiers are widely used in electronic systems. They provide high input impedance, low output impedance, and a voltage gain close to unity. For example, a level-shift buffer amplifier (LSBA) is employed in switched-capacitor circuits to bootstrap a virtual ground node, thereby improving circuit performance. See, for example, U.S. Patent No. 9,214,912 (which is hereby incorporated by reference).

[0004] FIG1 shows a prior art buffer amplifier circuit 10 including a source follower. The gate of the NMOS transistor M1 is the input terminal of the buffer amplifier, and the source of M1 is the output terminal. A current source I provides a bias current for M1, and the current I O is the load current (the current delivered to the load). The current source I is typically implemented by a transistor current source (e.g., an NMOS transistor). The gate-source voltage of M1 provides a level shift V between the input voltage and the output voltage. LS :

[0005]

[0006] Among them I D1 is the drain current through M1, and Is the ratio of W to L of M1. V T is the threshold voltage, μ n is the electron mobility, and C OX is the oxide capacitance per unit area.

[0007] The incremental gain of the buffer amplifier is given by

[0008]

[0009] where g m1 and r o1 are the transconductance and output resistance of M1, and R out is the incremental output resistance of the current source I. The incremental gain in equation (2) is typically slightly less than 1 and depends on the device geometry, bias conditions, and R out .

[0010] The output resistance R of the source follower buffer amplifier o Approximately the inverse of the transconductance of M1:

[0011]

[0012] Since VT 、μ n 、C OX With process, temperature, and supply voltage (PVT) variations of I, the level shift given by equation (1) varies considerably. T The change can be as much as 250-350mV within the PVT range. n 、C OX The variation of I and I significantly increases the level shift variation. In addition, as shown in equation (1), the load current I O Also affects level offset.

[0013] The large variation in level offset in a source-follower buffer amplifier presents a significant challenge in systems that require a precise constant level offset. For example, in the virtual ground bootstrap circuit of U.S. Patent 9,214,912, the level offset determines the reference voltage of the system and therefore needs to be kept constant. As can be seen in Equation (1), the level offset V is maintained by adjusting the current I. GS1 However, considering that V T Large changes in μ n and C OX For example, if M1 is biased in weak inversion, just to compensate for V T A change in Ω would require a current adjustment of more than three orders of magnitude, which is highly undesirable because important parameters of the buffer amplifier, such as bandwidth and output resistance, would change accordingly.

[0014] FIG2 illustrates another prior art LSBA 20 (also known as a flip source follower (FSF)). As in the source follower of FIG1 , V GS1 Gives the level offset:

[0015]

[0016] Transistor M2 provides negative feedback to keep the current through M1 constant at I, which is proportional to the load current I O The FSF has an additional advantage over the standard source follower in Figure 1 in that the negative feedback provided by M2 reduces the output resistance by g. m2 r o1 times, where g m2 is the transconductance of M2, and r o1 is the output resistance of M1. However, as in LSBA in Figure 1, the level shift is affected by V T 、μ n and C OX The influence of changes in the output voltage is very significant, making it sensitive to PVT changes.

[0017] Overview

[0018] The example embodiments described herein have innovative features, wherein no single feature is indispensable or solely responsible for its desired properties. The following description and drawings set forth in detail certain illustrative embodiments of the present disclosure, which illustrate several exemplary ways in which the various principles of the present disclosure may be implemented. However, the illustrative examples are not exhaustive of the many possible embodiments of the present disclosure. Without limiting the scope of the claims, some advantageous features will now be summarized. Other objects, advantages and novel features of the present disclosure will be set forth in the following detailed description of the present disclosure when considered in conjunction with the accompanying drawings, which are intended to illustrate (but not to limit) the present invention.

[0019] One or more embodiments are directed to a level-shifting buffer amplifier circuit having an input terminal and an output terminal, a first transistor, a current source, a variable resistor electrically coupled to the first transistor, wherein a resistance of the variable resistor is a function of a voltage at a control terminal, and wherein the buffer amplifier provides a constant level shift between the input terminal and the output terminal.

[0020] In some embodiments, the variable resistor may include a variable resistor. In other embodiments, the variable resistor may include a transistor (e.g., a PMOS transistor or an NMOS transistor). The one or more transistors may also include a drain terminal, a source terminal, and a gate terminal. In some aspects, the one or more transistors may have a variable resistor between their drain terminal and source terminal. In other aspects, the one or more transistors may have a gate terminal that serves as the control terminal.

[0021] One or more embodiments are directed to a level-shifting buffer amplifier that generates a level shift between an input terminal and an output terminal, the level-shifting buffer amplifier having first and second transistors, a current source, and a variable resistor electrically coupled to the first transistor, wherein a resistance of the variable resistor is a first function of a voltage at a control terminal, and wherein the level shift is a second function of the voltage at the control terminal.

[0022] Detailed description of the drawings

[0023] For a more complete understanding of the nature and advantages of the present concept, reference is made to the following detailed description of the preferred embodiments in conjunction with the accompanying drawings. In the drawings, like reference characters generally refer to like features (eg, functionally similar and / or structurally similar elements).

[0024] FIG. 1 is a schematic diagram of a source follower buffer amplifier circuit according to the prior art.

[0025] FIG. 2 is a schematic diagram of an inverted source follower buffer amplifier circuit according to the prior art.

[0026] Figure 3 is a schematic diagram of a level-shifting buffer amplifier circuit according to one or more embodiments.

[0027] Figure 4 is a schematic diagram of a level shift buffer amplifier circuit using an NMOS transistor as a variable resistor according to a first embodiment of the present invention.

[0028] Figure 5 is a schematic diagram of a first embodiment of a level shift buffer amplifier circuit using a PMOS transistor as a variable resistor according to the first embodiment of the present invention.

[0029] Figure 6 is a schematic diagram of a level shift buffer amplifier circuit according to a second embodiment of the present invention.

[0030] Figure 7 is a schematic diagram of a level shift buffer amplifier circuit according to a third embodiment of the present invention.

[0031] Figure 8 is a schematic diagram of a level shift buffer amplifier circuit according to a fourth embodiment of the present invention.

[0032] Figure 9 is a schematic diagram of a level shift buffer amplifier circuit according to a fifth embodiment of the present invention.

[0033] Figure 10 is a schematic diagram of a level shift buffer amplifier circuit according to a sixth embodiment of the present invention.

[0034] Figure 11 is a diagram of a control loop for maintaining a constant level shift in a level shift buffer amplifier circuit according to various embodiments of the present invention.

[0035] Figure 12 yes Figure 11 1 is a diagrammatic illustration of one embodiment of a combination of a differential amplifier and an integrator in a control loop shown in FIG.

[0036] Figure 13 The diagram illustrates an embodiment of an amplifier with variable resistance implemented in NMOS transistors.

[0037] Figure 14 An embodiment of an amplifier with variable resistance implemented in PMOS transistors is illustrated.

[0038] Figure 15 An embodiment including a source follower having a variable threshold transistor is illustrated.

[0039] Figure 16 An embodiment including a FSF having a variable threshold transistor is illustrated.

[0040] Figure 17 The diagram illustrates an embodiment including a feedback control loop.

[0041] Figure 18 The diagram illustrates the switching circuit portion including the differential switched capacitor integrator.

[0042] Specific instructions

[0043] The following discussion sets forth a detailed description of various concepts and embodiments related to the present invention's apparatus, which involves a constant level offset buffer amplifier circuit. It should be appreciated that the various concepts introduced above and discussed in greater detail below can be implemented in any of numerous ways, as the disclosed concepts are not limited to any particular implementation. Examples of specific implementations and applications are provided primarily for illustrative purposes.

[0044] It is apparent from equations (1) and (4) that the level offset of the prior art source follower buffer amplifier varies greatly over the PVT range. The inventors have recognized that it would be advantageous to provide control over the level offset so that it is constant (or less variable) over PVT variations, for example.

[0045] Figure 3 An exemplary buffer amplifier 30 is shown, which includes an NMOS input transistor M1, a current source I and a variable resistor R var .

[0046] Variable resistor R var An IR voltage drop is provided so that the level shift is given by the following equation:

[0047]

[0048] Where V GS1 is the gate-source voltage of M1, It is the ratio of the width (W) to the length (L) of M1.

[0049] From equation (5), we can see that adjusting R var The value of V T and A change of θ without changing the bias current I will be possible.

[0050] In some applications, adjusting R var It may be advantageous to have both and I to have greater flexibility in adjustments.

[0051] Figure 4The diagram illustrates a level shift buffer amplifier according to one or more embodiments, wherein the variable resistor R of the previous embodiment is replaced by an NMOS transistor MR1. var We note that in this embodiment and example, as well as in other embodiments and examples of the present invention, the replacement or substitution of a resistor (e.g., a variable resistor) with a transistor is intended to be broad, as will be understood by those skilled in the art. Thus, descriptions of a resistor or variable resistor including such other components (e.g., an NMOS transistor or a PMOS transistor) are intended to convey the general ability to insert or substitute one such component or variable resistor with another in a manner best suited for a given implementation.

[0052] The NMOS transistor MR1 is biased in the triode region so that its on-resistance R ON From R var The role of R var The control voltage V applied to the gate of MR1 CONT control.

[0053]

[0054] in is the ratio of W to L of MR1, V CONT is the control voltage applied to the gate of MR1, and V S is the voltage at the source of MR1 (which is the output voltage V O ).

[0055] Compared with the prior art LSBA of Figure 1, Figure 3 and Figure 4 The variable resistor implementation can result in higher output resistance and lower voltage gain. var Connect a resistor in series to the source of M1, increasing the output resistance to:

[0056]

[0057] Since according to equation (6), R var is a function of the output voltage, so it can be shown that the incremental gain is further reduced from equation (2) times, giving:

[0058]

[0059] Where V GSR1 is the gate-source voltage of MR1.

[0060] Figure 5 The diagram illustrates a level shift buffer amplifier according to one or more embodiments, wherein the variable resistor R varThe PMOS transistor MR2 is replaced by the PMOS transistor MR2. The PMOS transistor MR2 is biased in the triode region so that its on-resistance R ON From R var The role of R var By the control voltage V CONT control:

[0061]

[0062] in is the ratio of W to L of MR2, V CONT is the control voltage applied to the gate of MR2, and V S is the voltage at the source of MR2.

[0063] Figure 3 The output resistance of the embodiment of the present invention is Figure 5 The variable resistance in is given by the following equation:

[0064]

[0065] However, in this case, the incremental gain increases Times:

[0066]

[0067] Where V GSR2 is the gate-source voltage of MR2.

[0068] Due to Figure 4 Compared to the LSBA circuit using a variable resistor, the gain is closer to 1, so Figure 5 The variable resistor implementation in may be a preferred implementation for some applications.

[0069] Figure 6 Another embodiment of the present invention is shown, based on the FSF in FIG. 2 , which further includes a variable resistor R var The level shift is given by the following equation

[0070]

[0071] Where V GS1 is the gate-source voltage of M1, It is the ratio of W to L of M1.

[0072] In addition, the variable resistor R var You can Figure 7 In the NMOS transistor or Figure 8 is replaced or implemented by a PMOS transistor, where the resistance R is given by equations (6) and (9), respectively. var .

[0073] In some respects, Figure 3-Figure 5 Compared with the implementation in Figure 6-Figure 8 The implementation in eliminates or reduces the effect of load current, and the output resistance is also reduced due to the negative feedback provided by M2. The output resistance is given by the following equation:

[0074]

[0075] where g m1 and g m2 are the transconductances of M1 and M2, respectively, and r o1 is the output resistance of M1. It is given by the following equation Figure 7 Incremental gain of LSBA

[0076]

[0077] Where V GSR1 is the gate-source voltage of MR1.

[0078] Given by the following equation Figure 8 Incremental gain of LSBA

[0079]

[0080] Where V GSR2 is the gate-source voltage of MR2.

[0081] Figure 8 The incremental gain of the circuit is higher than Figure 7 The incremental gain of the circuit is 0.001 V and may be preferred for some applications.

[0082] Figure 9 The figure illustrates another embodiment of the present invention. It includes a first source follower M1 and a second source follower M2 and a series variable resistor R VAR Preferably, M1 and M2 have two different threshold voltages so that V T1 >V T2 , where V T1 is the threshold voltage of M1, and V T2 is the threshold voltage of M2. In one embodiment, M1 can be a standard V T device, and M2 can be a low V T In another embodiment, M1 can be a high V T device, and M2 can be a standard V T In yet another embodiment, M1 can be a high V T device, and M2 can be a low V T device. With R VARWhen R VAR When it is very small, R VAR Voltage drop IR within the range var In this case, most of the current I+I O flows through M2 because V T2 In this case, the gate-source voltage V GS2 Determine the level offset:

[0083]

[0084] Where V GS2 is the gate-source voltage of M2, and It is the ratio of W to L of M2.

[0085] By M2 g m2 Determine the output resistance:

[0086]

[0087] On the other hand, if R var Very large, most of the bias current I is directed to M1, and M2 is close to being turned off. In this case, the gate-source voltage V GS1 Determine the level offset:

[0088]

[0089] Where V GS1 is the gate-source voltage of M1, is the ratio of W to L of M1. m1 Determine the output resistance:

[0090]

[0091] By varying R between these two extremes var , the level offset can vary continuously between the values ​​given in equations (14) and (16). Therefore, the range of the level offset is given by

[0092]

[0093] In addition, you can Figure 10 As shown in FIG, NMOS transistors or Figure 11 The variable resistor R is realized by a PMOS transistor as shown in var .

[0094] The adjustability is given by the following equation. Adjustability is the difference between the upper and lower limits of the level offset.

[0095]

[0096] If M1 and M2 are of equal size, the adjustability is reduced to the difference between the threshold voltages:

[0097] ΔV LS ≈V T1 -V T2 (twenty two).

[0098] However, gives a wider range of adjustability. In addition, if transistors with different threshold voltages are not available, V T1 and V T2 Equal, unequal sizes between M1 and M2 give the adjustability of the following equation

[0099]

[0100] Figure 12 The figure illustrates another embodiment of the present invention. It includes a FSF having a first source follower M1 and a second source follower M2 and a series variable resistor R VAR Preferably, M1 and M2 have two different threshold voltages so that V T1 >V T2 , where V T1 is the threshold voltage of M1, and V T2 is the threshold voltage of M2. In one embodiment, M1 can be a standard V T device, and M2 can be a low V T In another embodiment, M1 can be a high V T device, and M2 can be a standard V T In yet another embodiment, M1 can be a high V T device, and M2 can be a low V T device. With R VAR When R VAR When it is very small, R VAR Voltage drop IR within the range var In this case, most of the current I flows through M2, and M1 is close to being disconnected. In this case, the gate-source voltage V GS2 Determine the level offset:

[0101]

[0102] Where V GS2 is the gate-source voltage of M2, is the ratio of W to L of M2. As in FSF, the output resistance is significantly reduced by the negative feedback provided by M3. m2 ro1 times and is given by the following equation:

[0103]

[0104] On the other hand, if R var Very large, most of the bias current I is directed to M1, and M2 is approximately disconnected. In this case, the gate-source voltage V GS1 Determine the level offset:

[0105]

[0106] Where V GS1 is the gate-source voltage of M1, is the ratio of W to L of M1. The output resistance is given by the following equation:

[0107]

[0108] By varying R between these two extremes var , the level offset can vary continuously between the values ​​given in equations (14) and (16). Therefore, the range of the level offset is given by

[0109]

[0110] In addition, you can Figure 13 and Figure 14 As shown in FIG, a variable resistor R is realized by an NMOS transistor or a PMOS transistor. var .

[0111] The adjustability is given by the following equation. Adjustability is the difference between the upper and lower limits of the level offset.

[0112]

[0113] If M1 and M2 are of equal size, the adjustability is reduced to the difference between the threshold voltages:

[0114] ΔV LS =V T1 -V T2 (30)

[0115] However, gives a wider range of adjustability. In addition, if transistors with different threshold voltages are not available, V T1 and V T2 Equal, unequal sizes between M1 and M2 give the adjustability of the following equation

[0116]

[0117] Figure 15 The figure illustrates another embodiment of the present invention. It includes a source follower with a variable threshold transistor M1. By changing the control voltage V cont To control the threshold voltage of M1. In one embodiment, the variable threshold transistor M1 is implemented in fully depleted silicon-on-insulator (FDSOI) technology. A control voltage V is applied to the back gate voltage of the transistor. cont For this embodiment, FDSOI technology is advantageous over bulk CMOS technology because the threshold voltage can be varied by large amounts (up to several hundred millivolts).

[0118] Figure 16 The figure illustrates another embodiment of the present invention. It includes a FSF with a variable threshold transistor M1. By changing the control voltage V cont To control the threshold voltage of M1. In one embodiment, the variable threshold transistor M1 is implemented in fully depleted silicon-on-insulator (FDSOI) technology. A control voltage V is applied to the back gate voltage of the transistor. cont .

[0119] Figure 17 The figure illustrates a feedback control loop for maintaining a constant level shift within the PVT variation range. Differential circuit 500 generates a level shift V LS With reference voltage V REF The difference between the reference voltage V REF Preferably independent of PVT variations. The reference voltage V may be generated, for example, by a bandgap reference source REF The difference V is converted by integrator 502. LS -V REF In various embodiments of the present invention, the output of the integrator drives the control voltage V cont In one embodiment, Figure 18 The differential switched capacitor integrator shown in FIG implements the differential circuit 500 and the integrator 502. Its operation is controlled by two non-overlapping clock phases Φ1 and Φ2. When Φ1 is "high", switches S1 and S2 are 'on', and S3 and S4 are 'off'. During this phase, the sampling capacitor C S The input voltage and output voltage of the buffer are sampled. The difference between the input voltage and output voltage of the buffer is equal to V LS When Φ2 is “high”, switches S3 and S4 are ‘on’, and S1 and S2 are ‘off’, thus S The reference voltage V REF It can be shown that the resulting change in the integrator output voltage ΔV is given by the following equation o

[0120] ΔVo =V IN -V OUT =V LS -V REF (32)

[0121] If V LS Greater than V REF , the integrator output voltage keeps increasing by ΔV after each clock cycle o , because ΔV o is positive. This increases the control voltage V cont In embodiments where the variable resistor is implemented by an NMOS transistor, this reduces R var , and thus lowering V LS Therefore, this negative feedback reduces V LS , making V LS =V REF In other embodiments, if V LS Greater than V REF , then the control voltage needs to be reduced. In these embodiments, it is necessary to reverse the polarity of the integrator output voltage. This can be achieved, for example, by using an inverting amplifier coupled to the integrator output or by using a fully differential integrator.

[0122] Although various inventive embodiments have been described and illustrated herein, those of ordinary skill in the art will readily envision various other means and / or structures for performing the functions and / or obtaining the results described herein and / or one or more of the advantages described herein, and each of such variations and / or modifications is considered to be within the scope of the inventive embodiments described herein. More generally, those skilled in the art will readily recognize that all parameters, dimensions, materials, and configurations described herein are intended to be exemplary, and that the actual parameters, dimensions, materials, and / or configurations will depend on the specific application or applications in which the inventive teachings are used. Those skilled in the art will recognize or be able to ascertain using no more than routine experimentation many equivalents to the specific inventive embodiments described herein. As a specific example, it may be desirable to Figure 3-Figure 16In the embodiment of the present invention, PMOS input transistors are used in the amplifier circuit in place of NMOS input transistors as shown in the exemplary figures. Those skilled in the art will recognize such a "flip" configuration. Therefore, it will be understood that the foregoing embodiments are presented as examples only, and within the scope of the appended claims and their equivalents, inventive embodiments may be implemented in other ways than those specifically described. The inventive embodiments of the present disclosure are directed to each individual feature, system, article, material, complete set of equipment and / or method described herein. In addition, any reasonable combination of two or more such features, systems, articles, materials, complete sets of equipment and / or methods (if such features, systems, articles, materials, complete sets of equipment and / or methods are not mutually inconsistent) is included within the scope of the invention of the present disclosure.

[0123] Furthermore, the invention described herein can be embodied as a method. The actions performed as part of a method can be ordered in any suitable manner. Thus, even if actions are shown as sequential actions in an illustrative embodiment, embodiments can be constructed in which the actions are performed in an order different from that illustrated (which may include performing some actions simultaneously).

[0124] The present invention should not be construed as limited to the specific embodiments described above, but rather should be construed to cover all aspects of the invention as fairly set forth in the appended claims. Various modifications, equivalent processes, and numerous structures to which the present invention may be applied will be apparent to those skilled in the art to which the present invention is directed after reviewing this disclosure. The claims are intended to cover such modifications and equivalents.

Claims

1. A level-shift buffer amplifier, comprising: Input terminals and output terminals; a first transistor; Current source; a variable resistor electrically coupled to the first transistor, wherein a resistance of the variable resistor is a function of a voltage at a control terminal; as well as a second transistor electrically coupled to the first transistor and the current source so as to provide negative feedback, wherein the buffer amplifier provides a constant level shift between the input terminal and the output terminal.

2. The buffer amplifier of claim 1, wherein the first transistor is an NMOS transistor.

3. The buffer amplifier of claim 1, wherein the first transistor is a PMOS transistor.

4. The buffer amplifier of claim 2, wherein: The variable resistor includes a second NMOS transistor having a variable resistance between a drain terminal and a source terminal; and The control terminal includes a gate terminal of the second NMOS transistor.

5. The buffer amplifier of claim 2, wherein: The variable resistor includes a PMOS transistor having a variable resistance between a drain terminal and a source terminal; and The control terminal includes a gate terminal of the PMOS transistor.

6. The buffer amplifier of claim 3, wherein: The variable resistor includes an NMOS transistor having a variable resistance between a drain terminal and a source terminal; and The control terminal includes a gate terminal of the NMOS transistor.

7. The buffer amplifier of claim 3, wherein: The variable resistor includes a second PMOS transistor having a variable resistance between a drain terminal and a source terminal; and The control terminal includes a gate terminal of the second PMOS transistor.

8. The buffer amplifier of claim 1 , wherein: The variable resistor includes a third transistor having a variable resistance between a drain terminal and a source terminal; and The control terminal includes a gate terminal of the third transistor.

9. The buffer amplifier of claim 8, wherein the third transistor comprises a PMOS transistor biased in a triode operating region.

10. The buffer amplifier of claim 9, wherein the third transistor comprises an NMOS transistor biased in a triode operating region.

11. A level shift buffer amplifier for generating a level shift between an input terminal and an output terminal, the level shift buffer amplifier comprising: Current source; a first transistor electrically coupled to the input terminal; a second transistor electrically coupled to the input terminal and the current source; as well as a variable resistor electrically coupled to the first transistor, wherein a resistance of the variable resistor is a first function of a voltage at a control terminal; Wherein the level shift is a second function of the voltage at the control terminal. 12 . The level shift buffer amplifier of claim 11 , wherein a threshold voltage of the first transistor is lower than a threshold voltage of the second transistor.

13. The level-shift buffer amplifier of claim 12, further comprising a third transistor electrically coupled to the first transistor and the second transistor to provide negative feedback.

14. The buffer amplifier of claim 13, wherein the first transistor is an NMOS transistor.

15. The buffer amplifier of claim 13, wherein the first transistor is a PMOS transistor.

16. A level-shift buffer amplifier, comprising: Input terminals and output terminals; a first transistor having a back gate terminal; Current source; as well as a second transistor electrically coupled to the first transistor and the current source so as to provide negative feedback, The first transistor is a fully depleted silicon-on-insulator (FD-SOI) transistor, and a control voltage is applied to the backgate terminal to provide a constant level shift between the input terminal and the output terminal.

17. The buffer amplifier of claim 16, wherein the first transistor is an NMOS transistor.

18. The buffer amplifier of claim 16, wherein the first transistor is a PMOS transistor.

19. A constant level shift circuit, comprising: a buffer amplifier having an input terminal, an output terminal, and a control terminal, wherein a level shift between the input terminal and the output terminal is a function of a voltage applied to the control terminal; a reference source, the reference source generating a reference voltage; a differential circuit electrically coupled to the reference source to generate a voltage difference between the level shift and the reference voltage; an integrator, wherein the integrator integrates the voltage difference to generate an output voltage; The output voltage is electrically coupled to the control terminal so that the level shift remains constant over process, supply voltage variations, and temperature variations.

20. The constant level shift circuit of claim 19, wherein the differential circuit comprises a first capacitor electrically coupled to the input terminal, the output terminal, and the reference source.

21. The constant level shift circuit of claim 20, wherein the integrator comprises an operational amplifier and a second capacitor electrically coupled to the operational amplifier.

22. The constant level offset circuit of claim 21, further comprising a plurality of switches electrically coupled to the first capacitor.

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