Programming operation execution during programming operation suspension

Abstract

This application relates to programming operation execution during programming operation suspension. A memory device includes a memory array and control logic operably coupled with the memory array. The control logic receives a first request from a requestor to perform a first memory access operation on the memory array and initiates the first memory access operation on the memory array. Prior to completion of the first memory access operation, the control logic receives a second request from the requestor to suspend execution of the first memory access operation and causes the memory device to enter a suspend state, where the first memory access operation is suspended during the suspend state. The control logic further receives a third request from the requestor to perform a dynamic single level cell (SLC) programming operation on the memory array while the memory device is in the suspend state and initiates the dynamic SLC programming operation on the memory array.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to a memory subsystem, and more specifically, to the execution of programming operations in a memory subsystem during a programming operation pause. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] In one aspect, this application relates to a memory device comprising: a memory array; and control logic operatively coupled to the memory array to perform operations including: receiving from a requesting party a first request to perform a first memory access operation on the memory array; initiating the first memory access operation on the memory array; receiving from the requesting party a second request to suspend the execution of the first memory access operation before completing the first memory access operation; putting the memory device into a suspended state, wherein the first memory access operation is suspended during the suspended state; receiving from the requesting party a third request to perform a dynamic single-level cell (SLC) programming operation on the memory array while the memory device is in the suspended state; and initiating the dynamic SLC programming operation on the memory array.

[0004] In another aspect, this application relates to a method comprising: receiving from a requesting party a first request to perform a first memory access operation on a memory device; initiating the first memory access operation on the memory device; receiving from the requesting party a second request to suspend the execution of the first memory access operation before completing the first memory access operation; putting the memory device into a suspended state, wherein the first memory access operation is suspended during the suspended state; receiving from the requesting party a third request to perform a dynamic single-level cell (SLC) programming operation on the memory device while the memory device is in the suspended state; and initiating the dynamic SLC programming operation on the memory device.

[0005] In another aspect, this application relates to a method comprising: sending a first request to a memory device including control logic and a memory array to perform a first memory access operation on the memory array; before completing the first memory access operation, sending a second request to the memory device to pause the execution of the first memory access operation, the second request causing the memory device to enter a paused state, wherein the first memory access operation is paused during the paused state; and sending a third request to the memory device to perform a dynamic single-level cell (SLC) programming operation on the memory device while the memory device is in the paused state. Attached Figure Description

[0006] This disclosure will be more fully understood in light of the detailed description provided below and the accompanying drawings of various embodiments thereof.

[0007] Figure 1 This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 2 This is a block diagram illustrating a memory subsystem that performs programming operations during a programming operation pause according to some embodiments of the present disclosure.

[0009] Figure 3 This is a flowchart of an instance controller method for executing programming operations during a programming operation pause, according to some embodiments of the present disclosure.

[0010] Figure 4 This is a flowchart of an instance memory device method for performing programming operations during a programming operation pause, according to some embodiments of the present disclosure.

[0011] Figure 5 This is a block diagram illustrating command state machine operations performed during a programming operation pause in a memory subsystem according to some embodiments of the present disclosure.

[0012] Figure 6 This is a block diagram of an example computer system in which embodiments of this disclosure may be operated. Detailed Implementation

[0013] This disclosure relates to the execution of programming operations in a memory subsystem during a programming operation pause. The memory subsystem may be a storage device, a memory module, or a mixture of both. The following is combined with… Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that includes one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request to retrieve data from the memory subsystem.

[0014] The memory subsystem may include high-density non-volatile memory devices, where data retention is required when no power is supplied to the memory devices. An example of a non-volatile memory device is a NAND flash memory device. (The following section combines...) Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die may consist of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and has various logic states associated with the number of bits stored. Logic states may be represented by binary values ​​(e.g., “0” and “1”) or combinations of such values.

[0015] Memory devices can consist of bits arranged in a two-dimensional or three-dimensional grid. Memory cells are etched onto a silicon wafer in an array of columns (hereinafter also referred to as bit lines) and rows (hereinafter also referred to as word lines). A word line can refer to one or more rows of memory cells in a memory device, which are used in conjunction with one or more bit lines to generate an address for each of the memory cells. The intersection of bit lines and word lines constitutes the address of a memory cell. Hereinafter, a block refers to a cell of a memory device used to store data and may include groups of memory cells, groups of word lines, word lines, or individual memory cells. One or more blocks can be grouped together to form planes of a memory device to allow concurrent operation on each plane. A memory device may include circuitry that performs concurrent memory page accesses on two or more memory planes. For example, a memory device may include multiple access line driver circuitry and power supply circuitry that can be shared by planes of the memory device to facilitate concurrent access to pages in two or more memory planes containing different page types. For ease of description, these circuits are often referred to as independent plane driver circuitry. Depending on the memory architecture employed, data can be stored across memory planes (i.e., in stripes). Therefore, a request to read a data segment (e.g., corresponding to one or more data addresses) can trigger two or more read operations performed on the memory plane of the memory device.

[0016] In some memory subsystems, it is common to receive a request to perform a memory access operation, such as programming data from the host system, and then subsequently receive a request to perform another memory access operation, such as immediately performing a read operation on the same data from the host system, even before the programming operation is complete. While the underlying memory device of the memory subsystem (e.g., NAND flash memory) is being programmed, conventional memory subsystems sometimes store the data being programmed in controller memory (e.g., dynamic random access memory (DRAM)) and then flush the controller memory when the programming operation is complete. A reasonably sized controller memory can hold the programmed data as long as the programming time (i.e., the time associated with performing the programming operation on the memory device) is relatively short. However, when the memory device uses certain types of memory cells, such as three-level cell (TLC) or four-level cell (QLC), the programming time can increase significantly. Therefore, the command latency associated with subsequently received memory access commands increases significantly. If a subsequent request to perform a read operation is received while the programming operation is still in progress, some memory subsystems must wait until the programming operation is complete before performing the read operation on the memory device. This can result in significant delays when responding to requests from the host system.

[0017] To reduce latency in mixed workloads (e.g., combinations of programming and reading operations, such as a programming operation immediately followed by a reading operation), some memory subsystems utilize programming pause protocols to allow subsequently received memory access commands (e.g., read operations) to access the memory device page on which programming is currently being performed. Programming pause protocols can temporarily pause programming operations on a memory device to allow access to the memory array. Specifically, when a programming operation (e.g., a TLC programming operation) is in progress, and the memory subsystem receives a request to perform a memory access operation on data stored in a memory device page, the pause manager of the memory subsystem controller can issue a specific programming pause command that puts the memory device into a paused state. Some memory devices and their associated pause protocols only allow a limited number of types of commands (e.g., single-plane or multi-plane read operations) to be executed while the memory device is in a paused state. However, some memory devices support different types of programming operations, such as dynamic single-level cell (SLC) programming operations, which require low memory endurance and have significantly shorter programming times than, for example, TLC programming operations. However, many pause protocols do not allow dynamic SLC programming operations to be performed while the memory device is in a paused state. Therefore, despite the shorter programming time, it is necessary to wait for dynamic SLC programming operations to be performed until any pending memory access operations are completed. This results in increased latency in responding to requests from the host system and adversely affects the quality of service provided by the memory subsystem.

[0018] Various aspects of this disclosure address the above and other shortcomings by allowing programming operations to be executed during a programming operation pause in the memory subsystem. In one embodiment, the control logic of the memory device receives a first request from a requesting party, such as a memory subsystem controller or a host system, to perform a first memory access operation on the memory array of the memory device, and initiates the first memory access operation on the memory array. In one embodiment, the first memory access operation is a multi-level cell (MLC) programming operation, such as a TLC programming operation or a QLC programming operation. Before completing the first memory access operation, the control logic receives a second request from the requesting party to pause the execution of the first memory access operation and puts the memory device into a paused state, during which the first memory access operation is paused. The control logic further receives a third request from the requesting party to perform a dynamic single-level cell (SLC) programming operation on the memory array while the memory device is in the paused state, and initiates a dynamic SLC programming operation on the memory array. The first memory access operation can then be resumed after the dynamic SLC programming operation is completed.

[0019] The advantages of this approach include, but are not limited to, improved performance in the memory subsystem. By means of the method described herein, the latency associated with subsequently received memory access commands (e.g., dynamic SLC programming) that require shorter operation times (e.g., programming time) to complete is reduced because the execution of these operations does not require waiting for ongoing memory access operations (e.g., MLC programming operations) to complete in a shorter operation time (e.g., programming time). Therefore, the overall quality of service level of the memory subsystem is improved because the minimum performance level required for processing memory access operations can be maintained.

[0020] Figure 1 This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of the like.

[0021] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital storage (SD) drives, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0022] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), Internet of Things (IoT) enabled device, embedded computer (e.g., computer included in a vehicle, industrial equipment or networked commercial device), or such computing device including memory and processing device.

[0023] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to…” or “coupled with…” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediate component), whether wired or wireless, and includes connections such as electrical, optical, magnetic, etc.

[0024] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110, for example, to write data to memory subsystem 110 and read data from memory subsystem 110.

[0025] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)). The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., a PCIe bus), host system 120 can further utilize an NVM Fast (NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for passing control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0026] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0027] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND type flash memory and in-place write memory, such as three-dimensional cross-point (“3D cross-point”) memory devices, which are cross-point arrays of non-volatile memory cells. The cross-point array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in volume resistance. Furthermore, compared to many flash-based memories, cross-point non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0028] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination of such arrays. In some embodiments, a particular memory device may include an SLC portion of memory cells, and MLC, TLC, QLC, or PLC portions. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical cells of the memory device used for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0029] Although non-volatile memory components such as 3D cross-point non-volatile memory cell arrays and NAND-type flash memories (e.g., 2D NAND, 3D NAND) are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0030] The memory subsystem controller 115 (or, for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, erasing data, and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0031] The memory subsystem controller 115 may be a processing device that includes one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines for controlling the operation of the memory subsystem 110 (including handling communication between the memory subsystem 110 and the host system 120).

[0032] In some embodiments, local memory 119 may include memory registers storing memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 in the present disclosure is described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0033] Typically, the memory subsystem controller 115 receives commands or operations from the host system 120 and translates these commands or operations into instructions or appropriate commands to perform the desired access to the memory device 130. The memory subsystem controller 115 may handle other operations such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry translates commands received from the host system into instructions for accessing the memory device 130 and translates responses associated with the memory device 130 into information for the host system 120.

[0034] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include caches or buffers (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0035] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device that includes the original memory device 130 having on-die control logic (e.g., local media controller 135) and a controller (e.g., memory subsystem controller 115) within the same memory device package for media management. An example of a managed memory device is a managed NAND (MNAND) device.

[0036] In one embodiment, memory subsystem 110 includes a memory interface component 113 that includes a pause manager 114. The memory interface component 113 is responsible for handling interactions between the memory subsystem controller 115 and memory devices (e.g., memory device 130) of the memory subsystem 110. For example, the memory interface component 113 may send memory access commands corresponding to requests received from host system 120 to memory device 130, such as programming commands, read commands, or other commands. Additionally, the memory interface component 113 may receive data from memory device 130, such as data retrieved in response to confirmation of a read command or successful execution of a programming command. In some instances, the memory subsystem controller 115 includes at least a portion of the pause manager 114. For example, the memory subsystem controller 115 may include a processor 117 (processing means) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, the memory interface component 113 is part of host system 110, an application, or an operating system. In one embodiment, memory interface 113 includes a pause manager 114 and other sub-components. The pause manager 114 can direct specific commands, including pause and resume commands, to memory device 130 to manage conflicts between different memory access operations. A conflict may occur when a request to perform a second memory access operation on a cell of the same data block, subblock, and word line is received, even while a first memory access operation is being performed on a cell of the same data block, subblock, and word line in memory device 130. In response to this conflict, the pause manager 114 can determine how to proceed. In one embodiment, the pause manager 114 can pause a first memory access operation by issuing a specified pause command to memory device 130 and then issuing a request to perform the second memory access operation while pausing the first memory access operation. In one embodiment, the second memory access operation may include a dynamic SLC programming operation, which has a substantially shorter programming time than an MLC programming operation. Further details regarding the operation of the pause manager 114 are described below.

[0037] In one embodiment, memory device 130 includes a pause agent 134 configured to perform a corresponding memory access operation in response to receiving a memory access command from pause manager 114. In some embodiments, local media controller 135 includes at least a portion of pause agent 134 and is configured to perform the functionality described herein. In some embodiments, pause agent 134 is implemented on memory device 130 using firmware, hardware components, or a combination thereof. In one embodiment, pause agent 134 receives a request from a requesting party, such as pause manager 114, to pause an ongoing memory access operation (e.g., an MLC programming operation) with a long operation time. In response, pause agent 134 may cause memory device 130 to enter a pause state, wherein a first memory access operation is paused during the pause state. While memory device 130 is in a pause state, pause agent may further receive one or more requests to perform additional memory access operations (e.g., dynamic SLC programming operations). The pause agent 134 can initiate a dynamic SLC programming operation, notify the pause manager 114 when the dynamic SLC programming operation is complete, and the pause manager 114 can send a request to resume paused memory access operations. Further details regarding the operation of the pause agent 134 are described below.

[0038] Figure 2 This is a block diagram 200 illustrating a memory subsystem for performing programming operations during a programming operation pause, according to some embodiments of the present disclosure. In one embodiment, a memory interface 113 is operatively coupled to a memory device 130. In one embodiment, the memory device 130 includes a page cache 240 and a memory array 250. The memory array 250 may comprise an array of memory cells formed at the intersection of word lines and bit lines (not shown), for example, word lines 252. In one embodiment, the memory cells are grouped into blocks, which may be further divided into sub-blocks, wherein a given word line of word line 252 is shared, for example, across multiple sub-blocks 254a, 254b, 254c, 254d. In one embodiment, each sub-block corresponds to a separate plane in the memory array 250. A group of memory cells associated with a word line within a sub-block is called a physical page. Each physical page in one of the sub-blocks may contain multiple page types. For example, a physical page formed by a single-level cell (SLC) has a single page type called a lower logical page (LP). Multilevel cell (MLC) physical page types may include LP and upper logical page (UP), TLC physical page types are LP, UP, and additional logical page (XP), and QLC physical page types are LP, UP, XP, and top logical page (TP). For example, a physical page formed by memory cells of the QLC memory type may have a total of four logical pages, where each logical page may store data different from the data stored in other logical pages associated with that physical page.

[0039] Depending on the programming scheme used, each logical page of the memory cell can be programmed in a separate programming pass, or multiple logical pages can be programmed together. For example, in a QLC physical page, LP can be programmed in one pass, and UP, XP, and TP can be programmed in a second pass. Other programming schemes are possible. However, in this example, before UP, XP, and TP are programmed in the second pass, data from LP is first read from the physical page in memory array 250 and can be stored in page cache 240 of memory device 130. Page cache 240 is a buffer for temporarily storing data being read from or written to memory array 250 of memory device 130, and may include cache register 242 and one or more data registers 244-246. For a read operation, data is read from memory array 250 into one of data registers 244-246, and then into cache register 242. Memory interface 113 can then read data from cache register 242. For programming operations, memory interface 113 writes data to cache register 242, which is then passed to one of data registers 244-246 and finally programmed into memory array 250. If the programming operation involves multiple pages (e.g., UP, XP, and TP), each page may have a dedicated data register to hold the data for that page.

[0040] In one embodiment, while a memory access operation is currently in progress, the pause manager 114 may send a request to pause the memory access operation (e.g., a pause command) to the memory device 130. The pause command may be received by the pause agent 134, which may put the memory device 130 into a paused state. In the paused state, the ongoing memory access operation performed on the memory array 250 (e.g., on word line 252 of the memory array 250) is paused. In one embodiment, the pause agent 134 stores progress information associated with the paused memory access operation in the page cache 240. For example, the pause agent 134 may, in response to receiving a pause command, store data already programmed into the memory array 250 in the page cache 240 (e.g., in one of data registers 244-246), where this data can be used to resume the paused memory access operation later.

[0041] Once a memory access operation is paused, the pause manager 114 can send a request to perform another memory access operation (e.g., a dynamic SLC programming operation) on the memory array 250 while the memory device 130 is in a paused state. The pause agent 134 can receive the request and initiate the dynamic SLC programming operation on the memory array 250. In one embodiment, two or more memory access operations can be performed while the original memory access operation is paused. After the dynamic SLC programming operation (and any other operation) is completed, the pause agent 134 can provide the requesting party with a notification indicating that the dynamic SLC programming operation has been completed. For example, the pause agent 134 can set a ready / busy signal to a specific level (e.g., a high voltage representing a logic "1") to indicate that the memory device 130 is ready to receive subsequent commands. In response, the pause manager can send a request to resume the previously paused memory access operation (e.g., a resume command) to the memory device 130. The pause agent 134 can receive the request to exit the paused state and resume the original memory access operation on the memory array 250 using progress information from the page cache 240. For example, pause agent 134 can read data stored in page cache 240, which was previously written to memory array 250, and compare this data with data in a resume command to determine the point at which memory access operations were interrupted when paused. Therefore, pause agent 134 can resume programming the data used for memory access operations into memory array 250 from that point.

[0042] Figure 3 This is a flowchart of an instance controller method for executing programming operations during a programming operation pause, according to some embodiments of the present disclosure. Method 300 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 300 is performed by… Figure 1 and Figure 2 The pause manager 114 executes. Although shown in a specific sequence or order, the order of processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0043] At operation 305, a command / request is sent. For example, processing logic (e.g., pause manager 114) may send a first request to a memory device, such as memory device 130, to perform a first memory access operation on the memory array (e.g., memory array 250) of the memory device. In one embodiment, the first memory access operation includes at least one of a programming operation, a read operation, or an erase operation. For example, the first memory access operation may include an MLC programming operation, such as a TLC programming operation or a QLC programming operation. In one embodiment, pause manager 114 sends a request, such as a first memory access command, to memory device 130 to perform the first memory access operation, which is received by pause agent 134. In one embodiment, pause manager 114 sends the request in response to a request received from, for example, another component of host system 120.

[0044] At operation 310, a command / request is sent. For example, before completing the first memory access operation (i.e., while memory device 130 is still performing the first memory access operation), the processing logic may send a second request to memory device 130 to pause the execution of the first memory access operation. In one embodiment, pause manager 114 sends a request to memory device 130 to pause the first memory access operation, such as a pause command, which is received by pause agent 134. In response, pause agent 134 may cause memory device 130 to enter a paused state, wherein the first memory access operation is paused during the paused state, such as relative to... Figure 4 To describe in more detail.

[0045] At operation 315, a command / request is sent. For example, the processing logic may send a third request to the memory device 130 to perform a second memory access operation on the memory array 250 of the memory device 130. In one embodiment, the second memory access operation includes at least one of a programming operation, a read operation, or an erase operation. For example, the second memory access operation may include a dynamic SLC programming operation. A dynamic SLC programming operation may have a shorter programming time than an MLC programming operation and a shorter programming time than a static SLC programming operation. That is, a dynamic SLC programming operation may complete faster than those other operations. In addition, a different fine-tuning setting of the memory device is used to perform the dynamic SLC programming operation compared to those fine-tuning settings used for the MLC programming operation or the static SLC programming operation. Furthermore, the dynamic SLC programming operation is performed relative to data with a lower priority than the data associated with the MLC programming operation or the static SLC programming operation. For example, when more critical data (i.e., data with a higher priority level) is to be written to the memory device 130, the pause manager 114 may issue a static SLC programming operation. However, when a small amount of critical data is to be written to memory device 130, pause manager 114 may issue dynamic SLC programming operations. In one embodiment, when memory device 130 is in a paused state, pause manager 114 sends a request to memory device 130 to perform a second memory access operation, such as a second memory access command, which is received by pause agent 134. In other embodiments, two or more additional memory access operations may be performed while memory device 130 is in a paused state.

[0046] At operation 320, a notification is received. For example, the processing logic may receive a notification from memory device 130 indicating that a second memory access operation (e.g., a dynamic SLC programming operation) has been completed. In one embodiment, memory device 130 outputs a ready / busy signal indicating the state of memory device 130. For example, when memory device 130 is ready (i.e., not currently performing a memory access operation), the signal may have a first voltage level (e.g., a high voltage level indicating logic "1"), and when memory device 130 is busy (i.e., currently performing a memory access operation), the signal may have a second voltage level (e.g., a low voltage level indicating logic "0"). In one embodiment, after the second memory access operation is completed, pause agent 134 may set the value of the ready / busy signal to the corresponding level, which is received by pause manager 114. Pause manager 114 may decode the signal level to determine the state of memory device 130.

[0047] At operation 325, a command / request is sent. For example, the processing logic may send a fourth request to memory device 130 to resume a first memory access operation to memory array 250 of memory device 130 (e.g., a previously suspended MLC programming operation). In one embodiment, pause manager 114 sends a request to memory device 130 to resume the first memory access operation, such as a resume command, which is received by pause agent 134. In one embodiment, the resume command causes the pause manager to resume the first memory access operation at the point where the first memory access operation was interrupted, such as relative to... Figure 4 To describe in more detail.

[0048] Figure 4 This is a flowchart of an instance memory device method for performing programming operations during a programming operation pause, according to some embodiments of the present disclosure. Method 400 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 400 is performed by… Figure 1 and Figure 2 The execution of agent 134 is paused. Although shown in a specific sequence or order, the order of processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0049] At operation 405, a command / request is received. For example, processing logic (e.g., pause agent 134) may receive a first request from a requesting party, such as memory subsystem controller 115, to perform a first memory access operation on the memory array (e.g., memory array 250) of a memory device (e.g., memory device 130). In one embodiment, the first memory access operation includes at least one of a programming operation, a read operation, or an erase operation. For example, the first memory access operation may include an MLC programming operation, such as a TLC programming operation or a QLC programming operation. In one embodiment, pause manager 114 sends a request, such as a first memory access command, to memory device 130 to perform the first memory access operation, which is received by pause agent 134.

[0050] At operation 410, a memory access operation is initiated. For example, processing logic may initiate a first memory access operation on memory array 250. In one embodiment, pause agent 134 may apply one or more programming pulses to the corresponding word line (e.g., word line 252) of memory array 250 to store data associated with the first memory access operation in memory cells of memory array 250. Since the first memory access operation may include an MLC programming operation, multiple pages may be programmed in one or more programming passes, such as LP, UP, XP, and TP.

[0051] At operation 415, a command / request is received. For example, before the first memory access operation is completed (i.e., while memory device 130 is still performing the first memory access operation), the processing logic may receive a second request from the requesting party to suspend the execution of the first memory access operation. In one embodiment, the pause manager 114 sends a request to the memory device 130 to suspend the first memory access operation, such as a pause command, which is received by the pause agent 134.

[0052] At operation 420, the state of the memory device is changed. For example, in response to receiving a pause command, pause agent 134 may put memory device 130 into a paused state. In one embodiment, a first memory access operation is paused (i.e., halted, stopped, interrupted) during the paused state. In one embodiment, pause agent 134 stores progress information associated with the first memory access operation in a page cache (e.g., page cache 240) of memory device 130. For example, pause agent 134 may, in response to entering the paused state, store data already programmed into memory array 250 in page cache 240 (e.g., one of data registers 244-246), where this data can be used to resume the paused memory access operation later. In one embodiment, pause agent 134 implements a command state machine, the operation 500 of which... Figure 5The command state machine includes a command interpreter 502 that receives and identifies commands (e.g., a pause command) from the requesting party. At 504, the command state machine enables the command. For example, if the received command is a pause command, the command state machine can transition the memory device 130 from its current state (e.g., a normal operating state) to a paused state. In the paused state, the command state machine can further receive additional commands (e.g., memory access commands), as described below. The command state machine further includes an address interpreter 512 that receives and identifies the address corresponding to the command received from the requesting party. At 514, the command state machine enables the address. The command state machine performs both command and address latching at 506 and triggers array operation at 508. In one embodiment, the latching is performed using a trigger circuit or other means, and the command machine address enable signal has been temporarily stored before the array operation is performed.

[0053] At operation 425, a command / request is received. For example, the processing logic may receive from the requesting party a third request to perform a second memory access operation on the memory array 250 of the memory device 130. In one embodiment, the second memory access operation includes at least one of a programming operation, a read operation, or an erase operation. For example, the second memory access operation may include a dynamic SLC programming operation. A dynamic SLC programming operation may have a shorter programming time than an MLC programming operation and a shorter programming time than a static SLC programming operation. That is, a dynamic SLC programming operation may complete faster than those other operations. In addition, a different fine-tuning setting of the memory device is used to perform the dynamic SLC programming operation compared to those fine-tuning settings used for the MLC programming operation or the static SLC programming operation. Furthermore, the dynamic SLC programming operation is performed relative to data with a lower priority than the data associated with the MLC programming operation or the static SLC programming operation. For example, the pause manager 114 may issue a static SLC programming operation when more critical data (i.e., data with a higher priority level) is to be written to the memory device 130. However, when a small amount of critical data is to be written to memory device 130, pause manager 114 may issue dynamic SLC programming operations. In one embodiment, when memory device 130 is in a paused state, pause manager 114 sends a request to memory device 130 to perform a second memory access operation, such as a second memory access command, which is received by pause agent 134. In other embodiments, two or more additional memory access operations may be performed while memory device 130 is in a paused state.

[0054] At operation 430, a memory access operation is initiated. For example, the processing logic may initiate a second memory access operation (e.g., a dynamic SLC programming operation) on memory array 250. In one embodiment, pause agent 134 may apply one or more programming pulses to the corresponding word line (e.g., word line 252) of memory array 250 to store data associated with the second memory access operation in the memory cells of memory array 250. At operation 435, the processing logic determines that the dynamic SLC programming operation is complete. The operation is complete when all associated data has been successfully programmed into memory array 250.

[0055] At operation 440, a notification is provided. For example, the processing logic may provide the requesting party with a notification indicating that a second memory access operation (e.g., a dynamic SLC programming operation) has completed. In one embodiment, memory device 130 outputs a ready / busy signal indicating the state of memory device 130. For example, when memory device 130 is ready (i.e., not currently performing a memory access operation), the signal may have a first voltage level (e.g., a high voltage level indicating logic "1"), and when memory device 130 is busy (i.e., currently performing a memory access operation), the signal may have a second voltage level (e.g., a low voltage level indicating logic "0"). In one embodiment, after the second memory access operation is completed, pause agent 134 may set the value of the ready / busy signal to the corresponding level, which is received by pause manager 114. Pause manager 114 may decode the signal level to determine the state of memory device 130.

[0056] At operation 445, a command / request is received. For example, the processing logic may receive from the requesting party a fourth request to resume a first memory access operation (e.g., a previously suspended MLC programming operation) to the memory array 250 of the memory device 130. In one embodiment, the pause manager 114 sends a request to the memory device 130 to resume the first memory access operation, such as a resume command, which is received by the pause agent 134.

[0057] At operation 450, the memory access operation is resumed. For example, the processing logic may cause memory device 130 to exit the suspended state and resume the first memory access operation at the point where it was interrupted, using progress information from page cache 240. In one embodiment, a pause agent 134 may read data stored in page cache 240, which was previously written to memory array 250, and compare this data with data in a resume command to determine the location where the memory access operation was interrupted when the pause occurred. Therefore, the pause agent 134 may resume programming the data used for the first memory access operation into memory array 250 from that point.

[0058] Figure 6 An example machine illustrating computer system 600 is provided, within which a set of instructions can be executed to cause the machine to perform any one or more of the methods discussed herein. In some embodiments, computer system 600 may correspond to a host system (e.g., Figure 1 The host system 120 includes a memory subsystem (e.g., Figure 1 The memory subsystem 110), coupled to or utilizing the memory subsystem, or may be used to perform controller operations (e.g., execute an operating system to perform operations corresponding to...). Figure 1 (The operation of the pause manager 114 and / or pause agent 134). In an alternative embodiment, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, operating at the capacity of a server or client machine in a client-server network environment.

[0059] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by the machine. Furthermore, although a single machine is described, the term "machine" should be understood to include any set of machines that individually or collectively execute one or more sets of instructions to perform any one or more of the methods discussed herein.

[0060] Example computer system 600 includes processing devices 602 that communicate with each other via bus 630, main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and data storage system 618.

[0061] Processing device 602 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 602 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. Computer system 600 may further include a network interface device 608 for communication on network 620.

[0062] Data storage system 618 may include machine-readable storage medium 624 (also referred to as computer-readable medium, such as non-transitory computer-readable medium) on which one or more sets of instructions 626 or software embodying any one or more of the methods or functions described herein are stored. The instructions 626 may also reside wholly or at least partially in main memory 604 and / or processing device 602 during execution by computer system 600, the main memory 604 and processing device 602 also constituting machine-readable storage medium. Machine-readable storage medium 624, data storage system 618, and / or main memory 604 may correspond to... Figure 1 The memory subsystem 110.

[0063] In one embodiment, instruction 626 includes instructions for implementing the corresponding Figure 1 The pause manager 114 and / or pause agent 134 provide functional instructions. Although the machine-readable storage medium 624 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0064] Some parts of the previously described algorithms and symbolic representations of operations on data bits within computer memory have been presented. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. In this document, and generally in general, an algorithm is conceived as a self-consistent sequence of operations that produce a desired result. An operation is an operation that requires physical manipulation of a physical quantity. Typically (but not always), these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been shown that it is sometimes convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc., primarily for common use.

[0065] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient notations for application to those quantities. This disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities in the registers and memories of a computer system, or other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage systems.

[0066] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for the desired purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0067] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices for performing the methods described herein. The structures of various such systems will be presented as set forth in the description below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0068] This disclosure may be provided as a computer program product or software, which may include machine-readable media on which instructions are stored for programming a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, machine-readable (e.g., computer-readable) media includes machine-readable storage media such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0069] In the foregoing description, embodiments of this disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A memory device, comprising: a memory array; and control logic operably coupled with the memory array to perform operations comprising: receiving, from a requestor, a first request to perform a first memory access operation on the memory array; initiating the first memory access operation on the memory array; receiving, from the requestor, a second request to suspend performing the first memory access operation before the first memory access operation is completed; causing the memory device to enter a suspend state, wherein the first memory access operation is suspended during the suspend state; receiving, from the requestor, a third request to perform a dynamic SLC programming operation on the memory array while the memory device is in the suspend state, wherein the dynamic SLC programming operation is performed using different trim settings of the memory device compared to trim settings of the memory device used when performing a static SLC programming operation, and wherein a program time associated with the dynamic SLC programming operation is less than a program time associated with the static SLC programming operation; and initiating the dynamic SLC programming operation on the memory array.

2. The memory device of claim 1, wherein the requestor comprises a memory sub-system controller of a memory sub-system that includes the memory device.

3. The memory device of claim 1, wherein the first memory access operation comprises a multi-level cell (MLC) programming operation.

4. The memory device of claim 3, wherein the dynamic SLC programming operation has a shorter program time than the MLC programming operation.

5. The memory device of claim 3, wherein the dynamic SLC programming operation is performed with respect to data having a lower priority than data associated with the MLC programming operation.

6. The memory device of claim 1, further comprising: a page cache operably coupled with the memory array and the control logic, wherein the control logic stores progress information associated with the first memory access operation in the page cache when the memory device is in the suspend state.

7. The memory device of claim 6, wherein the control logic is to perform operations further comprising: determining that the dynamic SLC programming operation is complete; providing a notification to the requestor indicating that the dynamic SLC programming operation is complete; receiving, from the requestor, a fourth request to resume the first memory access operation on the memory array; causing the memory device to exit the suspend state; and resuming the first memory access operation on the memory array using the progress information from the page cache.

8. A method for performing memory operations, comprising: receiving, from a requestor, a first request to perform a first memory access operation on a memory device; initiating the first memory access operation on the memory device; ​ receiving, from the requestor, a second request to suspend execution of the first memory access operation before the first memory access operation is completed; causing the memory device to enter a suspend state, wherein the first memory access operation is suspended during the suspend state; receiving, from the requestor, a third request to perform a dynamic SLC programming operation on the memory device while the memory device is in the suspend state, wherein the dynamic SLC programming operation is performed using different trim settings of the memory device compared to trim settings of the memory device used when performing a static SLC programming operation, and wherein a program time associated with the dynamic SLC programming operation is less than a program time associated with the static SLC programming operation; and initiating the dynamic SLC programming operation on the memory device.

9. The method of claim 8, wherein the requestor comprises a memory sub-system controller of a memory sub-system, the memory sub-system comprising the memory device.

10. The method of claim 8, wherein the first memory access operation comprises a multi-level cell (MLC) programming operation.

11. The method of claim 10, wherein the dynamic SLC programming operation has a shorter program time than the MLC programming operation.

12. The method of claim 10, wherein the dynamic SLC programming operation is performed with respect to data having a lower priority than data associated with the MLC programming operation.

13. The method of claim 8, further comprising: storing, in a page cache of the memory device, progress information associated with the first memory access operation while the memory device is in the suspend state.

14. The method of claim 13, further comprising: determining that the dynamic SLC programming operation is complete; providing a notification to the requestor indicating that the dynamic SLC programming operation is complete; receiving, from the requestor, a fourth request to resume the first memory access operation on the memory device; causing the memory device to exit the suspend state; and resuming the first memory access operation on the memory device using the progress information from the page cache.

15. A method for performing memory operations, comprising: sending, to a memory device comprising control logic and a memory array, a first request to perform a first memory access operation on the memory array; sending, to the memory device, a second request to suspend execution of the first memory access operation before the first memory access operation is completed, the second request causing the memory device to enter a suspend state, wherein the first memory access operation is suspended during the suspend state; and sending, to the memory device, a third request to perform a dynamic SLC programming operation on the memory device while the memory device is in the suspended state, wherein the dynamic SLC programming operation is performed using different trim settings of the memory device compared to trim settings of the memory device used when performing a static SLC programming operation, and wherein a program time associated with the dynamic SLC programming operation is less than a program time associated with the static SLC programming operation.

16. The method of claim 15, wherein the first memory access operation comprises a multi-level cell (MLC) programming operation.

17. The method of claim 16, wherein the dynamic SLC programming operation has a shorter program time than the MLC programming operation.

18. The method of claim 16, wherein the dynamic SLC programming operation is performed with respect to data having a lower priority than data associated with the MLC programming operation.

19. The method of claim 15, wherein the request to suspend performance of the first memory access operation causes the memory device to store progress information associated with the first memory access operation in a page cache of the memory device.

20. The method of claim 19, further comprising: receiving, from the memory device, a notification indicating completion of the dynamic SLC programming operation; sending, to the memory device, a fourth request to resume the first memory access operation on the memory device, the fourth request causing the memory device to exit a suspended state and resume the first memory access operation on the memory device using the progress information from the page cache.

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