Semiconductor device and manufacturing method thereof, three-dimensional memory and memory system

Abstract

The present application provides a semiconductor device and a manufacturing method thereof, as well as a three-dimensional memory and memory system. The manufacturing method of the semiconductor device includes: removing a portion of a substrate to form at least one first fin; forming a semiconductor layer on a top surface and a pair of side surfaces of the first fin, the semiconductor layer including a top portion located on the top surface and side portions located on the pair of side surfaces; removing the first fin; and forming a gate structure that circumferentially surrounds the top portion and passes through a region between the side portions. The present application can form a gate-wrap field-effect transistor based on a fin field-effect transistor manufacturing process.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology. Specifically, the present application relates to a semiconductor device and a manufacturing method thereof, a three-dimensional memory, and a memory system. Background Art

[0002] As semiconductor process nodes advance below 10nm, the channel length of conventional metal-oxide-semiconductor field-effect transistors (MOSFETs) has also shortened accordingly, and the gate's control over the channel has deteriorated, making short-channel effects (SCE) more likely to occur.

[0003] To improve gate control capabilities, Fin Field-Effect Transistor (FinFET) and Gate-all-around Field-Effect Transistor (GAAFET) have been promoted. The gate of FinFET can control the fin from three surfaces, which has stronger control over the channel. In addition, FinFET has better compatibility with existing integrated circuit manufacturing than other devices. The gate of GAAFET surrounds the channel area from all sides, which can further enhance the gate's control over the channel and is more effective in suppressing short channel effects.

[0004] It should be understood that this background technology section is intended in part to provide a useful background for understanding the technology, however, these contents are not necessarily what are known or understood by those skilled in the art before the filing date of this application. Summary of the Invention

[0005] On the one hand, the present application provides a method for manufacturing a semiconductor device, the method comprising: removing a portion of a substrate to form at least one first fin; forming a semiconductor layer on a top surface and a pair of side surfaces of the first fin, the semiconductor layer comprising a top portion located on the top surface and a side portion located on the pair of side surfaces; removing the first fin; and forming a gate structure that passes through an area between the side portions and circumferentially surrounds the top portion.

[0006] In one embodiment of the present application, the first fin and the semiconductor layer are made of different materials.

[0007] In one embodiment of the present application, in the same etching process, the first fin and the semiconductor layer have a predetermined etching selectivity ratio, so that the semiconductor layer is retained when the first fin is removed.

[0008] In one embodiment of the present application, the first fin includes silicon, and the semiconductor layer includes silicon germanium.

[0009] In one embodiment of the present application, forming the first fin includes: etching a substrate to form a plurality of protruding and discrete initial fins, the plurality of initial fins including at least one first initial fin; forming an isolation structure on the substrate to separate adjacent initial fins, with the top surface of the initial fin exposed; and removing a portion of the first initial fin through a pair of side surfaces of the first initial fin opposite to the isolation structure and the exposed top surface to form the first fin.

[0010] In one embodiment of the present application, the multiple initial fins include at least one second initial fin, wherein removing a portion of the first initial fin includes: forming a first mask layer covering the top surface of the second initial fin and a portion of the top surface of the first initial fin on the isolation structure; and removing the portion of the first initial fin using the first mask layer as a mask.

[0011] In one embodiment of the present application, removing the portion of the first initial fin using a first mask layer as a mask includes: removing a portion of the first initial fin located on a pair of side surfaces and a top surface thereof; removing a portion of the first mask layer located on the top surface of the first initial fin; forming a second mask layer on a pair of exposed side surfaces of the first initial fin; and removing another portion of the first initial fin located on the top surface thereof using the second mask layer as a mask.

[0012] In one embodiment of the present application, the method further includes: removing a portion of the isolation structure to expose a portion of the first fin and the second initial fin away from the substrate; and removing a portion of the at least one second initial fin to form at least one second fin.

[0013] In one embodiment of the present application, the method further includes: doping the semiconductor layer with a first conductivity type; and doping the second fin with a second conductivity type opposite to the first conductivity type.

[0014] In one embodiment of the present application, the method further includes: forming a gate dielectric layer covering the semiconductor layer and the first fin and the second fin in the remaining portion of the isolation structure; and forming a sacrificial gate layer spanning the first fin and the second fin on the gate dielectric layer; and forming a dielectric layer circumferentially surrounding the sacrificial gate layer on the gate dielectric layer.

[0015] In one embodiment of the present application, removing the first fin includes: removing the sacrificial gate layer; forming a third mask layer on the second fin; and using the third mask layer as a mask, removing at least a portion of the gate dielectric layer located on the first fin and the semiconductor layer.

[0016] In one embodiment of the present application, forming a gate structure surrounding the top of the semiconductor layer includes: sequentially forming a dielectric layer and a work function stack on the inner wall of the dielectric layer, the semiconductor layer, and the second fin; and filling a conductive material in the space defined by the work function stack to form a conductive layer surrounding the top of the semiconductor layer and across the second fin.

[0017] In one embodiment of the present application, forming the work function stack includes: forming a first type of work function layer on the dielectric layer; forming a second type of work function layer different from the first type on the first type of work function layer; and forming the first type of work function layer on a portion of the second type of work function layer located on the semiconductor layer.

[0018] Another aspect of the present application provides a semiconductor device, comprising: at least one semiconductor layer having a top portion located above a substrate and two side portions extending into the substrate; and a gate structure passing through a region between the side portions and circumferentially surrounding the top portion.

[0019] In one embodiment of the present application, the semiconductor device further includes: at least one fin protruding from the substrate, the fin being spaced apart from the semiconductor layer, wherein the gate structure spans the fin; and a shallow trench isolation structure located on the substrate to separate adjacent fins and the semiconductor layer.

[0020] In one embodiment of the present application, at least a portion of the top of the semiconductor layer contacting the two side portions is exposed, and the at least a portion of the semiconductor layer includes a first conductive type portion.

[0021] In one embodiment of the present application, at least a portion of the fin is exposed, and at least a portion of the fin includes a second conductive type portion opposite to the first conductive type portion.

[0022] In one embodiment of the present application, the gate structure includes a dielectric layer, a work function stack, and a conductive layer arranged in sequence from the outside to the inside.

[0023] In one embodiment of the present application, the portion of the work function stack located in the semiconductor layer includes: a first type of work function layer, a second type of work function layer, and a first type of work function layer stacked in sequence.

[0024] In one embodiment of the present application, the portion of the work function stack located at the fin includes: a work function layer of the first type and a work function layer of the second type arranged in sequence.

[0025] In one embodiment of the present application, the distance between the top of the semiconductor layer and the non-protruding portion of the substrate is between 400 angstroms and 900 angstroms.

[0026] In one embodiment of the present application, the thickness of the top of the semiconductor layer in a direction away from the substrate ranges from 100 angstroms to 300 angstroms.

[0027] In one embodiment of the present application, the height of the fin protruding from the substrate ranges from 400 angstroms to 900 angstroms.

[0028] Another aspect of the present application provides a three-dimensional memory, comprising: a memory array; and a peripheral circuit coupled to the memory array and comprising: the semiconductor device as described in any one of the above descriptions.

[0029] Yet another aspect of the present application provides a memory system, comprising: the three-dimensional memory as described above, configured to store data; and a memory controller coupled to the three-dimensional memory and configured to control the three-dimensional memory.

[0030] In one embodiment of the present application, the memory system includes: a solid-state drive or a memory card. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Other features, objects and advantages of the present application will become more apparent from the detailed description of the non-limiting embodiments made with reference to the following drawings.

[0032] Figure 1 is a flow chart of a method for manufacturing a semiconductor device according to one embodiment of the present application;

[0033] Figure 2-Figure 19 Schematic diagram of a method for manufacturing a semiconductor device according to one embodiment of the present application.

[0034] Figure 20 It is a schematic three-dimensional diagram of a semiconductor device according to one embodiment of the present application.

[0035] Figure 21 for Figure 20 The semiconductor device is shown as a schematic cross-sectional view along line AA.

[0036] Figure 22 is a schematic diagram of a three-dimensional memory including a peripheral circuit according to some embodiments of the present application;

[0037] Figure 23 is a block diagram of an exemplary system including a three-dimensional memory according to some embodiments of the present application;

[0038] Figure 24 is a schematic diagram of an exemplary memory card including a three-dimensional memory according to some embodiments of the present application;

[0039] Figure 25 is a schematic diagram of an exemplary solid-state drive (SSD) including three-dimensional memory according to some embodiments of the present application. DETAILED DESCRIPTION

[0040] In order to better understand the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely descriptions of exemplary embodiments of the present application and are not intended to limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements.

[0041] Note that references in the specification to "one embodiment," "an embodiment," "example embodiment," "some embodiments," etc., indicate that the described embodiment may include a particular feature, structure, or characteristic, but not every embodiment may include that particular feature, structure, or characteristic. Furthermore, these phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it would be within the knowledge of those skilled in the relevant art to implement such feature, structure, or characteristic in conjunction with other embodiments, whether or not explicitly described.

[0042] In general, terms can be understood, at least in part, from their use in context. For example, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense, depending, at least in part, on the context. Similarly, terms such as "a" or "the" can also be understood to convey singular usage or to convey plural usage, depending, at least in part, on the context. Furthermore, the term "based on" can be understood as not necessarily intended to convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, again depending, at least in part, on the context.

[0043] It should be readily understood that the meanings of “on,” “above,” and “over” in this disclosure should be interpreted in the broadest manner, such that “on” means not only “directly on something,” but also includes “on something” with intervening features or layers therebetween, and “above” or “over” means not only “above” or “over” something, but also includes “above” or “over” something with no intervening features or layers therebetween (i.e., directly on something).

[0044] Additionally, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and accordingly, the spatially relative descriptors used herein should be similarly interpreted.

[0045] As used herein, the term "layer" refers to a portion of a material comprising an area having a thickness. A layer may extend over the entire superstructure or substructure, or may have an extent that is smaller than the substructure or superstructure. In addition, a layer may be an area of a continuous structure that is uniform or non-uniform, the thickness of which is less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, and / or may have one or more layers thereon, above, and / or below it. A layer may include multiple layers.

[0046] In the drawings, the thickness, size, and shape of components have been slightly adjusted for ease of illustration. The drawings are for illustration only and are not drawn strictly to scale. For example, as used herein, the terms "substantially," "approximately," and similar terms are intended to indicate approximations, not degrees, and are intended to account for inherent variations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0047] It should also be understood that the terms "comprises," "including," "having," "includes," and / or "comprising," when used in this specification, indicate the presence of the stated features, elements, and / or components, but do not preclude the presence or addition of one or more other features, elements, components, and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than modifying the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application." And, the term "exemplarily" is intended to refer to an example or illustration.

[0048] Unless otherwise defined, all words used herein (including engineering terms and scientific and technological terms) have the same meaning as commonly understood by those skilled in the art to which this application belongs. It should also be understood that, unless otherwise specified in this application, words defined in commonly used dictionaries should be interpreted as having the same meaning as they do in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense.

[0049] It should be noted that, unless there is a conflict, the embodiments and features of the embodiments in this application can be combined with each other. In addition, unless explicitly limited or inconsistent with the context, the specific steps included in the methods described in this application are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0050] Figure 1 1 is a flow chart of a method 1000 for manufacturing a semiconductor device according to one embodiment of the present application. In some examples, the semiconductor device may be used as a part of a peripheral circuit of a three-dimensional memory, such as a three-dimensional NAND memory or a three-dimensional NOR memory. Figure 1 As shown, the method 1000 for manufacturing a semiconductor device includes:

[0051] S1: removing a portion of the substrate to form at least one first fin;

[0052] S2: forming a semiconductor layer on a top surface and a pair of side surfaces of the first fin, wherein the semiconductor layer includes a top portion located on the top surface and side portions located on the pair of side surfaces;

[0053] S3: removing the first fin;

[0054] S4: forming a gate structure passing through a region between the side portions and circumferentially surrounding the top portion.

[0055] The following will refer to Figure 2-Figure 25The schematic diagrams of each stage of the method for manufacturing a semiconductor device are shown to describe the above steps S1-S4 respectively. When describing the embodiments of the present application, for the convenience of explanation, the cross-sectional views showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of this application. In addition, in actual production, a three-dimensional space ruler of length, width and depth should be included. It should be understood that the operations shown in the method are not exhaustive, and other operations may also be performed before, after or between any of the operations described.

[0056] Step S1: removing a portion of the substrate to form at least one first fin;

[0057] For example, the substrate (e.g. Figure 2 The substrate 100 shown in the figure may be made of, for example, silicon (single crystal silicon or polycrystalline silicon), single crystal germanium (Ge), silicon germanium (GeSi), a silicon on insulator substrate, a germanium on insulator substrate, or a silicon germanium on insulator substrate.

[0058] In one embodiment of the present application, substrate 100 may be a substrate for fabricating peripheral circuits of a non-volatile memory device. The present application does not limit the structure, material, or formation process of substrate 100. Furthermore, substrate 100 may be ion-doped, and the type and concentration of the doped ions may be selected based on actual needs.

[0059] A first horizontal direction in or parallel to the top surface of substrate 100 represents the X direction, and a second direction in or parallel to the top surface of the substrate represents the Y direction. The first horizontal direction and the second horizontal direction are perpendicular to each other, that is, the X and Y directions are mutually perpendicular. A third direction perpendicular to the top surface of the substrate represents the Z direction. A symbol showing a combination of a circle and a cross near the letter "X" or "Y" indicates that the X or Y direction in the figure is directed inward relative to the drawing page.

[0060] In some examples, a suitable dry etching or wet etching process may be used to remove a portion of the substrate 100 to form at least one first fin (eg, Figure 7 It should be understood that the number of the first fin 101' may be one or more than one, and this application does not limit this.

[0061] Figure 2A schematic cross-sectional view along the ZX direction of a semiconductor structure after forming initial fins is shown in a method for manufacturing a semiconductor device according to one embodiment of the present application. In some examples, a substrate 100 can be etched using a suitable etching process to form a plurality of protruding and discrete initial fins, such as a first initial fin 101 and a second initial fin 102. In some examples, the first initial fin 101 and the second initial fin 102 can each include a portion 130 protruding from the substrate, a barrier layer 102, and a mask layer 104. Optionally, the first initial fin 101 and the second initial fin 102 can extend in one direction (e.g., the Y direction).

[0062] Continue to refer Figure 2 In some examples, a barrier layer 103 (e.g., a silicon oxide layer) and a mask layer 104 (e.g., a silicon nitride layer) may be sequentially formed on the substrate 100. Optionally, the barrier layer 103 located below the mask layer 104 may relieve stress between the substrate 100 and the mask layer 104 and protect the substrate 100 from damage caused by subsequent ion implantation of the substrate 100. Optionally, the barrier layer 103 and the mask layer 104 may be formed respectively by one or more thin film deposition processes selected from the group consisting of atomic layer deposition (ALD), chemical vapor deposition (CVD), high-density plasma chemical vapor deposition (HDP-CVD), and physical vapor deposition (PVD).

[0063] In some examples, a patterned photoresist layer (e.g., photoresist) can be formed on mask layer 104, and then the pattern of the photoresist can be transferred to mask layer 104 through a suitable etching process. During patterning, barrier layer 103 can be used to protect the underlying substrate 100 from damage. Optionally, after the etching process is performed, the photoresist can be removed, for example, by ashing and / or wet stripping processes.

[0064] Figure 3 A schematic cross-sectional view along the ZX direction of a semiconductor structure after forming an isolation structure according to a manufacturing method according to one embodiment of the present application is shown. In some examples, the isolation structure 105 separating the first initial fin 101 and the second initial fin 102 can be formed on the substrate 100 by one or more thin film deposition processes such as CVD, PVD, and ALD.

[0065] In some examples, at least one side surface of the first initial fin 101 and the second initial fin 102 may be exposed, and the isolation structure 105 may be formed on another pair of side surfaces of the first initial fin 101 and the second initial fin 102. In some examples, the isolation structure 105 may also cover the top surfaces of the first initial fin 101 and the second initial fin 102. Optionally, the top surface of the isolation structure 105 may be planarized using a chemical mechanical polishing (CMP) process. Optionally, the CMP process may stop at the top surface of the mask layer 104, thereby exposing the top surfaces of the first initial fin 101 and the second initial fin 102. Optionally, the first initial fin 101 and the second initial fin 102 may be exposed above the top surface of the mask layer 104.

[0066] As described herein, the first initial fin 101, the second initial fin 102, the isolation structure 105, and the substrate 100 each have a top surface and a side surface. The top surface can be a surface parallel or substantially parallel to the substrate 100 and facing away from the substrate 100; two opposing side surfaces form a pair, referred to as a "pair of side surfaces."

[0067] Figure 4-Figure 7 FIG. 1 is a schematic perspective view of a semiconductor structure formed after performing certain operations according to a manufacturing method of one embodiment of the present application. Figure 8 for Figure 7 Schematic diagram of the cross section along the ZX direction. Figure 4 As shown, in some examples, a portion of the first initial fin 101 may be removed through the exposed top surface of the first initial fin 101 and a pair of side surfaces opposite to the isolation structure 105 to form a Figure 7 The first fin 101' is shown. Optionally, the first fin 101' may extend into the non-protruding portion of the substrate 100. Alternatively, a pair of side surfaces of the first fin 101' formed by etching the first initial fin 101 may have an angle less than 90 degrees with the substrate 100, that is, the pair of side surfaces of the first fin 101' may be inclined surfaces.

[0068] Continue to refer Figure 4 In some examples, the first mask layer 106 covering the top surface of the second initial fin 102 and a portion of the top surface of the first initial fin 101 can be used as a mask to remove a portion of the first initial fin 101 to form the first fin 101'. Optionally, the first fin 101' can extend in the Y direction.

[0069] refer to Figure 4In some examples, a first mask layer 106 covering the top surface of the second initial fin 102 and a portion of the top surface of the first initial fin 101 can be formed on the isolation structure 105 by, for example, one or more thin film deposition methods such as CVD, PVD, or ALD. Alternatively, a mask layer (not shown) and a photoresist (not shown) can be sequentially formed on the isolation structure 105 to cover the second initial fin 102 and the first initial fin 101. The photoresist is then patterned using a mask (not shown). Subsequently, the pattern on the photoresist can be transferred to the mask layer by etching or other processes to form the first mask layer 106.

[0070] refer to Figure 5 In some examples, the first mask layer 106 can be used as a mask to remove a portion of a pair of side surfaces of the first initial fin 101 opposite to the isolation structure 105 through a suitable dry etching or wet etching process. Optionally, another portion of the top surface of the first initial fin 101 not covered by the first mask layer 106 can also be removed. Figure 5 In the example shown, the etching process may remove the barrier layer 102 and the mask layer 104 as well as a portion of the portion 130 protruding from the substrate.

[0071] refer to Figure 6 In some examples, a portion of the first mask layer 106 located on the top surface of the first initial fin 101 may be removed by a suitable dry etching or wet etching process. Figure 6 In some examples, a second mask layer 122 may be formed on a pair of exposed side surfaces of the first initial fin 101. For example, the second mask layer 122 may be used as a mask to remove another portion of the first initial fin 101 through the exposed top surface of the first initial fin 101, thereby forming Figure 7 and Figure 8 The first fin 101' shown in FIG. Figure 7 and Figure 8 In the example shown, the etching process may remove at least the remaining portion of the barrier layer 102 and the mask layer 104. Optionally, the height of the first fin 101' protruding from the substrate 100 may be between 400 angstroms and 900 angstroms.

[0072] Those skilled in the art should understand that part or all of the above process of forming the first fin 101 ′ may be applied to multiple initial fins to form any appropriate multiple fins when needed.

[0073] S2: forming a semiconductor layer on the top surface and a pair of side surfaces of the first fin, wherein the semiconductor layer includes The top of the top surface and the side portions located on the pair of side surfaces;

[0074] Figure 9 FIG1 shows a schematic cross-sectional view of a semiconductor structure along the ZY direction after forming a semiconductor layer according to a method for manufacturing a semiconductor device in accordance with an embodiment of the present application. Figure 9 As shown, in some examples, before forming the first fin (eg, Figure 8 After forming the first fin 101' as shown, a semiconductor layer 107 may be conformally formed on the top surface and a pair of side surfaces of the first fin 101' by one or more thin film forming processes such as CVD, PVD, ALD, and selective epitaxial growth processes.

[0075] In some examples where semiconductor layer 107 includes silicon germanium, the germanium content in the semiconductor layer including silicon germanium can be controlled to be between 15% and 50% by controlling parameters such as the temperature of the epitaxial growth process. For example, the process temperature of the epitaxial growth process can be controlled between 400°C and 500°C. The epitaxially grown semiconductor layer 107 can, for example, include a multilayer structure, wherein at least some of the layers in the multilayer structure have different silicon germanium contents. For example, in a multilayer structure including three layers, the germanium content of the middle layer of the three-layer structure is higher than the germanium content of the remaining two layers. The germanium content of each layer in the three-layer structure can be 20%, 50%, and 20%, respectively.

[0076] Continue to refer Figure 9 In some examples, the semiconductor layer 107 may have a top portion 1071 (e.g., a channel region) away from the substrate 100 and a side portion 1072 and a side portion 1073 (e.g., a source region and a drain region) extending to a non-protruding portion of the substrate 100. Optionally, the first fin 101' and the semiconductor layer 107 are made of different materials. In some examples, the material of the first fin 101' includes silicon, for example, and the material of the semiconductor layer 107 includes silicon germanium, for example.

[0077] In some examples, the distance between the top portion 1071 of the semiconductor layer 107 and the non-protruding portion of the substrate 100 ranges from 400 angstroms to 900 angstroms. Alternatively, the thickness of the top portion 1071 of the semiconductor layer 107 in a direction perpendicular or substantially perpendicular to the substrate 100 can range from 100 angstroms to 300 angstroms. For example, a CMP planarization process can be used to make the top surface of the semiconductor layer 107 coplanar with the top surface of the isolation structure 105.

[0078] In one embodiment of the present application, the etching process and thin film formation process described above may be performed in situ. In other words, the first fin 101' may be formed using, for example, an etching process; and the semiconductor layer 107 may be formed in situ on the top surface and a pair of side surfaces of the first fin 101' using, for example, a selective epitaxial growth process. Optionally, the manufacturing process for selective epitaxial growth of the semiconductor layer 107 may include one or more of vapor phase epitaxy (VPE), liquid phase epitaxy (LPE), and molecular beam epitaxy (MPE).

[0079] In-situ processing can be, for example, a processing process in which the intermediate of the semiconductor device (for example, the intermediate including the substrate 100, the first fin 101', the second initial fin 102, and the isolation structure 105) is not moved, so that the above two process steps are implemented in the same machine or chamber. In-situ processing can ensure high cleanliness of the semiconductor structure preparation process and improve the electrical characteristics of the finally formed semiconductor device.

[0080] In one embodiment of the present application, the semiconductor layer 107 and the first fin 101' may be doped with a first conductivity type by, for example, an ion implantation process. Optionally, the first conductivity type doping may be P-type doping, and the P-type doping particles may be, for example, boron, germanium, indium, etc. Optionally, the P-type doping may be, for example, light doping, and the doping concentration of the light doping may be, for example, 10 9 cm -3 ~10 12 cm -3 In other examples, the first conductive type doping may be N-type doping, which is not limited in this application.

[0081] In some examples where the semiconductor layer 107 includes silicon germanium and the substrate 100 includes silicon, silicon germanium helps to improve carrier mobility of the channel because silicon germanium has a higher mobility than polysilicon.

[0082] Figure 10 FIG1 shows a schematic cross-sectional view of a semiconductor structure along the ZX direction after forming the second fin portion according to a method for manufacturing a semiconductor device in accordance with an embodiment of the present application. Figure 10 As shown, in one embodiment of the present application, after forming the semiconductor layer 107, a portion of the isolation structure 105 may be removed in a direction close to the substrate 100 using, for example, a CMP process or an etching process, thereby forming a shallow trench isolation structure (STI) 108. Optionally, the top surface of the shallow trench isolation structure 108 may be lower than the top surfaces of the first fin 101' and the second fin 102'. The shallow trench isolation structure 108 can be used to isolate adjacent semiconductor elements, such as isolating adjacent field effect transistors. Optionally, the material forming the shallow trench isolation structure includes an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0083] As an option, the isolation structure 105 may be located relative to the substrate 100 and the first fin 101 ′ and the second initial fin 102 ( Figure 8) has an etching selectivity greater than a set value, for example, an etching selectivity greater than 8:1, so as to retain the substrate 100 and the first fin 101 ′ and the second preliminary fin 102 during the formation of the shallow trench isolation structure 108. In some examples, the shallow trench isolation structure 108 can expose the first fin 101 ′ and the second preliminary fin 102 and a portion of the semiconductor layer 107 away from the substrate 100.

[0084] Continue to refer Figure 10 In some examples, at least a portion of the exposed second initial fin 102 may be removed to form a second fin 102'. Optionally, the mask layer 104 and the barrier layer 103 of the second initial fin 102 may be removed in sequence to form the second fin 102'. The second fin 102' and the first fin 101' may, for example, extend in the same direction (for example, the Y direction). Optionally, after removing the mask layer 104 of the second initial fin 102, the second initial fin 102 may be doped with a second conductive type opposite to the first conductive type using an ion implantation process with the barrier layer 103 as protection. Optionally, in an example where the first conductive type is P-type doping, the second initial fin 102 may be doped with N-type conductive particles such as phosphorus, arsenic, and antimony. The doping of the N-type conductive particles may, for example, be light doping, and the doping concentration of the light doping may, for example, include 10 9 cm -3 ~10 12 cm -3 .

[0085] S3: removing the first fin;

[0086] In some examples, after forming the semiconductor layer 107, the first fin 101' ( Figure 10 ).

[0087] Figure 11-13 FIG. 1 is a schematic cross-sectional view taken along the ZX direction of a semiconductor structure formed after certain operations are performed according to a manufacturing method in accordance with an embodiment of the present application. Figure 14-15 Schematic diagram of projection along the ZX direction of a semiconductor structure formed after certain operations are performed according to a manufacturing method of one embodiment of the present application. Figure 16 and Figure 17 FIG. 1 is a partial perspective schematic diagram of a semiconductor structure formed after performing certain operations according to a manufacturing method of one embodiment of the present application. Figure 18 for Figure 17 The schematic projection diagram of the semiconductor structure along the ZX direction is shown.

[0088] like Figure 11As shown, in some examples, after forming the shallow trench isolation structure 108, a gate dielectric layer 109 can be formed on the top surface of the shallow trench isolation structure 108, the exposed semiconductor layer 107, and the surfaces of the first fin 101' and the second fin 102'. Exemplarily, the gate dielectric layer 109 can be formed by one or more thin film deposition processes such as ALD, CVD, HDP-CVD, and PVD. Optionally, the material of the gate dielectric layer 109 includes, for example, an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The gate dielectric layer 109 can be used to electrically isolate the gate and channel in subsequent processes and semiconductor devices.

[0089] In one embodiment of the present application, the gate dielectric layer 109 can be formed using an in-situ steam generation (ISSG) method. For example, after depositing a silicon nitride layer on the top surface of the shallow trench isolation structure 108, the exposed semiconductor layer 107, and the surfaces of the first fin 101' and the second fin 102' using ALD, the silicon nitride on the surface of the silicon nitride layer is oxidized to silicon dioxide using the in-situ steam generation method to form a conformal gate dielectric layer 109. The gate dielectric layer 109 conformally formed using the in-situ steam generation method has a uniform and controllable thickness, which is beneficial for improving gate control capability.

[0090] In one embodiment of the present application, the gate dielectric layer 109 may be directly deposited on the top surface of the shallow trench isolation structure 108, the exposed semiconductor layer 107, and the surfaces of the first fin 101' and the second fin 102' using an ALD process. The present application does not limit the specific method of forming the gate dielectric layer 109.

[0091] like Figure 12 As shown, in some examples, a sacrificial gate layer 110 spanning the semiconductor layer 107, the first fin 101', and the second fin 102' can be formed on the gate dielectric layer 109 by one or more thin film deposition processes such as CVD, PVD, or ALD. The sacrificial gate layer 110 can cover at least a portion of the exposed semiconductor layer 107, the first fin 101', and the second fin 102'.

[0092] Continue to refer Figure 12 In some examples, a sacrificial gate material covering the semiconductor layer 107, the first fin 101', the second fin 102', and the shallow trench isolation structure 108 can be formed on the gate dielectric layer 109. Optionally, a patterned hard mask layer 111 (e.g., nitride) can be formed on the sacrificial gate material, and using the hard mask layer 111 as a mask, a portion of the sacrificial gate material is removed to form a sacrificial gate layer 110 spanning the first fin 101' and the second fin 102'. Optionally, the size of the sacrificial gate layer 110 in the Y direction is, for example, greater than or equal to 20 nm. In some examples, the portion of the semiconductor layer 107 covered by the sacrificial gate layer 110 can serve as a channel region.

[0093] Optionally, the hard mask layer 111 may be retained until it is removed in a subsequent appropriate step. The sacrificial gate layer 110 may occupy the gate position and be removed and replaced with a suitable gate material in a subsequent step. For example, the material forming the sacrificial gate layer 110 may include polysilicon. Figure 13 As shown, in some examples, a dielectric layer 140 circumferentially surrounding the sacrificial gate layer 110 may be formed on the gate dielectric layer 109. Optionally, the size of the dielectric layer 140 in the Y direction may be smaller than the size of the semiconductor layer 107 and the first fin 101' and the second fin 102' in the Y direction, thereby exposing the ends of the semiconductor layer 107 and the first fin 101' and the second fin 102' in the Y direction. In some examples, the size of the dielectric layer 140 in the Y direction is, for example, greater than or equal to 10 nm. Optionally, the exposed end of the semiconductor layer 107 in the Y direction may serve as a source / drain region. In some cases, the dielectric layer 140 may be used to separate the sacrificial gate layer 110 and the channel region thereunder from the source / drain region and to protect the channel region from being damaged by subsequent ion implantation processes. In other cases, the dielectric layer 140 may be used to electrically isolate the sacrificial gate layer 110 from adjacent semiconductor devices. In addition, the dielectric layer 140 may also be used to define a subsequently formed gate structure (for example, Figure 19 The gate structure 121 shown in FIG. Alternatively, the dielectric layer 140 may include a spacer layer 112 and an interlayer dielectric layer (ILD) 113. In some examples, the spacer layer 112 and the interlayer dielectric layer 113 surrounding the gate dielectric layer 109 may be sequentially formed on the sacrificial gate dielectric layer 110 using one or more thin film deposition processes such as CVD, PVD, or ALD. In some examples where the hard mask layer 111 is retained, the hard mask layer 111 may be used as part of the spacer layer 112, and the remaining portion of the spacer layer 112 may be formed on this basis.

[0094] For example, the top surfaces of the spacer layer 112 and the interlayer dielectric layer 113 away from the substrate 100 can be thinned by, for example, a CMP process to expose the top surface of the sacrificial gate dielectric layer 110. Alternatively, the material of the spacer layer 112 can include, for example, silicon nitride. Alternatively, the material of the interlayer dielectric layer 113 can include, for example, an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0095] In one embodiment of the present application, after forming the spacer layer 112, the semiconductor layer 107 and the exposed ends of the first fin 101' and the second fin 102' may be heavily doped with conductive particles. For example, the spacer layer 112 may be used as a mask to perform heavy doping of the first conductivity type on the exposed ends of the semiconductor layer 107 and the first fin 101' by an ion implantation process, for example, doping with P-type conductive particles, the doping concentration of which may be, for example, 10 15 cm -3 ~10 20 cm -3 Optionally, the exposed end portion of the second fin 102 ′ may be doped with a second conductivity type opposite to the first conductivity type, for example, with N-type conductive particles.

[0096] like Figure 14 As shown, after the dielectric layer 140 is formed, the sacrificial gate layer 110 can be removed by, for example, a wet etching process, a dry etching process, or a combination thereof, thereby releasing the space 120 ( Figure 16 ), and expose the gate dielectric layer 109 in the space 120.

[0097] like Figure 15 As shown, in some examples, a third mask layer 114 covering the second fin 102 ′ can be formed on the gate dielectric layer 109 by one or more thin film deposition processes such as CVD, PVD, and ALD. Alternatively, a mask layer (not shown) and a photoresist (not shown) can be formed on the space 120 and the shallow trench isolation structure 108, and then the photoresist can be patterned using a mask (not shown). Subsequently, the pattern on the photoresist can be transferred to the mask layer by a process such as etching to form the third mask layer 114.

[0098] In some examples, the third mask layer 114 can be used as a mask to remove a portion of the gate dielectric layer 109 located above the first fin 101' and the semiconductor layer 107 using a dry etching process such as ion milling, plasma etching, reactive ion etching, and laser etching. Optionally, a portion of the gate dielectric layer 109 located above the shallow trench isolation structure 108 can also be removed. Optionally, the third mask layer 114 can also be removed using a suitable etching process. In some examples, under the same etching process, the third mask layer 114 has a high etching selectivity with the spacer layer 112, the interlayer dielectric layer 113, and the gate dielectric layer 109. This allows the spacer layer 112, the interlayer dielectric layer 113, and the gate dielectric layer 109 located above the first fin 101' to remain when the third mask layer 114 is removed. Optionally, the etching selectivity of the third mask layer 114 to the spacer layer 112 is, for example, 10 to 20:1. Optionally, the etching selectivity ratio of the third mask layer 114 to the interlayer dielectric layer 113 is, for example, 10-20:1, and the etching selectivity ratio of the third mask layer 114 to the gate dielectric layer 109 is, for example, 10-20:1.

[0099] In some examples, the third mask layer 114 may be used as a mask to remove the first fin 101'. Optionally, the third mask layer 114 may be further removed to form a Figure 16-Figure 18 The structure shown in Figure 16 In the example shown, at least a portion of the inner wall of the dielectric layer 140 (eg, the spacer layer 112), the top surface of the shallow trench isolation structure 108, the substrate 100, and the semiconductor layer 107 are exposed. Optionally, the remaining portion of the gate dielectric layer 109 on the second fin 102' may be exposed.

[0100] Continue to refer Figure 16 In some examples, after a portion of the gate dielectric layer 109 is removed, a suitable etching process (e.g., an isotropic wet etching process) may be used to remove the first fin 101'. Optionally, under the same etching process, the first fin 101' and the semiconductor layer 107 have a predetermined etching selectivity, so that the semiconductor layer 107 can be retained when the first fin 101' is removed. Exemplarily, the etching selectivity of the first fin 101' to the semiconductor layer 107 is greater than or equal to 10:1. Optionally, the formation method and process parameters of the first fin 101' and the semiconductor layer 107 may be adjusted, such as adjusting the process temperature, so that under the same etching process, the etching selectivity of the first fin 101' to the semiconductor layer 107 is greater than or equal to 20:1.

[0101] S4: forming a gate structure that passes through the region between the side portions and circumferentially surrounds the top portion.

[0102] Figure 19FIG. 1 is a partial perspective schematic diagram of a semiconductor structure after forming a gate structure according to a manufacturing method of an embodiment of the present application. Figure 19 As shown, in some examples, a gate structure 121 may be formed on the inner wall of the dielectric layer 140 (e.g., on the spacer layer 112), the top surface of the shallow trench isolation structure 108, the exposed portion of the substrate 100, the semiconductor layer 107, and the second fin 102'. Optionally, the gate structure 121 may pass through the region between the side portion 1072 and the side portion 1073 of the semiconductor layer 107 and circumferentially surround the top portion 1071 of the semiconductor layer 107. Optionally, the gate structure 121 may include a high-k dielectric layer 116, a work function stack, and a conductive layer 115 formed sequentially.

[0103] In some examples, a dielectric layer 116 may be formed on the spacer layer 112, the top surface of the shallow trench isolation structure 108 and the exposed portion of the substrate 100, the semiconductor layer 107, and the remaining portion of the gate dielectric layer 109 by one or more thin film deposition processes such as CVD, PVD, and ALD. The dielectric layer 116 may include, for example, a high-k dielectric constant material with a dielectric constant K ranging from 10 to 40, thereby effectively controlling the path from the gate to the channel potential, thereby suppressing increasing gate leakage current and worsening short channel effects.

[0104] In some examples, the first type work function layer 117 can be formed on the dielectric layer 116 by one or more thin film deposition processes such as CVD, PVD, and ALD. Optionally, the material used for the first type work function layer 117 includes, for example, any one of TiN, TaN, TiNx, TaNx, TiNSi, and combinations thereof.

[0105] In some examples, a second type of work function layer 118 different from the first type may be deposited on the first type of work function layer 117. Optionally, the material for the second type of work function layer 118 includes, for example, any one of Al, TiAl, TiAlx, TiAlCx, TiCx, TaCx, and combinations thereof.

[0106] In some examples, a third type of work function layer 119 of the same type as the first type of work function layer 117 may be formed on the portion of the second type of work function layer 118 located on the semiconductor layer 107. Optionally, the material of the third type of work function layer 119 located on the second type of work function layer 118 may be the same as the material of the first type of work function layer 117. Optionally, the thickness of the third type of work function layer 119 ranges from 3 nm to 6 nm. By adjusting the thickness of the third type of work function layer 119, a low threshold voltage of the semiconductor device can be achieved with low leakage current.

[0107] In some examples, one or more conductive materials, such as tungsten, cobalt, nickel, copper, aluminum, titanium nitride, and tantalum nitride, can be used to fill the space defined by the work function stack to form a conductive layer 115 surrounding a top portion 1071 (e.g., a channel region) of the semiconductor layer 107. In some examples, the conductive layer 115 can be formed by one or more processes selected from the group consisting of CVD, PVD, ALD, sputtering, thermal evaporation, and electron beam evaporation.

[0108] like Figure 20 As shown, in some examples, after forming the gate structure 121, the spacer layer 112 and the interlayer dielectric layer 113 can be removed to form a gate-around field-effect transistor and a fin field-effect transistor. For example, when the semiconductor layer 107 is doped with P-type conductive particles and the second fin 102' is doped with N-type conductive particles, a P-type gate-around field-effect transistor and an N-type fin field-effect transistor can be formed simultaneously.

[0109] It should be understood that the manufacturing method provided in the present application can also form only gate-wrap field effect transistors as needed, or simultaneously form N-type gate-wrap field effect transistors and P-type fin field effect transistors as needed.

[0110] On the one hand, the manufacturing method of the semiconductor device provided in the present application can form a conformal semiconductor layer as a channel region and source / drain region on the basis of the fin field effect transistor manufacturing process, and then obtain a cavity by removing the sacrificial gate layer 110 and the first fin 101' under the channel region, and form a gate-around field effect transistor by filling the cavity.

[0111] On the other hand, the manufacturing method of the present application is compatible with the existing fin field effect transistor manufacturing process, and the gate-around field effect transistor and the fin field effect transistor can be simultaneously produced by masking the first mask layer 106, the second mask layer 122 and the third mask layer 114. For example, a CMOS device with excellent characteristics that is compatible with the gate-around field effect transistor and the fin field effect transistor can be produced.

[0112] In another aspect of the present application, a semiconductor device is provided, which includes at least one semiconductor layer (eg Figure 21 The semiconductor layer 107 is shown as a semiconductor layer 107, and the semiconductor layer 107 has a semiconductor layer located on a substrate (eg Figure 21 The semiconductor device further includes a gate structure (eg, a top portion 1071 on the substrate 100) and a side portion 1072 and a side portion 1073 extending into the substrate 100. Figure 21 The gate structure 121 shown in FIG. 1 may pass through a region between the side portion 1072 and the side portion 1073 of the semiconductor layer 107 and circumferentially surround the top portion 1071 of the semiconductor layer 107 .

[0113] As an option, the two end portions of the semiconductor layer 107, for example, along the Y direction (for example, at least a portion where the top 1071 contacts the side portion 1072 and the side portion 1073, respectively) may be exposed, and at least a portion of the two exposed end portions may be doped with a first conductive type to form a first conductive portion (not shown). Optionally, the first conductive portion may be, for example, a heavily P-type doped portion. Optionally, the heavily P-type doped portion may serve as a source region and a drain region, and the top 1071 of the semiconductor layer 107 may serve as a channel region, which may extend between the source region and the drain region, so that the semiconductor device may be a P-type gate-around field-effect transistor. As another option, the two end portions may also be heavily N-type doped to form an N-type gate-around field-effect transistor.

[0114] Another aspect of the present application provides another semiconductor device 200, such as Figure 20 As shown, the semiconductor device 200 includes a substrate 100 , at least one fin 102 ′ protruding from the substrate 100 , a semiconductor layer 107 , a shallow trench isolation structure 108 , and a gate structure 121 .

[0115] like Figure 21 As shown, in some examples, the semiconductor layer 107 may have a top 1071 away from the substrate 100 and a side portion 1072 and a side portion 1073 extending into the substrate 100. Optionally, the semiconductor layer 107 and the fin 102' are made of different materials. In some examples, the material of the semiconductor layer 107 includes, for example, silicon germanium, and the material of the fin 102' includes, for example, silicon.

[0116] In some examples, the semiconductor layer 107 and the fin 102' may be spaced apart. Optionally, a shallow trench isolation structure 108 may be disposed on the substrate 100 to electrically separate the fin 102' and the semiconductor layer 107. Optionally, the height of the shallow trench isolation structure 108 in a direction perpendicular or substantially perpendicular to the substrate 100 is less than the height of the semiconductor layer 107 and the fin 102'.

[0117] In some examples, the distance between the top portion 1071 of the semiconductor layer 107 and the substrate 100 ranges from 400 angstroms to 900 angstroms. Alternatively, the thickness of the top portion 1071 of the semiconductor layer 107 in a direction perpendicular or substantially perpendicular to the substrate 100 ranges from 100 angstroms to 300 angstroms. Alternatively, the height of the fin 102' protruding from the substrate 100 ranges from 400 angstroms to 900 angstroms.

[0118] like Figure 21As shown, in some examples, the gate structure 121 can be disposed on the shallow trench isolation structure 108. Optionally, the gate structure 121 can also pass through the area between the side portion 1072 and the side portion 1073 of the semiconductor layer 107 and circumferentially surround the top 1071 of the semiconductor layer 107. Optionally, the gate structure 121 can also span the fin 102'. As an option, the gate structure 121 can be disposed on a portion of the top surface and a pair of side surfaces of the fin 102'.

[0119] In some examples, at least a portion of the fin 102' (for example, the two ends along the Y direction) may be exposed, and at least a portion of the two exposed ends may be doped with a second conductivity type opposite to the first conductivity type to form a second conductive portion, which is heavily doped. Optionally, the second conductive portion may be a heavily N-type doped portion. Exemplarily, the heavily N-type doped portion may serve as a source region and a drain region, and the portion under the gate structure 121 may serve as a channel region. In some examples, the portion of the semiconductor device 200 including the fin 102' may be an N-type fin field effect transistor. In other examples, the second type of doping may also be P-type doping, which is not limited in this application.

[0120] In an example where the semiconductor device 200 includes a P-type gate-around field effect transistor and an N-type fin field effect transistor, the semiconductor device 200 may be, for example, a CMOS inverter.

[0121] like Figure 20 and Figure 21 As shown, in some examples, the gate structure 121 includes a dielectric layer 116, a work function stack, and a conductive layer 115, which are sequentially arranged from the outside to the inside. For example, the dielectric layer 116 may include a high dielectric constant material with a dielectric constant K ranging from 10 to 40, thereby effectively controlling the path from the gate to the channel potential, thereby suppressing the increasing gate leakage current and the worsening short channel effect.

[0122] Optionally, the portion of the work function stack located at the fin 102' includes: a first-type work function layer 117 and a second-type work function layer 118 arranged in sequence. Optionally, the material used for the first-type work function layer 117 includes, for example, any one of TiN, TaN, TiNx, TaNx, TiNSi, and combinations thereof. Optionally, the material used for the second-type work function layer 118 includes, for example, any one of Al, TiAl, TiAlx, TiAlCx, TiCx, TaCx, and combinations thereof.

[0123] Optionally, the portion of the work function stack located on the semiconductor layer 107 includes a first type of work function layer 117, a second type of work function layer 118 different from the first type, and a third type of work function layer 119 that is the same as the first type, stacked in sequence. Optionally, the material of the third type of work function layer 119 may be the same as that of the first type of work function layer 117. Optionally, the thickness of the third type of work function layer 119 ranges from 3 nm to 6 nm. In some examples, the work function of a portion of the conductive layer (gate) 115 located on the fin 102 'can be adjusted by adjusting the thickness of the third type of work function layer 119, thereby achieving a low threshold voltage of the semiconductor device 200 under low leakage current conditions.

[0124] like Figure 20 and Figure 21 As shown, in some examples, the space defined by the work function stack can be filled with one or more conductive materials such as tungsten, cobalt, nickel, copper, aluminum, titanium nitride, and tantalum nitride to form a conductive layer 115 surrounding the top 1071 of the semiconductor layer 107.

[0125] Since the contents and structures involved in the above description of the manufacturing method 1000 may be fully or partially applicable to the semiconductor device 200 described herein, related or similar contents will not be described in detail.

[0126] Although an exemplary manufacturing method and structure of a semiconductor device are described herein, it is understood that one or more features may be omitted, replaced, or added to the structure of the semiconductor device. In addition, the illustrated layers and their materials are merely exemplary.

[0127] Some embodiments of the present application further provide a three-dimensional memory 404, such as Figure 22 As shown, in some examples, a three-dimensional memory 404 includes a coupled memory array 102 and a peripheral circuit 101, where the peripheral circuit 101 includes, for example, the semiconductor device 200 described above. In some embodiments, the memory array 102 and the peripheral circuit 101 can be arranged on the same chip. In other embodiments, the memory array 102 can be arranged on an array chip, and the peripheral circuit 101 can be arranged on a different chip (e.g., implemented using complementary metal oxide semiconductor (CMOS) technology and referred to as a CMOS chip). The array chip and the CMOS chip can be electrically coupled together through processes such as bonding. In some embodiments, the three-dimensional memory 404 is an integrated circuit (IC) package that encapsulates one or more array chips and CMOS chips.

[0128] Optionally, the three-dimensional memory 404 can be configured to store data in the memory array 102 and perform operations in response to received commands (CMD). In some embodiments, the three-dimensional memory 404 can receive write commands, read commands, erase commands, etc. and perform operations accordingly.

[0129] Typically, the memory array 102 may include one or more memory planes 160, and each memory plane in the memory plane 160 may include a plurality of memory blocks (e.g., Figure 22 Block-1 to Block-N shown). In some examples, concurrent operations may occur at different storage planes 160.

[0130] In some embodiments, the memory array 102 may be, for example, a flash memory array and may be implemented using 3D NAND flash memory technology. In some embodiments, the peripheral circuit 101 includes a row decoder (word line driver) 110, a page buffer (sense amplifier) 120, a data input / output (I / O) circuit 130, a voltage generator 140, and a control circuit 150 coupled together.

[0131] In some examples, row decoder (word line driver) 110 can be configured to drive a word line (WL) based on a row address (R-ADDR) from control circuit 150 and a word line voltage generated by voltage generator 140. In some embodiments, row decoder (word line driver) 110 can also select / deselect and drive a source select line (SSL) and a drain select line (DSL).

[0132] In some examples, page buffer (sense amplifier) 120 is coupled to the bit lines (BL) of memory array 102 and is configured to buffer data during read and write operations according to control signals from control circuit 150. Alternatively, page buffer (sense amplifier) 120 can sense a low-power signal representing a stored data bit from the bit line (BL) during a read operation.

[0133] In some examples, the peripheral circuit 101 further includes a column decoder (bit line driver) not shown, which may be configured to be controlled by the control circuit 150 .

[0134] In some examples, data I / O circuit 130 is coupled to page buffer 120 via data line DR. In one example (e.g., during a read operation), data I / O circuit 130 is configured to upload data read from memory array 102 to external circuitry (e.g., memory controller 406) via page buffer 120 and BL.

[0135] In some examples, voltage generator 140 is configured to generate appropriate voltages for proper operation of three-dimensional memory 404. For example, voltage generator 140 may generate appropriate read voltages, program voltages, or erase voltages during operation of three-dimensional memory 404.

[0136] In some examples, the control circuit 150 is configured to receive a command (CMD) and an address (ADDR), and based on the command and address, provide control signals to circuits such as the row decoder 110, the page buffer 120, the data I / O circuit 130, and the voltage generator 140. For example, the control circuit 150 can generate a row address R-ADDR and a column address C-ADDR based on the address ADDR, and provide the row address R-ADDR to the row decoder 110 and the column address to the data I / O circuit 130. In other examples, the control circuit 150 can control the voltage generator 140 to generate appropriate voltages based on the received CMD. The control circuit 150 can coordinate with other circuits to provide signals to the memory array 102 at appropriate times and voltages.

[0137] like Figure 23 As shown, in some examples, system 400 may include a host 408 and a memory system 402 having one or more three-dimensional memories 404 and a memory controller 406. Host 408 may be a processor of an electronic device, such as a central processing unit (CPU), or a system on a chip (SoC), such as an application processor (AP). Host 408 may be configured to send or receive data stored in three-dimensional memory 404. Alternatively, system 400 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein.

[0138] According to some embodiments, memory controller 406 is coupled to three-dimensional memory 404 and host 408 and is configured to control three-dimensional memory 404. Memory controller 406 can manage data stored in three-dimensional memory 404 and communicate with host 408. In some embodiments, memory controller 406 is designed to operate in low-duty-cycle environments, such as secure digital (SD) cards, compact flash (CF) cards, universal serial bus (USB) flash drives, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones. In some embodiments, memory controller 406 is designed to operate in high-duty-cycle environments, such as SSDs or embedded multimedia cards (eMMCs) used for data storage in mobile devices (such as smartphones, tablets, laptops, etc.) and enterprise storage arrays. Memory controller 406 can be configured to control operations of three-dimensional memory 404, such as read, erase, and program operations. The memory controller 406 may also be configured to manage various functions related to data stored or to be stored in the three-dimensional memory 404, including bad block management, garbage collection, logical-to-physical address translation, wear leveling, and the like. In some embodiments, the memory controller 406 may also be configured to process error correction code (ECC) for data read from or written to the three-dimensional memory 404. Any other suitable functions may also be performed by the memory controller 406, such as formatting the three-dimensional memory 404. The memory controller 406 may communicate with an external device (e.g., the host 408) according to a specific communication protocol. For example, the memory controller 406 may communicate with the external device using at least one of various interface protocols, such as the USB protocol, the MMC protocol, the Peripheral Component Interconnect (PCI) protocol, the PCI-Express (PCI-E) protocol, the Advanced Technology Attachment (ATA) protocol, the Serial ATA protocol, the Parallel ATA protocol, the Small Computer Small Device Interface (SCSI) protocol, the Enhanced Small Disk Interface (ESDI) protocol, the Integrated Drive Electronics (IDE) protocol, the FireWire protocol, and the like.

[0139] The memory controller 406 and the one or more three-dimensional memories 404 can be integrated into various types of storage devices, for example, included in the same package, such as a universal flash memory (UFS) package or an eMMC package. That is, the memory system 402 can be implemented as and packaged into different types of terminal electronic products. Figure 24In one example shown, the memory controller 406 and the single three-dimensional memory 404 may be integrated into a memory card 502. The memory card 502 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 502 may further include a computer that connects the memory card 502 to a host (e.g., Figure 23 The host 408 in the memory card connector 504 is electrically coupled. Figure 25 In another example shown, the memory controller 406 and the plurality of three-dimensional memories 404 may be integrated into the SSD 506. The SSD 506 may further include a processor that interfaces the SSD 506 with a host (e.g., Figure 23 In some embodiments, the storage capacity and / or operating speed of the SSD 506 is greater than the storage capacity and / or operating speed of the memory card 502.

[0140] The above description is merely an embodiment of the present application and an illustration of the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to the technical solutions formed by a specific combination of the above-mentioned technical features, but should also cover other technical solutions formed by any combination of the above-mentioned technical features or their equivalents without departing from the technical concept. For example, a technical solution formed by replacing the above-mentioned features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method for manufacturing a semiconductor device, comprising: removing a portion of the substrate to form at least one first fin; forming a semiconductor layer on a top surface and a pair of side surfaces of the first fin, the semiconductor layer including a top portion located on the top surface and side portions located on the pair of side surfaces; removing the first fin; as well as A gate structure is formed passing through a region between the side portions and circumferentially surrounding the top portion.

2. The method according to claim 1, wherein The first fin and the semiconductor layer are made of different materials.

3. The method according to claim 1, wherein In the same etching process, the first fin and the semiconductor layer have a predetermined etching selectivity ratio, so that the semiconductor layer is retained when the first fin is removed.

4. The method according to claim 2, wherein: The first fin includes silicon, and the semiconductor layer includes silicon germanium.

5. The method according to claim 1, wherein Forming the first fin includes: Etching the substrate to form a plurality of protruding and discrete initial fins, the plurality of initial fins including at least one first initial fin; forming an isolation structure on the substrate to separate adjacent initial fins, with top surfaces of the initial fins exposed; and A portion of the first preliminary fin is removed through a pair of side surfaces and an exposed top surface of the first preliminary fin opposite to the isolation structure to form the first fin. 6 . The method according to claim 5 , wherein the plurality of initial fins include at least one second initial fin, wherein: Removing a portion of the first initial fin includes: forming a first mask layer on the isolation structure, covering a top surface of the second initial fin and a portion of a top surface of the first initial fin; removing a portion of the first initial fin located on a pair of side surfaces and a top surface thereof; removing a portion of the first mask layer located on a top surface of the first initial fin; forming a second mask layer on a pair of exposed side surfaces of the first initial fin; and Using the second mask layer as a mask, another portion of the first initial fin located on the top surface thereof is removed.

7. The method according to claim 6, further comprising: removing a portion of the isolation structure to expose a portion of the first fin and the second initial fin away from the substrate; as well as A portion of the at least one second preliminary fin is removed to form at least one second fin.

8. The method according to claim 7, further comprising: performing a first conductivity type doping on the semiconductor layer; as well as The second fin is doped with a second conductivity type opposite to the first conductivity type.

9. The method according to claim 7, further comprising: forming a gate dielectric layer covering the semiconductor layer and the first fin and the second fin on the remaining portion of the isolation structure; forming a sacrificial gate layer on the gate dielectric layer, spanning the first fin and the second fin; as well as A dielectric layer is formed on the gate dielectric layer and circumferentially surrounds the sacrificial gate layer. 10 . The method according to claim 9 , wherein removing the first fin comprises: removing the sacrificial gate layer; forming a third mask layer on the second fin; as well as Using the third mask layer as a mask, remove at least a portion of the gate dielectric layer located on the first fin and the semiconductor layer.

11. The method according to claim 10, wherein: Forming a gate structure surrounding a top portion of the semiconductor layer includes: forming a dielectric layer and a work function stack in sequence on an inner wall of the dielectric layer, the semiconductor layer, and the second fin; and A conductive material is filled in the space defined by the work function stack to form a conductive layer surrounding the top of the semiconductor layer and crossing the second fin.

12. The method according to claim 11, wherein Forming the work function stack includes: forming a first type of work function layer on the dielectric layer; forming a second type of work function layer different from the first type on the first type of work function layer; and The first type of work function layer is formed on a portion of the second type of work function layer located on the semiconductor layer.

13. Semiconductor devices, including: at least one semiconductor layer having a top portion located above the substrate and two side portions extending into the substrate; as well as a gate structure passing through a region between the side portions and circumferentially surrounding the top portion; The top and the side are formed based on the same thin film deposition process or the same selective epitaxial process.

14. The semiconductor device according to claim 13, further comprising: at least one fin protruding from the substrate, the fin being spaced apart from the semiconductor layer, wherein the gate structure spans the fin; and A shallow trench isolation structure is located on the substrate to separate the adjacent fins and the semiconductor layer.

15. The semiconductor device according to claim 13, wherein At least a portion of the top of the semiconductor layer that contacts the two side portions is exposed, and the at least a portion of the semiconductor layer includes a first conductive type portion; and at least a portion of the fin is exposed, and the at least a portion of the fin includes a second conductive type portion that is opposite to the first conductive type.

16. The semiconductor device according to claim 14, wherein The gate structure includes a dielectric layer, a work function stack and a conductive layer which are sequentially arranged from the outside to the inside.

17. The semiconductor device according to claim 16, wherein The portion of the work function stack located in the semiconductor layer includes: a first type of work function layer, a second type of work function layer, and a first type of work function layer stacked in sequence, and the portion of the work function stack located in the fin includes: the first type of work function layer and the second type of work function layer arranged in sequence.

18. A three-dimensional memory, comprising: Storage arrays; as well as A peripheral circuit is coupled to the memory array and includes: the semiconductor device according to any one of claims 13 to 17.

19. A memory system comprising: The three-dimensional memory of claim 18, configured to store data; as well as A memory controller is coupled to the three-dimensional memory and configured to control the three-dimensional memory.

20. The memory system of claim 19, comprising: Solid-state drive or memory card.

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