A three-dimensional integrated embedded microchannel active heat dissipation packaging method and structure

Abstract

The invention discloses a three-dimensional integrated embedded microchannel active heat dissipation packaging method and structure, belonging to the field of integrated circuit packaging. The substrate is etched and filled to form a TSV copper column and thinned to form a silicon-based substrate; a microchannel groove and an inlet and outlet channel blind hole are etched on the silicon-based substrate; the microchannel cover plate and the silicon-based substrate are silicon-silicon bonded; the TSV adapter chip is flip-chip welded to the silicon-based substrate, and the heterogeneous chip is bonded to the microchannel cover plate; the gap between the bumps at the flip-chip welding of the TSV adapter chip is filled with bottom filling glue; the flip-chip TSV adapter chip and the heterogeneous chip are potted and cured to reconstruct to form a resin wafer; the copper column of the TSV adapter chip and the bumps of the heterogeneous chip are thinned; multi-layer interconnection rewiring is formed on the resin wafer; the silicon-based substrate is thinned; the heterogeneous chip is fixed in the chip slot, and the RDL and UBM multi-layer interconnection metal rewiring are realized in sequence; solder balls are planted at the UBM, and then the three-dimensional integrated silicon-based wafer is diced to form a final package.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit packaging, and in particular to a three-dimensional integrated embedded microchannel active heat dissipation packaging method and structure. Background Art

[0002] With the development of microelectronics and microelectromechanical systems (MEMS) technology, especially the emergence of new interconnect technologies such as flip chip (FC) and multi-chip module (MCM), chip integration and performance are constantly improving. The rapid development of chip miniaturization and high integration has brought great challenges to the effective heat dissipation of electronic chips. Especially in three-dimensional packaging systems, more and more attention is paid to the thermal management of the package. This is because: (1) Three-dimensional packaging systems often integrate multiple chips, which generate a lot of heat, but the packaging area has not increased significantly, and it is more difficult to dissipate heat at the bottom of the three-dimensional stack; (2) Under high power density, due to the difference in thermal expansion coefficients of the stacked materials in the three-dimensional packaging structure, the large wall temperature rise will generate thermal-mechanical stress at the interface between different materials, seriously affecting the reliability of the system.

[0003] In three-dimensional stacked chips, heat flow is mainly transmitted in the vertical direction. The commonly used three-dimensional packaging heat dissipation method is to attach a cold plate and a heat sink to the back of the packaging structure to transfer heat to the system environment or air. However, this heat dissipation structure is not in direct contact with the chip, and there are plastic packaging materials and multi-layer chips in the middle. Due to the low thermal conductivity of the plastic packaging material and the large thermal resistance of the multi-layer material interface, the heat cannot be transferred out in a timely and efficient manner, which leads to poor packaging reliability and affects its use. The microfluidic active heat dissipation technology integrates the microfluidic channel inside the package body, and removes the heat generated by the chip inside the package body through fluid flow. Its heat transfer efficiency is much greater than that of heat sink type heat dissipation, which can ensure that electronic devices work at a specified temperature. Summary of the invention

[0004] The object of the present invention is to provide a three-dimensional integrated embedded microchannel active heat dissipation packaging method and structure to solve the problem of low heat dissipation efficiency of existing three-dimensional packaging.

[0005] In order to solve the above technical problems, the present invention provides a three-dimensional integrated embedded microchannel active heat dissipation packaging method, comprising:

[0006] Providing a substrate, etching and filling holes on it to form TSV copper pillars, and thinning it to make it leaky, so as to make a silicon-based substrate;

[0007] Etching microfluidic channels and blind holes for inlet and outlet channels on a silicon substrate;

[0008] The silicon microfluidic cover plate is bonded to the silicon-based substrate to seal the microfluidic channel and form a microfluidic unit;

[0009] The TSV transfer chip with bumps is flip-chip soldered to the silicon substrate; the heterogeneous chip with bumps is bonded to the microchannel cover plate through thermal conductive glue using the wafer reconstruction process;

[0010] Use underfill to fill the gaps between the bumps of the flip-chip of the TSV adapter chip;

[0011] Using wafer-level molding technology, the flip-chip TSV adapter chip and heterogeneous chip are encapsulated with resin molding compound, and then cured and reconstructed to form a resin wafer.

[0012] Thin the resin wafer to expose the copper pillars of the TSV transfer chip and the bumps of the heterogeneous chip;

[0013] Using wafer-level rewiring process to form multi-layer interconnect rewiring on resin wafer;

[0014] The bottom of the silicon-based substrate is thinned to expose the TSV copper pillars and microchannel grooves, and a chip groove is etched at the bottom of the silicon-based substrate;

[0015] The re-provided heterogeneous chip is fixed in the chip slot by thermal conductive glue, and the RDL and UBM multi-layer interconnect metal rewiring is realized in sequence by Pi glue and wafer-level multi-layer rewiring process;

[0016] By using the wafer-level ball implantation process, solder balls are implanted at the UBM of the reconstructed multi-layer silicon-based wafer, and then the three-dimensional integrated silicon-based wafer is diced to form the final package.

[0017] Optionally, the microfluidic unit is composed of an upper surface of a silicon-based substrate and a silicon microfluidic cover plate that are sealed and connected.

[0018] Optionally, the substrate material of the heterogeneous chip includes Si, GaAs, GaN and SiC; the bump materials grown on the heterogeneous chip and the TSV adapter chip include Cu, CuSn, CuNiSn, CuNiSnAg, SnPb and SnAgCu.

[0019] Optionally, the flip-chip welding method of the heterogeneous chip and the TSV adapter chip includes reflow welding and hot pressing welding.

[0020] Optionally, the method of filling the gaps between the bumps at the flip-chip solder joint of the TSV adapter chip with the underfill includes a dry film pressing process and a dispensing process.

[0021] Optionally, the wafer-level multi-layer rewiring process is a wiring process in which a passivation layer and a metal layer overlap multiple times.

[0022] Optionally, the multi-layer interconnect metal rewiring includes at least one metal layer; the thickness of the passivation layer is greater than the thickness of the formed metal layer, and the passivation layer covers the metal layer; the thickness of the metal layer is not less than 1 μm, and the thickness of the passivation layer is not less than 3 μm.

[0023] Optionally, the process of implanting solder balls at the UBM includes wafer-level implantation, single-chip implantation and solder paste printing; the composition of the solder balls includes SnPb and SnAgCu.

[0024] The present invention also provides a three-dimensional integrated embedded microchannel active heat dissipation packaging structure, which is prepared by the three-dimensional integrated embedded microchannel active heat dissipation packaging method.

[0025] The three-dimensional integrated embedded microchannel active heat dissipation packaging method and structure provided by the present invention has the following beneficial effects:

[0026] (1) The silicon substrate chip embedding structure and the microchannel cover chip bonding structure are used to make the heat dissipation microchannel directly contact with the back of the functional chip to form a direct heat dissipation channel, greatly reducing thermal resistance and achieving faster heat dissipation;

[0027] (2) The microfluidic structure with sub-micron or millimeter size is directly embedded in the three-dimensional integrated package. The coolant flows in from the inlet and takes away the heat generated by the chip inside the package. This is a direct and efficient substrate-level active heat dissipation method, which realizes the multi-dimensional and multi-scale thermal management of the three-dimensional packaging system.

[0028] (3) The embedded silicon substrate fan-out technology and resin-based wafer reconstruction technology are used to achieve multi-chip three-dimensional heterogeneous integration, and the chip directly fans out the IO, which greatly reduces the thermal resistance on both sides of the package, further improving the heat dissipation efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a schematic diagram of the process of the three-dimensional integrated embedded microchannel active heat dissipation packaging method provided by the present invention;

[0030] Figure 2 It is a schematic diagram of manufacturing a silicon-based substrate;

[0031] Figure 3 It is a schematic diagram of etching microfluidic channels and blind holes for inlet and outlet channels on a silicon substrate;

[0032] Figure 4 It is a schematic diagram of silicon-silicon bonding between a silicon microfluidic cover plate and a silicon-based substrate to achieve microfluidic channel sealing;

[0033] Figure 5 It is a schematic diagram of flip-chip bonding of a heterogeneous chip and a TSV adapter chip;

[0034] Figure 6 It is a schematic diagram of filling the gaps between the bumps at the flip-chip of the TSV transfer chip with underfill;

[0035] Figure 7 It is a schematic diagram of using a resin molding compound to pot and solidify the flip-chip TSV adapter chip and the heterogeneous chip to form a resin wafer;

[0036] Figure 8 It is a schematic diagram of thinning the resin wafer to expose the copper pillars of the TSV transfer chip and the bumps of the heterogeneous chip;

[0037] Fig. 9 It is a schematic diagram of forming multi-layer interconnect rewiring on a resin wafer using a wafer-level rewiring process;

[0038] Fig.10 It is a schematic diagram of thinning the bottom of the silicon-based substrate to expose the TSV copper pillars and the inlet and outlet channels of the microchannels and etching a chip groove at the bottom of the silicon-based substrate;

[0039] Fig.11 It is a schematic diagram of fixing heterogeneous chips in chip slots and forming multi-layer interconnect metal rewiring;

[0040] Fig.12 It is a schematic diagram of implanting solder balls at the UBM of a reconstructed multi-layer silicon-based wafer. DETAILED DESCRIPTION

[0041] The following is a further detailed description of a three-dimensional integrated embedded microfluidic active heat dissipation packaging method and structure proposed by the present invention in combination with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description and claims. It should be noted that the drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0042] The present invention provides a three-dimensional integrated embedded microchannel active heat dissipation packaging method, the process is as follows: Figure 1 As shown, the following steps are included:

[0043] Step S11, providing a substrate 111, etching and filling holes to form TSV copper pillars 112, and thinning to make them leak out, so as to form a silicon-based substrate, such as Figure 2 As shown;

[0044] Step S12, etching the microchannel groove 113 and the inlet and outlet channel blind holes on the silicon substrate (the inlet and outlet channel blind holes are very long and are obviously different from the grooves, not shown in the figure), such as Figure 3 As shown;

[0045] Step S13, the silicon microfluidic cover plate 114 is bonded to the silicon-based substrate to seal the microfluidic channel and form a microfluidic unit. Figure 4 As shown;

[0046] Step S14, the TSV transfer chip 115 grows bumps, and then the TSV transfer chip 115 with bumps is flip-chip soldered to the silicon-based substrate; the heterogeneous chip 116 (including chip Die-1 and chip Die-2) with bumps is bonded to the microchannel cover plate 114 through thermal conductive glue by using a wafer reconstruction process, such as Figure 5 As shown;

[0047] The substrate material of the heterogeneous chip includes Si, GaAs, GaN and SiC, one heterogeneous chip is made of one material, and different heterogeneous chips can be made of different materials or the same material; the bump materials grown on the heterogeneous chip and the TSV adapter chip include Cu, CuSn, CuNiSn, CuNiSnAg, SnPb and SnAgCu; the flip-chip welding method of the heterogeneous chip 116 and the TSV adapter chip 115 includes reflow soldering and hot pressing welding;

[0048] Step S15: fill the gaps between the bumps of the flip-chip solder joint of the TSV transfer chip 115 with the underfill 117. Figure 6 As shown;

[0049] The method of filling the gaps between the bumps at the flip-chip solder joint of the TSV transfer chip with the underfill glue includes a dry film pressing process and a glue dispensing process;

[0050] Step S16: Use a wafer-level molding process to encapsulate the flip-chip TSV transfer chip 115 and the heterogeneous chip 116 with a resin molding material 118, and cure and reconstruct them to form a resin wafer. Figure 7 As shown;

[0051] Step S17, thinning the resin wafer to expose the copper pillars of the TSV transfer chip 115 and the bumps of the heterogeneous chip 116, such as Figure 8 As shown;

[0052] Step S18: Use wafer-level rewiring process to form multi-layer interconnect rewiring 119 on the resin wafer. Fig. 9 As shown;

[0053] Step S19, thinning the bottom of the silicon-based substrate to expose the TSV copper pillar 112 and the microchannel groove 113, and etching a chip groove 120 at the bottom of the silicon-based substrate, as shown in FIG. Fig.10 As shown;

[0054] Step S20: fix the newly provided heterogeneous chips (including chip Die-3 and chip Die-4) in the chip slot 120 by means of thermal conductive adhesive, and use Pi adhesive and wafer-level multi-layer rewiring process to sequentially implement multi-layer interconnect metal rewiring 121 of RDL and UBM, as shown in FIG. Fig.11 As shown;

[0055] The wafer-level multi-layer rewiring process is a wiring process in which a passivation layer and a metal layer overlap multiple times; the multi-layer interconnect metal rewiring 121 includes at least one metal layer; the thickness of the passivation layer is greater than the thickness of the formed metal layer, and the passivation layer covers the metal layer; the thickness of the metal layer is not less than 1 μm, and the thickness of the passivation layer is not less than 3 μm;

[0056] Step S21, using the wafer-level ball implantation process, implant solder balls 122 at the UBM of the reconstructed multi-layer silicon-based wafer, and then scribe the three-dimensional integrated silicon-based wafer to form the final package, such as Fig.12 As shown; the process of planting solder balls at the UBM includes wafer-level ball planting, single-chip ball planting and printing solder paste; the composition of the solder balls is SnPb or SnAgCu.

[0057] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A three-dimensional integrated embedded microchannel active heat dissipation packaging method, characterized in that: include: Providing a substrate, etching and filling holes therein to form TSV copper pillars, and thinning the surface with the TSV copper pillars to make them leak out, thereby manufacturing a silicon-based substrate; A microchannel groove and an inlet and outlet channel blind hole are etched on the surface of a silicon substrate having a TSV copper pillar; The silicon microfluidic cover plate is bonded to the silicon-based substrate to seal the microfluidic channel and form a microfluidic unit; The TSV transfer chip with bumps is flip-chip soldered to the silicon substrate; the heterogeneous chip with bumps is bonded to the microchannel cover plate through thermal conductive glue using the wafer reconstruction process; Use underfill to fill the gaps between the bumps of the flip-chip of the TSV adapter chip; Using wafer-level molding technology, the flip-chip TSV adapter chip and heterogeneous chip are encapsulated with resin molding compound, and then cured and reconstructed to form a resin wafer. Thin the resin wafer to expose the copper pillars of the TSV transfer chip and the bumps of the heterogeneous chip; Using wafer-level rewiring process to form multi-layer interconnect rewiring on resin wafer; The bottom of the silicon-based substrate is thinned to expose the TSV copper pillars and microchannel grooves, and a chip groove is etched at the bottom of the silicon-based substrate; The re-provided heterogeneous chip is fixed in the chip slot by thermal conductive glue, and the RDL and UBM multi-layer interconnect metal rewiring is realized in sequence by using Pi glue and wafer-level multi-layer rewiring process; By using the wafer-level ball implantation process, solder balls are implanted at the UBM of the reconstructed multi-layer silicon-based wafer, and then the three-dimensional integrated silicon-based wafer is diced to form the final package.

2. The three-dimensional integrated embedded microchannel active heat dissipation packaging method according to claim 1, characterized in that: The micro-channel unit is composed of an upper surface of a silicon-based substrate and a silicon micro-channel cover plate which are sealed and connected.

3. The three-dimensional integrated embedded microchannel active heat dissipation packaging method according to claim 1, characterized in that: The substrate materials of the heterogeneous chip include Si, GaAs, GaN and SiC; the bump materials grown on the heterogeneous chip and the TSV transfer chip include Cu, CuSn, CuNiSn, CuNiSnAg, SnPb and SnAgCu.

4. The three-dimensional integrated embedded microchannel active heat dissipation packaging method according to claim 1, characterized in that: The flip-chip welding method of the heterogeneous chip and the TSV adapter chip includes reflow welding and hot pressing welding.

5. The three-dimensional integrated embedded microchannel active heat dissipation packaging method according to claim 1, characterized in that: The method of filling the gaps between the bumps at the flip-chip solder joint of the TSV transfer chip with the underfill glue includes a dry film pressing process and a glue dispensing process.

6. The three-dimensional integrated embedded microchannel active heat dissipation packaging method according to claim 1, characterized in that: The wafer-level multi-layer rewiring process is a wiring process in which a passivation layer and a metal layer overlap multiple times.

7. The three-dimensional integrated embedded microchannel active heat dissipation packaging method according to claim 6, characterized in that: The multi-layer interconnect metal rewiring includes at least one metal layer; the thickness of the passivation layer is greater than the thickness of the formed metal layer, and the passivation layer covers the metal layer; the thickness of the metal layer is not less than 1 μm, and the thickness of the passivation layer is not less than 3 μm.

8. The three-dimensional integrated embedded microchannel active heat dissipation packaging method according to claim 1, characterized in that: The process of planting solder balls at the UBM includes wafer-level ball planting, single-chip ball planting and solder paste printing; the composition of the solder balls includes SnPb and SnAgCu.

9. A three-dimensional integrated embedded microchannel active heat dissipation packaging structure, characterized in that: It is prepared by the three-dimensional integrated embedded microchannel active heat dissipation packaging method described in any one of claims 1-8.

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