Structure, manufacturing method and power electronics device of vertical structure power device
By designing structures such as P-type layer, dielectric layer, and N-type region in vertical power devices, fast recovery diodes and IGBTs are connected in parallel, solving the problems of complex processes and low reliability, and achieving the effects of simplified processes and improved reliability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN SIRIUS SEMICON CO LTD
- Filing Date
- 2021-12-31
- Publication Date
- 2026-08-04
AI Technical Summary
Vertical power devices are complex to manufacture and have low reliability, especially since additional wiring is required to connect the IGBT and FRD.
By employing a specific structural design consisting of a P-type layer, a dielectric layer, an N-type region, an isolation region, and a P-type region and an N-type region, fast recovery diodes and IGBTs are connected in parallel. The connection between N-type semiconductor pillars and P-type semiconductor pillars simplifies the process and improves reliability.
This technology enables the parallel connection of fast recovery diodes and IGBTs, eliminating the need for additional wiring, simplifying the manufacturing process, and improving device reliability and switching speed.
Smart Images
Figure CN114429953B_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of semiconductor technology, and in particular relates to the structure, manufacturing method and power electronic equipment of a vertical structure power device. Background Technology
[0002] An insulated-gate bipolar transistor (IGBT) is a power transistor with high current density. Its structure can be regarded as a combination of a metal-oxide-semiconductor field-effect transistor (MOSFET) and a bipolar junction transistor (BJT). Although it has the advantages of fast switching of MOSFET and high current density of BJT, it also inherits the disadvantage of slow switching speed of BJT.
[0003] Therefore, in practical application circuits, in order to improve the operating speed of IGBTs, a reverse fast recovery diode (FRD) is often connected in parallel.
[0004] With advancements in manufacturing processes and the widespread adoption of horizontally oriented three-dimensional field-effect transistors (such as FinFETs, Gate-all-around (GAA), and nanosheets), vertically oriented three-dimensional power devices, such as tunneling field-effect transistors, have emerged.
[0005] However, the related vertical power devices require additional wiring to connect the IGBT and FRD, resulting in complex manufacturing processes and low reliability. Summary of the Invention
[0006] The purpose of this application is to provide a structure, manufacturing method and power electronic device for a vertical structure power device, in order to solve the problems of complex process and low reliability of related vertical structure power devices.
[0007] This application provides a structure for a vertical power device, including:
[0008] P-type layer and dielectric layer;
[0009] A first N-type region, an isolation region, and a second N-type region are located between the upper surface of the P-type layer and the lower surface of the dielectric layer; the first N-type region, the isolation region, and the second N-type region are arranged sequentially on a horizontal plane;
[0010] The P-type region and the third N-type region are disposed on the upper surface of the dielectric layer and are interconnected with each other;
[0011] An N-type semiconductor pillar disposed in the dielectric layer and connecting the P-type region and the first N-type region;
[0012] A P-type semiconductor pillar disposed in the dielectric layer and connecting the second N-type region and the third N-type region;
[0013] A metal layer disposed between the dielectric layer and the second N-type region and on the side surface of the P-type semiconductor pillar.
[0014] In one embodiment, the N-type semiconductor pillar is a lightly doped N-type semiconductor pillar, the first N-type region is a heavily doped first N-type region, and the P-type region is a heavily doped P-type region.
[0015] In one embodiment, the P-type layer is a highly doped P-type layer, the second N-type region is a lightly doped second N-type region, the third N-type region is a highly doped third N-type region, and the P-type semiconductor pillar is a highly doped P-type semiconductor pillar.
[0016] In one embodiment, there are one or more P-type semiconductor pillars and one or more N-type semiconductor pillars.
[0017] In one embodiment, the P-type region and the third N-type region serve as the emitter of the vertical structure power device, the metal layer serves as the gate of the vertical structure power device, and the P-type layer serves as the collector of the vertical structure power device.
[0018] This application also provides a method for manufacturing a vertical structure power device, the method comprising:
[0019] Forming a P-type layer;
[0020] A first N-type region and a second N-type region are formed on the upper surface of the P-type layer;
[0021] An N-type semiconductor pillar is formed on the upper surface of the first N-type region, and a P-type semiconductor pillar is formed on the upper surface of the second N-type region, with an isolation region formed between the first N-type region and the second N-type region;
[0022] A metal layer is formed on the side surface of the P-type semiconductor pillar and the upper surface of the second N-type region;
[0023] A dielectric layer is formed on the upper surface of the first N-type region, the isolation region, and the metal layer;
[0024] A P-type region connected to the N-type semiconductor pillar is grown on the upper surface of the dielectric layer, and a third N-type region connected to the P-type semiconductor pillar is grown on the upper surface of the dielectric layer; wherein the P-type region and the third N-type region are connected.
[0025] In one embodiment, forming the first N-type region and the second N-type region on the upper surface of the P-type layer includes:
[0026] Ion implantation is performed in a first region on the upper surface of the P-type layer to form a highly doped first N-type region;
[0027] Ion implantation is performed in a second region on the upper surface of the P-type layer to form a lightly doped second N-type region.
[0028] In one embodiment, forming an N-type semiconductor pillar on the upper surface of the first N-type region, forming a P-type semiconductor pillar on the upper surface of the second N-type region, and forming an isolation region between the first N-type region and the second N-type region includes:
[0029] A first semiconductor pillar is formed on the upper surface of the first N-type region, and a second semiconductor pillar is formed on the upper surface of the second N-type region;
[0030] Ions are implanted into the upper surface of the first semiconductor pillar to form a lightly doped N-type semiconductor pillar;
[0031] Ion implantation is performed on the upper surface of the second semiconductor pillar to form a highly doped P-type semiconductor pillar;
[0032] An isolation region is formed between the first N-type region and the second N-type region by imaging and filling.
[0033] In one embodiment, forming a dielectric layer on the upper surface of the first N-type region, the isolation region, and the metal layer specifically involves:
[0034] The dielectric layer is formed on the upper surface of the first N-type region, the isolation region, and the metal layer, and the dielectric layer is etched back to expose the N-type semiconductor pillar and the P-type semiconductor pillar.
[0035] This application also provides a power electronic device, which includes the structure of the vertical power device described above.
[0036] The beneficial effects of this invention compared to the prior art are as follows: Since the first N-type region, the isolation region, and the second N-type region are sequentially arranged on a horizontal plane between the upper surface of the P-type layer and the lower surface of the dielectric layer; the P-type semiconductor pillar is disposed in the dielectric layer and connects the second N-type region and the third N-type region; since the N-type semiconductor pillar is disposed in the dielectric layer and connects the P-type region and the first N-type region, and the metal layer is disposed between the dielectric layer and the second N-type region and on the side surface of the P-type semiconductor pillar, the P-type semiconductor pillar, the second N-type region, and the third N-type region form a fast recovery diode; and since the metal layer serves as the gate, a channel can be formed on the side surface of the P-type semiconductor pillar, allowing the P-type layer, the second N-type region, the P-type semiconductor pillar, the third N-type region, and the metal layer to form an IGBT, with the P-type region and the third N-type region interconnected. The first N-type region is disposed on the upper surface of the P-type layer. Therefore, no additional wiring is required to connect the fast recovery diode and the IGBT in parallel, simplifying the process and improving reliability. Attached Figure Description
[0037] To more clearly illustrate the technical inventions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0038] Figure 1 A three-dimensional structural schematic diagram of a vertical power device provided in an embodiment of this application;
[0039] Figure 2 A schematic diagram illustrating the formation of a P-type layer in a manufacturing method for a vertical structure power device provided in this application embodiment;
[0040] Figure 3 A schematic diagram illustrating the formation of a first N-type region and a second N-type region in a manufacturing method for a vertical structure power device provided in this application embodiment;
[0041] Figure 4 This is a schematic diagram illustrating the formation of N-type semiconductor pillars, P-type semiconductor pillars, and isolation regions in a manufacturing method for a vertical structure power device provided in this application embodiment.
[0042] Figure 5 A schematic diagram illustrating the formation of a metal layer in a manufacturing method for a vertical structure power device provided in this application embodiment;
[0043] Figure 6 A schematic diagram illustrating the formation of a dielectric layer in a manufacturing method for a vertical structure power device provided in this application embodiment;
[0044] Figure 7 This is a schematic diagram of the P-type region and the third N-type region in the manufacturing method of the vertical structure power device provided in the embodiments of this application. Detailed Implementation
[0045] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.
[0046] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.
[0047] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.
[0048] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0049] Figure 1 The module structure of the vertical power device provided in the embodiment of the present invention is shown. For ease of explanation, only the parts related to the embodiment of the present invention are shown, and are described in detail below:
[0050] The structure of the vertical power device includes a P-type layer 11, a dielectric layer 12, a first N-type region 13, an isolation region 14, a second N-type region 15, a P-type region 16 and a third N-type region 17, an N-type semiconductor pillar 18, a P-type semiconductor pillar 19 and a metal layer 20.
[0051] The first N-type region 13, the isolation region 14, and the second N-type region 15 are located between the upper surface of the P-type layer 11 and the lower surface of the dielectric layer 12; the first N-type region 13, the isolation region 14, and the second N-type region 15 are arranged sequentially on a horizontal plane.
[0052] The interconnected P-type region 16 and the third N-type region 17 are disposed on the upper surface of the dielectric layer 12.
[0053] N-type semiconductor pillars 18 are disposed in dielectric layer 12 and connect P-type region 16 and first N-type region 13.
[0054] P-type semiconductor pillars 19 are disposed in dielectric layer 12 and connect the second N-type region 15 and the third N-type region 17.
[0055] The metal layer 20 is disposed between the dielectric layer 12 and the second N-type region 15 and on the side surface of the P-type semiconductor pillar 19.
[0056] It is worth emphasizing that the N-type semiconductor pillar 18 is a lightly doped N-type semiconductor pillar 18, the first N-type region 13 is a heavily doped first N-type region 13, and the P-type region 16 is a heavily doped P-type region 16.
[0057] The fast recovery diode, composed of a low-doped N-type semiconductor pillar 18, a high-doped first N-type region 13, and a high-doped P-type region 16, has a fast switching speed between conduction and cutoff, which improves the operating frequency of vertical structure power devices and improves the waveform.
[0058] It should be noted that the P-type layer 11 is a highly doped P-type layer 11, the second N-type region 15 is a lightly doped second N-type region 15, the third N-type region 17 is a highly doped third N-type region 17, and the P-type semiconductor pillar 19 is a highly doped P-type semiconductor pillar 19.
[0059] An IGBT transistor is formed by a highly doped P-type layer 11, a lightly doped second N-type region 15, a highly doped third N-type region 17, a highly doped P-type semiconductor pillar 19, and a metal layer 20. This IGBT transistor reduces switching time and switching losses.
[0060] As an example and not a limitation, there may be one or more P-type semiconductor pillars 19 and one or more N-type semiconductor pillars 18.
[0061] The number of P-type semiconductor pillars 19 and N-type semiconductor pillars 18 can be flexibly set according to the conduction current of the vertical structure power device.
[0062] In a specific implementation, P-type region 16 and third N-type region 17 serve as the emitter of the vertical structure power device, metal layer 20 serves as the gate of the vertical structure power device, and P-type layer 11 serves as the collector of the vertical structure power device; thus, the vertical structure power device includes a fast recovery diode and a vertical structure IGBT, wherein the fast recovery diode and the vertical structure IGBT are connected in parallel.
[0063] Corresponding to an embodiment of a vertical structure power device, the present invention also provides an embodiment of a method for manufacturing a vertical structure power device.
[0064] A method for manufacturing a vertical structure power device, the method comprising steps 401 to 406.
[0065] In step 401, as Figure 2 As shown, a P-type layer 11 is formed.
[0066] There are two scenarios for step 401. In the first scenario, a P-type layer 11 is formed on the lower surface of the substrate by ion implantation; in the second scenario, a P-type substrate is provided as the P-type layer 11.
[0067] In step 402, as Figure 3 As shown, a first N-type region 13 and a second N-type region 15 are formed on the upper surface of the P-type layer 11.
[0068] In specific implementation, step 402 includes steps 402-1 and 402-2.
[0069] In step 402-1, ion implantation is performed in a first region on the upper surface of the P-type layer 11 to form a highly doped first N-type region 13;
[0070] In step 402-2, ion implantation is performed in the second region on the upper surface of the P-type layer 11 to form a lightly doped second N-type region 15.
[0071] The highly doped first N-type region 13 and the lightly doped second N-type region 15 can be interconnected.
[0072] In step 403, as Figure 4 As shown, an N-type semiconductor pillar 18 is formed on the upper surface of the first N-type region 13, and a P-type semiconductor pillar 19 is formed on the upper surface of the second N-type region 15, and an isolation region 14 is formed between the first N-type region 13 and the second N-type region 15.
[0073] In specific implementation, step 403 includes steps 403-1 to 402-4.
[0074] In step 403-1, a first semiconductor pillar is formed on the upper surface of the first N-type region 13, and a second semiconductor pillar is formed on the upper surface of the second N-type region 15;
[0075] A first semiconductor pillar can be formed on the upper surface of the first N-type region 13 by photolithography, and a second semiconductor pillar can be formed on the upper surface of the second N-type region 15.
[0076] In step 403-2, ion implantation is performed on the upper surface of the first semiconductor pillar to form a lightly doped N-type semiconductor pillar 18.
[0077] In step 403-3, ions are implanted into the upper surface of the second semiconductor pillar to form a highly doped P-type semiconductor pillar 19.
[0078] In step 403-4, an isolation region 14 is formed between the first N-type region 13 and the second N-type region 15 by imaging and filling. The imaging includes an etching process.
[0079] In step 404, as Figure 5 As shown, a metal layer 20 is formed on the side surface of the P-type semiconductor pillar 19 and the upper surface of the second N-type region 15.
[0080] A metal layer 20 can be formed on the side surface of the P-type semiconductor pillar 19 and the upper surface of the second N-type region 15 by processes such as vapor deposition or sputtering.
[0081] In step 405, as Figure 6 As shown, a dielectric layer 12 is formed on the upper surface of the first N-type region 13, the isolation region 14, and the metal layer 20.
[0082] In a specific implementation, a dielectric layer 12 is formed on the upper surface of the first N-type region 13, the isolation region 14 and the metal layer 20, and the dielectric layer 12 is etched back to expose the N-type semiconductor pillar 18 and the P-type semiconductor pillar 19.
[0083] The dielectric layer 12 can be formed on the upper surface of the first N-type region 13, the isolation region 14 and the metal layer 20 by processes such as vapor deposition or sputtering.
[0084] In step 406, as Figure 7 As shown, a P-type region 16 connected to an N-type semiconductor pillar 18 is grown on the upper surface of the dielectric layer 12, and a third N-type region 17 connected to a P-type semiconductor pillar 19 is grown on the upper surface of the dielectric layer 12; wherein, the P-type region 16 and the third N-type region 17 are connected.
[0085] In a specific implementation, a P-type region 16 connected to the N-type semiconductor pillar 18 is grown on the upper surface of the dielectric layer 12 by a process such as vapor deposition or sputtering, and a third N-type region 17 connected to the P-type semiconductor pillar 19 is grown on the upper surface of the dielectric layer 12 by a process such as vapor deposition or sputtering.
[0086] Step 407 may also be included after step 406.
[0087] In step 407, the P-type region and the third N-type region are electrically connected by metal to serve as the emitter of the vertical structure power device; the metal layer is electrically connected by metal to serve as the gate of the vertical structure power device; and the P-type layer is electrically connected by metal to serve as the collector of the vertical structure power device.
[0088] It is worth noting that the dielectric layer can be silicon oxide or silicon nitride. The metal layer can be gold or palladium. The insulating layer can be silicon oxide.
[0089] This invention comprises a P-type layer, a dielectric layer, a first N-type region, an isolation region, a second N-type region, a P-type region, and a third N-type region, an N-type semiconductor pillar, a P-type semiconductor pillar, and a metal layer. The first N-type region, the isolation region, and the second N-type region are located between the upper surface of the P-type layer and the lower surface of the dielectric layer and are arranged sequentially on a horizontal plane. The interconnected P-type region and the third N-type region are disposed on the upper surface of the dielectric layer. The N-type semiconductor pillar is disposed in the dielectric layer and connects the P-type region and the first N-type region. The P-type semiconductor pillar is disposed in the dielectric layer and connects the second N-type region and the third N-type region. The metal layer is disposed between the dielectric layer and the second N-type region and on the side surface of the P-type semiconductor pillar. Because the first N-type region, the isolation region, and the second N-type region are arranged sequentially between the upper surface of the P-type layer and the lower surface of the dielectric layer; P A P-type semiconductor pillar is disposed in the dielectric layer and connects the second N-type region and the third N-type region. Since the P-type semiconductor pillar is disposed in the dielectric layer on a horizontal plane and connects the P-type region and the first N-type region, and a metal layer is disposed between the dielectric layer and the second N-type region and on the side surface of the P-type semiconductor pillar, the P-type semiconductor pillar, the second N-type region, and the third N-type region form a fast recovery diode. The metal layer serves as the gate and can form a channel on the side surface of the P-type semiconductor pillar, so that the P-type layer, the second N-type region, the P-type semiconductor pillar, the third N-type region, and the metal layer form an IGBT. The P-type region and the third N-type region are interconnected, and the first N-type region is disposed on the upper surface of the P-type layer. Therefore, there is no need for additional wiring to connect the fast recovery diode and the IGBT, which simplifies the process and improves reliability.
[0090] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.
[0091] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.
Claims
1. A structure for a vertical power device, characterized in that, include: P-type layer and dielectric layer; A first N-type region, an isolation region, and a second N-type region are located between the upper surface of the P-type layer and the lower surface of the dielectric layer; the first N-type region, the isolation region, and the second N-type region are arranged sequentially on a horizontal plane; The P-type region and the third N-type region are disposed on the upper surface of the dielectric layer and are interconnected with each other; An N-type semiconductor pillar disposed in the dielectric layer and connecting the P-type region and the first N-type region; A P-type semiconductor pillar disposed in the dielectric layer and connecting the second N-type region and the third N-type region; A metal layer disposed between the dielectric layer and the second N-type region and on the side surface of the P-type semiconductor pillar.
2. The structure of the vertical power device as described in claim 1, characterized in that, The N-type semiconductor pillar is a lightly doped N-type semiconductor pillar, the first N-type region is a heavily doped first N-type region, and the P-type region is a heavily doped P-type region.
3. The structure of the vertical power device as described in claim 1, characterized in that, The P-type layer is a highly doped P-type layer, the second N-type region is a lightly doped second N-type region, the third N-type region is a highly doped third N-type region, and the P-type semiconductor pillar is a highly doped P-type semiconductor pillar.
4. The structure of the vertical power device as described in claim 1, characterized in that, The P-type semiconductor pillar is one or more, and the N-type semiconductor pillar is one or more.
5. The structure of the vertical power device as described in claim 1, characterized in that, The P-type region and the third N-type region serve as the emitter of the vertical structure power device, the metal layer serves as the gate of the vertical structure power device, and the P-type layer serves as the collector of the vertical structure power device.
6. A method for manufacturing a vertical power device, characterized in that, The manufacturing method includes: Forming a P-type layer; A first N-type region and a second N-type region are formed on the upper surface of the P-type layer; An N-type semiconductor pillar is formed on the upper surface of the first N-type region, and a P-type semiconductor pillar is formed on the upper surface of the second N-type region, with an isolation region formed between the first N-type region and the second N-type region; A metal layer is formed on the side surface of the P-type semiconductor pillar and the upper surface of the second N-type region; A dielectric layer is formed on the upper surface of the first N-type region, the isolation region, and the metal layer; A P-type region connected to the N-type semiconductor pillar is grown on the upper surface of the dielectric layer, and a third N-type region connected to the P-type semiconductor pillar is grown on the upper surface of the dielectric layer; wherein the P-type region and the third N-type region are connected.
7. The method for manufacturing a vertical structure power device according to claim 6, characterized in that, The formation of the first N-type region and the second N-type region on the upper surface of the P-type layer includes: Ion implantation is performed in a first region on the upper surface of the P-type layer to form a highly doped first N-type region; Ion implantation is performed in a second region on the upper surface of the P-type layer to form a lightly doped second N-type region.
8. The method for manufacturing a vertical structure power device according to claim 6, characterized in that, The step of forming an N-type semiconductor pillar on the upper surface of the first N-type region, forming a P-type semiconductor pillar on the upper surface of the second N-type region, and forming an isolation region between the first N-type region and the second N-type region includes: A first semiconductor pillar is formed on the upper surface of the first N-type region, and a second semiconductor pillar is formed on the upper surface of the second N-type region; Ions are implanted into the upper surface of the first semiconductor pillar to form a lightly doped N-type semiconductor pillar; Ion implantation is performed on the upper surface of the second semiconductor pillar to form a highly doped P-type semiconductor pillar; An isolation region is formed between the first N-type region and the second N-type region by imaging and filling.
9. The method for manufacturing a vertical structure power device according to claim 6, characterized in that, The formation of a dielectric layer on the upper surface of the first N-type region, the isolation region, and the metal layer specifically involves: The dielectric layer is formed on the upper surface of the first N-type region, the isolation region, and the metal layer, and the dielectric layer is etched back to expose the N-type semiconductor pillar and the P-type semiconductor pillar.
10. A power electronic device, characterized in that, The power electronic device includes the structure of a vertical power device as described in any one of claims 1 to 5.