A shielded gate trench power device and its manufacturing method

Abstract

The present invention provides a shielded gate trench power device and a method for manufacturing the same, comprising: a substrate having a device region and an electrode connection region, the device region having a first trench and the electrode connection region having a plurality of second trenches; a source polysilicon layer located within and filling the second trenches; a shield gate filling a portion of the depth of the first trenches; a first dielectric layer filling at least one of the first trenches adjacent to the second trenches and filling a portion of the depth of the remaining first trenches; a gate polysilicon layer located to fill the remaining depth of the first trenches; and a first metal wiring layer located on the first dielectric layer and electrically connected to the gate polysilicon layer and the source polysilicon layer. The first trenches, where side etching occurs, are insulated from the remaining gate polysilicon layer and the source polysilicon layer, thereby fundamentally avoiding device short circuits that may be caused by side etching.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor preparation, and in particular to a shielded gate trench power device and a preparation method thereof. Background Art

[0002] In recent years, trench MOSFET technology has made great progress. In order to further achieve higher power handling speed and lower power loss, the industry has further proposed a new trench MOSFET structure. Among the new trench MOSFET structures, the most representative is the shielded gate trench technology. Shielded gate trench power devices are also commonly called SGT devices. The shielding gate can be used as an "in-body field plate" to reduce the electric field in the drift region, thereby reducing the resistance of the drift region. Therefore, shielded gate trench power devices usually have lower on-resistance and higher breakdown voltage.

[0003] Figure 1 Schematic diagram of the structure of a shielded gate trench power device, such as Figure 1 As shown, the device region 100a of the shielded gate trench power device is composed of a plurality of periodically arranged unit cell structures, each unit cell structure including: a substrate 100 of a first conductivity type and an epitaxial layer 102 of the first conductivity type located on the substrate 100. A first trench 104 is formed in the epitaxial layer 102, and a shield gate 108 and a gate polysilicon layer 114 are disposed in the first trench 104. A shield gate dielectric layer 106 is formed between the shield gate 108 and the bottom and sidewalls of the first trench 104. The gate polysilicon layer 114 is located above the shield gate 108. A gate isolation layer 110 is formed between the gate polysilicon layer 114 and the shield gate 108. A gate dielectric layer 112 is formed between the gate polysilicon layer 114 and the sidewalls of the first trench 104.

[0004] An electrode connection region 100b in the region outside the device region 100a is used to lead out the electrodes within the device region 100a. A second trench 103 is formed within the electrode connection region 100b. The second trench 103 and the first trench 104 can be formed simultaneously and interconnected. The second trench 103 is filled with a source polysilicon layer 107. An oxide layer 105 is formed between the source polysilicon layer 107 and the bottom and sidewalls of the second trench 103. The source polysilicon layer 107 is in contact with the shield gate 108. Specifically, a well region 116 of the second conductivity type is formed in the epitaxial layer 102. A first source region 118a and a second source region 118b of the first conductivity type are formed in the well region 116 on both sides of the first trench 104, respectively.

[0005] A first dielectric layer 120 and a first metal wiring layer 122 are sequentially formed on the epitaxial layer 102 . The first metal wiring layer 122 is in contact and connected to the source polysilicon layer 107 , the shield gate 108 , the gate polysilicon layer 114 and the first source region 118 a near the second trench 103 through an opening in the first dielectric layer 120 .

[0006] like Figure 2 As shown, the oxide layer 105 and the shield gate dielectric layer 106 are typically formed simultaneously. The source polysilicon layer 107 and the shield gate 108 may also be formed simultaneously, but the source polysilicon layer 107 is not etched back, so that the source polysilicon layer 107 completely fills the second trench 103. However, before forming the gate polysilicon layer 114, the second dielectric layer 109 needs to be etched to form the gate isolation layer 110. In existing processes, the mask layer 111 is typically formed on the electrode connection region 10b, and the second dielectric layer 109 in the first trench 104 is removed by wet etching.

[0007] The etching time for removing the second dielectric layer 109 by wet etching is relatively long. During the etching process, the photoresist is immersed in the wet etching solution, and its adhesion decreases, causing the wet etching solution to laterally etch the second dielectric layer 109 and the oxide layer 105 in the second trench 103 at the outermost edge of the electrode connection area 100b covered by the photoresist, thereby generating a gap 115. Figure 4 for Figure 2 The SEM topography of the second trench of the shielded gate trench power device shown in FIG. Figure 4 As shown, the second groove 103 at the outermost edge of the electrode connection area 100 b generates the gap 115 .

[0008] like Figure 3 As shown, when the gate polysilicon layer 114 is further formed in the first trench 104, the polysilicon will fill the gap 115 in the second trench 103. The polysilicon in the gap 115 is difficult to remove, which will cause the size and position of the opening corresponding to the source polysilicon layer 107 in the first dielectric layer 120 to deviate, thereby causing a short circuit between the gate and the source, causing damage to the shielding gate trench power device. Summary of the Invention

[0009] The object of the present invention is to provide a shielded gate trench power device and a preparation method thereof, so as to avoid the short circuit problem caused by the lateral etching phenomenon and improve the reliability of the device.

[0010] In order to achieve the above object, the present invention provides a shielded gate trench power device, comprising:

[0011] A substrate having a device region and an electrode connection region, wherein the device region has a first trench and the electrode connection region has a plurality of second trenches;

[0012] a source polysilicon layer, located in the second trench and filling the second trench;

[0013] a shield grid located in the first trench and filling a portion of the depth of the first trench;

[0014] a first dielectric layer filling at least one of the first trenches adjacent to the second trench and filling a portion of the depth of the remaining first trenches;

[0015] a gate polysilicon layer, located at a remaining depth of the first trench;

[0016] The first metal wiring layer is located on the first dielectric layer and is electrically connected to the gate polysilicon layer and the source polysilicon layer.

[0017] Optionally, the shielded gate trench power device further includes:

[0018] A second dielectric layer is located between the substrate and the first metal wiring layer and covers the substrate, the gate polysilicon layer, the source polysilicon layer and the first dielectric layer. The first metal wiring layer passes through the second dielectric layer and is electrically connected to the gate polysilicon layer and the source polysilicon layer.

[0019] Optionally, the shielded gate trench power device further includes:

[0020] The second metal wiring layer is located above the first dielectric layer and is insulated from the first metal wiring layer.

[0021] Optionally, the shielded gate trench power device further includes:

[0022] A source region is located in the substrate on both sides of the first trench, and the first metal wiring is electrically connected to the source region.

[0023] Optionally, the first metal wiring layer and the second metal wiring layer are located in the same layer and are patterned from the same metal layer.

[0024] Based on the same inventive concept, the present invention also provides a method for preparing a shielded gate trench power device, comprising:

[0025] Providing a substrate, wherein the substrate has a device region and an electrode connection region, forming a plurality of first trenches in the device region, and forming a plurality of second trenches in the electrode connection region;

[0026] forming a source polysilicon layer, a shield gate, a first dielectric layer, and a gate polysilicon layer on the substrate, wherein the source polysilicon layer is located in the second trench and fills the second trench, the shield gate is located in the first trench and fills a portion of the depth of the first trench, the first dielectric layer fills at least one of the first trenches adjacent to the second trench and fills a portion of the depth of the remaining first trenches, and the gate polysilicon layer is located on the shield gate and fills the remaining depth of the remaining first trenches;

[0027] A first metal wiring layer is formed on the substrate, wherein the first metal wiring layer is electrically connected to the gate polysilicon layer and the source polysilicon layer.

[0028] Optionally, the step of forming the source polysilicon layer, the shield gate, the first dielectric layer, and the gate polysilicon layer on the substrate includes:

[0029] forming the shielding gate in the first trench, wherein the shielding gate fills a portion of the depth of the first trench;

[0030] forming the source polysilicon layer in the second trench, wherein the source polysilicon layer fills the second trench;

[0031] forming a first dielectric layer on the substrate, wherein the first dielectric layer fills the remaining depth of the first trench and extends to cover the substrate and the source polysilicon layer;

[0032] Etching the first dielectric layer, retaining the first dielectric layer in at least one first trench adjacent to the second trench, and removing the first dielectric layer on the substrate in the device region and a portion of the first dielectric layer in the remaining first trench;

[0033] Filling the remaining depth of the first trench with a gate polysilicon layer

[0034] Optionally, after forming the source polysilicon layer, the shield gate, the first dielectric layer, and the gate polysilicon layer, and before forming the first metal wiring layer, the method further includes:

[0035] forming a second dielectric layer on the substrate, wherein the second dielectric layer covers the substrate, the gate polysilicon layer, the source polysilicon layer and the first dielectric layer;

[0036] etching the second dielectric layer to form a first opening exposing the gate polysilicon layer and the source polysilicon layer; and

[0037] When forming the first metal wiring layer, the first metal wiring layer covers the second dielectric layer and fills the first opening to contact the gate polysilicon layer and the source polysilicon layer.

[0038] Optionally, when etching the second dielectric layer, a second opening is formed to expose the first dielectric layer in at least one first groove adjacent to the second groove. When forming the first metal wiring layer, a second metal wiring layer insulated from the first metal wiring layer is also formed simultaneously, and the second metal wiring layer fills the second opening.

[0039] Optionally, the step of forming the first wiring layer and the second wiring layer further includes:

[0040] forming a metal layer on the second dielectric layer;

[0041] The metal layer is etched to form the first metal wiring layer and the second metal wiring layer.

[0042] The present invention provides a method for fabricating a shielded gate trench power device, comprising: a substrate having a device region and an electrode connection region, the device region having a plurality of first trenches, and the electrode connection region having a plurality of second trenches; a source polysilicon layer located within and filling the second trenches; a shield gate located within and filling a portion of the depth of the first trenches; a first dielectric layer filling at least one of the first trenches adjacent to the second trenches and filling a portion of the depth of the remaining first trenches; a gate polysilicon layer located and filling the remaining depth of the remaining first trenches; and a first metal wiring layer located on the substrate and electrically connected to the gate polysilicon layer and the source polysilicon layer. By changing the etching range of the first dielectric layer, lateral etching occurs in the first trenches adjacent to the second trenches, and the first trenches undergoing lateral etching are insulated from the gate polysilicon layer and the source polysilicon layer, thereby fundamentally avoiding the device short circuit problem that may be caused by lateral etching and improving device reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 It is a schematic structural diagram of a shielded gate trench power device;

[0044] Figures 2-3 A flow chart of a method for preparing a shielded gate trench power device;

[0045] Figure 4 for Figure 2 The scanning electron microscope topography image of the second trench of the shielded gate trench power device shown;

[0046] Figure 5A flowchart of a method for manufacturing a shielded gate trench power device provided in Example 1 of the present invention;

[0047] Figures 6 to 17 A schematic structural diagram corresponding to the corresponding steps of a method for manufacturing a shielded gate trench power device provided in the first embodiment of the present invention;

[0048] Figure 18 A schematic structural diagram of a shielded gate trench power device provided in the second embodiment of the present invention;

[0049] The accompanying drawings are as follows:

[0050] 100, 200 - substrate; 100a, 200a - device region; 100b, 200b - electrode connection region; 102, 202 - epitaxial layer; 103, 203 - first trench; 104, 204 - second trench; 105, 205 - oxide layer; 106, 206 - shielding gate dielectric layer; 107, 207 - source polysilicon layer; 108, 208 - shielding gate; 109, 209 - first dielectric layer; 1 10, 210 - gate isolation layer; 111, 211 - mask layer; 112, 212 - gate dielectric layer; 114, 214 - gate polysilicon layer; 115, 215 - gap; 116, 216 - well region; 118a, 218a - first source region; 118b, 218b - second source region; 120, 220 - second dielectric layer; 122, 222 - first metal wiring layer; 226 - second metal wiring layer. DETAILED DESCRIPTION

[0051] The following is a more detailed description of the specific embodiments of the present invention with reference to schematic diagrams. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are greatly simplified and not to exact scale, and are only used for the purpose of conveniently and clearly illustrating the embodiments of the present invention.

[0052] Hereinafter, the terms "first," "second," and the like are used to distinguish between similar elements and are not necessarily used to describe a particular order or chronological sequence. It is to be understood that these terms, when used in this manner, are interchangeable where appropriate. Similarly, if a method described herein comprises a series of steps, the steps presented herein are not necessarily the only order in which the steps may be performed, and some of the steps described may be omitted and / or other steps not described herein may be added to the method.

[0053] Example 1

[0054] Figure 17 This is a schematic diagram of the structure of the shielded gate trench power device provided in this embodiment, as shown in FIG. Figure 17As shown, this embodiment provides a shielded gate trench power device, including: a substrate 200, the substrate 200 having a device area 200a and an electrode connection area 200b, the device area 200a having a plurality of first trenches 203, and the electrode connection area 200b having a plurality of second trenches 204; a source polysilicon layer 207, located in the second trenches 204 and filling the second trenches 204; a shield gate 208, located in the first trenches 203 and filling a portion of the depth of the first trenches 203; a first dielectric layer 209, filling at least one of the first trenches 203 adjacent to the second trenches 204 and filling the remaining portion of the depth of the first trenches 203; a gate polysilicon layer 214, located at the remaining depth of the first trenches 203; and a first metal wiring layer 222, located on the substrate 200 and electrically connected to the gate polysilicon layer 214 and the source polysilicon layer 207.

[0055] When forming the first metal wiring layer 222, the first groove 203 adjacent to the second groove 204 that undergoes side etching is not connected as an effective structure. One of the first grooves 203 is discarded, fundamentally avoiding the problem of device short circuit caused by side etching.

[0056] Furthermore, the shielded gate trench power device also includes a second dielectric layer 220, which is located between the substrate 200 and the first metal wiring layer 222, and covers the substrate 200, the gate polysilicon layer 214, the source polysilicon layer 207 and the first dielectric layer 209. The first metal wiring layer 222 passes through the second dielectric layer 220 and is electrically connected to the gate polysilicon layer 214 and the source polysilicon layer 207.

[0057] Continue reading Figure 17 The shielded gate trench power device also includes a source region, which is located in the substrate 200 on both sides of the first trench 203. The source region includes a first source region 218a and a second source region 218b. Compared with the second source region 218b, the first source region 218a is closer to the source polysilicon layer 207, and the first source region 218a is electrically connected to the source polysilicon layer 207 through the first metal wiring layer 222.

[0058] The substrate 200 is a first conductive type silicon substrate 200 , a first conductive type epitaxial layer 202 is formed on the surface of the first conductive type silicon substrate 200 , and the first trench 203 and the second trench 204 are formed in the epitaxial layer 202 .

[0059] Based on this, this embodiment also provides a method for preparing a shielded gate trench power device. Figure 5 A flowchart of a method for preparing a shielded gate trench power device provided in this embodiment is shown in FIG. Figure 5 As shown, the present invention provides a method for preparing a shielded gate trench power device, comprising:

[0060] Step S1: providing a substrate, wherein the substrate has a device region and an electrode connection region, forming a plurality of first trenches in the device region, and forming a plurality of second trenches in the electrode connection region;

[0061] Step S2: forming a source polysilicon layer, a shield gate, a first dielectric layer, and a gate polysilicon layer on the substrate, wherein the source polysilicon layer is located in the second trench and fills the second trench, the shield gate is located in the first trench and fills a portion of the depth of the first trench, the first dielectric layer fills at least one of the first trenches adjacent to the second trench and fills a portion of the depth of the remaining first trenches, and the gate polysilicon layer is located on the shield gate and fills the remaining depth of the remaining first trenches;

[0062] Step S3: forming a first metal wiring layer on the substrate, wherein the first metal wiring layer is electrically connected to the gate polysilicon layer and the source polysilicon layer.

[0063] Figures 6 to 17 The present invention provides a method for preparing a shielded gate trench power device, which is a schematic structural diagram corresponding to the corresponding steps. Figures 6 to 17 A method for manufacturing a shielded gate trench power device provided in this embodiment is described in more detail, wherein an optional embodiment of the present invention is illustrated.

[0064] like Figure 6 and Figure 7 As shown, a substrate 200 having a first conductivity type is provided. The substrate 200 includes a device region 200a and an electrode connection region 200b. The electrode connection region 200b leads out the electrode in the device region 200a. A drain region is formed on a first surface of the substrate 200, and an epitaxial layer 202 having the first conductivity type is formed on a second surface of the substrate 200. The doping concentration of the substrate 200 is higher than the doping concentration of the epitaxial layer 202.

[0065] The epitaxial layer 202 is etched to form a plurality of first trenches 203 in the device region 200a and a plurality of second trenches 204 in the electrode connection region 200b. The first trenches 203 and the second trenches 204 are formed simultaneously and interconnected, and the depth of the first trenches 203 and the depth of the second trenches 204 can be the same. The shape of the bottom corners of the first trenches 203 and the second trenches 204 can be arc-shaped or right-angled. The arc-shaped trenches can reduce stress between subsequent film layers and the epitaxial layer 202. In this embodiment, the bottom corners of the first trenches 203 and the second trenches 204 are right-angled.

[0066] like Figure 8 As shown, an oxide layer 205 is formed on the bottom and sidewalls of the first trench 203 and the second trench 204 .

[0067] like Figure 9 As shown, a conductive layer is formed on the substrate 200, and the conductive layer covers the oxide layer 205 and fills the first trench 203 and the second trench 204. The conductive layer can be a conductive material such as polysilicon, aluminum, tungsten or titanium. In this embodiment, the material of the conductive layer is polysilicon.

[0068] Furthermore, the conductive layer and the oxide layer 205 are etched back to remove a portion of the oxide layer 205 on the sidewalls of the first trench 203. The remaining oxide layer 205 forms a shield gate dielectric layer 206. A portion of the conductive layer in the first trench 203 is also etched away, and the remaining conductive layer forms a shield gate 208. Simultaneously, the conductive layer in the second trench 204 forms a source polysilicon layer 207. The upper surface of the source polysilicon layer 207 can be slightly lower than the upper surface of the epitaxial layer 202. In other optional embodiments, the upper surface of the conductive layer, the source polysilicon layer 207, can be flush with the upper surface of the epitaxial layer 202.

[0069] like Figure 10 As shown, a first dielectric layer 209 is formed on the epitaxial layer 202 . The first dielectric layer 209 fills the remaining portion of the first trench 203 and extends to cover the surface of the epitaxial layer 202 . The first dielectric layer 209 may be silicon oxide or silicon nitride.

[0070] like Figure 11 and Figure 12As shown, a patterned mask layer 211 is formed on the first dielectric layer 209. The mask layer 211 is a photoresist. The mask layer 211 covers the electrode connection region 200b and the first dielectric layer 209 on at least one first trench 203 adjacent to the second trench 204. A wet etching process is used to remove the first dielectric layer 209 on the exposed epitaxial layer 202. The etching process then continues to remove the portion of the first dielectric layer 209 within the first trench 203. The remaining first dielectric layer 209 in the first trench 203 forms a gate isolation layer 210.

[0071] See Figure 12 Since the etching time of the first dielectric layer 209 is relatively long, the photoresist is immersed in the wet etching solution during the etching process, and its adhesion decreases, causing the wet etching solution to cause lateral etching of the second dielectric layer 209 and even the oxide layer 205 in the first trench 203 adjacent to the second trench 204 covered by the mask layer 211, thereby forming a gap 215.

[0072] like Figure 13 and Figure 14 As shown, after the gate isolation layer 210 is formed, the first dielectric layer 209 and the mask layer 211 remaining on the surface of the substrate 200 are removed.

[0073] Furthermore, the gate dielectric layer 212 is formed on the exposed sidewalls of the first trench 203 , and then polysilicon is filled in the remaining portion of the first trench 203 to form a gate polysilicon layer 214 . When filling the first trench 203 with polysilicon, polysilicon is also filled in the gap 215 at the same time.

[0074] Figure 15 for Figure 13 The SEM image of the shielded gate trench power device shown in Figure 15 As shown, the gap 215 is generated in the first trench 203 adjacent to the second trench 204 , and no side etching occurs to the source polysilicon layer 207 in the second trench 204 .

[0075] like Figure 16 As shown, a first ion implantation process is performed on the epitaxial layer 202 to form a well region 216 in the epitaxial layer 202. The well region 216 has the second conductivity type. Then, a second ion implantation process is performed on the well region 216 on both sides of the first trench 203 to form a first source region 218a and a second source region 218b in the well region 216. The first source region 218a and the second source region 218b have the first conductivity type.

[0076] like Figure 17As shown, a second dielectric layer 220 is formed on the epitaxial layer 202 , and the second dielectric layer 220 covers the substrate, the gate polysilicon layer 214 , the source polysilicon layer 207 and the first dielectric layer 209 . The material of the second dielectric layer 220 may be silicon nitride or silicon oxide.

[0077] Then, the second dielectric layer 220 is etched to form first openings corresponding to the gate polysilicon layer 214 , the source polysilicon layer 207 and the first source region 218 a in the second dielectric layer 220 , and the first trench 203 adjacent to the second trench 204 that is laterally etched is covered by the second dielectric layer 220 .

[0078] Furthermore, a metal layer is formed on the substrate 200 and etched to form a patterned first metal wiring layer 222. The first metal wiring layer 222 covers the second dielectric layer 220 and fills the first opening, electrically connecting the gate polysilicon layer 214, the source polysilicon layer 207, and the first source region 218a. The first source region 218a is located closer to the source polysilicon layer 207, facilitating the formation of the first metal wiring layer 222.

[0079] When the first metal wiring layer 222 is subsequently formed, the shield gate 208 within the first trench 203 and the polysilicon within the slit 215, which are laterally etched, are insulated from the gate polysilicon layer 214 and the source polysilicon layer 207, thereby fundamentally avoiding device short circuits that may be caused by the lateral etching. It should also be understood that the number of first trenches 203 covered by the mask layer 211 during the etching of the first dielectric layer 209 can be adjusted based on the corrosiveness of the wet etching solution, the wet etching time, and the width of the formed slit 215. This embodiment only illustrates the case where one first trench 203 is omitted.

[0080] Example 2

[0081] Figure 18 A schematic structural diagram of a shielded gate trench power device provided in an embodiment is shown in FIG. Figure 18 As shown, the only difference between this embodiment and embodiment one is that the shielded gate trench power device in this embodiment also includes: a second metal wiring layer 226, which is located on the second dielectric layer 220 and is connected to the polysilicon in the gap 215 through the second dielectric layer 220, and the second metal wiring layer 226 is insulated from the first metal wiring layer 222.

[0082] Specifically, when etching the second dielectric layer 220, a second opening is formed to expose the polysilicon within the gap 215. When forming the first metal wiring layer 222, a second metal wiring layer 226 is also formed, which is insulated from the first metal wiring layer 222. The second metal wiring layer 226 fills the second opening to contact the polysilicon within the gap 215. Although the second metal wiring layer 226 leads the polysilicon within the gap 215 out, the first metal wiring layer 222 and the second metal wiring layer 226 are insulated, thus avoiding device short circuits caused by lateral etching.

[0083] In this embodiment, the first metal wiring layer 222 and the second metal wiring layer 226 are located on the same layer and are patterned from the same metal layer. The steps of forming the first metal wiring layer 222 and the second metal wiring layer 226 include: forming a metal layer on the second dielectric layer 220, and then etching the metal layer to form the patterned first metal wiring layer 222 and the second metal wiring layer 226.

[0084] In summary, the present invention provides a shielded gate trench power device and a preparation method thereof, comprising: a substrate 200, wherein the substrate 200 has a device area 200a and an electrode connection area 200b, wherein the device area 200a has a plurality of first trenches 203, and the electrode connection area 200b has a plurality of second trenches 204; a source polysilicon layer 207, located in the second trenches 204 and filling the second trenches 204; a shield gate 208, located in the first trenches 203 and filling a portion of the depth of the first trenches 203; a first dielectric layer 209, filling at least one of the first trenches 203 adjacent to the second trenches 204 and filling the remaining portion of the depth of the first trenches 203; a gate polysilicon layer 214, located at the remaining depth of the remaining first trenches 203; and a first metal wiring layer 222, located on the substrate 200 and electrically connected to the gate polysilicon layer 214 and the source polysilicon layer 207. By changing the etching range of the first dielectric layer 209, lateral etching occurs in the first trench 203 adjacent to the second trench 204, and the first trench 203 where the lateral etching occurs is insulated from the gate polysilicon layer 214 and the source polysilicon layer 207, thereby fundamentally avoiding the device short circuit problem that may be caused by lateral etching, and improving the reliability of the device.

[0085] The above description is merely a preferred embodiment of the present invention and does not limit the present invention in any way. Any person skilled in the art who, without departing from the scope of the present invention, makes any equivalent substitution, modification, or other changes to the technical solution and technical content disclosed in the present invention shall be deemed to be within the scope of the present invention and still fall within the scope of protection of the present invention.

Claims

1. A shielded gate trench power device, characterized in that: include: A substrate having a device region and an electrode connection region, wherein the device region has a plurality of first trenches and the electrode connection region has a plurality of second trenches; a source polysilicon layer, located in the second trench and filling the second trench; a shield grid located in the first trench and filling a portion of the depth of the first trench; a first dielectric layer filling at least one of the first trenches adjacent to the second trench and partially filling the remaining first trenches, wherein, by changing the etching range of the first dielectric layer, lateral etching occurs in the first trench adjacent to the second trench, and the first trench where the lateral etching occurs is insulated from the gate polysilicon layer and the source polysilicon layer; a gate polysilicon layer, filling the remaining depth of the first trench; The first metal wiring layer is located on the substrate and is electrically connected to the gate polysilicon layer and the source polysilicon layer.

2. The shielded gate trench power device according to claim 1, wherein: Also includes: A second dielectric layer is located between the substrate and the first metal wiring layer and covers the substrate, the gate polysilicon layer, the source polysilicon layer and the first dielectric layer. The first metal wiring layer passes through the second dielectric layer and is electrically connected to the gate polysilicon layer and the source polysilicon layer.

3. The shielded gate trench power device according to claim 2, wherein: Also includes: The second metal wiring layer is located above the first dielectric layer and is insulated from the first metal wiring layer.

4. The shielded gate trench power device according to claim 3, wherein: The first metal wiring layer and the second metal wiring layer are located in the same layer and are patterned from the same metal layer.

5. The shielded gate trench power device according to claim 1, wherein: Also includes: The source region is located in the substrate on both sides of the first trench, and the first metal wiring layer is also electrically connected to the source region.

6. A method for preparing a shielded gate trench power device, characterized in that: include: Providing a substrate, wherein the substrate has a device region and an electrode connection region, forming a plurality of first trenches in the device region, and forming a plurality of second trenches in the electrode connection region; A source polysilicon layer, a shield gate, a first dielectric layer, and a gate polysilicon layer are formed on the substrate, wherein the source polysilicon layer is located in the second trench and fills the second trench, the shield gate is located in the first trench and fills a portion of the depth of the first trench, the first dielectric layer fills at least one of the first trenches adjacent to the second trench, and fills a portion of the depth of the remaining first trenches, wherein, by changing the etching range of the first dielectric layer, side etching occurs in the first trench adjacent to the second trench, and the first trench where side etching occurs is insulated from the gate polysilicon layer and the source polysilicon layer; the gate polysilicon layer is located on the shield gate and fills the remaining depth of the remaining first trench; A first metal wiring layer is formed on the substrate, wherein the first metal wiring layer is electrically connected to the gate polysilicon layer and the source polysilicon layer.

7. The method for preparing a shielded gate trench power device according to claim 6, wherein: The step of forming the source polysilicon layer, the shield gate, the first dielectric layer and the gate polysilicon layer on the substrate includes: forming the shielding gate in the first trench, wherein the shielding gate fills a portion of the depth of the first trench; forming the source polysilicon layer in the second trench, wherein the source polysilicon layer fills the second trench; forming a first dielectric layer on the substrate, wherein the first dielectric layer fills the remaining depth of the first trench and extends to cover the substrate and the source polysilicon layer; Etching the first dielectric layer, retaining the first dielectric layer in at least one first trench adjacent to the second trench, and removing the first dielectric layer on the substrate in the device region and a portion of the first dielectric layer in the remaining first trench; A gate polysilicon layer is filled in the remaining depth of the remaining first trench.

8. The method for preparing a shielded gate trench power device according to claim 6, wherein: After forming the source polysilicon layer, the shield gate, and the gate polysilicon layer, and before forming the first metal wiring layer, the method further includes: forming a second dielectric layer on the substrate, wherein the second dielectric layer covers the substrate, the gate polysilicon layer, the source polysilicon layer and the first dielectric layer; etching the second dielectric layer to form a first opening exposing the gate polysilicon layer and the source polysilicon layer; and When forming the first metal wiring layer, the first metal wiring layer covers the second dielectric layer and fills the first opening to contact the gate polysilicon layer and the source polysilicon layer.

9. The method for preparing a shielded gate trench power device according to claim 8, wherein: When etching the second dielectric layer, a second opening is formed to expose the first dielectric layer in at least one of the first grooves adjacent to the second groove. When forming the first metal wiring layer, a second metal wiring layer insulated from the first metal wiring layer is also formed simultaneously, and the second metal wiring layer fills the second opening.

10. The method for preparing a shielded gate trench power device according to claim 9, wherein: The step of forming the first metal wiring layer and the second metal wiring layer further includes: forming a metal layer on the second dielectric layer; The metal layer is etched to form the first metal wiring layer and the second metal wiring layer.

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