Dynamic random access memory structure and forming method thereof

Abstract

A dynamic random access memory and a method for forming the same include: providing a substrate having a first surface and a second surface facing each other, the substrate including a plurality of discrete active regions extending in a first direction and including a plurality of independent channel regions arranged along the first direction; forming a plurality of wordline gate structures within each active region, each wordline gate structure adjacent to a channel region, the plurality of wordline gate structures extending through the active region along a second direction perpendicular to the first direction; after forming the plurality of wordline gate structures, forming a first device layer on the first surface; forming a first dielectric layer on the first device layer; forming a plurality of stress regulation structures within the first dielectric layer; and after forming the plurality of stress regulation structures, forming a second device layer on the second surface. This reduces warpage of the dynamic random access memory and improves memory reliability.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a dynamic random access memory and a forming method thereof. Background Art

[0002] With the rapid development of technology, semiconductor memory is widely used in electronic devices. Dynamic random access memory (DRAM) is a type of volatile memory and is the most commonly used solution for storing large amounts of data.

[0003] Typically, a dynamic random access memory is composed of a plurality of memory cells. Each memory cell is mainly composed of a transistor and a capacitor controlled by the transistor, and each memory cell is electrically connected to each other through a word line and a bit line.

[0004] However, existing dynamic random access memories still have many problems. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a dynamic random access memory and a forming method thereof, so as to reduce the warping of the dynamic random access memory and improve the reliability of the memory.

[0006] To solve the above technical problems, the technical solution of the present invention provides a dynamic random access memory, comprising: a substrate, the substrate having a first surface and a second surface opposite to each other, the substrate including a plurality of mutually discrete active regions, the active regions extending in a first direction, the active regions including a plurality of mutually independent channel regions arranged along the first direction; a plurality of word line gate structures located in each active region, each word line gate structure adjacent to a channel region, the plurality of word line gate structures penetrating the active region along a second direction, the second direction being perpendicular to the first direction; a first device layer located on the first surface; a first dielectric layer located on the first device layer; a plurality of stress adjustment structures located within the first dielectric layer; and a second device layer located on the second surface.

[0007] Optionally, the plurality of stress adjustment structures include: a plurality of first adjustment structures extending along the second direction, the first adjustment structures being used to cut off the stress in the first direction.

[0008] Optionally, the plurality of stress adjustment structures include: a plurality of second adjustment structures extending along the first direction, the second adjustment structures being used to cut off stress in a second direction.

[0009] Optionally, the method further includes: a second stress adjustment layer located between the first device layer and the first dielectric layer, wherein the second stress adjustment layer is used to simultaneously adjust stress in the first direction and the second direction.

[0010] Optionally, the method further includes: a second stress adjustment layer located on the first dielectric layer and the plurality of stress adjustment structures, wherein the second stress adjustment layer is used to simultaneously adjust stress in the first direction and the second direction.

[0011] Optionally, the first device layer includes: a plurality of capacitors, each of the capacitors being electrically connected to one of the channel regions; and the second device layer includes: a plurality of bit lines, each of the bit lines being electrically connected to a plurality of channel regions in an active region.

[0012] Optionally, each of the bit lines has a bit line projection on the second surface, and each of the bit line projections is within the range of one active region.

[0013] Optionally, it also includes: a second stress adjustment layer located between the several capacitors and the first dielectric layer, the second stress adjustment layer being used to simultaneously adjust the stress in the first direction and the second direction; a capacitor plate located between the several capacitors and the second stress adjustment layer; and a second dielectric layer located between the capacitor plate and the second stress adjustment layer.

[0014] Optionally, the first device layer includes: a plurality of bit lines, each bit line is electrically connected to a plurality of channel regions in an active region; the second device layer includes: a plurality of capacitors, each capacitor is electrically connected to one of the channel regions.

[0015] Optionally, the material of the stress adjustment structure is different from the material of the first dielectric layer.

[0016] Optionally, the material of the stress adjustment structure includes silicon oxide, silicon nitride, metal or polysilicon.

[0017] Optionally, the material of the second stress adjustment layer includes silicon oxide, silicon nitride, metal or polysilicon.

[0018] Optionally, the height of the stress adjustment structure is equal to the thickness of the first dielectric layer.

[0019] Optionally, the method further includes: a bonding dielectric layer located on the first dielectric layer and the plurality of stress adjustment structures; and a carrier substrate bonded to the bonding dielectric layer.

[0020] Correspondingly, the technical solution of the present invention also provides a method for forming a dynamic random access memory, comprising: providing a substrate, the substrate having a first surface and a second surface relative to each other, the substrate including a plurality of mutually discrete active regions, the active regions extending in a first direction, the active regions including a plurality of mutually independent channel regions arranged along the first direction; forming a plurality of word line gate structures in each active region, each word line gate structure being adjacent to a channel region, the plurality of word line gate structures penetrating the active region along a second direction, the second direction being perpendicular to the first direction; after forming the plurality of word line gate structures, forming a first device layer on the first surface; forming a first dielectric layer on the first device layer; forming a plurality of stress adjustment structures in the first dielectric layer; and after forming the plurality of stress adjustment structures, forming a second device layer on the second surface.

[0021] Optionally, the method for forming a plurality of stress adjustment structures in the first dielectric layer includes: forming a first mask layer on the surface of the first dielectric layer, the first mask layer exposing a portion of the surface of the first dielectric layer; etching the first dielectric layer using the first mask layer as a mask to form a plurality of stress adjustment structure openings in the first dielectric layer; and forming a plurality of stress adjustment structures in the plurality of stress adjustment structure openings.

[0022] Optionally, the depth of the stress adjustment structure opening is equal to the thickness of the first dielectric layer.

[0023] Optionally, before forming the first dielectric layer, the method further includes: forming a second stress adjustment layer on the first device layer, wherein the second stress adjustment layer is used to simultaneously adjust stress in the first direction and the second direction.

[0024] Optionally, the first device layer includes: a plurality of capacitors, each of the capacitors being electrically connected to one of the channel regions.

[0025] Optionally, before forming the second stress adjustment layer, the method further includes: forming capacitor plates on the surfaces of several capacitors, wherein the surfaces of the capacitor plates are higher than the capacitor surfaces; and forming a second dielectric layer on the surfaces of the capacitor plates.

[0026] Optionally, the first device layer includes: a plurality of capacitors, each of the capacitors being electrically connected to one of the channel regions; and the second device layer includes: a plurality of bit lines, each of the bit lines being electrically connected to a plurality of channel regions in an active region.

[0027] Optionally, the first device layer includes: a plurality of bit lines, each bit line is electrically connected to a plurality of channel regions in an active region; the second device layer includes: a plurality of capacitors, each capacitor is electrically connected to one of the channel regions.

[0028] Optionally, before forming the second device layer, it also includes: forming a bonding dielectric layer on the first dielectric layer and several stress adjustment structures; providing a carrier substrate; bonding the carrier substrate to the bonding dielectric layer; after bonding the carrier substrate to the bonding dielectric layer, thinning the substrate from the second side.

[0029] Optionally, before forming the second device layer, the method further includes: forming a second stress adjustment layer on the first dielectric layer and the plurality of stress adjustment structures, wherein the second stress adjustment layer is used to simultaneously adjust stress in the first direction and the second direction.

[0030] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0031] In the method for forming a dynamic random access memory according to the technical solution of the present invention, since a first dielectric layer is formed on the first device layer, and a plurality of stress adjustment structures are formed in the first dielectric layer before the second device layer is formed on the second surface, the stress in the first and second directions can be cut off and neutralized by the plurality of stress adjustment structures according to the structural warping of the memory before the second device layer is formed, thereby achieving local stress adjustment, so that the degree of warping of the second surface before the second device layer is formed is reduced. Therefore, when forming a photolithography pattern layer for patterning the second device layer, the pattern of the photolithography pattern layer is easily aligned with the pattern of the active area and the channel area on the second surface, and the overlay accuracy of the formed second device layer is high, thereby reducing the risk of disconnection and virtual connection between the second device layer and the channel area, and improving the reliability of the memory.

[0032] Furthermore, before forming the first dielectric layer, it also includes: forming a second stress adjustment layer on the first device layer, and the second stress adjustment layer is used to simultaneously adjust the stress in the first direction and the second direction. Therefore, through the second stress adjustment layer, before forming a plurality of stress adjustment structures, a force opposite to the warping direction can be applied to the structural integrity of the memory to pre-integrately reduce the warping of the structure of the memory in the first direction and the second direction. Therefore, when the warping situation is more serious, not only the warping degree of the second surface is better reduced, but also the process difficulty and complexity of local stress adjustment using a plurality of stress adjustment structures are reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figures 1 to 3 The present invention is a structural schematic diagram of each step of a method for forming a dynamic random access memory.

[0034] Figure 4 yes Figure 2 Schematic diagram of the overall warping of the structure.

[0035] Figures 5 to 16It is a structural diagram of each step in a method for forming a dynamic random access memory according to an embodiment of the present invention. DETAILED DESCRIPTION

[0036] As described in the background art, existing dynamic random access memories still need to be improved. This will now be analyzed and explained in conjunction with specific embodiments.

[0037] Figures 1 to 3 The present invention is a structural schematic diagram of each step of a method for forming a dynamic random access memory.

[0038] Please refer to Figure 1 A substrate 100 is provided, wherein the substrate 100 has a first surface 101 and a second surface 102 relative to each other, and the substrate 100 also has a plurality of separate active regions S1, wherein the active regions S1 extend in a first direction X, and wherein the active regions S1 have a plurality of independent channel regions S2 arranged along the first direction X.

[0039] Please continue to refer to Figure 1 A plurality of word line gate structures 120 are formed in each active region S1 . The plurality of word line gate structures 120 penetrate the active region S1 along a second direction (not marked in the figure). Each word line gate structure 120 is adjacent to one channel region S2 .

[0040] The second direction is perpendicular to the first direction X. The word line gate structure 120 includes a word line gate 121 and a word line gate dielectric layer 122 located between the word line gate and the channel region S2 .

[0041] Please continue to refer to Figure 1 , a plurality of capacitors 130 are formed on the first surface 101 , and each capacitor 130 is electrically connected to one channel region S2 .

[0042] Please continue to refer to Figure 1 A carrier wafer 140 is provided, and after forming a plurality of capacitors 130 , the carrier wafer 140 is bonded to the substrate 100 , with the carrier wafer 140 facing the first surface 101 .

[0043] Please refer to Figure 2 After bonding the carrier wafer 140 to the substrate 100 , the substrate 100 is flipped over, and the substrate 100 is thinned from the second surface 102 .

[0044] Please refer to Figure 3After thinning the substrate 100, a bit line material layer (not marked in the figure) is formed on the second surface 102; a bit line mask layer (not marked in the figure) is formed on the surface of the bit line material layer; the bit line material layer is etched using the bit line mask layer as a mask to form a plurality of bit lines 150 extending in the first direction X on the second surface 102, and the bit lines 150 are in contact with the surface of the channel region S2 of the second surface 102.

[0045] In the above method, before forming a plurality of bit lines 150 on the second surface 102, the active area S1, the word line gate structure 120 and other structures need to be formed on the first surface 101, and the carrier wafer 140 needs to be bonded toward the first surface 101, and the substrate 100 needs to be thinned from the second surface 102. Therefore, before forming the bit line patterning layer, the substrate 100 and the structure formed before forming the bit line patterning layer are affected by factors such as local stress caused by various process steps and the formed structure. The overall warping (such as Figure 4 As shown in FIG, the photolithography process for forming the bit line mask layer is difficult to align with the active area S1 pattern of the second surface 102 (i.e., the surface of the active area S1 exposed on the second surface 102). As a result, the formed bit line 150 is easily disconnected from the channel area S2, causing partial or complete failure of the memory and poor memory reliability.

[0046] To address the above technical issues, the present invention provides a dynamic random access memory (DRAM) and a method for forming the same. A substrate is provided, the substrate having a first surface and a second surface facing each other. The substrate includes a plurality of discrete active areas extending in a first direction and including a plurality of independent channel regions arranged along the first direction. Within each active area, a plurality of wordline gate structures are formed, each adjacent to a channel region. The plurality of wordline gate structures extend through the active area along a second direction perpendicular to the first direction. After forming the plurality of wordline gate structures, a first device layer is formed on the first surface. A first dielectric layer is formed on the first device layer. A plurality of stress regulation structures are formed within the first dielectric layer. After forming the plurality of stress regulation structures, a second device layer is formed on the second surface. Consequently, warpage of the DRAM can be reduced, thereby improving the reliability of the DRAM.

[0047] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0048] Figures 5 to 16 It is a structural diagram of each step in a method for forming a dynamic random access memory according to an embodiment of the present invention.

[0049] Please refer to Figure 5 and Figure 6 , Figure 5 yes Figure 6 Schematic diagram of the top view of the structure along the middle direction A, Figure 6 yes Figure 5 A schematic cross-sectional structure diagram along direction A1-A2 is provided, showing a substrate 200.

[0050] The substrate 200 has a first side 201 and a second side 202 opposite to each other.

[0051] The substrate 200 includes a plurality of separate active regions I. The active regions I extend in a first direction X. The active regions I include a plurality of independent channel regions II arranged along the first direction X.

[0052] The substrate 200 is made of semiconductor material.

[0053] In this embodiment, the substrate 200 is made of silicon. In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-component semiconductor material composed of Group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator. The multi-component semiconductor material composed of Group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0054] In this embodiment, the method for forming the substrate 200 includes: providing an initial substrate (not labeled in the figure); forming a plurality of first isolation masks (not labeled in the figure) separated from each other on a surface of the initial substrate, wherein the first isolation masks extend along a first direction X, and the plurality of first isolation masks are arranged along a second direction Y; etching the initial substrate using the plurality of first isolation masks as masks to form a plurality of first isolation openings (not labeled in the figure) in the initial substrate, wherein the first isolation openings extend along the first direction X, the plurality of first isolation openings are arranged along the second direction Y, and the first surface 201 exposes the first isolation openings.

[0055] The second direction Y is perpendicular to the first direction X.

[0056] Thus, the substrate 200 is formed, and adjacent active regions I are separated by the first isolation openings.

[0057] In this embodiment, a first isolation structure 210 is provided between adjacent active regions I.

[0058] The material of the first isolation structure 210 includes a dielectric material, and the dielectric material includes silicon oxide or a low-K material (K is less than 3.9). The purpose of using the low-K material is to further reduce parasitic capacitance through the material with a low dielectric constant.

[0059] The method for forming the first isolation structure 210 includes: forming an isolation structure material layer in a plurality of first isolation openings and on the first surface 201, wherein the surface of the isolation structure material layer is higher than the first surface 201; flattening the isolation structure material layer until the first surface 201 is exposed, and forming the first isolation structure 210 in the first isolation openings.

[0060] Please refer to Figure 7 and Figure 8 , Figure 7 yes Figure 8 Schematic diagram of the top view of the structure along the middle direction A, Figure 8 yes Figure 7 A schematic cross-sectional structure diagram along the center direction B1-B2 shows that a plurality of word line gate structures 220 are formed in each active area I, each word line gate structure 220 is adjacent to a channel area II, and the plurality of word line gate structures 220 penetrate the active area I along the second direction Y.

[0061] The word line gate structure 220 includes a gate 221 and a gate dielectric layer 222 located between the gate 221 and the substrate 200 .

[0062] In this embodiment, the method for forming a plurality of word line gate structures 220 includes: etching the first surface 201 and the plurality of first isolation structures 210 to form a plurality of word line gate openings (not marked in the figure) in the substrate 200 and the plurality of first isolation structures 210, wherein the channel region II is located between adjacent word line gate openings and is adjacent to at least one word line gate opening; forming a gate dielectric layer 222 on the inner wall surface of the word line gate opening; after forming the gate dielectric layer 222, forming a gate 221 in the word line gate opening.

[0063] In this embodiment, the gate 221 is a single layer and is made of, for example, polysilicon or metal.

[0064] In other embodiments, the gate is a composite gate, comprising a first gate and a second gate located on top of the first gate, wherein the first gate and the second gate are made of different materials. The first gate is made of a metal material, and the second gate structure is made of polysilicon. Because the gate comprises a first gate and a second gate made of different materials, the threshold voltage of the wordline gate structure can be adjusted by adjusting the volume ratio of the first gate and the second gate to meet different device design requirements.

[0065] In this embodiment, the gate dielectric layer 222 is made of silicon oxide or a low-K material.

[0066] In other embodiments, the material of the gate dielectric layer includes a high-K material (K greater than 3.9), and the high-K material includes aluminum oxide or hafnium oxide.

[0067] In this embodiment, the top surface of the gate 221 is lower than the first surface 201 . After the wordline gate structure 220 is formed, a capping dielectric layer 223 is formed in the wordline gate opening. The capping dielectric layer 223 is located on the top surface of the gate 221 .

[0068] The function of the covering dielectric layer 223 is to protect the word line gate structure 220, reduce damage to the word line gate structure 220 in subsequent processes, and ensure the insulation between the word line gate structure 220 and the first device layer formed subsequently to meet the circuit design requirements of the memory.

[0069] In this embodiment, the material of the covering dielectric layer 223 includes a dielectric material, and the dielectric material includes silicon oxide or a low-K material. The purpose of using the low-K material is to further reduce parasitic capacitance by using a material with a low dielectric constant.

[0070] In this embodiment, after forming the capping dielectric layer 223, a second isolation structure 224 is formed between adjacent wordline gate structures 220. The second isolation structure 224 is also located in the channel region II and is adjacent to one wordline gate structure 220. The second isolation structure 224 improves the insulation between adjacent wordline gate structures 220 in the first direction X to meet device design requirements.

[0071] Since the second isolation structure 224 is formed before the subsequent formation of the stress adjustment structure, the steps between the subsequent formation of the stress adjustment structure and the formation of the second device layer can be further reduced, so that the stress can be adjusted more accurately in the subsequent process to better reduce warping.

[0072] In other embodiments, the second isolation structure may be formed after the substrate 200 is subsequently thinned from the second surface 202 .

[0073] It should be noted that, for ease of understanding, Figure 7 The cover dielectric layer 223 is not shown.

[0074] It is important to understand that Figure 6 and Figure 7 The figure only schematically illustrates one arrangement of the wordline gate structures 220 and the second isolation structures 224. The wordline gate structures 220 and the second isolation structures 224 can be arranged in any other manner according to actual design requirements. The specific arrangement of the wordline gate structures 220 and the second isolation structures 224 should not be construed as limiting the scope of protection of the present invention.

[0075] In this embodiment, after forming the capping dielectric layer 223 and before subsequently forming the first device layer, an ion implantation process is performed on the first surface 201 to implant dopant ions into the substrate 200, thereby forming a first doped region (not shown) exposed by the first surface 201 within the channel region II. The dopant ions in the first doped region include N-type ions or P-type ions. The N-type ions include phosphorus ions, arsenic ions, or antimony ions, and the P-type ions include boron ions, boron fluoride ions, or indium ions.

[0076] Next, please refer to Figure 9 , Figure 9 and Figure 8 In the same viewing direction, a first device layer 230 is formed on the first surface 201.

[0077] In this embodiment, the first device layer 230 includes: a plurality of capacitors 231 , each of the capacitors 231 being electrically connected to one of the channel regions II.

[0078] In this embodiment, each capacitor 231 is in contact with the surface of the first doped region in one channel region II.

[0079] In this embodiment, the capacitor 231 includes a first electrode layer 231 a , a second electrode layer 231 c , and a capacitor dielectric layer 231 b located between the first electrode layer 231 a and the second electrode layer 231 c .

[0080] In this embodiment, the capacitor dielectric layer 231b is in a “U” shape.

[0081] In other embodiments, the shape of the capacitor dielectric layer includes a planar shape, and accordingly, the surface of the first electrode layer is flat, and the surface of the second electrode layer is flat.

[0082] The material of the first electrode layer 231a includes: metal or metal nitride; the material of the second electrode layer 231c includes: metal or metal nitride; wherein the metal includes: a combination of one or more of copper, aluminum, tungsten, cobalt, nickel and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.

[0083] The material of the capacitor dielectric layer 231 b includes high-K materials such as titanium oxide, zirconium oxide, and hafnium oxide.

[0084] In this embodiment, the first device layer 230 further includes a first device dielectric layer 232 surrounding the plurality of capacitors 231 .

[0085] In this embodiment, the method for forming the first device layer 230 includes: forming a first device dielectric layer 232 on the first surface 201; etching the first device dielectric layer 232 to form a plurality of capacitor openings (not marked in the figure) in the first device dielectric layer 232, wherein the bottom of the capacitor openings exposes the surface of the first doped region; forming a first electrode layer 231a on the inner wall surfaces of the plurality of capacitor openings; forming a capacitor dielectric film (not marked in the figure) on the surface of the first electrode layer 231a and the surface of the first device dielectric layer 232, wherein the portion of the capacitor dielectric film located on the surface of the first electrode layer is the capacitor dielectric layer 231b; and forming a second electrode film (not marked in the figure) on the surface of the capacitor dielectric film, wherein the portion of the second electrode film located on the surface of the capacitor dielectric layer 231b is the second electrode layer 231c.

[0086] In other embodiments, the first device layer further includes: a plurality of capacitor conductive structures located between the first surface and the plurality of capacitors and surrounded by the first device dielectric layer, the top surface of each capacitor conductive structure being in contact with the capacitor, and the bottom surface of each capacitor conductive structure being in contact with the surface of the first doped region, thereby electrically connecting each capacitor to a channel region.

[0087] In another embodiment, the first device layer includes: a plurality of bit lines, each bit line being electrically connected to a plurality of channel regions within an active region; and a first device dielectric layer surrounding the plurality of bit lines.

[0088] Please refer to Figure 10 , Figure 10 and Figure 9 The viewing direction is consistent with that of FIG. 2 , and capacitor plates 240 are formed on the surfaces of the capacitors 231 . The surfaces of the capacitor plates 240 are higher than the surfaces of the capacitors 231 .

[0089] In this embodiment, the capacitor plate 240 includes: a first capacitor plate 241, the surface of which is higher than the surface of the second electrode film; and a second capacitor plate 242 located on the surface of the first capacitor plate 241. The first capacitor plate 241 is made of silicon, and the second capacitor plate 242 is made of tungsten.

[0090] The process of forming the capacitor plate 240 includes a chemical vapor deposition process, etc.

[0091] Please continue to refer to Figure 10 , forming a second dielectric layer 250 on the surface of the capacitor plate 240 .

[0092] In this embodiment, the second dielectric layer 250 is made of a dielectric material, and the dielectric material includes silicon oxide or a low-K (K less than 3.9) material.

[0093] The process of forming the second dielectric layer 250 includes a chemical vapor deposition process, etc.

[0094] Please refer to Figure 11 , Figure 11 and Figure 10 A second stress adjustment layer 260 is formed on the first device layer 230 in the same viewing direction. The second stress adjustment layer 260 is used to adjust the stress in the first direction X and the second direction Y at the same time.

[0095] Since the second stress adjustment layer 260 is formed before the subsequent formation of the first dielectric layer, a force opposite to the warping direction can be applied to the overall structure of the memory before the subsequent formation of the plurality of stress adjustment structures, thereby preliminarily reducing the overall warping of the memory structure in the first direction X and the second direction Y. Therefore, when the warping is more severe, not only is the degree of warping of the second surface 202 reduced, but the process difficulty and complexity of performing local stress adjustment using the plurality of stress adjustment structures is also reduced.

[0096] Specifically, on the one hand, the required second stress adjustment layer 260 can be formed to adjust the stress based on the warping of the formed structure and the warping predicted by experience, thereby reducing the more serious warping as a whole. On the other hand, since the overall stress adjustment is performed in advance through the second stress adjustment layer 260 before the local stress adjustment is performed through several stress adjustment structures in the future, the number of stress adjustment structures that need to be formed subsequently and the complexity of the structure can be reduced.

[0097] The material of the second stress adjustment layer 260 includes silicon oxide, silicon nitride, metal or polysilicon.

[0098] It should be understood that the material of the second stress-regulating layer 260 is selected based on the warping direction (i.e., the type of stress to be reduced or neutralized). For example, when neutralizing tensile stress in the structure, materials such as metal, polysilicon, and silicon nitride can be used; when neutralizing compressive stress in the structure, materials such as silicon oxide and silicon nitride can be used.

[0099] Specifically, in this embodiment, the second stress adjustment layer 260 is formed on the surface of the second dielectric layer 250 .

[0100] In another embodiment, the first device layer includes a plurality of bit lines and a first device dielectric layer, and the second stress adjustment layer is formed on the first device layer.

[0101] Please refer to Figure 12 and Figure 13 , Figure 12 yes Figure 13 Schematic diagram of the top view of the structure along the middle direction A, Figure 13 yes Figure 12 A schematic cross-sectional structural diagram along the direction B1 - B2 shows that a first dielectric layer 270 is formed on the surface of the second stress adjustment layer 260 .

[0102] The material of the first dielectric layer 270 includes dielectric material.

[0103] Please continue to refer to Figure 12 and Figure 13 , a plurality of stress adjustment structures 271 are formed in the first dielectric layer 270 .

[0104] The material of the stress adjustment structure 271 is different from the material of the first dielectric layer 270 .

[0105] In this embodiment, the plurality of stress adjustment structures 271 include at least one of: a plurality of first adjustment structures 271 a extending along the second direction Y; and a plurality of second adjustment structures 271 b extending along the first direction Y.

[0106] The first adjustment structure 271a is used to cut off the stress in the first direction X to reduce the warping in the first direction X. The second adjustment structure 271b is used to cut off the stress in the second direction Y to reduce the warping in the second direction Y.

[0107] The material of the stress adjustment structure 271 includes silicon oxide, silicon nitride, metal or polysilicon.

[0108] Similar to the second stress regulation layer 260, the material of the stress regulation structure 271 is selected based on the warping direction (i.e., the type of stress to be reduced or neutralized). For example, when neutralizing tensile stress in the structure, materials such as metal, polysilicon, and silicon nitride can be used; when neutralizing compressive stress in the structure, materials such as silicon oxide and silicon nitride can be used.

[0109] A height H1 of the stress adjustment structure 271 is less than or equal to a thickness H2 of the first dielectric layer 270 .

[0110] Preferably, the height H1 of the stress adjustment structure 271 is equal to the thickness H2 of the first dielectric layer 270 .

[0111] In this embodiment, the method for forming a plurality of stress adjustment structures 271 in the first dielectric layer 270 includes: forming a first mask layer (not marked in the figure) on the surface of the first dielectric layer 270, wherein the first mask layer exposes a portion of the surface of the first dielectric layer 270; etching the first dielectric layer 270 using the first mask layer as a mask to form a plurality of stress adjustment structure openings (not marked in the figure) in the first dielectric layer 270; and forming a plurality of stress adjustment structures 271 in the plurality of stress adjustment structure openings.

[0112] The depth of the stress adjustment structure opening is less than or equal to the thickness H2 of the first dielectric layer 270 , so as to form a stress adjustment structure 271 with a height H1 less than or equal to the thickness H2 .

[0113] Preferably, the depth of the stress adjustment structure opening is equal to the thickness H2 of the first dielectric layer 270 .

[0114] It should be understood that the deeper the depth of the opening of the stress adjustment structure (ie, the greater the height H1 ), the greater the adjusted stress, and a better stress adjustment effect can be achieved.

[0115] In this embodiment, the process of etching the first dielectric layer 270 includes at least one of a dry etching process and a wet etching process.

[0116] In this embodiment, the method for forming a plurality of stress adjustment structures 271 in a plurality of stress adjustment structure openings includes: forming a stress adjustment structure material layer in the plurality of stress adjustment structure openings and on the surface of the first dielectric layer 270, wherein the surface of the stress adjustment structure material layer is higher than the surface of the first dielectric layer 270; and flattening the stress adjustment structure material layer until the surface of the first dielectric layer 270 is exposed.

[0117] In this embodiment, the process of forming the stress adjustment structural material layer includes a chemical vapor deposition process, a physical vapor deposition process, etc.; the process of planarizing the stress adjustment structural material layer includes a chemical mechanical polishing process, etc.

[0118] In this embodiment, after forming a plurality of stress adjustment structure openings, the first mask layer is removed.

[0119] Compared to this embodiment, in another embodiment, the second stress adjustment layer 260 is not formed before forming the first dielectric layer 270. Instead, the second stress adjustment layer is formed on the first dielectric layer and the stress adjustment structures after forming the plurality of stress adjustment structures and before subsequently forming the bonding dielectric layer. The second stress adjustment layer is used to adjust stress in the first direction and the second direction at the same time. Since the second stress adjustment layer is formed on the first dielectric layer and the stress adjustment structures after forming the plurality of stress adjustment structures, the stress adjustment capability can be further enhanced on the basis of stress adjustment by the plurality of stress adjustment structures. Please refer to Figure 14 , Figure 14 and Figure 13 In the same viewing direction, a bonding dielectric layer 280 is formed on the first dielectric layer 270 and the plurality of stress adjustment structures 271 .

[0120] Please continue to refer to Figure 14 , providing a carrier substrate 281 , and bonding the carrier substrate 281 to the bonding dielectric layer 280 .

[0121] Next, please refer to Figure 15 and Figure 16 , Figure 15 yes Figure 16 Schematic diagram of the top view of the structure along the center direction C, Figure 16 yes Figure 15 A schematic cross-sectional structural diagram along the direction C1 - C2 , showing that the substrate 200 is thinned from the second surface 202 .

[0122] Specifically, in this embodiment, after the carrier substrate 281 is bonded to the bonding dielectric layer 280 , the substrate 200 and the carrier substrate 281 are flipped over, and the substrate 200 is thinned from the second surface 202 until the bottom surface of the first isolation structure 210 is exposed.

[0123] In this embodiment, the process of thinning the substrate 200 includes a chemical mechanical polishing process.

[0124] In this embodiment, after the substrate 200 is thinned from the second surface 202, an ion implantation process is performed on the second surface 202 to implant dopant ions into the substrate 200, thereby forming a second doped region (not shown) exposed by the second surface 202 in the channel region II. The dopant ions in the second doped region include N-type ions or P-type ions. The N-type ions include phosphorus ions, arsenic ions, or antimony ions, and the P-type ions include boron ions, boron fluoride ions, or indium ions.

[0125] Please continue to refer to Figure 15 and Figure 16 After forming the plurality of stress adjustment structures 271 , a second device layer 290 is formed on the second surface 202 .

[0126] Since the first dielectric layer 270 is formed on the first device layer 230 and a plurality of stress adjustment structures 271 are formed in the first dielectric layer 270 before the second device layer 290 is formed on the second surface 202, the stress in the first direction X and the second direction Y can be cut off and neutralized by the plurality of stress adjustment structures 271 according to the structural warping of the memory before the second device layer 290 is formed, thereby achieving local stress adjustment, so that the warping degree of the second surface 202 before the formation of the second device layer 290 is reduced. Therefore, when forming a photolithography pattern layer for patterning the second device layer 290, the pattern of the photolithography pattern layer is easily aligned with the pattern of the active area I and the channel area II on the second surface 202, and the formed second device layer 290 has high overlay accuracy, thereby reducing the risk of disconnection and virtual connection between the second device layer 290 and the channel area II, thereby improving the reliability of the memory.

[0127] Specifically, in this embodiment, after the second doping region is formed, the second device layer 290 is formed on the second surface 202 .

[0128] The second device layer 290 includes: a plurality of bit lines 291 , each of which is electrically connected to a plurality of channel regions II in an active region I.

[0129] In this embodiment, each bit line 291 contacts the surfaces of the second doping regions of a plurality of channel regions II within one active region I.

[0130] Preferably, each bit line 291 has a bit line projection (not marked in the figure) on the second surface 202, and each bit line projection is within the range of one active region I, so as to further reduce the risk of disconnection or virtual connection between the bit line 291 and the channel region II.

[0131] It should be noted that the projection of the bit line within the range of one active region I means that the projection of the bit line is within the area of ​​the surface of one active region I exposed by the second surface 202 .

[0132] In this embodiment, the second device layer 290 further includes a second device dielectric layer 292 surrounding a plurality of bit lines 291 .

[0133] In this embodiment, the method for forming the second device layer 290 includes: forming a second device dielectric layer 292 on the second surface 202; etching the second device dielectric layer 292 to form a plurality of bit line openings (not marked in the figure) in the second device dielectric layer 292, wherein the bottom of the bit line opening exposes the surface of the second doped region; and forming a bit line 291 in the bit line opening.

[0134] In other embodiments, the second device layer further includes: a plurality of bit line conductive structures located between the second surface and the plurality of bit lines and surrounded by the second device dielectric layer, the surface of each bit line conductive structure being in contact with the bit line surface and the surface of the first doped region, respectively, so that each bit line 291 is electrically connected to a plurality of channel regions II within an active region I.

[0135] In another embodiment, the second device layer includes: a plurality of capacitors, each of the capacitors being electrically connected to one of the channel regions; and a second device dielectric layer surrounding the plurality of capacitors.

[0136] Accordingly, an embodiment of the present invention further provides a dynamic random access memory formed by the above method, please continue to refer to Figure 15 and Figure 16, comprising: a substrate 200, the substrate 200 having a first surface 201 and a second surface 202 opposite to each other, the substrate 200 including a plurality of separate active areas I, the active areas I extending in a first direction X, the active areas I including a plurality of independent channel areas II arranged along the first direction X; a plurality of word line gate structures 220 located in each active area I, each word line gate structure 220 adjacent to one channel area II, the plurality of word line gate structures 220 penetrating the active area I along a second direction Y, the second direction Y being perpendicular to the first direction X; a first device layer 230 located on the first surface 201; a first dielectric layer 270 located on the first device layer 230; a plurality of stress adjustment structures 271 located in the first dielectric layer 270; and a second device layer 290 located on the second surface 202.

[0137] The substrate 200 is made of semiconductor material.

[0138] In this embodiment, the substrate 200 is made of silicon. In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-component semiconductor material composed of Group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator. The multi-component semiconductor material composed of Group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0139] In this embodiment, a first isolation structure 210 is provided between adjacent active regions I. The first surface 201 exposes a top surface of the first isolation structure 210 , and the second surface 202 exposes a bottom surface of the first isolation structure 210 .

[0140] The material of the first isolation structure 210 includes a dielectric material, and the dielectric material includes silicon oxide or a low-K material (K is less than 3.9). The purpose of using the low-K material is to further reduce parasitic capacitance through the material with a low dielectric constant.

[0141] In this embodiment, the word line gate structure 220 includes a gate 221 and a gate dielectric layer 222 located between the gate 221 and the substrate 200 .

[0142] In this embodiment, the gate 221 is a single layer and is made of, for example, polysilicon or metal.

[0143] In other embodiments, the gate is a composite gate, comprising a first gate and a second gate located on top of the first gate, wherein the first gate and the second gate are made of different materials. The first gate is made of a metal material, and the second gate structure is made of polysilicon. Because the gate comprises a first gate and a second gate made of different materials, the threshold voltage of the wordline gate structure can be adjusted by adjusting the volume ratio of the first gate and the second gate to meet different device design requirements.

[0144] In this embodiment, the gate dielectric layer 222 is made of silicon oxide or a low-K material.

[0145] In other embodiments, the material of the gate dielectric layer includes a high-K material (K greater than 3.9), and the high-K material includes aluminum oxide or hafnium oxide.

[0146] In this embodiment, the top surface of the gate 221 is lower than the first surface 201 , and the dynamic random access memory further includes a covering dielectric layer 223 located on the top surface of the gate 221 .

[0147] In this embodiment, the material of the covering dielectric layer 223 includes a dielectric material, and the dielectric material includes silicon oxide or a low-K material. The purpose of using the low-K material is to further reduce parasitic capacitance by using a material with a low dielectric constant.

[0148] In this embodiment, the dynamic random access memory further includes: a second isolation structure 224 located between adjacent word line gate structures 220, the first surface exposes the surface of the second isolation structure 224, and the second isolation structure 224 is also located in the channel region II and is adjacent to one word line gate structure 220.

[0149] It should be understood that the wordline gate structures 220 and the second isolation structures 224 can be arranged according to actual design requirements. The specific arrangement of the wordline gate structures 220 and the second isolation structures 224 should not be a feature that limits the scope of protection of the present invention.

[0150] In other embodiments, the dynamic random access memory further includes: a second isolation structure located between adjacent word line gate structures, the second surface exposing a surface of the second isolation structure, the second isolation structure also located in the channel region and adjacent to one word line gate structure.

[0151] In this embodiment, the material of the first dielectric layer 270 includes a dielectric material, and the material of the stress adjustment structure 271 is different from the material of the first dielectric layer 270 .

[0152] In this embodiment, the plurality of stress adjustment structures 271 include at least one of a plurality of first adjustment structures 271 a extending along the second direction Y and a plurality of second adjustment structures 271 b extending along the first direction X.

[0153] The first adjustment structure 271 a is used to cut off the stress in the first direction X to reduce the warping in the first direction X.

[0154] The second adjustment structure 271b is used to cut off the stress in the second direction Y to reduce the warping in the second direction Y.

[0155] In this embodiment, the material of the stress adjustment structure 271 includes silicon oxide, silicon nitride, metal or polysilicon.

[0156] A height H1 of the stress adjustment structure 271 is less than or equal to a thickness H2 of the first dielectric layer 270 .

[0157] Preferably, the height H1 of the stress adjustment structure 271 is equal to the thickness H2 of the first dielectric layer 270 .

[0158] In this embodiment, the channel region II includes a first doping region (not marked in the figure) and a second doping region. The first doping region is exposed by the first surface 201 , and the second doping region is exposed by the second surface 202 .

[0159] Among them, the doping ions in the first doping region include N-type ions or P-type ions, and the doping ions in the second doping region include N-type ions or P-type ions, the N-type ions include phosphorus ions, arsenic ions or antimony ions, and the P-type ions include boron ions, boron fluoride ions or indium ions.

[0160] In this embodiment, the first device layer 230 includes: a plurality of capacitors 231 , each of the capacitors 231 being electrically connected to one of the channel regions II.

[0161] In this embodiment, each capacitor 231 is in contact with the surface of the first doped region in one channel region II.

[0162] In this embodiment, the capacitor 231 includes a first electrode layer 231 a , a second electrode layer 231 c , and a capacitor dielectric layer 231 b located between the first electrode layer 231 a and the second electrode layer 231 c .

[0163] In this embodiment, the capacitor dielectric layer 231b is in a “U” shape.

[0164] In other embodiments, the shape of the capacitor dielectric layer includes a planar shape, and accordingly, the surface of the first electrode layer is flat, and the surface of the second electrode layer is flat.

[0165] The material of the first electrode layer 231a includes: metal or metal nitride; the material of the second electrode layer 231c includes: metal or metal nitride; wherein the metal includes: a combination of one or more of copper, aluminum, tungsten, cobalt, nickel and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.

[0166] The material of the capacitor dielectric layer 231 b includes high-K materials such as titanium oxide, zirconium oxide, and hafnium oxide.

[0167] In this embodiment, the first device layer 230 further includes a first device dielectric layer 232 surrounding the plurality of capacitors 231 .

[0168] In other embodiments, the first device layer further includes: a plurality of capacitor conductive structures located between the first surface and the plurality of capacitors and surrounded by the first device dielectric layer, the top surface of each capacitor conductive structure being in contact with the capacitor, and the bottom surface of each capacitor conductive structure being in contact with the surface of the first doped region, thereby electrically connecting each capacitor to a channel region.

[0169] In this embodiment, the second device layer 290 includes: a plurality of bit lines 291 , each of which is electrically connected to a plurality of channel regions II in one active region I.

[0170] In this embodiment, each bit line 291 contacts the surfaces of the second doping regions of a plurality of channel regions II within one active region I.

[0171] Preferably, each bit line 291 has a bit line projection (not marked in the figure) on the second surface 202, and each bit line projection is within the range of one active region I, so as to further reduce the risk of disconnection or virtual connection between the bit line 291 and the channel region II.

[0172] In this embodiment, the second device layer 290 further includes a second device dielectric layer 292 surrounding a plurality of bit lines 291 .

[0173] In other embodiments, the second device layer further includes: a plurality of bit line conductive structures located between the second surface and the plurality of bit lines and surrounded by the second device dielectric layer, the surface of each bit line conductive structure being in contact with the bit line surface and the surface of the first doped region, respectively, so that each bit line 291 is electrically connected to a plurality of channel regions II within an active region I.

[0174] In another embodiment, the first device layer includes: a plurality of bit lines, each bit line is electrically connected to a plurality of channel regions within an active region; a first device dielectric layer surrounding the plurality of bit lines; the second device layer includes: a plurality of capacitors, each capacitor is electrically connected to a channel region; and a second device dielectric layer surrounding the plurality of capacitors.

[0175] In this embodiment, the dynamic random access memory further includes a second stress adjustment layer 260 located between the first device layer 230 and the first dielectric layer 270 . The second stress adjustment layer 260 is configured to adjust stress in the first direction X and the second direction Y simultaneously.

[0176] Specifically, in this embodiment, the second stress adjustment layer 260 is located between the plurality of capacitors 231 and the first dielectric layer 270 .

[0177] In another embodiment, the second stress adjustment layer is located between the plurality of bit lines and the first dielectric layer, and the second stress adjustment layer is used to adjust stress in the first direction and the second direction simultaneously.

[0178] In yet another embodiment, the second stress adjustment layer is located on the first dielectric layer and the plurality of stress adjustment structures, and the second stress adjustment layer is configured to adjust stress in the first direction and the second direction simultaneously.

[0179] In this embodiment, the material of the second stress adjustment layer 260 includes silicon oxide, silicon nitride, metal or polysilicon.

[0180] In this embodiment, the dynamic random access memory further includes: a capacitor plate 240 located between the plurality of capacitors 231 and the second stress adjustment layer 260 ; and a second dielectric layer 250 located between the capacitor plate 240 and the second stress adjustment layer 260 .

[0181] In this embodiment, the surface of the capacitor plate 240 is higher than the surface of the capacitor 231. The capacitor plate 240 includes: a first capacitor plate 241, the surface of which is higher than the surface of the capacitor 231; and a second capacitor plate 242 located on the surface of the first capacitor plate 241. The first capacitor plate 241 is made of silicon, and the second capacitor plate 242 is made of tungsten.

[0182] In this embodiment, the second dielectric layer 250 is made of a dielectric material, and the dielectric material includes silicon oxide or a low-K (K less than 3.9) material.

[0183] In this embodiment, the dynamic random access memory further includes: a bonding dielectric layer 280 located on the first dielectric layer 270 and the plurality of stress adjustment structures 271 ; and a carrier substrate 281 bonded to the bonding dielectric layer 280 .

[0184] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A dynamic random access memory, characterized in that: include: A substrate having a first surface and a second surface opposite to each other, the substrate including a plurality of mutually separated active regions, the active regions extending in a first direction, and the active regions including a plurality of mutually independent channel regions arranged along the first direction; a plurality of word line gate structures located in each active area, each word line gate structure being adjacent to a channel area, the plurality of word line gate structures penetrating the active area along a second direction, the second direction being perpendicular to the first direction; A first device layer located on the first surface, the first device layer comprising: a plurality of bit lines, each bit line being electrically connected to a plurality of channel regions within an active region; a first dielectric layer on the first device layer; a plurality of stress regulation structures located within the first dielectric layer; A second device layer located on the second surface, wherein the second device layer includes: a plurality of capacitors, each of the capacitors being electrically connected to one of the channel regions.

2. The dynamic random access memory according to claim 1, wherein: The plurality of stress adjustment structures include: a plurality of first adjustment structures extending along the second direction, wherein the first adjustment structures are used to cut off the stress in the first direction.

3. The dynamic random access memory according to claim 1 or 2, wherein: The plurality of stress adjustment structures include: a plurality of second adjustment structures extending along the first direction, and the second adjustment structures are used to cut off the stress in the second direction.

4. The dynamic random access memory according to claim 1, wherein: Also includes: A second stress adjustment layer is located between the first device layer and the first dielectric layer, and the second stress adjustment layer is used to simultaneously adjust stress in the first direction and the second direction.

5. The dynamic random access memory according to claim 1, wherein: Also includes: A second stress adjustment layer is located on the first dielectric layer and the plurality of stress adjustment structures, and the second stress adjustment layer is used to simultaneously adjust stress in the first direction and the second direction.

6. The dynamic random access memory according to claim 1, wherein: The first device layer includes: a plurality of capacitors, each of which is electrically connected to one of the channel regions; the second device layer includes: a plurality of bit lines, each of which is electrically connected to a plurality of channel regions in one active region.

7. The dynamic random access memory according to claim 6, wherein: Each of the bit lines has a bit line projection on the second surface, and each of the bit line projections is within the range of one active region.

8. The dynamic random access memory according to claim 6, wherein: Also includes: a second stress adjustment layer located between the plurality of capacitors and the first dielectric layer, the second stress adjustment layer being configured to simultaneously adjust stress in the first direction and the second direction; a capacitor plate located between the plurality of capacitors and the second stress adjustment layer; and a second dielectric layer located between the capacitor plate and the second stress adjustment layer.

9. The dynamic random access memory according to claim 1, wherein: The material of the stress adjustment structure is different from the material of the first dielectric layer.

10. The dynamic random access memory according to claim 9, wherein: The material of the stress adjustment structure includes silicon oxide, silicon nitride, metal or polysilicon.

11. The dynamic random access memory according to claim 4, 5 or 8, wherein: The material of the second stress adjustment layer includes silicon oxide, silicon nitride, metal or polysilicon.

12. The dynamic random access memory according to claim 1, wherein: The height of the stress adjustment structure is equal to the thickness of the first dielectric layer.

13. The dynamic random access memory according to claim 1, wherein: Also includes: a bonding dielectric layer located on the first dielectric layer and the plurality of stress modulation structures; A carrier substrate is bonded to the bonding dielectric layer.

14. A method for forming a dynamic random access memory, characterized in that: include: Providing a substrate, wherein the substrate has a first surface and a second surface opposite to each other, the substrate comprising a plurality of mutually separate active regions, the active regions extending in a first direction, and the active regions comprising a plurality of mutually independent channel regions arranged along the first direction; forming a plurality of word line gate structures in each active area, each word line gate structure being adjacent to a channel area, and the plurality of word line gate structures penetrating the active area along a second direction, wherein the second direction is perpendicular to the first direction; After forming a plurality of word line gate structures, forming a first device layer on the first surface, the first device layer comprising: a plurality of capacitors, each of the capacitors being electrically connected to one of the channel regions; forming a first dielectric layer on the first device layer; forming a plurality of stress regulation structures in the first dielectric layer; After forming the plurality of stress adjustment structures, a second device layer is formed on the second surface, wherein the second device layer includes a plurality of bit lines, each of which is electrically connected to a plurality of channel regions in one active region.

15. The method for forming a dynamic random access memory according to claim 14, wherein: The method for forming a plurality of stress adjustment structures in the first dielectric layer includes: forming a first mask layer on the surface of the first dielectric layer, the first mask layer exposing a portion of the surface of the first dielectric layer; etching the first dielectric layer using the first mask layer as a mask to form a plurality of stress adjustment structure openings in the first dielectric layer; and forming a plurality of stress adjustment structures in the plurality of stress adjustment structure openings.

16. The method for forming a dynamic random access memory according to claim 15, wherein: The depth of the stress adjustment structure opening is equal to the thickness of the first dielectric layer.

17. The method for forming a dynamic random access memory according to claim 14, wherein: Before forming the first dielectric layer, the method further includes: forming a second stress adjustment layer on the first device layer, wherein the second stress adjustment layer is used to simultaneously adjust stress in the first direction and the second direction.

18. The method for forming a dynamic random access memory according to claim 17, wherein: The first device layer includes: a plurality of capacitors, each of which is electrically connected to one of the channel regions.

19. The method for forming a dynamic random access memory according to claim 18, wherein: Before forming the second stress adjustment layer, the method further includes: forming capacitor plates on the surfaces of several capacitors, wherein the surfaces of the capacitor plates are higher than the capacitor surfaces; and forming a second dielectric layer on the surfaces of the capacitor plates.

20. The method for forming a dynamic random access memory according to claim 14, wherein: The first device layer includes: a plurality of bit lines, each of which is electrically connected to a plurality of channel regions in an active region; the second device layer includes: a plurality of capacitors, each of which is electrically connected to one of the channel regions.

21. The method for forming a dynamic random access memory according to claim 14, wherein: Before forming the second device layer, it also includes: forming a bonding dielectric layer on the first dielectric layer and several stress adjustment structures; providing a carrier substrate; bonding the carrier substrate to the bonding dielectric layer; after bonding the carrier substrate to the bonding dielectric layer, thinning the substrate from the second side.

22. The method for forming a dynamic random access memory according to claim 14, wherein: Before forming the second device layer, the method further includes: forming a second stress adjustment layer on the first dielectric layer and the plurality of stress adjustment structures, wherein the second stress adjustment layer is used to simultaneously adjust stress in the first direction and the second direction.

Images