Display substrate, preparation method thereof and display device

Abstract

A display substrate includes a display area, a notched area, and a capacitance compensation area. The display area at least partially surrounds the notched area, and the capacitance compensation area is located between the display area and the notched area. The capacitance compensation area is provided with a first capacitance compensation unit. The first capacitance compensation unit includes a semiconductor structure, a first metal structure, and a second metal structure arranged in sequence on a base. An insulating layer between the semiconductor structure and the second metal structure is provided with a plurality of first vias, and the second metal structure is connected with the semiconductor structure through the plurality of first vias. The first metal structure includes a plurality of second gate lines extending along a first direction. The second gate lines form a capacitance with the second metal structure and the semiconductor structure. The plurality of first vias are arranged along the first direction, and in a second direction perpendicular to the first direction, a distance between two adjacent first vias is at least greater than a sum of widths of two second gate lines.

Description

Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, and in particular to a display substrate and its preparation method, and a display device. Background Technology

[0002] With the rapid development of display technology, consumers have increasingly higher requirements for the appearance of display devices. Many display panels have changed from the traditional square shape to the currently popular irregular shapes, such as rounded corners and notched displays. These irregular shapes undoubtedly pose a challenge to manufacturers. For example, irregularly shaped displays with notches (e.g., "notch" screens) are increasingly being adopted by mobile phone manufacturers. These irregularly shaped displays are advantageous for achieving a higher screen-to-body ratio, and the notch design allows for space for components such as the front-facing camera. However, this notch design can cause differences in the gate line signals of pixels on both sides of the notch compared to pixels in other display areas, potentially leading to display inhomogeneity (Mura) problems. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a display substrate, a method for fabricating the same, and a display device.

[0005] On one hand, this disclosure provides a display substrate, including: a display area, a cutout area, and a capacitance compensation area. The display area at least partially surrounds the cutout area, and the capacitance compensation area is located between the display area and the cutout area. Multiple first gate lines are disposed within the display area. A first capacitance compensation unit is disposed within the capacitance compensation area. The first capacitance compensation unit includes: a semiconductor structure, a first metal structure, and a second metal structure sequentially disposed on a substrate. The semiconductor structure is insulated from the first metal structure, and the first metal structure is insulated from the second metal structure. An insulating layer between the semiconductor structure and the second metal structure is provided with multiple first vias, and the second metal structure is connected to the semiconductor structure through the multiple first vias. The first metal structure includes multiple second gate lines extending along a first direction, at least one second gate line being connected to a corresponding first gate line; the orthographic projection of the second gate line on the substrate at least partially overlaps with the orthographic projection of the second metal structure on the substrate, and the orthographic projection of the second gate line on the substrate at least partially overlaps with the orthographic projection of the semiconductor structure on the substrate; the second gate line, the second metal structure, and the semiconductor structure form a capacitor. The plurality of first vias are arranged along the first direction, and in a second direction perpendicular to the first direction, the distance between two adjacent first vias is at least greater than the sum of the widths of the two second gate lines.

[0006] On the other hand, this disclosure provides a display device including a display substrate as described above.

[0007] On the other hand, this disclosure provides a method for fabricating a display substrate. The display substrate includes: a display area, a cutout area, and a capacitance compensation area, wherein the display area at least partially surrounds the cutout area, and the capacitance compensation area is located between the display area and the cutout area. The fabrication method includes: providing a substrate; and sequentially forming a semiconductor structure, a first metal structure, and a second metal structure on the substrate in the capacitance compensation area located between the display area and the cutout area. The semiconductor structure is insulated from the first metal structure, and the first metal structure is insulated from the second metal structure. An insulating layer between the semiconductor structure and the second metal structure is provided with a plurality of first vias, and the second metal structure is connected to the semiconductor structure through the plurality of first vias. The first metal structure includes a plurality of second gate lines extending along a first direction, respectively connected to a plurality of first gate lines within the display area; the orthographic projection of the second gate lines on the substrate at least partially overlaps with the orthographic projection of the second metal structure on the substrate, and the orthographic projection of the second gate lines on the substrate at least partially overlaps with the orthographic projection of the semiconductor structure on the substrate; the second gate lines, the second metal structure, and the semiconductor structure form a capacitor. The plurality of first vias are arranged along the first direction, and in a second direction perpendicular to the first direction, the distance between two adjacent first vias is at least greater than the sum of the widths of the two second gate lines.

[0008] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0009] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0010] Figure 1 This is a schematic diagram of the structure of a display substrate according to at least one embodiment of the present disclosure;

[0011] Figure 2 This is a partial schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0012] Figure 3 This is an equivalent circuit diagram of the driving circuit for a sub-pixel according to at least one embodiment of the present disclosure;

[0013] Figure 4 This is a top view of the driving circuit of a sub-pixel according to at least one embodiment of the present disclosure;

[0014] Figure 5AThis is a top view of a driving circuit after the semiconductor layer has been formed, according to at least one embodiment of this disclosure;

[0015] Figure 5B This is a top view of the driving circuit after the first conductive layer has been formed according to at least one embodiment of the present disclosure;

[0016] Figure 5C This is a top view of the driving circuit after the second conductive layer is formed according to at least one embodiment of the present disclosure;

[0017] Figure 5D This is a top view of the driving circuit after the third conductive layer is formed according to at least one embodiment of the present disclosure;

[0018] Figure 6 for Figure 2 A cross-sectional view along the PP direction;

[0019] Figure 7 for Figure 2 A magnified view of a portion of region Q in the middle;

[0020] Figure 8A for Figure 7 Top view of a semiconductor structure;

[0021] Figure 8B for Figure 7 Top view of the second metal structure in the middle;

[0022] Figure 9 This is a schematic diagram of a capacitor compensation region according to at least one embodiment of the present disclosure;

[0023] Figure 10 for Figure 9 A cross-sectional view along the PP direction;

[0024] Figure 11 for Figure 9 A magnified view of a portion of the central region S1;

[0025] Figure 12A for Figure 11 Top view of a semiconductor structure;

[0026] Figure 12B for Figure 11 Top view of the second metal structure in the middle;

[0027] Figure 13 This is a schematic diagram of another structure of the capacitance compensation region according to at least one embodiment of the present disclosure;

[0028] Figure 14 for Figure 13 A cross-sectional view along the PP direction;

[0029] Figure 15 for Figure 13 A magnified view of a portion of the central region S2;

[0030] Figure 16A for Figure 15 Top view of a semiconductor structure;

[0031] Figure 16B for Figure 15 Top view of the second metal structure in the middle;

[0032] Figure 17 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Detailed Implementation

[0033] This disclosure describes several embodiments, but these descriptions are exemplary and not limiting, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the embodiments, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0034] This disclosure includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this disclosure may also be combined with any conventional features or elements to form a unique technical solution as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other technical solutions to form another unique technical solution as defined by the claims. Therefore, it should be understood that any feature shown or discussed in this disclosure may be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, one or more modifications and changes may be made within the scope of the appended claims.

[0035] Furthermore, in describing representative embodiments, the specification may have presented a method or process as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims relating to the method or process should not be limited to the steps performed in the order written, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments disclosed herein.

[0036] The embodiments will now be described with reference to the accompanying drawings. These embodiments can be implemented in several different forms. Those skilled in the art will readily understand that the methods and content can be varied in different forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as being limited to the content described in the following embodiments.

[0037] In the accompanying drawings, the size of each component, the thickness of a layer, or the area are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of each part in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0038] The ordinal numbers such as "first," "second," and "third" used in this disclosure are provided to avoid confusion among the constituent elements, not to limit the quantity. In this disclosure, "multiple" can refer to two or more numbers.

[0039] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. It is understood that when an element such as a layer, film, region, or substrate is referred to as being "above" or "below" another element, that element may be located "directly" above or below the other element, or there may be intermediate elements. The positional relationships of the constituent elements vary appropriately depending on the direction in which each constituent element is described. Therefore, the terminology used is not limited to those described in the specification and may be appropriately replaced as appropriate.

[0040] In this disclosure, terms such as “connection,” “coupled,” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. An “electrical connection” includes situations where constituent elements are connected together by a component having some electrical function. There are no particular limitations on the “component having some electrical function” as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of “components having some electrical function” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with one or more functions.

[0041] In this disclosure, "parallel" means that the angle formed by two straight lines is greater than or equal to -10° and less than 10°, or may include the angle being greater than or equal to -5° and less than 5°. Furthermore, "perpendicular" means that the angle formed by two straight lines is greater than or equal to 80° and less than 100°, or may include the angle being greater than or equal to 85° and less than 95°.

[0042] In this disclosure, the terms "film" and "layer" can be interchanged. For example, sometimes "conductive layer" can be replaced with "conductive film". Similarly, sometimes "insulating film" can be replaced with "insulating layer".

[0043] In this disclosure, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this disclosure, the channel region refers to the region through which current primarily flows. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0044] Those skilled in the art will understand that the transistors used in all embodiments of this disclosure can be thin-film transistors, field-effect transistors, or other devices with the same characteristics. Exemplarily, the thin-film transistors used in the embodiments of this disclosure can be oxide semiconductor transistors. Since the source and drain electrodes of the switching transistors used here are symmetrical, their source and drain electrodes can be interchanged. In the embodiments of this disclosure, the control electrode can be the gate electrode. To distinguish the two electrodes of the transistor other than the gate electrode, one electrode is called the first electrode, and the other electrode is called the second electrode. The first electrode can be either the source electrode or the drain electrode, and the second electrode can be either the drain electrode or the source electrode.

[0045] This disclosure provides a display substrate and its preparation method, as well as a display device, which can improve the display effect of the display device.

[0046] This disclosure provides a display substrate, including: a display area, a cutout area, and a capacitance compensation area. The display area at least partially surrounds the cutout area, and the capacitance compensation area is located between the display area and the cutout area. Multiple first gate lines are disposed within the display area. A first capacitance compensation unit is disposed within the capacitance compensation area. The first capacitance compensation unit includes: a semiconductor structure, a first metal structure, and a second metal structure sequentially disposed on a substrate. The semiconductor structure is insulated from the first metal structure, and the first metal structure is insulated from the second metal structure. An insulating layer between the semiconductor structure and the second metal structure has multiple first vias, and the second metal structure is connected to the semiconductor structure through the multiple first vias. The first metal structure includes multiple second gate lines extending along a first direction, and at least one second gate line is connected to a corresponding first gate line. The orthographic projection of the second gate line on the substrate at least partially overlaps with the orthographic projection of the second metal structure on the substrate, and the orthographic projection of the second gate line on the substrate at least partially overlaps with the orthographic projection of the semiconductor structure on the substrate. The second gate line, the second metal structure, and the semiconductor structure form a capacitor. Multiple first vias are arranged along a first direction, and in a second direction perpendicular to the first direction, the distance between two adjacent first vias is at least greater than the sum of the widths of the two second gate lines.

[0047] In this disclosure, "width" refers to the feature dimension in the direction perpendicular to the extension direction of the signal line. For example, the width of the second gate line is the length of the second gate line along the second direction.

[0048] The display substrate provided in this embodiment, by setting a first capacitor compensation unit in the capacitor compensation area between the display area and the notch area, can compensate for the load capacitance of the first gate line that bypasses the notch area in the display area, thereby ensuring the display uniformity of the display area. Furthermore, the plurality of first vias connecting the semiconductor structure and the second metal structure are arranged along a first direction, and in the second direction, the distance between two adjacent first vias is at least greater than the sum of the widths of the two second gate lines, which can save the space occupied by the first capacitor compensation unit and help reduce the bezel size.

[0049] In some exemplary embodiments, the first metal structure includes N second gate lines extending along a first direction, where N is an integer greater than 1. In some examples, N can be determined based on the length of the capacitance compensation region along the second direction and the width of the second gate lines. For example, the total width of the N second gate lines is less than the length of the capacitance compensation region along the second direction. In the second direction perpendicular to the first direction, the distance between two adjacent first vias is at least greater than the sum of the widths of the two second gate lines and less than the sum of the widths of the N second gate lines. For example, in the second direction perpendicular to the first direction, the N second gate lines can be grouped together, with multiple first vias arranged along the first direction on opposite sides of the N second gate lines.

[0050] In some exemplary embodiments, the first metal structure includes N second gate lines extending along a first direction, where N is an integer greater than 1. In a second direction perpendicular to the first direction, the distance between two adjacent first vias is greater than the sum of the widths of the N second gate lines. For example, in the second direction perpendicular to the first direction, two or more second gate lines can be grouped together, and multiple first vias arranged along the first direction can be provided at the adjacent edges of any two groups of second gate lines. However, this embodiment is not limited to this.

[0051] In some exemplary embodiments, the semiconductor structure may include at least one semiconductor block. A plurality of first vias may be located on one side edge or opposite sides of the at least one semiconductor block in a second direction. In some examples, the semiconductor structure may include a plurality of semiconductor blocks arranged in an array. For example, the semiconductor block located in the middle region of the semiconductor block array may be rectangular, and the semiconductor blocks located in the two side edge regions in the first direction may be triangular or trapezoidal, with the longer side of the triangle or trapezoid adjacent to the rectangular semiconductor block. Alternatively, the semiconductor structure may include a single semiconductor block. However, this embodiment is not limited to this.

[0052] In some exemplary embodiments, the semiconductor structure includes a plurality of semiconductor blocks arranged sequentially along a first direction, at least one of which has a length ranging from 10 to 300 micrometers along the first direction. For example, the length of the semiconductor block along the first direction can be 260 micrometers. However, this embodiment is not limited thereto.

[0053] In some exemplary embodiments, the width of at least one second gate line included in the first metal structure may differ from the width of adjacent second gate lines. For example, the first metal structure may include multiple second gate lines with different widths. However, this embodiment is not limited to this. In this exemplary embodiment, when the shapes of the semiconductor structure and the second metal structure are fixed, by adjusting the width of the second gate line of the first metal structure, the capacitance formed by the second gate line, the second metal structure, and the semiconductor structure can be adjusted, thereby achieving targeted compensation of the load capacitance of the first gate line connected to the second gate line within the display area.

[0054] In some exemplary embodiments, the orthographic projection of the second metal structure onto the substrate may overlap with the orthographic projection of the semiconductor structure onto the substrate. However, this embodiment is not limited to this. In some examples, the orthographic projection of the second metal structure onto the substrate and the orthographic projection of the semiconductor structure onto the substrate may partially overlap.

[0055] In some exemplary embodiments, the capacitance compensation region may further include a second capacitance compensation unit. The second capacitance compensation unit may include a third metal structure and a fourth metal layer structure sequentially disposed on the substrate and insulated from each other. The third metal structure and the first metal structure are co-layered, and the fourth metal structure and the second metal structure are co-layered. The orthographic projections of the third metal structure and the fourth metal structure on the substrate at least partially overlap, and the third and fourth metal structures form a capacitor. In some examples, the second capacitance compensation unit may be located on the side of the first capacitance compensation unit closer to the display area. However, this embodiment is not limited to this.

[0056] In some exemplary embodiments, the second metal structure includes at least a first potential signal line extending along a first direction. For example, the first potential signal line may be a low-potential power line (VSS) or a high-potential power line (VDD) in the display substrate. However, this embodiment is not limited to this. In some examples, the first potential signal line may be other traces providing low-potential signals, or other traces providing high-potential signals. This embodiment does not limit the concepts of high and low potentials; high and low potentials are relative terms.

[0057] In some exemplary embodiments, the display substrate may further include a border region located around the display area and away from the cutout area. The width of the first potential signal line in the capacitance compensation region may be greater than the width of the first potential signal line in the border region. Multiple positions of the first potential signal line in the border region may be configured with equal widths. Multiple positions of the first potential signal line in the capacitance compensation region may have different widths.

[0058] In some exemplary embodiments, the first potential signal line within the capacitance compensation region has a main body and an extension. The main body extends along a first direction, the extension extends along a second direction, and the end of the extension near the trench region is connected to the main body. The length of the extension in the first direction gradually increases and then decreases along the direction away from the trench region. However, this embodiment is not limited to this. In some examples, the length of the extension in the first direction gradually increases or gradually decreases and then increases along the direction away from the trench region.

[0059] In some exemplary embodiments, the second metal structure further includes an extension electrode. The extension electrode is connected to the first potential signal line via multiple connecting electrodes. In some examples, the first potential signal line is a low-potential power line, in which case the extension electrode is located on the side of the first potential signal line away from the trench area. In some examples, the first potential signal line is a high-potential power line, in which case the extension electrode is located on the side of the first potential signal line closer to the trench area. However, this embodiment is not limited to this. By providing the extension electrode in this exemplary embodiment, the coverage area of ​​the first capacitance compensation unit can be increased.

[0060] In some exemplary embodiments, multiple connecting electrodes may be disposed in the same layer as the first metal structure, or multiple connecting electrodes may be disposed in the same layer as the first gate line. However, this embodiment is not limited to this. In some exemplary embodiments, the insulating layer between the film layer containing the multiple connecting electrodes and the second metal structure may be provided with multiple second vias. The extension electrode and the first potential signal line may be connected to the connecting electrodes through the multiple second vias respectively. Wherein, the first vias and the second vias may be spaced apart from each other and arranged along a first direction. However, this embodiment is not limited to this. In some examples, the first vias and the second vias may be arranged along the first direction respectively, and in the second direction, the distance between the first vias and the second vias may be at least greater than the sum of the widths of the two second gate lines.

[0061] In some exemplary embodiments, the display area may be provided with a plurality of sub-pixels arranged in a regular pattern. At least one sub-pixel may include: a light-emitting element and a driving circuit for driving the light-emitting element to emit light. The driving circuit may include a plurality of transistors and a storage capacitor. The display area may include: a substrate and a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer sequentially disposed on the substrate. The semiconductor layer may include: an active layer of a plurality of transistors; the first conductive layer may include: gate electrodes of a plurality of transistors, a first electrode of a storage capacitor, and a first gate line connected to the gate electrode; the second conductive layer may include: a second electrode of a storage capacitor; the third conductive layer may include: source electrodes and drain electrodes of a plurality of transistors. The semiconductor structure and the semiconductor layer may be disposed in the same layer; the first metal structure and the second conductive layer may be disposed in the same layer; the second metal structure and the third conductive layer may be disposed in the same layer. The second gate line included in the first metal structure is connected to the corresponding first gate line in the first conductive layer.

[0062] The following examples illustrate the display substrate provided in the embodiments of this disclosure.

[0063] Figure 1 This is a schematic diagram of the structure of a display substrate according to at least one embodiment of the present disclosure. Figure 1 As shown, this embodiment provides a display substrate, which may include: a display area A, a capacitance compensation area B1, a bezel area B2, and a cutout area C. The cutout area C may be located on one side of the display area A. The display area A may extend outward to form the capacitance compensation area B1 and the bezel area B2; that is, the display area A, the capacitance compensation area B1, and the bezel area B2 may be continuous areas. The cutout area C and the display area A may be two areas interconnected by the capacitance compensation area B1 and not overlapping. The cutout area C and the capacitance compensation area B1 may be interconnected and not overlapping.

[0064] In at least one exemplary embodiment, such as Figure 1 As shown, the capacitance compensation area B1 can be located on the side of display area A closest to the cutout area C, and can also be located between the cutout area C and display area A. The side of display area A away from the cutout area C can be surrounded by the bezel area B2. The shape of the connected capacitance compensation area B1 and bezel area B2 is the same as the shape of the outer contour of display area A. In other words, the connected capacitance compensation area B1 and bezel area B2 are set around the outer contour of display area A. For example, if part of the outer contour of display area A is arc-shaped, the area surrounding that part of the outer contour can be an arc-shaped area with the same curvature.

[0065] In at least one exemplary embodiment, such as Figure 1 As shown, display area A, capacitance compensation area B1, border area B2, and cutout area C can form a closed shape. The closed shape can be a rounded rectangle, and the cutout area C can be located at the edge of the closed shape. In other words, the cutout area C can be at least partially surrounded by display area A. Figure 1 The display substrate shown can be used to form a "notch" screen. However, this embodiment is not limited to this. For example, the closed shape can be a circle or a triangle (including rounded triangles), etc.

[0066] In at least one exemplary embodiment, such as Figure 1 As shown, the cutout area C can be a notched structure. The display area A can include a first sub-display area A1, a second sub-display area A2, and a third sub-display area A3. The first sub-display area A1, the second sub-display area A2, and the third sub-display area A3 surround the cutout area C from three sides, forming a notched structure. The first sub-display area A1 and the second sub-display area A2 are located on opposite sides of the cutout area C, and the third sub-display area A3 is located on the same side as the first sub-display area A1, the cutout area C, and the second sub-display area A2. The first sub-display area A1 and the second sub-display area A2 resemble the two "ears" of the third sub-display area A3. However, this embodiment is not limited to this. In some examples, the cutout area can be a closed shape completely surrounded by the display area (e.g., a square hole, a round hole, etc.). The cutout area can, for example, be used to reserve design space for components such as a front-facing camera.

[0067] Figure 2 This is a partial schematic diagram of a display substrate according to at least one embodiment of the present disclosure. Figure 1 and Figure 2As shown, scan driving circuits 210a and 210b can be arranged in the border areas B2 on both sides of the display area A. The first sub-display area A1 can be provided with a plurality of regularly arranged sub-pixels (not shown), a plurality of first gate lines 321 connected to the scan driving circuit 210a and extending along the first direction D1, and a plurality of data lines (not shown) extending along the second direction D2. The second sub-display area A2 can be provided with a plurality of sub-pixels (not shown), a plurality of first gate lines 321 connected to the scan driving circuit 210b and extending along the first direction D1, and a plurality of data lines (not shown) extending along the second direction D2. The capacitance compensation area B1 is provided with a plurality of second gate lines 322, all of which extend along an extension direction parallel to the edge of the capacitance compensation area B1 near the side of the display area A. The third sub-display area A3 may be provided with a plurality of regularly arranged sub-pixels (not shown), a plurality of first gate lines 321 connected to scan driving circuits 210a and 210b and extending along a first direction D1, and a plurality of data lines (not shown) extending along a second direction D2. The first direction D1 (e.g., row direction) may be perpendicular to the second direction D2 (e.g., column direction). At least one sub-pixel may include: a light-emitting element and a driving circuit for driving the light-emitting element to emit light. The driving circuit may include a plurality of transistors and a storage capacitor.

[0068] In at least one exemplary embodiment, such as Figure 2 As shown, multiple first gate lines 321 can be respectively connected to scan drive circuits 210a and 210b located in the border areas B2 on both sides of the display area A. Any scan drive circuit may include multiple cascaded shift register units. To facilitate the differentiation of gate lines and sub-pixel rows, in Figure 1 Sometimes, the rows are numbered sequentially from top to bottom as row 1, row 2, ..., row M.

[0069] In some examples, the driving circuit for a sub-pixel is illustrated by including seven transistors and a storage capacitor. Figure 3 This is an equivalent circuit diagram of the driving circuit for a sub-pixel according to at least one embodiment of the present disclosure. For example... Figure 3 As shown, the driving circuit of this exemplary embodiment includes: a first transistor M1 to a seventh transistor M7 and a storage capacitor Cst. The first transistor M1 is a driving transistor. The second transistor M2 to the seventh transistor M7 are all switching transistors.

[0070] In this exemplary embodiment, the control electrode of the first transistor M1 is connected to the first node N1, the first terminal of the first transistor M1 is connected to the second node N2, and the second terminal of the first transistor M2 is connected to the third node N3. The control electrode of the second transistor M2 is connected to the scan line GATE, the first terminal of the second transistor M2 is connected to the data line DATA, and the second terminal of the second transistor M2 is connected to the second node N2. The control electrode of the third transistor M3 is connected to the scan line GATE, the first terminal of the third transistor M3 is connected to the first node N1, and the second terminal of the third transistor M3 is connected to the third node N3. The control electrode of the fourth transistor M4 is connected to the reset signal line RST, the first terminal of the fourth transistor M4 is connected to the initial signal line Vint, and the second terminal of the fourth transistor M4 is connected to the first node N1. The control electrode of the fifth transistor M5 is connected to the light emission control line EM, the first terminal of the fifth transistor M5 is connected to the high-potential power supply line VDD, and the second terminal of the fifth transistor M5 is connected to the second node N2. The control electrode of the sixth transistor M6 is connected to the light emission control line EM, the first terminal of the sixth transistor M6 is connected to the third node N3, and the second terminal of the sixth transistor M6 is connected to the fourth node N4. The control electrode of the seventh transistor M7 is connected to the reset signal line RST, the first electrode of the seventh transistor M7 is connected to the initial signal line Vint, and the second electrode of the seventh transistor M7 is connected to the fourth node N4. The first electrode of the storage capacitor Cst is connected to the first node N1, and the second electrode of the storage capacitor Cst is connected to the first power supply line VDD. The anode of the light-emitting element EL is connected to the fourth node N4, and the cathode of the light-emitting element EL is connected to the low-potential power supply line VSS.

[0071] In this exemplary embodiment, the first gate line connected to the scan driving circuits 210a and 210b may include a scan line GATE and a reset signal line RST. For example, the scan line GATE connected to the sub-pixel of the nth row may be the first gate line of the nth row, and the reset signal line RST connected to the sub-pixel of the nth row may be the first gate line of the (n-1)th row, where n is an integer greater than 1.

[0072] The following example uses transistors M1 through M7, all of which are P-type thin-film transistors. Figure 3 The operation of the provided drive circuit is illustrated by example. Figure 3 As shown, the driving circuit involved in this exemplary embodiment may include: six switching transistors (M2 to M7), one driving transistor (M1), one capacitor unit (Cst), five signal input terminals (DATA, GATE, EM, RST, and Vint), and two power supply terminals (VDD and VSS). Exemplarily, the high-potential power line VDD can continuously provide a high-level signal, and the low-potential power line VSS can continuously provide a low-level signal.

[0073] During the reset phase, the scan line GATE receives a high-level signal, and the second transistor M2 and the third transistor M3 are turned off. The light emission control line EM receives a high-level signal, and the fifth transistor M5 and the sixth transistor M6 are turned off. The reset signal line RST receives a low-level signal, and the fourth transistor M4 and the seventh transistor M7 are turned on, providing the initial signal line Vint input signal to the first node N1 and the fourth node N4 to reset the first node N1 and the fourth node N4, thereby eliminating the influence of the previous frame signal.

[0074] During the write phase, the reset signal line RST receives a high-level signal, turning off the fourth transistor M4 and the seventh transistor M7. The light-emitting control line EM receives a high-level signal, turning off the fifth transistor M5 and the sixth transistor M6. The scan line GATE receives a low-level signal, turning on the second transistor M2 and the third transistor M3. The second transistor M2 turns on, providing the data signal input to the data line DATA at the second node N2. At this time, the potential of the second node N2 is Vn2 = Vdata, where Vdata is the voltage value of the data signal. The third transistor M3 turns on, connecting the first node N1 and the third node N3, i.e., connecting the control electrode of the first transistor M1 to its second electrode. This allows the data signal transmitted to the second node N2 and the threshold voltage Vth (i.e., the compensation signal) of the first transistor M1 to be written to the first node N1, while simultaneously charging the storage capacitor Cst. At this time, the potential of the first node N1 is Vn1 = Vdata - Vth. Through the write phase, the data signal can be written to the control electrode of the first transistor M1, and the threshold voltage of the first transistor M1 can be compensated, thus eliminating the influence of the threshold voltage of the first transistor M1 on the drive current during the light-emitting phase.

[0075] During the light-emitting phase, the reset signal line RST receives a high-level signal, turning off the fourth transistor M4 and the seventh transistor M7. The scan line GATE receives a high-level signal, turning off the second transistor M2 and the third transistor M3. The light-emitting control line EM receives a low-level signal, turning on the fifth transistor M5 and the sixth transistor M6. The fifth transistor M5 turns on, providing the signal input from the first power line VDD to the second node N2. At this time, Vn2 = Vvdd. The first transistor M1 turns on under the influence of the signals (i.e., the data signal and the compensation signal) from the first node N1, and outputs a drive current under the influence of the signal provided by the first power line VDD to drive the light-emitting element EL to emit light. The potential of the first node N1 remains constant at Vdata - Vth under the influence of the storage capacitor Cst. Therefore, the source-gate voltage of the first transistor M1 can be: Vsg = Vn2 - Vn1 = Vvdd - Vdata + Vth.

[0076] According to the following transistor IV curve equation: I = K(Vsg - Vth) 2 =K(Vvdd-Vdata)2 ;

[0077] Wherein, K is a fixed constant related to the process parameters and geometry of the driving transistor (i.e., the first transistor M1).

[0078] Therefore, the driving current is independent of the threshold voltage of the first transistor M1 (i.e., the driving transistor), eliminating the influence of the threshold voltage on the light-emitting element EL, thereby improving display uniformity and luminous efficiency.

[0079] In at least one exemplary embodiment, the display area may include: a substrate and a semiconductor layer, a first conductive layer, a second conductive layer and a third conductive layer sequentially disposed on the substrate. Figure 4 This is a top view of the driving circuit of a sub-pixel according to at least one embodiment of the present disclosure. Figure 5A This is a top view of a driving circuit after the semiconductor layer has been formed, according to at least one embodiment of the present disclosure. Figure 5B This is a top view of a driving circuit after the first conductive layer has been formed, according to at least one embodiment of this disclosure. Figure 5C This is a top view of the driving circuit after the second conductive layer has been formed, according to at least one embodiment of this disclosure. Figure 5D This is a top view of the driving circuit after the third conductive layer has been formed, according to at least one embodiment of this disclosure.

[0080] In at least one exemplary embodiment, such as Figure 4 and Figure 5A As shown, the semiconductor layer may include: the active layer of the first to seventh transistors. At least one active layer may include: a channel region, a first doped region, and a second doped region. The channel region may be undoped and has semiconductor characteristics. The first and second doped regions may be located on opposite sides of the channel region and are doped with impurity particles, thus exhibiting conductivity. The impurities may vary depending on the type of transistor. The first or second doped region of the semiconductor layer can be interpreted as the source or drain electrode of the transistor. For example, the source electrode of the first transistor may correspond to the first doped region doped with impurities around the channel region T1 of the active layer; the drain electrode of the first transistor may correspond to the second doped region doped with impurities around the channel region T1 of the active layer. Additionally, portions of the active layer between transistors can be interpreted as doped wiring, which can be used to electrically connect the transistors. Figure 5A In the diagram, T1 represents the communication region of the active layer of the first transistor, T2 represents the communication region of the active layer of the second transistor, T3 represents the communication region of the active layer of the third transistor, T4 represents the communication region of the active layer of the fourth transistor, T5 represents the communication region of the active layer of the fifth transistor, T6 represents the communication region of the active layer of the sixth transistor, and T7 represents the communication region of the active layer of the seventh transistor.

[0081] In at least one exemplary embodiment, such as Figure 4 and Figure 5B As shown, the first conductive layer may include: a light-emitting control line EM, a scan line GATE, a reset signal line RST, and a first electrode CE1 of the storage capacitor Cst. The control electrode (i.e., gate electrode) of the first transistor and the first electrode CE1 of the storage capacitor Cst are integrally structured, meaning that the first electrode CE1 of the storage capacitor Cst also serves as the gate electrode of the first transistor. The gate electrodes of the fourth and seventh transistors are integrally structured with the reset signal line RST. The gate electrodes of the second and third transistors are integrally structured with the scan line GATE. The gate electrodes of the fifth and sixth transistors are integrally structured with the light-emitting control line EM. However, this embodiment is not limited to this.

[0082] In at least one exemplary embodiment, such as Figure 4 and Figure 5C As shown, the second conductive layer may include a second electrode CE2 for the initial signal line Vint and the storage capacitor Cst. The second electrode CE2 has a cutout region. The orthographic projection of the gate electrode of the first transistor onto the substrate may cover the orthographic projection of the cutout region onto the substrate. The orthographic projection of the cutout region onto the substrate may be a polygon. However, this embodiment is not limited to this.

[0083] In at least one exemplary embodiment, such as Figure 4 and Figure 5DAs shown, the third conductive layer may include: a data line DATA, a first power line VDD, and multiple connection electrodes CP1, CP2, and CP3. The data line DATA is parallel to the first power line VDD. The data line DATA can be connected to the first electrode of the second transistor through an opening in the insulating layer between the third conductive layer and the semiconductor layer. The first power line VDD can be connected to the first electrode of the fifth transistor through an opening in the insulating layer between the third conductive layer and the semiconductor layer. The first power line VDD can be connected to the second electrode CE2 of the storage capacitor through an opening in the insulating layer between the third conductive layer and the second conductive layer. One end of the connection electrode CP1 can be connected to the first electrode CE1 of the storage capacitor through an opening in the insulating layer between the third conductive layer and the first conductive layer, and the orthographic projection of the opening on the substrate is located within the hollowed-out area of ​​the second electrode CE2 of the storage capacitor; the other end of the connection electrode CP1 can be connected to the first electrode of the third transistor through an opening in the insulating layer between the third conductive layer and the semiconductor layer. One end of connecting electrode CP2 can be connected to the initial signal line Vint through an opening in the insulating layer between the third conductive layer and the second conductive layer; the other end of connecting electrode CP2 can be connected to the second electrode of the fourth transistor and the first electrode of the seventh transistor through an opening in the insulating layer between the third conductive layer and the semiconductor layer. One end of connecting electrode CP3 can be connected to the second electrode of the sixth transistor through an opening in the insulating layer between the third conductive layer and the semiconductor layer; the other end of connecting electrode CP3 can be connected to the second electrode of the seventh transistor of the next row of sub-pixels through an opening in the insulating layer between the third conductive layer and the semiconductor layer. The light-emitting element may include: an anode, a light-emitting functional layer, and a cathode. For example, the anode can be connected to connecting electrode CP3.

[0084] In at least one exemplary embodiment, such as Figure 2 As shown, the first N first gate lines 321 in sequence from top to bottom (i.e., multiple first gate lines located within the first sub-display area A1) can be connected to the first N first gate lines 321 in the second sub-display area A2 respectively via multiple second gate lines 322 within the capacitance compensation area B1. Any second gate line 322 within the capacitance compensation area B1 can connect to the first gate lines 321 in the same row within the first sub-display area A1 and the second sub-display area A2. Multiple first gate lines 321 in the third sub-display area A3 (e.g., the N+1th to Mth first gate lines) can extend parallel to each other along the first direction D1. Each first gate line 321 can be configured to connect to a row of sub-pixels. In some examples, each first gate line can be configured to provide a scan signal to a row of sub-pixels. In some examples, each first gate line can be configured to provide a scan signal to a row of sub-pixels and a reset signal to the previous row of sub-pixels. However, this embodiment is not limited in this respect.

[0085] In at least one exemplary embodiment, such as Figure 2 As shown, the first gate lines 321 in the first sub-display area A1 and the second sub-display area A2 cannot be directly connected laterally to each other. Instead, they are interconnected by bypassing the slotted area C through the second gate lines 322 in the capacitance compensation area B1. The density of the second gate lines 322 in the capacitance compensation area B1 is greater than the density of the first gate lines 321 in the display area A. Moreover, the second gate lines 322 in the capacitance compensation area B1 can extend along the outer contour of the display area A, that is, along the direction parallel to the edge of the display area A near the capacitance compensation area B1. For example, if part of the outer contour of the display area A is arc-shaped, the second gate lines 322 in the capacitance compensation area B1 can be formed by connecting multiple straight line segments to extend along the outer contour shape of the display area A. However, this embodiment is not limited to this. In some examples, the second gate lines in the capacitance compensation area B1 may include curved segments to extend along the outer contour shape of the display area.

[0086] In at least one exemplary embodiment, such as Figure 2 As shown, due to the presence of the notch region C, some sub-pixels are removed, resulting in a smaller number of sub-pixels connected to the first gate line 321 in the first sub-display area A1 and the second sub-display area A2 compared to the number of sub-pixels connected to the first gate line 321 in the third sub-display area A3. Consequently, the loading capacitance of the first gate line in the first and second sub-display areas A1 and A2 is less than that in the third sub-display area A3. This causes a difference in data writing time between the sub-pixels in the first and second sub-display areas A1 and A2 and the sub-pixels in the third sub-display area A3, resulting in display unevenness (Mura) and affecting the display effect. This exemplary embodiment compensates for the missing loading capacitance of the first gate line in the first and second sub-display areas A1 and A2 by providing a first capacitance compensation unit 221 in the capacitance compensation area B1.

[0087] Figure 6 for Figure 2 A cross-sectional schematic diagram along the PP direction is shown, in which the film structure of the capacitor compensation region B1 is illustrated using only five second gate lines 322 as an example. Figure 7 for Figure 2 A partially enlarged schematic diagram of region Q in the middle. In at least one exemplary embodiment, as shown... Figure 2 , Figure 6 and Figure 7As shown, a first capacitance compensation unit 221 is disposed within the capacitance compensation region B1. The first capacitance compensation unit 221 may include: a semiconductor structure 31, a first metal structure 32, and a second metal structure 33 sequentially disposed on the substrate 10. The semiconductor structure 31 is insulated from the first metal structure 32, and the first metal structure 32 is insulated from the second metal structure 33. Figure 2 As shown, the structures of the first capacitor compensation unit 221 near the first display area A1 and near the second display area A2 can be mirror images of each other along the center line of the display substrate in the first direction D1. The following description, with reference to the accompanying drawings, illustrates and explains the structure of the first capacitor compensation structure 221 near the first display area A1 as an example.

[0088] Figure 8A for Figure 7 A top view of a semiconductor structure. (e.g.) Figure 6 , Figure 7 and Figure 8A As shown, the semiconductor structure 31 may include a plurality of regularly arranged semiconductor blocks 310a and 310b. Semiconductor block 310a is a rectangular semiconductor block. Semiconductor blocks 310b are arranged at both ends of the plurality of semiconductor blocks 310a along a first direction. The size of the plurality of semiconductor blocks 310a may be the same, or may decrease from the middle to the two edges along the first direction D1. The length of the semiconductor blocks 310b located at the edges may first increase and then decrease along the first direction D1. However, this embodiment is not limited to this. In some examples, the semiconductor structure may include multiple rows of semiconductor blocks. Trapezoidal or triangular semiconductor blocks may be arranged at the edges of each row, and rectangular semiconductor blocks may be arranged in the middle area. Taking the arrangement of trapezoidal semiconductor blocks at the edges of each row as an example, the long side of the trapezoidal semiconductor block is adjacent to the rectangular semiconductor block.

[0089] In at least one exemplary embodiment, such as Figure 6 and Figure 7 As shown, the first metal structure 32 may include a plurality of second gate lines 322 extending along a first direction D1. The widths W of the plurality of second gate lines 322 may be different. The orthographic projection of any second gate line 322 on the substrate partially overlaps with the orthographic projection of the semiconductor block of the semiconductor structure on the substrate. However, this embodiment is not limited in this respect. For example, the widths of the plurality of second gate lines may be the same.

[0090] Figure 8B for Figure 7 A top view of the second metal structure in the middle. (See image.) Figure 6 , Figure 7 and Figure 8BAs shown, the second metal structure 33 may include a first potential signal line 331. For example, the first potential signal line 331 may be a low-potential power line (VSS). The first potential signal line 331 may include a main body portion 3311 and an extension portion 3312. The main body portion 3311 extends along a first direction D1, and the extension portion 3312 extends along a second direction D2, with one end of the extension portion 3312 near the trench area connected to the main body portion 3311. The length of the extension portion 3312 in the first direction D1 gradually increases and then decreases along the direction away from the trench area. However, this embodiment is not limited in this respect. For example, the length of the extension portion in the first direction may increase along the direction away from the trench area, or decrease first and then increase, or decrease.

[0091] In at least one exemplary embodiment, such as Figure 6 and Figure 7 As shown, the insulating layer between the semiconductor structure 31 and the second metal structure 33 (such as...) Figure 6 As shown, the second metal structure 33 (including a first insulating layer 13, a second insulating layer 16, and a third insulating layer 18) can be provided with multiple first vias 501. The first potential signal line 331 of the second metal structure 33 can be electrically connected to the semiconductor blocks 310a and 310b of the semiconductor structure 31 through the multiple first vias 501. Figure 6 , Figure 7 , Figure 8A and Figure 8B As shown, in the first capacitor compensation unit 221, the orthogonal projection of the first potential signal line 331 of the second metal structure 33 onto the substrate 10 can cover the orthogonal projection of the semiconductor structure 31 onto the substrate 10. For example... Figure 6 and Figure 7 As shown, the orthogonal projection of the first potential signal line 331 of the second metal structure 33 onto the substrate 10 can overlap with the orthogonal projection portions of multiple second gate lines 322 onto the substrate 10. At least one orthogonal projection of the second gate line 322 onto the substrate 10 can overlap with the orthogonal projection portion of the semiconductor structure 31 onto the substrate 10. For example... Figure 7 As shown, multiple first vias 501 can be arranged regularly along the first direction D1 to form two opposing rows of first vias 501.

[0092] In this exemplary embodiment, in the first capacitance compensation unit 221, the second gate line 322 of the first metal structure 32 can form a three-layer capacitor structure with the semiconductor structure 31 and the first potential signal line 331 of the second metal structure 33, serving as a compensation capacitor for the first gate line of the display area connected to the second gate line 322, thereby increasing the load capacitance of the first gate line within the first and second sub-display areas. The first potential signal line 331 and the semiconductor structure 31 are electrically connected to each other and can jointly serve as the first electrode of the compensation capacitor, while the second gate line 322 can serve as the second electrode of the compensation capacitor. The size of the compensation capacitor can be designed through theoretical simulation calculations. In some examples, after designing the size of the compensation capacitor based on theoretical simulations, the shapes of the first potential signal line and the semiconductor structure are essentially fixed. Therefore, the size of the compensation capacitor can be adjusted by adjusting the dimensions of the second gate line; for example, the width of the second gate line can be adjusted. In some examples, within the capacitance compensation region B1, the widths of multiple second gate lines can be different, thereby providing compensation capacitors of different sizes to the first gate line connected to the second gate line, achieving the effect of targeted compensation of the load capacitance of the first gate line. The width of the second gate line and the width of the first gate line connected to it can be the same or different. However, this embodiment is not limited to this.

[0093] In at least one exemplary embodiment, such as Figure 6 As shown, the third sub-display area A3 may include: a substrate 10 and a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer sequentially disposed on the substrate 10. The semiconductor layer may include: an active layer 12 of a transistor. The first conductive layer may include: a gate electrode 14 of the transistor, a first electrode 15 of a storage capacitor, and a first gate line (not shown) connected to the gate electrode. The second conductive layer may include: a second electrode 17 of the storage capacitor. The third conductive layer may include: a source electrode 20 and a drain electrode 19 of the transistor. A buffer layer 11 may be disposed on the side of the active layer 12 near the substrate 10. A first insulating layer 13 may be disposed between the active layer 12 and the first conductive layer. A second insulating layer 16 may be disposed between the first conductive layer and the second conductive layer. A third insulating layer 18 may be disposed between the second conductive layer and the third conductive layer. On the side of the third conductive layer away from the substrate 10, a fourth insulating layer, a fourth conductive layer (e.g., including the anode of a light-emitting element), a pixel defining layer, an organic light-emitting layer, a cathode layer, and an encapsulation layer may be sequentially formed to form a sub-pixel. The structure of the first and second sub-display areas is the same as that of the third sub-display area, so it will not be described again here.

[0094] In at least one exemplary embodiment, such as Figure 6As shown, the semiconductor structure 31 of the capacitance compensation region B1 can be disposed on the same layer as the semiconductor layer of the third sub-display region A3, the first metal structure 32 of the capacitance compensation region B1 can be disposed on the same layer as the second conductive layer of the third sub-display region A3, and the second metal structure 33 of the capacitance compensation region B1 can be disposed on the same layer as the third conductive layer of the third sub-display region A3. A first insulating layer 13, a second insulating layer 16, and a third insulating layer 18 can be disposed between the second metal structure 33 and the semiconductor structure 31. However, this embodiment is not limited in this respect. In some examples, the fourth conductive layer may include a connection electrode for connecting the drain electrode of the transistor and the anode of the light-emitting element. A fourth insulating layer may be disposed between the third conductive layer and the fourth conductive layer. A fifth insulating layer, a fifth conductive layer (e.g., including the anode of the light-emitting element), a pixel defining layer, an organic light-emitting layer, a cathode layer, and an encapsulation layer can be sequentially formed on the side of the fourth conductive layer away from the substrate to form a sub-pixel. In this example, the first metal structure of the capacitance compensation region can be disposed on the same layer as the third conductive layer of the display region, and the second metal structure of the capacitance compensation region can be disposed on the same layer as the fourth conductive layer of the display region.

[0095] In at least one exemplary embodiment, such as Figure 7 As shown, multiple second gate lines 322 forming the first capacitor compensation unit 221 can extend parallel to each other along the first direction D1. Multiple first vias 501 can be arranged along the extension direction of the second gate lines 322 (i.e., the first direction D1). In the second direction D2, perpendicular to the first direction D1, the distance between two adjacent first vias 501 can be at least greater than the sum of the widths of the two second gate lines 322. For example, if the capacitor compensation region has N second gate lines, then in the second direction D2, the distance between two adjacent first vias 501 can be greater than the sum of the widths of the N second gate lines. That is, multiple first vias are provided at the opposite edges of the N second gate lines along the second direction to achieve electrical connection between the semiconductor structure and the second metal structure. However, this embodiment is not limited in this respect. For example, if the capacitor compensation region has N second gate lines, then in the second direction, the distance between two adjacent first vias can be less than the sum of the widths of the N second gate lines and greater than the sum of the widths of N / 2 second gate lines, where N can be an integer greater than 4. That is, the N second gate lines are divided into two groups, and multiple first vias are provided at the junction of the two groups of second gate lines along the second direction and at the outer edge, thereby realizing the electrical connection between the semiconductor structure and the second metal structure. In this exemplary embodiment, adjacent second gate lines between the two rows of first vias can be arranged compactly, thereby reducing the spacing between adjacent second gate lines, saving the occupied border area, and facilitating the implementation of a narrow bezel design.

[0096] In at least one exemplary embodiment, such as Figure 7 and Figure 8AAs shown, taking a rectangular semiconductor block as an example, the multiple first vias 501 can be arranged on opposite sides of the rectangular semiconductor block 310a along the second direction D2 (e.g., the upper and lower edges along the second direction D2). Since the orthographic projection of a rectangular semiconductor block 310a onto the substrate can overlap with multiple second gate lines 322, the distance between adjacent first vias 501 along the second direction D2 can be greater than the sum of the widths of the multiple second gate lines 322. In this example, the first via 501 can be a square via. However, this embodiment is not limited to this. For example, the first via 501 can be circular or elongated, etc.

[0097] In at least one exemplary embodiment, such as Figure 7 and Figure 8A As shown, at least one rectangular semiconductor block 310a may have multiple first vias 501 disposed on one side edge in the second direction D2, and two rows of first vias 501 may be regularly arranged on opposite side edges. In some examples, the spacing between two adjacent first vias 501 in the first direction D1 may be greater than or equal to 1 micrometer (μm). However, this embodiment is not limited to this. In some examples, the multiple first vias may be arranged only on one side edge of the rectangular semiconductor block in the second direction, for example, at the upper or lower edge position along the second direction. On the semiconductor block 310b at the edge position of the semiconductor structure along the first direction, the multiple first vias 501 may be arranged at the farthest edge position of the semiconductor block 310b along the second direction D2.

[0098] The technical solution of this embodiment is further illustrated below through an example of the fabrication process of the display substrate. The "patterning process" mentioned in this embodiment includes processes such as film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping, which are known and mature fabrication processes. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, which are not limited here. In the description of this embodiment, "thin film" refers to a thin film made of a certain material on a substrate using deposition or other processes.

[0099] In some exemplary embodiments, the fabrication process of the display substrate provided by this exemplary embodiment may include steps (1) to (6).

[0100] (1) A semiconductor layer is formed in the display area, and a semiconductor structure is formed in the capacitance compensation area. In some exemplary embodiments, a buffer layer 11 is formed on the substrate 10, a semiconductor thin film is deposited on the buffer layer 11, and the semiconductor thin film is patterned by a patterning process. A semiconductor layer is formed in the display area A, and a semiconductor structure 31 is formed in the capacitance compensation area B1. In some examples, the semiconductor structure and the semiconductor layer are disposed on the same layer. Figure 6 , Figure 7 and Figure 8A As shown, the semiconductor layer may include the active layer 12 of a transistor, and the semiconductor structure may include a plurality of regularly arranged semiconductor blocks 310a and 310b. The size of each semiconductor block 310a or 310b may be larger than the size of the active layer of any transistor in the display area. In some examples, the semiconductor block may be rectangular. For example, the length of the semiconductor block in the capacitance compensation region B1 along the first direction D1 may range from 10 to 300 micrometers, for example, it may be 260 micrometers. However, this embodiment is not limited to this.

[0101] The substrate 10 can be a flexible substrate, made of materials such as polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer film.

[0102] The semiconductor thin film can be made of one or more materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, and polythiophene. In other words, this embodiment is applicable to display substrates based on top gate thin film transistors (TFTs) manufactured using oxide technology, silicon technology, and organic technology.

[0103] (2) On the substrate where the aforementioned structure is formed, a first conductive layer is formed in the display area. In some exemplary embodiments, a first insulating film and a first conductive film are sequentially deposited on the substrate 10 where the aforementioned structure is formed. The first conductive film is patterned using a patterning process to form a first insulating layer 13 covering the semiconductor structure and semiconductor layer. The first conductive layer is then formed on the first insulating layer 13 in the display area A. The first conductive layer may include: a first gate line, a gate electrode 14 of a transistor, and a first electrode 15 of a storage capacitor, such as... Figure 6 As shown.

[0104] (3) On the substrate forming the aforementioned structure, a second conductive layer is formed in the display area, and a first metal structure is formed in the capacitance compensation area. In some examples, the second conductive layer and the first metal structure may be disposed in the same layer. In some exemplary embodiments, a second insulating film and a second conductive film are deposited on the substrate 10 forming the aforementioned structure, and the second conductive film is patterned by a patterning process to form a second insulating layer 16 covering the first conductive layer, and a second conductive layer is formed on the second insulating layer 16 in the display area A, and a first metal structure 32 is formed on the second insulating layer 16 in the capacitance compensation area B1, such as... Figure 6 As shown. The second conductive layer of display area A may include the second electrode 17 of the storage capacitor; the first metal structure 32 of capacitance compensation area B1 may include multiple second gate lines 322. The first gate lines in display area A may be connected to the gate electrode of the transistor. The position of the second electrode 17 of the storage capacitor corresponds to the first electrode 15.

[0105] In some exemplary embodiments, the second gate line 322 of the first metal structure 32 can be connected to the first gate line of the first conductive layer through vias formed in the second insulating layer 16, thereby connecting the first gate lines in the first sub-display area and the second sub-display area through the second gate line. In some examples, gate line connection electrodes can be provided at the junction of the first sub-display area and the capacitance compensation area, and at the junction of the second sub-display area and the capacitance compensation area. The gate line connection electrodes are disposed in the same layer as the second gate line and connected to it, and are connected to the first gate line of the first sub-display area and the first gate line of the second sub-display area through vias formed in the second insulating layer, respectively. Alternatively, the second gate line of the capacitance compensation area can extend to the junction of the first sub-display area and the capacitance compensation area, and the second gate line is connected to the first gate line of the first sub-display area and the first gate line of the second sub-display area through vias formed in the second insulating layer, respectively. However, this embodiment is not limited in this respect.

[0106] (4) On the substrate forming the aforementioned structure, a third conductive layer is formed in the display area, and a second metal structure is formed in the capacitance compensation area. In some examples, the third conductive layer and the second metal structure may be disposed in the same layer. In some exemplary embodiments, a third insulating film is deposited on the substrate 10 forming the aforementioned structure, and the third insulating film is patterned by a patterning process to form a third insulating layer 18. A plurality of vias are formed on the third insulating layer 18 in the display area A, exposing the two ends of the active layer respectively. A plurality of first vias 501 are formed on the third insulating layer 18 in the capacitance compensation area B1, exposing the opposite two side edges of the semiconductor structure 31 in the second direction D2 respectively. Then, a third conductive film is deposited, and the third conductive film is patterned by a patterning process to form a third conductive layer in the display area A and a second metal structure 33 in the capacitance compensation area B1. The third conductive layer may include the source electrode 20, drain electrode 19, power line (not shown), and data signal line (not shown) pattern of the transistor, such as Figure 6 As shown. In some examples, the second metal structure 33 may include a first potential signal line 331, such as a low-potential power line, as... Figure 6 As shown. The source electrode 20 and drain electrode 19 are respectively connected to the two ends of the active layer 12. The first potential signal line 331 can be connected to the semiconductor structure 31 through the first via 501.

[0107] (5) A fourth insulating layer is formed on the substrate 10 on which the aforementioned structure is formed. The fourth insulating layer may be an organic material such as a polysiloxane-based material, an acrylic-based material, or a polyimide-based material. The fourth insulating layer may be referred to as a planarization layer. In some examples, the fourth insulating layer may include a stacked structure of inorganic and organic materials.

[0108] (6) On the substrate forming the aforementioned structure, a light-emitting element is formed in the display area. In some exemplary embodiments, an anode is formed in the display area A on the substrate 10 forming the aforementioned structure. The anode can be connected to the drain of a transistor through a via on the fourth insulating layer. Then, a pixel definition film is coated, and a pixel definition layer pattern is formed by mask exposure and development, defining an opening area for exposing the anode. Then, an organic light-emitting layer is formed in the opening area by vapor deposition or inkjet printing, and a cathode covering the organic light-emitting layer is formed by vapor deposition. Then, an inorganic / organic / inorganic three-layer encapsulation layer can be formed to complete the encapsulation of the display substrate.

[0109] The pixel-defining film can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate.

[0110] In some examples, the organic light-emitting layer may primarily include a light-emitting material layer. In some examples, the organic light-emitting layer may include: a hole injection layer, a hole transport layer, a light-emitting material layer, an electron transport layer, and an electron injection layer arranged sequentially, which can improve the efficiency of electron and hole injection into the light-emitting material layer. However, this embodiment is not limited to this.

[0111] In some examples, the buffer layer 11, the first insulating layer 13, the second insulating layer 16, and the third insulating layer 18 can be made of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), etc., or can be made of high dielectric constant (Highk) materials, such as aluminum oxide (AlOx), hafnium oxide (HfOx), tantalum oxide (TaOx), etc., or can be single-layer, multi-layer, or composite layers. Typically, the first insulating layer 13 and the second insulating layer 16 can be referred to as gate insulating layers, and the third insulating layer 18 can be referred to as interlayer insulating layers.

[0112] In some examples, the first to fourth conductive films can all be made of metallic materials, such as silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), or alloys of the above metals, such as aluminum-niobium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They can be multilayer stacked structures, such as Mo / Cu / Mo or Mo / Al / Mo, or stacked structures formed by metals and transparent conductive materials, such as ITO / Ag / ITO.

[0113] In some examples, the anode may be at least one transparent conductive material selected from indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium oxide (IGO), and zinc aluminum oxide (AZO). The cathode may be silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or compounds thereof. However, this embodiment is not limited in this respect.

[0114] The display substrate provided in this exemplary embodiment can increase the load capacitance of the first gate line in the first sub-display area and the second sub-display area by using a first capacitor compensation unit disposed within the capacitor compensation area, thereby improving the display uniformity of the display area. Furthermore, by providing a first via at the edge position in the second direction of the semiconductor structure, the space occupied by the first capacitor compensation unit can be reduced, which is beneficial for reducing the bezel size. Moreover, in this exemplary embodiment, since the original bezel area already contains the first potential signal line, there is no need to add an additional structure to compensate for the load capacitance of the first gate line in the display area, facilitating the reduction of the display substrate's bezel and promoting narrow bezel design.

[0115] Figure 9This is a schematic diagram of the structure of the capacitance compensation region according to at least one embodiment of the present disclosure. Figure 1 A magnified view of region S in the diagram. Figure 10 for Figure 9 A cross-sectional view along the PP direction. Figure 11 for Figure 9 A magnified view of a portion of region S1 in the diagram. Figure 12A for Figure 11 A top view of the semiconductor structure. Figure 12B for Figure 11 A top view of the second metal structure in the diagram.

[0116] In at least one exemplary embodiment, such as Figure 9 and Figure 10 As shown, a first capacitor compensation unit 221 and a second capacitor compensation unit 222 are disposed within the capacitor compensation region B1. The first capacitor compensation unit 221 may include: a semiconductor structure, a first metal structure, and a second metal structure sequentially disposed on the substrate 10. The semiconductor structure includes: multiple semiconductor blocks 311 and 312. The first metal structure includes multiple second gate lines 322. The second metal structure includes: a first potential signal line 331 and an extended electrode 332. In this example, the first potential signal line 331 is a low-potential power line. The second capacitor compensation unit 222 may include: a third metal structure and a fourth metal structure sequentially disposed on the substrate 10 and insulated from each other. The third metal structure includes multiple second gate lines, and the fourth metal structure includes the first potential signal line. The third metal structure and the first metal structure are co-layered, and the fourth metal structure and the second metal structure are co-layered. In the second capacitor compensation unit 222, the third metal structure and the fourth metal structure can form a capacitor. The second gate line included in the third metal structure is continuous with the second gate line included in the first metal structure, and the first potential signal line included in the fourth metal structure is continuous with the first potential signal line included in the second metal structure. Within the capacitance compensation region, the second capacitance compensation unit 222 may be located on the side of the first capacitance compensation unit 221 closer to the first sub-display area or on the side closer to the second sub-display area. However, this embodiment is not limited in this respect.

[0117] In at least one exemplary embodiment, such as Figure 1 and Figure 9 As shown, within the capacitance compensation area, the second gate line closer to the slotted area can increase the load capacitance of the first gate line in the first sub-display area and the second sub-display area through the second capacitance compensation unit 222 and the first capacitance compensation unit 221; the second gate line farther from the display area can increase the load capacitance of the first gate line in the first sub-display area and the second sub-display area solely through the first capacitance compensation unit 221.

[0118] In at least one exemplary embodiment, such as Figure 9 and Figure 10 As shown, an extension electrode 332 can be provided on the side of the first potential signal line 331 near the third sub-display area (i.e., the side away from the cutout area). The extension electrode 332 and the first potential signal line 331 can be electrically connected through multiple connecting electrodes 35. For example, the multiple connecting electrodes 35 can be disposed in the same layer as the second gate line 322. The extension electrode 332 and the first potential signal line 331 are respectively connected to the connecting electrodes 35 through second vias disposed on the third insulating layer 18. However, this embodiment is not limited to this. In some examples, the multiple connecting electrodes 35 can be disposed in the same layer as the first gate line of the display area and the gate electrode of the transistor.

[0119] During the fabrication of the display substrate, to effectively prevent water and oxygen from entering the display area, isolation trenches or dams are formed around the display area in the bezel region. To avoid forming water and oxygen channels, a continuous second metal structure is not formed at the location of the isolation trenches or dams. For example... Figure 11 and Figure 12B As shown in this exemplary embodiment, by setting an extension electrode 332 that is discontinuous with the first potential signal line 331, and by using a connection electrode 35 disposed in the same layer as the first metal structure to achieve electrical connection between the extension electrode 332 and the first potential signal line 331, not only can the coverage of the first capacitor compensation unit be expanded, but the influence of isolation trenches or isolation dams on the capacitor compensation unit can also be avoided.

[0120] In at least one exemplary embodiment, such as Figure 1 , Figure 2 and Figure 9 As shown, within the capacitance compensation region B1, multiple second gate lines 322 may each include two curved segments and one straight segment. The two ends of the straight segment of one second gate line 322 are connected to a curved segment. One curved segment can connect to the first gate line 321 within the first sub-display region A1, and the other curved segment can connect to the first gate line 321 within the second sub-display region A2. That is, the second gate lines 322 within the capacitance compensation region B1 can extend along the outer contour of the display region A. However, this embodiment is not limited to this.

[0121] In at least one exemplary embodiment, the width of the first potential signal line 331 may be greater than the width of the second gate line 322. The orthographic projection of the curved segment of the second gate line 322 near the trench area onto the substrate can be covered by the orthographic projection of the first potential signal line 331 onto the substrate, thereby causing the second gate line and the first potential signal line to overlap and form a capacitor, serving as a second capacitance compensation unit to increase the load capacitance on the first gate line.

[0122] In at least one exemplary embodiment, such as Figure 9As shown, the first potential signal line forming the first capacitor compensation unit 221 may have a main body extending along a first direction D1 and an extension extending along a second direction D2. One end of the extension near the trench area is connected to the main body, and the length of the extension in the first direction D1 may gradually increase in the direction away from the trench area. The length of the extension electrode forming the first capacitor compensation unit 221 in the first direction D1 may gradually increase in the direction away from the trench area. In this example, as... Figure 12A As shown, the semiconductor structure may include a plurality of regularly arranged semiconductor blocks 311 corresponding to the first potential signal line and a plurality of regularly arranged semiconductor blocks 312 corresponding to the extended electrodes. In some examples, the dimensions of semiconductor blocks 311 and 312 may be the same or different. For example, the length of semiconductor block 311 along the second direction D2 may be greater than the length of semiconductor block 312 along the second direction D2. However, this embodiment is not limited in this respect.

[0123] In this exemplary embodiment, such as Figure 9 As shown, since the lengths of the first potential signal line 331 and the extended electrode 332 vary along the first direction D1, the overlap areas of the first potential signal line 331 and the extended electrode 332 with different second gate lines are different. This allows for the provision of compensation capacitors of different sizes to different second gate lines, achieving the effect of targeted compensation of the gate line load capacitance. In some examples, the size of the compensation capacitor can also be adjusted by adjusting the shape of the semiconductor structure to achieve the same targeted compensation effect.

[0124] In at least one exemplary embodiment, such as Figure 9 and Figure 11 As shown, both the first via 501 and the second via 502 are located at the edge of the first potential signal line 331 away from the trench area, and at the edge of the first extended electrode 332 near the trench area. The first via 501 and the second via 502 can be arranged at intervals and extend along the first direction D1. In the second direction D2, the distance between the first potential signal line 331 and the extended electrode 332 is greater than 10 micrometers. Therefore, as... Figure 11 The distance between the two rows of first vias 501 arranged along the first direction D1 and along the second direction D2 is at least greater than the width of the two second gate lines. The first vias 501 can also be located at the edge of the first potential signal line 331 near the trench area and at the edge of the extended electrode 332 away from the trench area. However, this embodiment is not limited to this. In some examples, the second via 502 can be located at the edge of the first potential signal line 331 away from the trench area and at the edge of the extended electrode 332 near the trench area; the first via 501 can be located at the edge of the first potential signal line 331 near the trench area and at the edge of the extended electrode 332 away from the trench area.

[0125] Figure 13 This is another structural schematic diagram of the capacitance compensation region according to at least one embodiment of the present disclosure. Figure 1 A magnified view of region S in the diagram. Figure 14 for Figure 13 A cross-sectional view along the PP direction. Figure 15 for Figure 13 A magnified view of region S2 in the image. Figure 16A for Figure 15 A top view of the semiconductor structure. Figure 16B for Figure 15 A top view of the second metal structure in the diagram.

[0126] In at least one exemplary embodiment, such as Figure 1 , Figure 13 and Figure 14 As shown, a first capacitance compensation unit 221 is provided within the capacitance compensation region B1. The first capacitance compensation unit 221 may include: a semiconductor structure 31, a first metal structure, and a second metal structure sequentially disposed on the substrate 10. The semiconductor structure includes: a plurality of semiconductor blocks 311 and 312. The first metal structure includes: a plurality of second gate lines 322. The second metal structure includes: a first potential signal line 331 and an extension electrode 332. In this example, the first potential signal line 331 is a high-potential power line (VDD). A second potential signal line 333 is provided on the side of the extension electrode 332 near the trench area, and the second potential signal line 33 is, for example, a low-potential power line (VSS). In this exemplary embodiment, in the first capacitance compensation unit 221, the second gate lines, the semiconductor structure, and the first potential signal line can form a capacitor, and the second gate lines, the semiconductor structure, and the extension electrode can form a capacitor.

[0127] In at least one exemplary embodiment, such as Figure 13 and Figure 15 As shown, the first potential signal line 331 can extend from the third sub-display area to the capacitance compensation area. The extension electrode 332 is discontinuous with the first potential signal line 331 and can be electrically connected through multiple connecting electrodes 35. The connecting electrodes 35 can be disposed on the same layer as the second gate line 322. The extension electrode 332 and the first potential signal line 331 are respectively connected to the connecting electrode 35 through third vias disposed on the third insulating layer 18. In this exemplary embodiment, as... Figure 15 and Figure 16B As shown, by setting an extension electrode 332 that is discontinuous with the first potential signal line 331, and by using a connection electrode 35 that is disposed in the same layer as the first metal structure to achieve electrical connection between the extension electrode 332 and the first potential signal line 331, not only can the coverage of the first capacitor compensation unit be expanded, but the influence of isolation trenches or isolation dams on the capacitor compensation unit can also be avoided.

[0128] In at least one exemplary embodiment, such as Figure 13 As shown, the length of the first potential signal line 331 forming the first capacitor compensation unit 221 in the first direction D1 can gradually decrease along the direction closer to the trench area. However, this embodiment is not limited to this. In some examples, the length of the first potential signal line in the first direction can gradually increase and then decrease along the direction closer to the trench area. For example... Figure 13 As shown, the length of the extended electrode forming the first capacitor compensation unit 221 in the first direction D1 can gradually decrease along the direction closer to the trench area. In this example, as... Figure 16A As shown, the semiconductor structure may include a plurality of regularly arranged semiconductor blocks 311 corresponding to the first potential signal line and a plurality of regularly arranged semiconductor blocks 312 corresponding to the extended electrodes. In some examples, the dimensions of semiconductor blocks 311 and 312 may be the same or different. For example, the length of semiconductor block 311 along the second direction D2 may be greater than the length of semiconductor block 312 along the second direction D2. However, this embodiment is not limited in this respect.

[0129] In at least one exemplary embodiment, such as Figure 15 As shown, the first via 501 and the second via 502 can both be located at the edge of the first potential signal line 331 near the trench area, and at the edge of the extended electrode 332 away from the trench area. The first via 501 and the second via 502 can be arranged at intervals and extend along the first direction D1. In the second direction D2, the distance between the first potential signal line 331 and the extended electrode 332 is greater than 10 micrometers. Therefore, as... Figure 15 As shown, the distance between the two rows of first vias 501 arranged along the first direction D1 at the adjacent edge positions of the first potential signal line 331 and the extended electrode 332 is at least greater than the width of the two second gate lines. The first vias 501 can also be arranged at the edge position of the extended electrode 332 near the second potential signal line 333, and at the edge position of the first potential signal line 331 away from the trench area. However, this embodiment is not limited to this.

[0130] In this exemplary embodiment, by employing a second metal structure (including a first potential signal line and an extended electrode), a semiconductor structure, and a second gate line to form a capacitor, the load capacitance is compensated, thereby improving the display uniformity of the display substrate. Furthermore, by providing a first via at the edge position of the first potential signal line and the extended electrode along the second direction, the space occupied by the first capacitor compensation unit can be reduced, thus facilitating narrow bezel design.

[0131] At least one embodiment of this disclosure also provides a method for fabricating a display substrate, used to fabricate the display substrate as described above. The fabrication method of this embodiment includes: providing a substrate; and sequentially forming a semiconductor structure, a first metal structure, and a second metal structure on the substrate in a capacitance compensation region located between a display region and a trench region. The semiconductor structure is insulated from the first metal structure, and the first metal structure is insulated from the second metal structure. An insulating layer between the semiconductor structure and the second metal structure is provided with a plurality of first vias, and the second metal structure is connected to the semiconductor structure through the plurality of first vias. The first metal structure includes a plurality of second gate lines extending along a first direction, respectively connected to the plurality of first gate lines within the display region. The orthographic projection of the second gate lines on the substrate at least partially overlaps with the orthographic projection of the second metal structure on the substrate, and the orthographic projection of the second gate lines on the substrate at least partially overlaps with the orthographic projection of the semiconductor structure on the substrate. The second gate lines, the second metal structure, and the semiconductor structure form a capacitor. The plurality of first vias are arranged along the first direction, and in a second direction perpendicular to the first direction, the distance between two adjacent first vias is at least greater than the sum of the widths of two second gate lines.

[0132] In some exemplary embodiments, the above-described fabrication method may further include: sequentially forming a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer on a substrate in the display area. The semiconductor layer includes an active layer of multiple transistors; the first conductive layer includes a gate electrode of the multiple transistors, a first electrode of a storage capacitor, and a first gate line connected to the gate electrode; the second conductive layer includes a second electrode of the storage capacitor; and the third conductive layer includes a source electrode and a drain electrode of the multiple transistors. The semiconductor structure is disposed on the same layer as the semiconductor layer, the first metal structure is disposed on the same layer as the second conductive layer, and the second metal structure is disposed on the same layer as the third conductive layer. The second gate line included in the first metal structure is connected to the corresponding first gate line in the first conductive layer.

[0133] The fabrication process of the display substrate provided in this embodiment can be referred to the description of the foregoing embodiments, and therefore will not be repeated here.

[0134] Figure 17 Example diagrams of a display device provided for at least one embodiment of this disclosure. For example... Figure 17 As shown, the display device 61 provided in this embodiment includes a display substrate 610. The display substrate 610 is the same as the display substrate provided in the previous embodiment, and its implementation principle and effect are similar, so it will not be described again here. In some examples, the display substrate can be an OLED display substrate. In some examples, the display device can be any product or component with display function, such as an OLED display device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator; this embodiment is not limited to this.

[0135] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, characterized in that, include: The display area includes a cutout area and a capacitance compensation area, wherein the display area at least partially surrounds the cutout area, and the capacitance compensation area is located between the display area and the cutout area; a plurality of first grid lines are provided within the display area. The capacitance compensation area is provided with a first capacitance compensation unit. The first capacitor compensation unit includes: a semiconductor structure, a first metal structure, and a second metal structure sequentially disposed on a substrate; the semiconductor structure and the first metal structure are mutually insulated, and the first metal structure and the second metal structure are mutually insulated; an insulating layer between the semiconductor structure and the second metal structure is provided with a plurality of first vias, and the second metal structure is connected to the semiconductor structure through the plurality of first vias; The first metal structure includes a plurality of second gate lines extending along a first direction, at least one second gate line being connected to a corresponding first gate line; the orthographic projection of the second gate line on the substrate at least partially overlaps with the orthographic projection of the second metal structure on the substrate, and the orthographic projection of the second gate line on the substrate at least partially overlaps with the orthographic projection of the semiconductor structure on the substrate; the second gate line forms a capacitor with the second metal structure and the semiconductor structure; the second metal structure includes at least: a first potential signal line extending along the first direction; The plurality of first vias are arranged along the first direction, and in the second direction perpendicular to the first direction, the distance between two adjacent first vias is at least greater than the sum of the widths of the two second gate lines; The capacitance compensation area is further provided with a second capacitance compensation unit, which includes: a third metal structure and a fourth metal structure that are sequentially disposed on the substrate and are mutually insulated; the third metal structure and the first metal structure are in the same layer, and the fourth metal structure and the second metal structure are in the same layer; the orthographic projection of the third metal structure on the substrate and the orthographic projection of the fourth metal structure on the substrate at least partially overlap, and the third metal structure and the fourth metal structure form a capacitor; The second gate line included in the third metal structure is continuous with the second gate line included in the first metal structure, and the first potential signal line included in the fourth metal structure is continuous with the first potential signal line included in the second metal structure. Within the capacitor compensation area, the second grid line closer to the trench area is connected to both the second capacitor compensation unit and the first capacitor compensation unit; the second grid line farther from the trench area is connected only to the first capacitor compensation unit.

2. The display substrate according to claim 1, characterized in that, The first metal structure includes N second gate lines extending along a first direction, where N is an integer greater than 1; In a second direction perpendicular to the first direction, the distance between two adjacent first vias is at least greater than the sum of the widths of the two second gate lines and less than the sum of the widths of the N second gate lines.

3. The display substrate according to claim 1, characterized in that, The first metal structure includes N second gate lines extending along a first direction, where N is an integer greater than 1; In a second direction perpendicular to the first direction, the distance between two adjacent first vias is greater than the sum of the widths of N second gate lines.

4. The display substrate according to claim 1, characterized in that, The semiconductor structure includes at least one semiconductor block, and the plurality of first vias are respectively located on one side edge or opposite two sides edge of the at least one semiconductor block in the second direction.

5. The display substrate according to claim 4, characterized in that, The semiconductor structure includes a plurality of semiconductor blocks arranged sequentially along a first direction, wherein at least one semiconductor block has a length ranging from 10 to 300 micrometers along the first direction.

6. The display substrate according to claim 1, characterized in that, The orthogonal projection of the second metal structure onto the substrate overlaps the orthogonal projection of the semiconductor structure onto the substrate.

7. The display substrate according to claim 1, characterized in that, The width of at least one second gate line included in the first metal structure is different from the width of the adjacent second gate line.

8. The display substrate according to claim 1, characterized in that, The display substrate further includes: a border area located around the display area and away from the cutout area; wherein the width of the first potential signal line in the capacitance compensation area is greater than the width of the first potential signal line in the border area.

9. The display substrate according to claim 1, characterized in that, The first potential signal line in the capacitor compensation area has a main body and an extension. The main body extends along the first direction, and the extension extends along the second direction. The end of the extension near the trench area is connected to the main body. The length of the extension in the first direction gradually increases and then decreases in the direction away from the trench area.

10. The display substrate according to claim 1, characterized in that, The second metal structure further includes an extended electrode, which is connected to the first potential signal line via a plurality of connecting electrodes.

11. The display substrate according to claim 10, characterized in that, The insulating layer between the multiple connecting electrodes and the second metal structure is provided with multiple second vias, and the extended electrode and the first potential signal line are respectively connected to the connecting electrodes through the multiple second vias; The first via and the second via are spaced apart from each other and arranged along the first direction.

12. The display substrate according to claim 1, characterized in that, The first potential signal line is a low-potential power line or a high-potential power line.

13. The display substrate according to claim 1, characterized in that, The display area is provided with a plurality of sub-pixels arranged in a regular manner. At least one sub-pixel includes: a light-emitting element and a driving circuit for driving the light-emitting element to emit light. The driving circuit includes a plurality of transistors and a storage capacitor. The display area includes: a substrate and a semiconductor layer, a first conductive layer, a second conductive layer and a third conductive layer sequentially disposed on the substrate; The semiconductor layer includes: an active layer of multiple transistors; The first conductive layer includes: gate electrodes of a plurality of transistors, a first electrode of a storage capacitor, and a first gate line connected to the gate electrodes; The second conductive layer includes: a second electrode for a storage capacitor; The third conductive layer includes: source electrodes and drain electrodes of multiple transistors; The semiconductor structure is disposed in the same layer as the semiconductor layer, the first metal structure is disposed in the same layer as the second conductive layer, and the second metal structure is disposed in the same layer as the third conductive layer; The second gate line included in the first metal structure is connected to the corresponding first gate line in the first conductive layer.

14. A display device, characterized in that, Includes the display substrate as described in any one of claims 1 to 13.

15. A method for preparing a display substrate, characterized in that, The display substrate includes a display area, a cutout area, and a capacitance compensation area. The display area at least partially surrounds the cutout area, and the capacitance compensation area is located between the display area and the cutout area. The preparation method includes: Provide a base; In the capacitance compensation region, a semiconductor structure, a first metal structure, and a second metal structure are sequentially formed on the substrate. The semiconductor structure is insulated from the first metal structure, and the first metal structure is insulated from the second metal structure. An insulating layer between the semiconductor structure and the second metal structure has multiple first vias. The second metal structure is connected to the semiconductor structure through these multiple first vias. The first metal structure includes multiple second gate lines extending along a first direction, each connected to multiple first gate lines within the display area. The orthographic projections of the second gate lines on the substrate at least partially overlap with the orthographic projections of the second metal structure on the substrate, and also at least partially overlap with the orthographic projections of the semiconductor structure on the substrate. The second gate lines, the second metal structure, and the semiconductor structure form a capacitor. The multiple first vias are arranged along the first direction, and in a second direction perpendicular to the first direction, the distance between two adjacent first vias is at least greater than the sum of the widths of the two second gate lines. The second metal structure includes at least: a first potential signal line extending along a first direction; The capacitance compensation area is further provided with a second capacitance compensation unit, which includes: a third metal structure and a fourth metal structure that are sequentially disposed on the substrate and are mutually insulated; the third metal structure and the first metal structure are in the same layer, and the fourth metal structure and the second metal structure are in the same layer; the orthographic projection of the third metal structure on the substrate and the orthographic projection of the fourth metal structure on the substrate at least partially overlap, and the third metal structure and the fourth metal structure form a capacitor; The second gate line included in the third metal structure is continuous with the second gate line included in the first metal structure, and the first potential signal line included in the fourth metal structure is continuous with the first potential signal line included in the second metal structure. Within the capacitor compensation area, the second grid line closer to the trench area is connected to both the second capacitor compensation unit and the first capacitor compensation unit; the second grid line farther from the trench area is connected only to the first capacitor compensation unit.

16. The preparation method according to claim 15, characterized in that, The preparation method further includes: forming a semiconductor layer, a first conductive layer, a second conductive layer and a third conductive layer sequentially on the substrate in the display area; The semiconductor layer includes: an active layer of multiple transistors; The first conductive layer includes: gate electrodes of a plurality of transistors, a first electrode of a storage capacitor, and a first gate line connected to the gate electrodes; The second conductive layer includes: a second electrode for a storage capacitor; The third conductive layer includes: source electrodes and drain electrodes of multiple transistors; The semiconductor structure is disposed in the same layer as the semiconductor layer, the first metal structure is disposed in the same layer as the second conductive layer, and the second metal structure is disposed in the same layer as the third conductive layer; The second gate line included in the first metal structure is connected to the corresponding first gate line in the first conductive layer.

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