A circuit to prevent power supply voltage from affecting shutdown delay

Abstract

A circuit for preventing power supply voltage from affecting shutdown delay, characterized in that: the circuit includes an enable output unit, a mirror current generating unit and a negative feedback unit; wherein the enable output unit is connected to the feedback unit and the mirror current generating unit respectively, and is used to generate a chip enable signal based on the input of a system enable signal, and output the chip enable signal; the mirror current generating unit is used to generate a stable mirror current based on the state of the chip enable signal, and replace the high-end mirror tube in the enable output unit; the feedback unit is used to receive the chip enable signal from the enable output unit, control the conduction of the mirror tube in the enable output unit, and stabilize the delay of the chip enable signal relative to the system enable signal based on the mirror current generated by the mirror current generating unit. The present invention has low cost, low power consumption in the system enable process, and stable and predictable shutdown delay.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and more particularly to a circuit for preventing power supply voltage from affecting shutdown delay. Background Art

[0002] At present, in the control circuit for turning on or off the upper and lower tubes of a DC-DC (Direct Current-Direct Current, also known as DC-DC) converter, the system enable signal is usually used as the input of the circuit, and after passing through multiple stages of inverters, the control signal for turning on or off is output. There is usually a certain turn-off delay between the control signal for turning on or off generated in this way and the enable signal at its input end.

[0003] Generally speaking, this delay includes the charging delay t0 caused by the parasitic capacitance on the power tube where the enable signal is located, the transmission delays t1 and t2 caused by the multi-stage inverter, etc. Generally speaking, the charging delay t0 of the parasitic capacitance on the power tube will change with the change of the power supply voltage, and the transmission delay of the inverter will also be affected by the power supply voltage to a certain extent. It can be seen that the turn-off delay of the control circuit of the on or off in the prior art will change due to the influence of the power supply voltage. This change causes an error in the timing of the circuit at the back end of the control signal, which may seriously affect the output performance.

[0004] In the prior art, the size of the MOS tube in the multi-stage inverter can generally be designed, for example, the width-to-length ratio of the NMOS tube and the PMOS tube in the inverter is reasonably designed, for example, the width-to-length ratio of the NMOS tube is 80 to 100 times that of the PMOS tube, so that the flip threshold of the inverter is only determined by the threshold turn-on voltage of the NMOS.

[0005] The charging delay t0 of the power tube will still change greatly with the change of the power supply voltage. With the development of technology in the field of integrated circuits, the requirements for the accuracy of shutdown control of equipment or components are gradually increasing. This makes the shutdown delay of the existing on or off control circuit unable to fully meet the precise requirements of the synchronization logic in the subsequent circuit when the power supply voltage is not stable enough. For the prior art, the power supply voltage of some control circuits is itself affected by, for example, the bootstrap capacitor, and it is difficult to maintain a stable value, which further deteriorates the synchronization between the chip enable signal and the subsequent circuit.

[0006] On the other hand, in some applications, the total shutdown delay, that is, the sum of the charging delay t0 and the transmission delays t1 and t2 caused by the multi-stage inverter, has a maximum limit. In order to ensure that the total shutdown delay does not exceed the set threshold, the prior art generally adopts a method of providing a larger charging current. However, this method consumes a lot of power in the system enable control process.

[0007] In order to solve the above problems, a new circuit is urgently needed to prevent the power supply voltage from affecting the shutdown delay. Summary of the invention

[0008] In order to solve the deficiencies in the prior art, the purpose of the present invention is to provide a circuit for preventing the power supply voltage from affecting the shutdown delay. A mirror current generating unit and a feedback unit are added to the original circuit. The feedback unit starts the mirror current generating unit and turns off the high-end mirror tube in the original enable output unit. The mirror current generating unit generates a stable mirror current and replaces the high-end mirror tube to provide the enable output unit with a charging current for the enable power tube, thereby preventing the output delay of the chip enable signal from being correlated with the power supply voltage Vdd and ensuring the fixity of the output delay.

[0009] The present invention adopts the following technical solution.

[0010] A first aspect of the present invention relates to a circuit for preventing power supply voltage from affecting shutdown delay, wherein the circuit includes an enable output unit, a mirror current generating unit and a negative feedback unit; the enable output unit is connected to the feedback unit and the mirror current generating unit respectively, and is used to generate a chip enable signal based on the input of a system enable signal and output the chip enable signal; the mirror current generating unit is used to generate a stable mirror current based on the state of the chip enable signal and replace the high-end mirror tube in the enable output unit; the feedback unit is used to receive the chip enable signal from the enable output unit, control the mirror tube in the enable output unit to be turned on, and stabilize the delay of the chip enable signal relative to the system enable signal based on the mirror current generated by the mirror current generating unit.

[0011] Preferably, the mirror current generating unit includes a first branch, a second branch, a third branch, and high-end feedback tubes Mp0 and Mp3; wherein the first branch, the second branch and the third branch are interconnected to generate a mirror current that is unrelated to the power supply voltage; the first branch, the second branch and the third branch are mirror-connected to the high-end feedback tubes Mp0 and Mp3, respectively, so as to input the mirror current into the enable output unit through the high-end feedback tube.

[0012] Preferably, the first branch includes a MOS tube Mp7 and a transistor Q2, and the second branch includes a MOS tube Mp6 and a transistor Q1, and a voltage-dividing resistor R1; wherein the sources of the MOS tubes Mp6 and Mp7 are connected to the power supply voltage Vdd, and the gates are connected to each other and to the drain of Mp7; the drain of the MOS tube Mp6 is connected to the collector of the transistor Q1, the drain of the MOS tube Mp7 is connected to the collector of the transistor Q2, the bases of the transistors Q1 and Q2 are connected, and the emitter of the transistor Q1 is grounded at the same time as the emitter of the transistor Q2 after passing through the resistor R1.

[0013] Preferably, the third branch includes a MOS tube Mp5 and a transistor Q0; wherein the source of the MOS tube Mp5 in the third branch is connected to the power supply voltage, the gate is connected to the drain of the MOS tube Mp6 in the second branch, and the drain is connected to the collector and base of the transistor Q0; the emitter of the transistor Q0 is grounded, and the collector and base are connected to the bases of the transistors Q1 and Q2 in the first branch and the second branch.

[0014] Preferably, the mirror generation unit also includes a state control tube, which is Mn4, a gate connected to the chip enable signal, a drain connected to the bases of transistors Q0, Q1 and Q2 respectively, and a source grounded.

[0015] Preferably, the feedback unit includes MOS tubes Mp4, Mn3 and Mn3a; wherein Mp4 is mirror-connected to the MOS tubes Mp6 and Mp7 in the first branch and the second branch, and the high-end feedback tubes Mp0 and Mp3; the gate of the MOS tube Mn2 is connected to the chip enable signal in the enable output unit after passing through an inverter, the drain is connected to the drain of Mp4, and the source is connected to the resistor R0 in the enable output unit and the source of the MOS tube Mn1; the gate of the MOS tube Mn3a is connected to the power supply voltage, the source is connected to the drain of Mn3, and the drain is connected to the drain of Mp6 in the first branch.

[0016] Preferably, when the system enable signal is switched to a low level, the chip enable signal outputs a high level after a delay, so that the MOS tubes Mn3 and Mn3a are turned off, and the state control tube Mn4 in the mirror current generating unit is turned on, so that the mirror current generating unit cannot generate a mirror current.

[0017] Preferably, when the system enable signal is switched to a high level, the chip enable signal outputs a low level after a delay, the MOS tubes Mn3 and Mn3a are turned on and start the first branch, the second branch and the third branch and then turned off, and at the same time, the mirror current generating unit generates a stable mirror current and turns off the MOS tubes Mp1 and Mp2.

[0018] Preferably, when the system enable signal is switched to a high level, the drain voltage of the power tube Mn0 receiving the enable signal in the enable output unit increases to a delay of t0 for the first inverter in the enable output unit to start working; and, Where V th_Mn1 C is the threshold voltage of the lower tube Mn1 of the first inverter in the enable output unit. Mn0 V is the drain-to-ground capacitance of the power tube Mn0 that receives the enable signal in the enable output unit. T is the thermal voltage of the transistors Q1 and Q2 in the mirror current generating unit, N is the ratio of the current density of the transistors Q1 and Q2 in the mirror current generating unit, and R1 is the resistance value of the voltage dividing resistor R1 in the second branch.

[0019] Preferably, the shutdown delay of the circuit is R=t0+t1+t2, which tends to be stable when the power supply voltage changes; wherein t1 is the delay of enabling the first inverter in the output unit, and t2 is the delay of enabling the second inverter in the output unit, both of which are less than the delay t0 for the first inverter in the output unit to start working.

[0020] The beneficial effect of the present invention is that, compared with the prior art, a circuit for preventing the power supply voltage from affecting the shutdown delay is provided, a mirror current generating unit and a feedback unit are added to the original circuit, the feedback unit starts the mirror current generating unit and turns off the high-end mirror tube in the original enable output unit, the mirror current generating unit generates a stable mirror current and replaces the high-end mirror tube to provide the enable output unit with a charging current for the enable power tube, thereby eliminating the correlation between the output delay of the chip enable signal and the power supply voltage Vdd to the greatest extent, and ensuring the fixed output delay. The method of the present invention is simple, low in cost, has low power consumption in the system enable process, saves electric energy, and has a stable and predictable shutdown delay.

[0021] The beneficial effects of the present invention also include:

[0022] 1. By reasonably designing the proportional relationship between the length of the charging delay t0 and the delay length of the inverter, the delay of the inverter will still be affected by the power supply voltage to a certain extent, but will not have a significant impact on the total delay of the chip enable signal.

[0023] 2. In the present invention, based on the rising edge state of each system enable signal, the first, second and third branches are turned on and the current output is stabilized, and based on the falling edge state of each system enable signal, the mirror current generating unit is turned off. This method fully ensures the stability of the turn-off delay without affecting the turn-on time. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1It is a structural schematic diagram of an enabling control circuit in the prior art of the present invention;

[0025] Figure 2 A schematic diagram of a potential change curve and a time delay of each point in an enabling control circuit according to the prior art of the present invention;

[0026] Figure 3 The schematic diagram is a structural diagram of a circuit for preventing power supply voltage from affecting shutdown delay in the present invention. DETAILED DESCRIPTION

[0027] The present application is further described below in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and cannot be used to limit the protection scope of the present application.

[0028] Figure 1 FIG. 1 is a schematic diagram of a structure of an enabling control circuit in the prior art of the present invention. Figure 1 As shown, the enabling control circuit in the prior art includes a mirror unit and a first and a second inverter. Among them, the mirror unit includes an enabling input power tube Mn0, and the other parts can be used to generate a mirror current of the power tube Mn0, and the current actually passing through the source and drain of the power tube Mn0 during the conduction process is calculated. In addition, a plurality of inverters are cascaded after the drain of the power tube Mn0 in the circuit, and after passing through the inverter, the output signal further increases the delay.

[0029] In one embodiment of the present invention, there is only one mirror unit and two inverters between the enable input terminal and the chip enable signal output terminal, so the total turn-off delay can be the sum of the charging delay of the mirror unit, that is, Mn0, and the delays of the two inverters. As described in the formula, T = t0 + t1 + t2.

[0030] Figure 2 This is a schematic diagram of the potential change curve and delay of each point in an enabling control circuit of the prior art of the present invention. Figure 2 As shown, in the first aspect, in the present invention, when the enable signal changes from high to low, the delay of the mirror unit is Among them, parameter C Mn0 To enable the drain-to-ground capacitance of the power tube Mn0, which is mainly formed by the gate-drain capacitance of the Mn0 tube, the parameter V Mn1_th is the threshold opening voltage of the NMOS tube Mn1 in the first inverter. That is, as the enable signal EN becomes low level, Mn0 is turned off, enabling the mirror current I Mp1 Gradually accumulating, the gate-drain capacitance in Mn0 is fully charged, and the drain voltage of Mn0 increases until the inverter connected to the rear end of the power tube Mn0 is activated, and this delay t0 ends.

[0031] In addition, I Mp1To enable the mirror current, its value can refer to Figure 1 In the circuit structure of the mirror unit, since a mirror image is formed between Mp1 and Mp2, and the gate voltage of the MOS tube Mn2 is the power supply voltage, at this time, Mn2 is in the on state, and its source-drain voltage is too small to be ignored, the enabling mirror current can be calculated, specifically:

[0032] Substituting the value of the enabled mirror current into the delay formula of the mirror unit, we can obtain It can be seen that the delay caused by the mirror unit is not only related to the resistance value of resistor R0, the threshold voltage of MOS tube Mn1 and other constants that are fixed after the circuit is designed, but also closely related to the power supply voltage. It can be inferred from the formula that as the power supply voltage gradually increases, the transmission delay of the mirror unit will decrease, and as the power supply voltage gradually decreases, the transmission delay of the mirror unit will increase. However, the power supply voltage is closely related to important parameters such as the actual function and control logic of the circuit, and it cannot be set as a fixed constant. It can be seen that the circuit cannot achieve a fixed delay when the power supply voltage changes.

[0033] After studying the problems in the prior art, it is found that if it is desired to change the problem that the turn-off delay varies with the power supply voltage, it is necessary to make improvements based on the circuit.

[0034] Figure 3 FIG. 1 is a schematic diagram of a circuit for preventing power supply voltage from affecting shutdown delay in the present invention. Figure 3 As shown, a circuit for preventing power supply voltage from affecting shutdown delay, wherein the circuit includes an enable output unit, a mirror current generating unit and a feedback unit; the enable output unit is connected to the feedback unit and the mirror current generating unit respectively, and is used to generate a chip enable signal based on the input of a system enable signal, and output the chip enable signal; the mirror current generating unit is used to generate a stable mirror current based on the state of the chip enable signal, and replace the high-end mirror tube in the enable output unit; the feedback unit is used to receive the chip enable signal from the enable output unit, control the mirror tube in the enable output unit to be turned on, and stabilize the delay of the chip enable signal relative to the system enable signal based on the mirror current of the mirror current generating unit.

[0035] It can be understood that the circuit in the present invention can achieve control of the mirror current by replacing the high-end mirror tube of the enable output unit. Since the value of the mirror current is independent of the power supply voltage Vdd, the delay of the chip enable signal output by the circuit of the present invention is also independent of the power supply voltage Vdd, and is only related to the relevant parameters in the circuit. Therefore, once the circuit parameters are fully determined, the value of the mirror current is constant, which makes the charging delay not change due to the influence of the charging current. At this time, if the delay t1+t2 of the inverter accounts for a low proportion of the total shutdown delay, it can be ignored, thereby ensuring the relative constancy of the total delay.

[0036] Specifically, the enable output unit includes a current mirror composed of Mp1 and Mp2, a first inverter and a second inverter; wherein the drain of Mp1 in the current mirror is connected to the enable power tube Mn0 and the first inverter respectively, for receiving the system enable signal EN. Specifically, when EN is at a high level, Mn0 is turned on, thereby reducing the voltage at point A in the circuit, and when EN is at a low level, Mp0 is turned on, so that the voltage at point A can gradually increase. When the voltage at point A rises to a level higher than the turn-on threshold of the NMOS tube in the first inverter, the first inverter is flipped. The first inverter is reversed based on the voltage at point A, and the output voltage of the first inverter is provided to the input of the second inverter; the second inverter is reversed based on the input voltage provided by the first inverter, and the output voltage of the second inverter is used as the chip enable signal at the output of the enable output unit.

[0037] It can be understood that the enabling output unit in the present invention can be similar to the circuit in the prior art, both of which include a current mirror, a first inverter and a second inverter.

[0038] In order to make the current mirror generate a stable charging current, the drain of Mp2 is also connected to Mn2 and resistor R0 in sequence. Since Mn2 is small in size, its source-drain voltage drop can be ignored. Therefore, the current of the Mp2 and Mp1 current mirrors is calculated based on the voltage drop of R0. In the present invention, the current can be calculated based on the resistance value of resistor R0 and the voltage of its two segments, which will be described in detail later.

[0039] When the power tube Mn0 receives the enable signal for a period of time, the gate-drain capacitance of Mn0 can be fully charged, and the voltage accumulated at the drain gradually increases until it is sufficient to turn on the NMOS tube Mn1 in the inverter. When the drain voltage of Mn0 is greater than the turn-on threshold voltage of the inverter, the NMOS tube in the inverter is turned on, and the delay caused by the mirror unit ends.

[0040] In the present invention, the structures of the first and second inverters can adopt various structures commonly used in the prior art. In one embodiment of the present invention, the inverter is a CMOS tube inverter. In the inverter, the gate of the NMOS tube and the gate of the PMOS tube are connected through a NOT gate as the input end of the inverter, the source of the PMOS tube is connected to the power supply voltage, the source of the NMOS tube is grounded, and the drains of the NMOS tube and the PMOS tube are connected to each other and serve as the output end of the inverter.

[0041] As described in the background technology, under certain conditions, the turn-on or turn-off delay of Mn1 and Mn2 is still affected to a certain extent by the power supply voltage after the parameters such as the width-to-length ratio are determined. Therefore, in the present invention, the delays t1 and t2 of the first inverter and the second inverter can be set to be much smaller than the charging delay t0, thereby minimizing the impact of the power supply voltage on the total delay.

[0042] Preferably, the mirror current generating unit includes a first branch, a second branch, a third branch, and high-end feedback tubes Mp0 and Mp3; wherein the first branch, the second branch and the third branch are interconnected to generate a mirror current that is unrelated to the power supply voltage; the first branch, the second branch and the third branch are respectively connected to the high-end feedback tubes Mp0 and Mp3 to input the mirror current into the enable output unit through the high-end feedback tubes.

[0043] It can be understood that the mirror current generating unit in the present invention includes multiple branches in sequence, and the proportional relationship between the current and voltage between each branch can be obtained through the mirror connection mode and the width-to-length ratio of the MOS tubes between each branch.

[0044] Since the second branch includes a voltage divider resistor R1, when the feedback unit is not conducting and does not affect the mirror current generating unit, the accurate value of the mirror current can be calculated based on the resistance of the voltage divider resistor and the voltage difference between the two ends. Since the value of the current in the mirror current generating unit is only related to the resistance of the voltage divider resistor R1 and the voltage difference between the base and emitter of the two transistors Q1 and Q2, it can also be considered that the current does not change with the change of the power supply voltage. In this case, the current in the high-end feedback tube generated by the mirror current is also constant.

[0045] Preferably, the first branch includes a MOS tube Mp7 and a transistor Q2; the second branch includes a MOS tube Mp6 and a transistor Q1, and a voltage-dividing resistor R1; wherein the sources of the MOS tubes Mp6 and Mp7 are connected to the power supply voltage Vdd, and the gates are connected to each other and to the drain of Mp7; the drain of the MOS tube Mp6 is connected to the collector of the transistor Q1, the drain of the MOS tube Mp7 is connected to the collector of the transistor Q2, the bases of the transistors Q1 and Q2 are connected, and the emitter of the transistor Q1 is grounded at the same time as the emitter of the transistor Q2 after passing through the resistor R1.

[0046] It is understandable that in the present invention, the first branch is only composed of Mp7 and Q2 in series, because in the mirror circuit, each mirror tube is connected to the gate of Mp6 and Mp7 to achieve mirroring. Figure 3 As shown, multiple PMOS transistors, including Mp0, Mp3, Mp6 in the mirror current generating unit, and Mp4 in the feedback unit, are connected to the gate of Mp7 to form a mirror. Mp7 When , the source-drain currents of the other mirror tubes also have the same value or are in a set ratio.

[0047] Preferably, the third branch includes a MOS tube Mp5 and a transistor Q0; wherein the source of the MOS tube Mp5 in the third branch is connected to the power supply voltage, the gate is connected to the drain of the MOS tube Mp6 in the second branch, and the drain is connected to the collector and base of the transistor Q0; the emitter of the transistor Q0 is grounded; the collector and the base are connected to the bases of the transistors Q1 and Q2 in the first branch and the second branch.

[0048] Preferably, the mirror generation unit also includes a state control tube, which is Mn4, a gate connected to the chip enable signal, a drain connected to the bases of transistors Q0, Q1 and Q2 respectively, and a source grounded.

[0049] The state control tube in the present invention can be connected between the base of transistors Q0, Q1 and Q2 and the ground potential, and can be connected to the chip enable signal, that is, Figure 3 When the chip enable signal is at a high level, the NMOS transistor Mn4 is turned on and the base voltage of the transistor is pulled down to zero level. At this time, the first, second and third branches no longer output stable current.

[0050] On the other hand, when the chip enable signal is at a low level, the NMOS tube is turned off, and at this time, the first, second and third branches output stable currents to achieve stability in the charging delay.

[0051] Preferably, the feedback unit includes MOS tubes Mp4, Mn3 and Mn3a; wherein Mp4 is mirror-connected to the MOS tubes Mp6 and Mp7 in the first branch and the second branch, and the high-end feedback tubes Mp0 and Mp3; the gate of the MOS tube Mn2 is connected to the chip enable signal in the enable output unit after passing through an inverter, the drain is connected to the drain of Mp4, and the source is connected to the resistor R0 in the enable output unit and the source of the MOS tube Mn1; the gate of the MOS tube Mn3a is connected to the power supply voltage, the source is connected to the drain of Mn3, and the drain is connected to the drain of Mp6 in the first branch.

[0052] It is understandable that, in the present invention, the third inverter can be cascaded with the first and second inverters, and its input terminal is connected to the feedback unit. Figure 3 When the output of the third inverter is at a high level, the circuit can turn on Mn3 and Mn3a at the same time, and when the output of the third inverter is at a low level, both Mn3 and Mn3a are in an off state.

[0053] Preferably, when the system enable signal is switched to a low level, the chip enable signal outputs a high level after a delay, so that the MOS tubes Mn3 and Mn3a are turned off, and the state control tube Mn4 in the mirror current generating unit is turned on, so that the mirror current generating unit cannot generate a mirror current.

[0054] It can be understood that, due to the effect of the feedback unit, the circuit in the present invention can have two different working modes. One working mode can be understood as a state where the enable signal is switched from a high level to a low level. In this state, with the effect of the enable unit, the chip enable signal is at a high level, which makes the output low after passing through the third inverter, so the Mn3 tube is turned off. In addition, due to the effect of the state control tube Mn4, the first, second and third branches no longer output current. At this time, the Mp1 and Mp2 tubes are normally turned on, and the circuit works like the circuit in the prior art without feedback.

[0055] Preferably, when the system enable signal is switched to a high level, the chip enable signal outputs a low level after a delay, and the MOS tubes Mn3 and Mn3a are turned on and start the first branch, the second branch and the third branch and then turned off. At the same time, the mirror current generating unit generates a stable mirror current and turns off the MOS tubes Mp1 and Mp2. In addition, in this case, since the source-drain voltage drop of Mp3 is also small, the voltage at point C can rise higher, approximately equal to the power supply voltage Vdd, which makes the gate-source voltage difference of Mp2 small and difficult to turn on. Exactly the same is that Mp0 will also pull up the drain voltage of Mp1, thereby turning off Mp1.

[0056] Preferably, when the system enable signal is switched to a high level, the drain voltage of the power tube Mn0 receiving the enable signal in the enable output unit increases to a delay of t0 for the first inverter in the enable output unit to start working; and, Where V th_Mn1 C is the threshold voltage of the lower tube Mn1 of the first inverter in the enable output unit. Mn0 V is the drain-to-ground capacitance of the power tube Mn0 that receives the enable signal in the enable output unit. T is the thermal voltage of the transistors Q1 and Q2 in the mirror current generating unit, N is the ratio of the current density of the transistors Q1 and Q2 in the mirror current generating unit, and R1 is the resistance value of the voltage dividing resistor R1 in the second branch.

[0057] It is understandable that in the present invention, due to the shutdown of Mp1 and Mp2, the mirror current received at point A and point C is generated based on the mirror current generating unit, and the value is stable. Therefore, the charging delay t0 can also remain stable.

[0058] The reason why the current of the mirror current generating unit can remain unchanged is that the currents of the first branch and the second branch are set in a constant ratio. For example, when the currents of the two branches are equal, the voltage division on the resistor R1 is equal to the base-emitter voltage difference of the transistors Q1 and Q2. Therefore, ΔV be =V be2 -V be1 =V T lnN. That is, the mirror current is This current is used as a charging current and input into the drain of Mn0 to charge the gate-drain capacitance of Mn0, thereby obtaining That is, the time required to charge the capacitor until the drain voltage of Mn0 is equal to the NMOS transistor turn-on voltage of the first inverter is the charging delay.

[0059] It can be seen that the charging delay is no longer affected by the power supply voltage, but is fixed according to the parameters of transistors Q1, Q2, inverter and Mn0.

[0060] Preferably, the shutdown delay of the circuit is T=t0+t1+t2, which does not change with the change of the power supply voltage; wherein t1 is the delay of the first inverter in the enable output unit, and t2 is the delay of the second inverter in the enable output unit, both of which are less than the delay t0 for the first inverter in the enable output unit to start working.

[0061] It can be seen that the total turn-off delay of the circuit can be ensured to be stable to the greatest extent after the first and second inverters are reasonably selected and t1+t2<<t0 is ensured.

[0062] The beneficial effect of the present invention is that, compared with the prior art, a circuit for preventing the power supply voltage from affecting the shutdown delay is provided, a mirror current generating unit and a negative feedback unit are added to the original circuit, the negative feedback unit starts the mirror current generating unit and turns off the high-end mirror tube in the original enable output unit, the mirror current generating unit generates a stable mirror current and replaces the high-end mirror tube to provide the mirror current for the enable output unit, thereby eliminating the influence of the correlation between the output delay of the chip enable signal and the power supply voltage Vdd on the shutdown delay to the greatest extent. The method of the present invention is simple, low in cost, low in power consumption after the system enable end, saves electric energy, and the shutdown delay is stable and predictable.

[0063] The applicant of the present invention has made a detailed explanation and description of the implementation examples of the present invention in conjunction with the drawings in the specification. However, those skilled in the art should understand that the above implementation examples are only preferred implementation schemes of the present invention, and the detailed description is only to help readers better understand the spirit of the present invention, but not to limit the scope of protection of the present invention. On the contrary, any improvements or modifications based on the inventive spirit of the present invention should fall within the scope of protection of the present invention.

Claims

1. A circuit for preventing power supply voltage from affecting shutdown delay, characterized in that: The circuit includes an enable output unit, a mirror current generating unit and a feedback unit; wherein, The enable output unit is connected to the feedback unit and the mirror current generating unit respectively, and is used to generate a chip enable signal based on the input of the system enable signal, and output the chip enable signal; The mirror current generating unit is used to generate a stable mirror current based on the state of the chip enable signal and replace the high-end mirror tube in the enable output unit; The feedback unit is used to receive the chip enable signal from the enable output unit, control the current mirror in the enable output unit to be turned on, and stabilize the delay of the chip enable signal relative to the system enable signal based on the mirror current generated by the mirror current generation unit; The mirror current generating unit includes a first branch, a second branch, a third branch, and high-end feedback tubes Mp0 and Mp3; wherein, The first branch, the second branch and the third branch are connected to each other and used to generate a mirror current irrelevant to the power supply voltage; The first branch, the second branch and the third branch are mirror-connected to the high-end feedback tubes Mp0 and Mp3 respectively, so as to input the mirror current into the enable output unit through the high-end feedback tube; The first branch includes a MOS transistor Mp7 and a transistor Q2, and the second branch includes a MOS transistor Mp6, a transistor Q1, and a voltage-dividing resistor R1; wherein, The sources of the MOS tubes Mp6 and Mp7 are connected to the power supply voltage Vdd, and the gates are connected to each other and connected to the drain of Mp7; The drain of the MOS transistor Mp6 is connected to the collector of the transistor Q1, the drain of the MOS transistor Mp7 is connected to the collector of the transistor Q2, the bases of the transistors Q1 and Q2 are connected, and the emitter of the transistor Q1 is grounded together with the emitter of the transistor Q2 after passing through the resistor R1; The third branch includes MOS tube Mp5 and transistor Q0; wherein, The source of the MOS transistor Mp5 in the third branch is connected to the power supply voltage, the gate is connected to the drain of the MOS transistor Mp6 in the second branch, and the drain is connected to the collector and base of the transistor Q0; The emitter of the transistor Q0 is grounded, and the collector and the base are connected to the bases of the transistors Q1 and Q2 in the first branch and the second branch; the mirror current generating unit also includes a state control tube, the state control tube is Mn4, the gate is connected to the chip enable signal, the drain is respectively connected to the bases of the transistors Q0, Q1 and Q2, and the source is grounded; The feedback unit includes MOS tubes Mp4, Mn3 and Mn3a; wherein, The Mp4 is mirror-connected to the MOS tubes Mp6 and Mp7 in the first branch and the second branch, and the high-end feedback tubes Mp0 and Mp3; The gate of the MOS transistor Mn2 is connected to the chip enable signal in the enable output unit through an inverter, the drain is connected to the drain of Mp4, and the source is connected to the resistor R0 in the enable output unit and the source of the MOS transistor Mn1; The gate of the MOS tube Mn3a is connected to the power supply voltage, the source is connected to the drain of Mn3, and the drain is connected to the drain of Mp6 in the first branch; When the system enable signal is switched to a low level, the chip enable signal outputs a high level after a delay, so that the MOS tubes Mn3 and Mn3a are turned off, and the state control tube Mn4 in the mirror current generating unit is turned on, so that the mirror current generating unit cannot generate a mirror current; When the system enable signal is switched to a high level, the chip enable signal outputs a low level after a delay, the MOS tubes Mn3 and Mn3a are turned on and start the first branch, the second branch and the third branch and then turned off, and at the same time, the mirror current generating unit generates a stable mirror current and turns off the MOS tubes Mp1 and Mp2, and the enable output unit includes a current mirror composed of Mp1 and Mp2.

2. A circuit for preventing power supply voltage from affecting shutdown delay according to claim 1, characterized in that: When the system enable signal is switched to a high level, the drain voltage of the power tube Mn0 in the enable output unit that receives the enable signal rises to a delay of t0 until the first inverter in the enable output unit starts to work; and Where V th_Mn1 is the threshold turn-on voltage of the lower tube Mn1 of the first inverter in the enable output unit, C Mn0 is the drain-to-ground capacitance of the power tube Mn0 receiving the enable signal in the enable output unit, V T is the thermal voltage of transistors Q1 and Q2 in the mirror current generating unit, N is the ratio of the current densities of transistors Q1 and Q2 in the mirror current generating unit, R1 is the resistance value of the voltage-dividing resistor R1 in the second branch.

3. A circuit for preventing power supply voltage from affecting shutdown delay according to claim 2, characterized in that: The turn-off delay of the circuit is T=t0+t1+t2, and tends to be stable when the power supply voltage changes; Among them, t1 is the delay of the first inverter in the enable output unit, and t2 is the delay of the second inverter in the enable output unit, both of which are shorter than t0, the delay of the first inverter in the enable output unit starting to work.

Images