Method for manufacturing asymmetric vertical nanowire MOSFET and asymmetric vertical nanowire MOSFET

Abstract

A method for fabricating an asymmetric vertical nanowire MOSFET (100) on a semiconductor substrate (110) comprising at least one vertical nanowire (125) is provided, the at least one vertical nanowire comprising a core portion (120) and a shell portion (130) surrounding the core portion (120). The method comprises: depositing a protective layer (140) on a semiconductor substrate (110); forming a top contact (150) around a remaining portion (120t) of a vertical nanowire (125) not covered by the protective layer (140); removing the protective layer (140); depositing a spacer layer (160) on the semiconductor substrate (110); removing an outer shell portion of a middle portion (125i) of a bottom portion (125b) of the vertical nanowire (125); trimming an outer shell portion of an upper portion (125u) of the bottom portion (125b) of the vertical nanowire (125); depositing a metal gate (170) on the spacer layer (160), and forming a lower source-drain portion and an upper source-drain portion.

Description

Technical Field

[0001] The inventive concept relates to a method for fabricating an asymmetric vertical nanowire metal oxide semiconductor field effect transistor (MOSFET) on a semiconductor substrate and an asymmetric vertical nanowire MOSFET. Background Art

[0002] Over the past few years, vertical nanowire MOSFET devices have been developed that allow for all-around gate geometries. In particular, MOSFETs formed from III-V materials integrated on Si substrates offer the potential to reduce supply voltage and, therefore, power consumption. However, compared to state-of-the-art lateral MOSFETs, vertical nanowire MOSFETs have demonstrated considerably lower performance. This lower performance of vertical nanowire MOSFETs may be related to their longer gate length, higher access resistance, and higher capacitance compared to lateral MOSFETs. Summary of the Invention

[0003] It is an object of the inventive concept to at least partially overcome one or more of the above-mentioned limitations of the prior art.

[0004] According to one aspect of the present invention, there is provided a method for fabricating an asymmetric vertical nanowire MOSFET on a semiconductor substrate comprising at least one vertical nanowire, wherein the at least one vertical nanowire comprises a core portion and a shell portion, the shell portion surrounding the core portion along the height of the nanowire, the method comprising: depositing a protective layer on the semiconductor substrate and around a bottom portion of the vertical nanowire; forming a top contact around a remaining portion of the vertical nanowire not covered by the protective layer; removing the protective layer by etching; depositing a spacer layer on the semiconductor substrate and around a lower portion of the bottom portion of the vertical nanowire, wherein the thickness of the spacer layer is less than the protective layer. The protective layer has a thickness of 0.04mm and a thickness of the protective layer, and wherein the remaining portion of the bottom portion of the vertical nanowire not covered by the spacer layer includes a middle portion and an upper portion; removing the shell portion of the middle portion of the bottom portion of the vertical nanowire, thereby exposing the core portion of the vertical nanowire at the middle portion of the bottom portion of the vertical nanowire; trimming the shell portion of the upper portion of the bottom portion of the vertical nanowire, thereby reducing the thickness of the shell portion of the upper portion of the bottom portion of the vertical nanowire, or removing the shell portion of the upper portion of the bottom portion of the vertical nanowire; depositing a metal gate on the isolation layer and around the middle portion of the bottom portion of the nanowire; and forming a lower source-drain portion and an upper source-drain portion.

[0005] At least one vertical nanowire comprising a core portion and a shell portion allows, for example, a combination of two different materials. The step of depositing a protective layer on the semiconductor substrate and around the bottom portion of the vertical nanowire allows the bottom portion of the vertical nanowire to be protected during the step of forming a top contact. Thus, a top contact is formed on the remaining portion of the vertical nanowire (i.e., the top portion of the vertical nanowire not covered by the protective layer). In addition, the thickness of the protective layer can, for example, define the spacing between the top contact and the lower source-drain portion. The step of removing the protective layer by etching allows access to the bottom portion of the vertical nanowire while the top portion of the nanowire is covered by the top contact. The step of depositing a spacer layer on the semiconductor substrate and around the lower portion of the bottom portion of the vertical nanowire allows defining the spacing between the gate and the lower source-drain portion. For example, the thickness of the spacer layer can affect the spacing between the gate and the lower source-drain portion.

[0006] The steps of removing the shell portion of the middle portion of the bottom portion of the vertical nanowire and trimming the shell portion of the upper portion of the bottom portion of the vertical nanowire allow the formation of an asymmetric portion of the vertical nanowire arranged adjacent to the metal gate, i.e., the lower portion of the bottom portion of the vertical nanowire and the upper portion of the bottom portion of the vertical nanowire become asymmetric. For example, the thickness of the upper portion of the bottom portion of the vertical nanowire becomes smaller than the thickness of the lower portion of the bottom portion of the vertical nanowire. The asymmetric vertical nanowire MOSFET also allows the design of the gate-source capacitance (C gs ) and gate-drain capacitance (C gd ), which enables the realization of asymmetric C gs and C gd At the same time, the presence of the housing on at least one side of the metal gate in the immediate vicinity of the metal gate provides a means of reducing the access resistance, which is critical for digital and radio frequency (RF) applications. gs and C gd The power gain of the obtained asymmetric vertical nanowire MOSFET can also be improved.

[0007] A vertical nanowire MOSFET herein means a MOSFET comprising a semiconductor structure and further comprising a gate structure, the semiconductor structure comprising a lower source-drain portion and an upper source-drain portion and a channel portion, the channel portion being positioned between the lower source-drain portion and the upper source-drain portion and extending vertically therebetween, the gate structure extending vertically along the channel portion. The gate structure may at least partially surround the channel portion. In particular, the gate structure may surround the channel portion, in other words, forming a gate-all-around (GAA) structure. The lower source-drain portion and the upper source-drain portion and the channel portion may intersect with a common vertical plane. The channel portion is adapted (in use of the device) to conduct a vertical flow of charge carriers between the source and drain.

[0008] As used herein, the term "vertical" refers to a direction or orientation (e.g., a direction or orientation of a surface, dimension, or other feature) that is parallel to the normal direction of the substrate (i.e., the main extension plane or its main / upper surface). The term "horizontal" also refers to a direction or orientation that is parallel to the substrate (i.e., its main extension plane or main surface), or equivalently, transverse to the vertical direction.

[0009] For example, a “vertical nanowire” herein means that the nanowire extends highly parallel to the normal of the semiconductor substrate.

[0010] “On” herein means above and in contact with. For example, “depositing a protective layer on a semiconductor substrate” herein means that the protective layer is deposited above and in contact with the semiconductor substrate.

[0011] At the same time, terms such as "bottom", "top", "lower" and "middle", "upper" refer to relative positions as viewed in the vertical direction, and therefore do not imply an absolute orientation of the substrate or device. For example, the terms "bottom portion of the nanowire" and "top portion of the nanowire" refer to relative positions as viewed in the vertical direction, i.e., the "bottom portion" is arranged closer to the semiconductor substrate than the "top portion". In addition, the terms "lower portion of the bottom portion of the vertical nanowire", "middle" portion of the bottom portion of the vertical nanowire and "upper portion of the bottom portion of the vertical nanowire" refer to relative positions as viewed in the vertical direction, i.e., the "lower portion" is arranged closer to the semiconductor substrate than the "middle portion" and "upper portion", and the "middle portion" is arranged closer to the semiconductor substrate than the "upper portion". The terms "lower source-drain portion" and "upper source-drain portion" refer to the relative positions of the source-drain portions as viewed in the vertical direction.

[0012] “Asymmetric vertical nanowire MOSFET” herein means that the nanowire geometry near the metal gate is asymmetric, ie, the lower and upper parts of the bottom portion of the vertical nanowire are asymmetric.

[0013] The step of trimming the shell portion of the upper portion of the bottom portion of the vertical nanowire may include removing the shell portion of the upper portion of the bottom portion of the vertical nanowire, thereby exposing the core portion of the vertical nanowire at the upper portion of the bottom portion of the vertical nanowire. Therefore, an asymmetric vertical nanowire MOSFET can be realized, that is, the lower portion of the bottom portion of the vertical nanowire can have a shell portion, while the upper portion of the bottom portion of the vertical nanowire can have no shell portion or only a small shell portion.

[0014] The steps of removing the shell portion of the middle portion of the bottom portion of the vertical nanowire and trimming the shell portion of the upper portion of the bottom portion of the vertical nanowire can be performed by etching. Etching can help remove the shell portion of the middle portion of the bottom portion of the vertical nanowire and trim the shell portion of the upper portion of the bottom portion of the vertical nanowire. For example, etching can be performed so that the etching rate can be controlled. This in turn can allow for improved control during the steps of removing the shell portion of the middle portion of the bottom portion of the vertical nanowire and trimming the shell portion of the upper portion of the bottom portion of the vertical nanowire.

[0015] The steps of removing the shell portion of the middle portion of the bottom portion of the vertical nanowire and trimming the shell portion of the upper portion of the bottom portion of the vertical nanowire can be performed simultaneously. Therefore, it can be helpful to manufacture an asymmetric vertical nanowire MOSFET. For example, the number of processing steps for manufacturing an asymmetric vertical nanowire MOSFET can be reduced. "Simultaneously" here means that the steps of removing the shell portion of the middle portion of the bottom portion of the vertical nanowire and trimming the shell portion of the upper portion of the bottom portion of the vertical nanowire are completed simultaneously in the same process.

[0016] The method may further include masking an upper portion of the bottom portion of the vertical nanowire before removing the shell portion of the middle portion of the bottom portion of the vertical nanowire. Thus, during the step of removing the shell portion of the middle portion of the bottom portion of the vertical nanowire, the upper portion of the bottom portion of the vertical nanowire may be protected. This, in turn, may provide improved control over the fabrication of the asymmetric vertical nanowire MOSFET.

[0017] Before the step of trimming the shell portion of the upper portion of the bottom portion of the vertical nanowire, a step of depositing a metal gate on the spacer layer and around the middle portion of the bottom portion of the vertical nanowire may be performed. Therefore, during the step of trimming the shell portion of the upper portion of the bottom portion of the vertical nanowire, the metal gate may protect the middle portion of the bottom portion of the vertical nanowire. In other words, during the step of trimming the shell portion of the upper portion of the bottom portion of the vertical nanowire, the metal gate may mask the middle portion of the bottom portion of the vertical nanowire.

[0018] The method may further include exposing the upper portion of the bottom portion of the vertical nanowire before the step of trimming the shell portion of the upper portion of the bottom portion of the vertical nanowire. Thus, the exposing may allow access to the upper portion of the bottom portion of the vertical nanowire before the step of trimming the shell portion of the upper portion of the bottom portion of the vertical nanowire.

[0019] The core portion of the vertical nanowire can be formed of InAs, InGaAs, or a combination thereof. The core portion of the vertical nanowire can be formed of a binary material, a ternary material, or a combination thereof. The binary and ternary materials can be formed of any III-V semiconductor material. The core portion of the vertical nanowire can be doped with an n-type dopant or a p-type dopant.

[0020] The shell of the vertical nanowire can be formed of InGaAs with an n-type dopant dosage of at least 1×10 16 atoms / cm 3 The shell portion of the vertical nanowire can be formed of a binary material, a ternary material, or a combination thereof. The binary material and the ternary material can be formed of any III-V semiconductor material. The shell portion of the vertical nanowire can be doped with an n-type dopant or a p-type dopant. The dosage of the dopant can be in the range of 1×10 16 atoms / cm 3 to 1×10 20 atoms / cm 3 within the range.

[0021] According to another aspect of the present invention, an asymmetric vertical nanowire MOSFET is provided, the asymmetric vertical nanowire MOSFET comprising: at least one vertical nanowire, the at least one vertical nanowire being arranged on a semiconductor substrate, wherein the at least one vertical nanowire comprises a core portion and a shell portion, the shell portion surrounding the core portion along the height of the vertical nanowire; a first spacer layer, the first spacer layer being arranged on the semiconductor substrate and surrounding a lower portion of a bottom portion of the vertical nanowire; a metal gate, the metal gate being arranged on the first spacer layer and surrounding a middle portion of the bottom portion of the vertical nanowire, wherein the vertical nanowire The middle portion of the bottom portion of the straight nanowire includes a through recess in the shell portion, which surrounds the core portion; a second spacer layer, which is arranged on the metal gate and surrounds at least the upper portion of the bottom portion of the vertical nanowire, wherein the shell portion of the upper portion of the bottom portion of the vertical nanowire has a reduced thickness compared to the lower portion of the bottom portion of the vertical nanowire; a top contact, which is arranged around the top portion of the vertical nanowire, wherein the shell portion of the top portion of the vertical nanowire has a corresponding thickness compared to the lower portion of the bottom portion of the vertical nanowire; and a lower source-drain portion and an upper source-drain portion.

[0022] This aspect may generally present the same or corresponding advantages as the previous aspect.

[0023] The term "through-recess" in the shell portion of the middle portion of the bottom portion of the vertical nanowire means that there is no shell portion or only a small shell portion at least in a portion of the middle portion of the bottom portion of the vertical nanowire. In other words, at least a portion of the middle portion of the bottom portion of the vertical nanowire does not have any shell portion.

[0024] "Top contact" herein means a contact portion arranged at the top portion of a vertical nanowire. The top contact may be part of an upper source-drain portion. The top contact may be connected to the upper source-drain portion.

[0025] The asymmetric vertical nanowire MOSFET may include a first vertical nanowire having a first diameter and a second vertical nanowire having a second diameter different from the first vertical nanowire. Thus, the asymmetric vertical nanowire MOSFET may operate at different threshold voltages.

[0026] The first vertical nanowire may have a first core portion and a first shell portion, and the second vertical nanowire may have a second core portion and a second shell portion. The first vertical nanowire and the second vertical nanowire may be formed so that the first core portion may have the same diameter as the second core portion and the first shell portion may have a different diameter from the second shell portion. The first vertical nanowire and the second vertical nanowire may be formed so that the first core portion may have a different diameter from the second core portion and the first shell portion may have the same diameter as the second shell portion. The first vertical nanowire and the second vertical nanowire may be formed so that the first core portion may have a different diameter from the second core portion and the first shell portion may have a different diameter from the second shell portion.

[0027] The asymmetric vertical nanowire MOSFET may further include a gate oxide layer disposed between the core portion of the middle portion of the bottom portion of the vertical nanowire and the metal gate. The gate oxide may help modulate the conductance of the asymmetric vertical nanowire MOSFET channel. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and additional objects, features and advantages of the present invention will be better understood from the following illustrative and non-limiting detailed description with reference to the accompanying drawings, in which the same reference numerals will be used for the same elements unless otherwise specified.

[0029] Figure 1 to Figure 1 FIG0 schematically illustrates various steps of a method for fabricating an asymmetric vertical nanowire MOSFET on a semiconductor substrate. DETAILED DESCRIPTION

[0030] Now combine Figure 1 to Figure 1 0 discloses various methods for fabricating asymmetric vertical nanowire MOSFETs on a semiconductor substrate.

[0031] Figure 1 1 shows a cross-sectional view of a semiconductor substrate 110 including at least one vertical nanowire 125. Figure 1 , the Y-axis represents a vertical direction corresponding to a normal direction with respect to the upper surface of the semiconductor substrate 100. The X-axis represents a first horizontal direction along the semiconductor substrate 100, and the Z-axis represents a second horizontal direction along the semiconductor substrate 100, which is perpendicular to the first horizontal direction X. It should be noted that in the drawings, relative sizes of elements shown (such as the height, width, or thickness of the elements) are merely schematic, and for the purpose of clarity of explanation, these sizes may differ from physical structures.

[0032] The semiconductor substrate 110 can be any conventional substrate 110, such as a substrate suitable for MOSFET processing. The substrate 110 can be, for example, a semiconductor substrate, such as a Si substrate, a Ge substrate, or a silicon germanium (SiGe) substrate. Other examples include a silicon-on-insulator (SOI) substrate, a GeOI substrate, or a SiGeOI substrate. The substrate can include a stack of layers, such as an InAs layer formed on a Si substrate. The InAs layer can be epitaxially grown on the Si substrate. The InAs layer can be epitaxially grown in a manner known in the art. The InAs layer can be formed using any suitable conventional technique, such as chemical vapor deposition (CVD), metal organic CVD (MOCVD), molecular beam epitaxy (MBE), or vapor phase epitaxy (VPE). The typical thickness of the InAs layer can be in the range of 100 nm to 500 nm.

[0033] exist Figure 1 and subsequent figures, one vertical nanowire 125 is shown. However, it should be noted that the semiconductor substrate 110 may include any number of additional vertical nanowires 125 outside the illustrated area.

[0034] Figure 1The vertical nanowires 125 shown extend parallel to the Y direction. For example, a typical height of the vertical nanowires 125 can be in the range of 300 nm to 600 nm. Shorter heights in the range of 50 nm to 300 nm are also contemplated. The diameter of the vertical nanowires 125 (i.e., the diameter along the X-axis or Z-axis) can be in the range of 15 nm to 100 nm. Diameters of 5 nm to 15 nm are also contemplated. The vertical nanowires 125 can be formed in a manner known per se in the art (e.g., by etching an epitaxial semiconductor layer or layer stack formed on the semiconductor substrate 110). In the case where the InAs layer is formed on a Si substrate, the vertical nanowires 125 can be formed by etching the InAs layer formed on the Si substrate. The vertical nanowires 125 can be epitaxially grown on the semiconductor substrate 110 in a manner known per se in the art. For example, catalyst nanoparticles such as Au nanoparticles can be used to grow the vertical nanowires 125. The vertical nanowires 125 may be formed using any suitable conventional technique, such as CVD, MOCVD, MBE, or VPE.

[0035] Figure 1 The vertical nanowire 125 is shown to include a core portion 120 and a shell portion 130, which surrounds the core portion 120 along the height of the vertical nanowire. The core portion 120 of the vertical nanowire 125 can be formed of InAs, InGaAs, or a combination thereof. The core portion 120 of the vertical nanowire 125 can include a stack of layers along the vertical direction (i.e., along the height of the vertical nanowire 125). In other words, the core portion 120 of the vertical nanowire 125 can include an axial heterostructure. The core portion 120 of the vertical nanowire 125 can include a stack of layers perpendicular to the vertical direction (i.e., along the width of the vertical nanowire 125). In other words, the core portion 120 of the vertical nanowire 125 can include a radial heterostructure. Any layer of the stack of layers can be formed of a binary material or a ternary material, which is formed of a III-V semiconductor material. The core portion 120 of the vertical nanowire 125 can be doped with an n-type dopant or a p-type dopant. The diameter of the core portion 120 of the vertical nanowire 125 (ie, the diameter along the X-axis or the Z-axis) may be in the range of 5 nm to 80 nm.

[0036] The shell portion 130 of the vertical nanowire 125 may be formed of InGaAs. The shell portion 130 of the vertical nanowire 125 may include a stack of layers. Any layer of the stack of layers may be formed of a binary material or a ternary material formed of a III-V semiconductor material. The shell portion 130 of the vertical nanowire 125 may be doped with an n-type dopant or a p-type dopant. In the case of an n-type dopant, the n-type dopant dosage of the shell portion 130 of the vertical nanowire 125 may be in the range of 1×1016 to 1×10 20 atoms / cm 3 The n-type dopant dosage of the shell portion 130 of the vertical nanowire 125 may be at least 1×10 16 atoms / cm 3 The diameter of the shell portion 130 of the vertical nanowire 125 (ie, the diameter along the X-axis or the Z-axis) may be in the range of 3 nm to 20 nm.

[0037] The core portion 120 and the shell portion 130 of the vertical nanowire 125 can be formed in a manner known per se in the art. For example, in the case of epitaxial growth of the vertical nanowire 125, the growth of the core portion 120 and the shell portion 130 of the vertical nanowire 125 can be performed by selecting appropriate precursors that control epitaxial growth parameters (e.g., flow rate and temperature).

[0038] Furthermore, the semiconductor substrate 110 may include a first vertical nanowire 125 having a first diameter and a second vertical nanowire 125 having a second diameter different from the first vertical nanowire. In the case where the vertical nanowire 125 is epitaxially grown, the first and second vertical nanowires may be formed, for example, using catalyst nanoparticles having different diameters.

[0039] Now refer to Figure 2 The method then proceeds to depositing a protective layer 140 on the semiconductor substrate and around the bottom portion 125b of the vertical nanowire 125. The protective layer 140 can be formed from one or more organic or inorganic layers (such as hydrogen silsesquioxane (HSQ), SiNx, SiO2, BCB, and photoresist). The protective layer 140 can be deposited in a manner known in the art (such as spin coating). The typical thickness of the protective layer 140 can be in the range of 10 nm to 100 nm. Therefore, the typical height of the bottom portion 125b of the vertical nanowire 125 can be in the range of 10 nm to 100 nm.

[0040] Now refer to Figure 3 The method continues by forming a top contact 150 around the remaining portion 120 t of the vertical nanowire 125 not covered by the protective layer 140 . Figure 3A top contact 150 is shown formed on the top portion 125t of the vertical nanowire 125 that is not covered by the protective layer 140. The top contact 150 can be formed of any metal such as W, TiN and Ni. The top contact 150 may include a stack of one or more layers. The top contact 150 can be formed in a manner known per se in the art, such as sputtering and atomic layer deposition (ALD). The typical thickness of the top contact 150 along the X-axis or Z-axis can be in the range of 3nm to 50nm. For example, the top contact 150 can be formed by sputtering 20nm of W, atomic layer deposition (ALD) 5nm of TiN or 5nm of Ni.

[0041] Now refer to Figure 4 , the method proceeds to removing the protective layer 140. The step of removing the protective layer 140 can be completed by wet etching of the protective layer 140. The wet etching of the protective layer 140 can be performed using hydrofluoric acid (HF). The step of removing the protective layer 140 from the bottom portion 125b of the vertical nanowire 125 can be continued until the bottom portion 125b of the vertical nanowire 125 is exposed. Figure 4 The vertical nanowire 125 is shown after a step of removing the protection layer 140 from the bottom portion 125 b of the vertical nanowire 125 . Figure 4 It is shown that the bottom portion 125b of the vertical nanowire 125 is exposed.

[0042] Now refer to Figure 5 The method continues by depositing a spacer layer 160 on the semiconductor substrate 110 . Figure 5 A spacer layer 160 is shown deposited around the lower portion 1201 of the bottom portion 125b of the vertical nanowire 125 . Figure 5 It is further shown that the thickness of the spacer layer 160 is less than the thickness of the protection layer 140 . Figure 5 The remaining portion of the bottom portion 125b of the vertical nanowire 125 not covered by the spacer layer 160 is further shown to include a middle portion 125i and an upper portion 125u. The spacer layer 160 can be formed of an inorganic material such as SiO2 or an organic material such as BCB. The spacer layer 160 can be deposited in a manner known in the art, such as plasma-enhanced chemical vapor deposition (PECVD), CVD, spin coating, or ALD. A typical thickness of the spacer layer 160 can be in the range of 5 nm to 150 nm.

[0043] Now refer to Figure 6 The method continues by removing the outer shell portion of the middle portion 125i of the bottom portion 125b of the vertical nanowire 125. Figure 6It is shown that after the step of removing the shell portion of the middle portion 125i of the bottom portion 125b of the vertical nanowire 125, the core portion of the middle portion 125i of the bottom portion 125b of the vertical nanowire 125 has been exposed. The step of removing the shell portion of the middle portion 125i of the bottom portion 125b of the vertical nanowire 125 can be performed by etching. Etching can be performed in a manner known in the art, such as cyclic etching using, for example, hydrochloric acid (HCl) and oxygen treatment. Etching can be performed in situ or by transferring samples between different devices. The chemical substance can further be selected to be selective or non-selective with respect to the core and shell materials.

[0044] Before the step of removing the outer shell portion of the middle portion 125i of the bottom portion 125b of the vertical nanowire 125, the upper portion 125u of the bottom portion 125b of the vertical nanowire 125 may be masked. The masking of the upper portion 125u of the bottom portion 125b of the vertical nanowire 125 may be performed in a manner known per se in the art.

[0045] Now refer to Figure 7a , the method proceeds to trimming the outer shell portion of the upper portion 125u of the bottom portion 125b of the vertical nanowire 125 . Figure 7a It is shown that the thickness of the shell portion at the upper portion 125u of the bottom portion 125b of the vertical nanowire 125 has been reduced. Figure 7a The shell thickness at the upper portion 125u of the bottom portion 125b of the vertical nanowire 125 is shown to be less than the shell thickness at the lower portion 120l of the bottom portion 125b of the vertical nanowire 125, that is, the shell thicknesses at the upper portion 125u and the lower portion 120l of the bottom portion 125b of the vertical nanowire 125 are asymmetric. In the case where the upper portion 125u of the bottom portion 125b of the vertical nanowire 125 has been masked, before removing the shell portion of the middle portion 125i of the bottom portion 125b of the vertical nanowire 125, the method may further include exposing the upper portion 125u of the bottom portion 125b of the vertical nanowire 125 before trimming the shell portion of the upper portion 125u of the bottom portion 125b of the vertical nanowire 125.

[0046] The step of trimming the shell portion of the upper portion 125u of the bottom portion 125b of the vertical nanowire 125 can be performed by etching. The trimming step can be performed in a manner similar to the step of removing the shell portion of the middle portion 125i of the bottom portion 125b of the vertical nanowire 125. The trimming step can be controlled so that the desired thickness of the shell portion of the upper portion 125u of the bottom portion 125b of the vertical nanowire 125 can be removed. The trimming step can be controlled, for example, by controlling the etching time. After the trimming step, the thickness of the shell portion of the upper portion 125u of the bottom portion 125b of the vertical nanowire 125 can be reduced by 30%-80%. Before the step of trimming the shell portion of the upper portion 125u of the bottom portion 125b of the vertical nanowire 125, the middle portion 125i of the bottom portion 125b of the vertical nanowire 125 can be masked. The masking of the middle portion 125 i of the bottom portion 125 b of the vertical nanowire 125 may be performed by repeating the above process steps using a new mask having a different thickness than the mask used to mask the upper portion 125 u of the bottom portion 125 b of the vertical nanowire 125 .

[0047] Now refer to Figure 7b , the step of trimming the outer shell portion of the upper portion 125 u of the bottom portion 125 b of the vertical nanowire 125 may include removing the outer shell portion of the upper portion 125 u of the bottom portion 125 b of the vertical nanowire 125 . Figure 7b It is shown that the core portion of the vertical nanowire 125 has been exposed at the upper portion 125u of the bottom portion 125b of the vertical nanowire 125. In other words, the upper portion 125u and the lower portion 125l of the bottom portion 125b of the vertical nanowire 125 have become asymmetric.

[0048] Still refer to Figure 7b , the step of removing the shell portion of the middle portion 125i of the bottom portion 125b of the vertical nanowire 125 and the step of removing the shell portion of the upper portion 125u of the bottom portion 125b of the vertical nanowire 125 can be performed by etching. The step of removing the shell portion of the middle portion 125i of the bottom portion 125b of the vertical nanowire 125 and the step of trimming the shell portion of the upper portion 125u of the bottom portion 125b of the vertical nanowire 125 can be performed simultaneously. For example, the step of removing the shell portion of the middle portion 125i of the bottom portion 125b of the vertical nanowire 125 and the step of trimming the shell portion of the upper portion 125u of the bottom portion 125b of the vertical nanowire 125 can be performed in the same etching process using the same etchant.

[0049] The method may include forming a gate oxide layer around the core portion of the middle portion 125i of the bottom portion 125b of the vertical nanowire 125. The gate oxide layer may be made of at least one high-k dielectric material (such as HfO x ). The gate oxide layer can be formed in a manner known in the art, such as ALD. The typical thickness of the gate oxide layer can be in the range of 1 nm to 6 nm. An example of a gate oxide layer can be Al2O3 / HfO2, with a typical thickness of 1 nm Al2O3.

[0050] Now refer to Figure 8a and Figure 8b The method continues by depositing a metal gate 170 on the spacer layer 160 and around the middle portion 125i of the bottom portion 125b of the vertical nanowire 125, that is, depositing the metal gate 170 on the spacer layer 160 and around the gate oxide layer (if present). The metal gate 170 can be deposited in a manner known in the art, such as sputtering and ALD. The metal gate 170 can be formed of at least one metal, such as TiN and W. The typical thickness of the metal gate 170 can be in the range of 5 nm to 100 nm.

[0051] refer to Figure 8a Before the step of trimming the outer shell of the upper portion 125u of the bottom portion 125b of the vertical nanowire 125, the step of depositing the metal gate 170 on the spacer layer 160 and around the middle portion 125i of the bottom portion 125b of the vertical nanowire 125 may be performed. In other words, after the step of depositing the gate oxide layer and the metal gate 170 on the spacer layer 160 and around the middle portion 125i of the bottom portion 125b of the vertical nanowire 125, the step of trimming the outer shell of the upper portion 125u of the bottom portion 125b of the vertical nanowire 125 may be performed. In this way, during the step of trimming the outer shell of the upper portion 125u of the bottom portion 125b of the vertical nanowire 125, the middle portion 125i of the bottom portion 125b of the vertical nanowire 125 may be protected by the metal gate 170.

[0052] Now refer to Figure 9a and Figure 9b, the method may continue by depositing another spacer layer 180 (e.g., a second spacer layer 180) on the metal gate 170 and around at least the upper portion 125u of the bottom portion 125b of the vertical nanowire 125. The second spacer layer 180 may be deposited in a manner similar to the spacer layer 160 (i.e., the first spacer layer 160). The thickness of the second spacer layer 180 may be in the range of 20nm to 200nm. The second spacer layer 180 may be deposited such that the thickness of the second spacer layer 180 may be similar to the height of the upper portion 125u of the bottom portion 125b of the vertical nanowire 125. The second spacer layer 180 may be deposited such that the thickness of the second spacer layer 180 may be greater than the height of the upper portion 125u of the bottom portion 125b of the vertical nanowire 125.

[0053] Now refer to Figure 10a and Figure 10b The method continues by forming a lower source-drain portion 110 and an upper source-drain portion 190. The lower source-drain portion and the upper source-drain portion may be included in a lower source-drain contact and an upper source-drain contact, respectively. Figure 10a and Figure 10b An example of an upper source-drain portion 190 is shown, i.e., a metallic upper source-drain portion 190 has been deposited on the second spacer layer 180 and around the top portion 125t of the vertical nanowire 125. The upper source-drain portion 190 can have a thickness similar to the height of the top portion 125t of the bottom portion 125b of the vertical nanowire 125. The upper source-drain portion 190 can have a thickness different from the height of the top portion 125t of the bottom portion 125b of the vertical nanowire 125. The upper source-drain portion 190 can be deposited in a manner known per se in the art, such as sputtering.

[0054] In the case where the semiconductor substrate 110 includes a highly doped portion (eg, a highly doped InAs layer formed on a Si substrate), the highly doped portion may be formed as the lower source and drain portion. Figure 10a and Figure 10b As shown, the semiconductor substrate 110 serves as the lower source-drain portion 110. The lower source-drain portion can be formed in a manner known per se in the art. For example, the lower source-drain portion can be formed by patterning a highly doped portion using, for example, electron beam lithography.

[0055] Still refer to Figure 10a and Figure 10b , these figures schematically illustrate two examples of asymmetric vertical nanowire MOSFETs 100 . Figure 10a and Figure 10b Two asymmetric vertical nanowire MOSFETs 100 are shown, which include at least one vertical nanowire 125 arranged on a semiconductor substrate 110 . Figure 10a and Figure 10b It is further shown that at least one vertical nanowire 125 includes a core portion 120 and a shell portion 130 . Figure 10a and Figure 10b The shell portion 130 is shown surrounding the core portion 120 along the height of the vertical nanowires 125 . Figure 10a and Figure 10b Further shown is a first spacer layer 160 disposed on the semiconductor substrate 110 and surrounding a lower portion 125 l of the bottom portion 125 b of the vertical nanowire 125 . Figure 10a and Figure 10b Further shown is a metal gate 170 disposed on the first spacer layer 160 and surrounding the middle portion 125 i of the bottom portion 125 b of the vertical nanowire 125 . Figure 10a and Figure 10b The middle portion 125 i of the bottom portion 125 b of the vertical nanowire 125 is shown to include a through recess in the outer shell portion such that the recess surrounds the core portion 120 .

[0056] Figure 10a and Figure 10b A second spacer layer 180 is shown disposed on the metal gate 170 and surrounding at least an upper portion 125 u of the bottom portion 125 b of the vertical nanowire 125 . Figure 10a and Figure 10b It is further shown that the shell portion of the upper portion 125 u of the bottom portion 125 b of the vertical nanowire 125 has a reduced thickness compared to the lower portion 125 l of the bottom portion 125 b of the vertical nanowire 125 . Figure 10a and Figure 10b Further shown is a top contact 150 disposed around the top portion 125t of the vertical nanowire 125 . Figure 10a and Figure 10b It is shown that the outer shell portion of the top portion 125t of the vertical nanowire 125 has a corresponding thickness compared to the lower portion 125l of the bottom portion 125b of the vertical nanowire 125. Figure 10a and Figure 10b Further shown are a lower source drain portion 110 and an upper source drain portion 190 . Figure 10a and Figure 10b The asymmetric vertical nanowire MOSFET 100 presented in Figure 1 illustrates a transistor having an asymmetric shell structure around the gate metal 170. The asymmetric shell structure provides low access resistance on one side of the metal gate due to the presence of the shell portion 130. On the other side of the metal gate, the asymmetric shell structure provides low capacitance due to the separation of the shell portion 130 from the metal gate 170. The combination of these two properties offers advantages in the design of high-frequency transistors, including their gain characteristics.

[0057] In the foregoing, the inventive concept has been described primarily with reference to a limited number of examples. However, as those skilled in the art will readily appreciate, within the scope of the inventive concept as defined by the appended claims, other examples than the examples disclosed above are equally possible. Those skilled in the art will recognize that the present invention is by no means limited to the preferred embodiments described above. On the contrary, many modifications and variations are possible within the scope of the appended claims.

[0058] For example, after removing the shell portion of the middle portion of the bottom portion of the vertical nanowire, a portion of the core portion of the middle portion of the bottom portion of the vertical nanowire can be removed. For another example, after removing the shell portion of the upper portion of the bottom portion of the vertical nanowire, a portion of the core portion of the upper portion of the bottom portion of the vertical nanowire can be removed. In addition, variations of the disclosed embodiments are understood and implemented by skilled artisans in practicing the claimed invention by studying the drawings, the disclosure, and the appended claims.

Claims

1. A method for fabricating an asymmetric vertical nanowire MOSFET on a semiconductor substrate comprising at least one vertical nanowire, wherein: The at least one vertical nanowire comprises a core portion and a shell portion, the shell portion surrounding the core portion along the height of the vertical nanowire, the method comprising: depositing a protective layer on the semiconductor substrate and around a bottom portion of the vertical nanowire, forming a top contact around the remaining portion of the vertical nanowire not covered by the protective layer, The protective layer is removed by etching. depositing a spacer layer on the semiconductor substrate and around a lower portion of the bottom portion of the vertical nanowire, wherein a thickness of the spacer layer is less than a thickness of the protective layer, and wherein a remaining portion of the bottom portion of the vertical nanowire not covered by the spacer layer includes a middle portion and an upper portion, removing a shell portion of a middle portion of a bottom portion of the vertical nanowire, thereby exposing a core portion of the vertical nanowire at the middle portion of the bottom portion of the vertical nanowire, Before the step of removing the outer shell portion of the middle portion of the bottom portion of the vertical nanowire, masking the upper portion of the bottom portion of the vertical nanowire, trimming the shell portion of the upper portion of the bottom portion of the vertical nanowire to reduce the thickness of the shell portion of the upper portion of the bottom portion of the vertical nanowire, or removing the shell portion of the upper portion of the bottom portion of the vertical nanowire, depositing a metal gate on the spacer layer and only around the middle portion of the bottom portion of the vertical nanowire, and A lower source-drain portion and an upper source-drain portion are formed.

2. The method according to claim 1, wherein The step of trimming the shell portion of the upper portion of the bottom portion of the vertical nanowire includes removing the shell portion of the upper portion of the bottom portion of the vertical nanowire, thereby exposing the core portion of the vertical nanowire at the upper portion of the bottom portion of the vertical nanowire.

3. The method according to claim 1, wherein The step of removing the shell portion of the middle portion of the bottom portion of the vertical nanowire and the step of trimming the shell portion of the upper portion of the bottom portion of the vertical nanowire are performed by etching.

4. The method according to claim 1, wherein The step of removing the shell portion of the middle portion of the bottom portion of the vertical nanowire and the step of trimming the shell portion of the upper portion of the bottom portion of the vertical nanowire are performed simultaneously.

5. The method according to claim 1, wherein Before the step of trimming the outer shell portion of the upper portion of the bottom portion of the vertical nanowire, the step of depositing the metal gate on the spacer layer and around the middle portion of the bottom portion of the vertical nanowire is performed.

6. The method according to claim 5, further comprising: Prior to the step of trimming the outer shell portion of the upper portion of the bottom portion of the vertical nanowire, the upper portion of the bottom portion of the vertical nanowire is exposed.

7. The method according to claim 6, wherein: The core portion of the vertical nanowire is formed of InAs, InGaAs or a combination thereof.

8. The method according to claim 1, wherein The shell of the vertical nanowire is formed of InGaAs, and the n-type dopant dosage is at least 1×10 16 atoms / cm 3 .

9. An asymmetric vertical nanowire MOSFET, comprising: At least one vertical nanowire is arranged on a semiconductor substrate, wherein the at least one vertical nanowire comprises a core portion and a shell portion, the shell portion surrounding the core portion along the height of the vertical nanowire, a first spacer layer disposed on the semiconductor substrate and surrounding a lower portion of the bottom portion of the vertical nanowire, a metal gate disposed on the first spacer layer and surrounding a middle portion of a bottom portion of the vertical nanowire, wherein the middle portion of the bottom portion of the vertical nanowire comprises a through recess in the shell portion, the recess surrounding the core portion, a second spacer layer disposed on the metal gate and surrounding at least an upper portion of the bottom portion of the vertical nanowire, wherein the upper portion of the bottom portion of the vertical nanowire has a shell portion having a reduced thickness compared to a lower portion of the bottom portion of the vertical nanowire or does not have a shell portion, wherein the metal gate and the upper portion of the bottom portion of the vertical nanowire are disposed such that at least a portion of the upper portion of the bottom portion of the vertical nanowire is free of the metal gate, a top contact disposed around a top portion of the vertical nanowire, wherein a shell portion of the top portion of the vertical nanowire has a corresponding thickness compared to a lower portion of the bottom portion of the vertical nanowire, and a lower source-drain portion and an upper source-drain portion.

10. The asymmetric vertical nanowire MOSFET according to claim 9, wherein: The asymmetric vertical nanowire MOSFET includes a first vertical nanowire having a first diameter and a second vertical nanowire having a second diameter different from the first vertical nanowire. 11 . The asymmetric vertical nanowire MOSFET according to claim 9 , further comprising a gate oxide layer disposed between a core portion of a middle portion of a bottom portion of the vertical nanowire and the metal gate.

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