Circuits and related chips
The circuit design with separate scan trigger loops for loading and capturing phases simplifies scan testing in circuits with memories, addressing complexity issues and reducing area requirements.
Patent Information
- Application Number
- CN202011208632.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2020-11-03
- Publication Date
- 2024-12-27
- Estimated Expiration
- 2040-11-03
AI Technical Summary
Implementing scan tests in circuits with multiple memories is challenging due to the increased complexity and difficulty in designing circuits that include memory parts, especially when the circuit clock is high.
A circuit design that includes scan triggers with specific loading and capturing phases, eliminating the need for a bypass circuit between memory stages, and utilizing multiplexers and NOT gates to create separate loops for data transmission during capture phases, reducing loop distances and circuit area.
This design simplifies the implementation of scan tests in circuits with memories by reducing loop complexity and circuit area, making it easier to meet operating frequencies and improve test coverage.
Smart Images
Figure CN114441930B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a circuit, and more particularly to a circuit and a related chip coupled to a memory and not using a bypass circuit between the previous and next stages of the memory. Background Art
[0002] When a circuit containing memory is scanned, its scope does not include the memory part. In order to make the circuits before and after the memory more completely included in the scan test scope, special attention needs to be paid to the design. However, when the circuit clock is high and there are many memories in the circuit, the difficulty of implementing the above design will be greatly increased. Summary of the invention
[0003] The present invention discloses a circuit coupled to a memory, the circuit comprising: a plurality of scan triggers, each having a data input terminal, a scan input terminal, a clock input terminal, a scan enable terminal and an output terminal, wherein when the scan enable terminal receives a first potential, the data received by the data input terminal is output from the output terminal according to the first clock received by the clock input terminal, and when the scan enable terminal receives a second potential, the data received by the scan input terminal is output from the output terminal according to the second clock received by the clock input terminal, and the plurality of scan triggers comprises: a first scan trigger, which is a scan trigger at a previous stage of the input terminal of the memory, and whose output terminal is coupled to the input terminal of the memory; and a second scan trigger, which is an output terminal of the memory. The circuit comprises a scan trigger of a subsequent stage of the first scan trigger, whose input terminal is coupled to the output terminal of the memory; wherein the circuit has a loading phase and a capturing phase in the scanning mode, in the loading phase, the scan enable terminal of each of the plurality of scan triggers receives the second potential, and in the capturing phase, the scan enable terminal of each of the plurality of scan triggers receives the first potential; in the loading phase, the data outputted by the output terminal of the first scan trigger reaches the scan input terminal of the second scan trigger through the loading path; and in the capturing phase, the data outputted by the output terminal of the first scan trigger returns to the data input terminal of the first scan trigger through the first loop, and the first loop does not pass through the second scan trigger.
[0004] The invention discloses a chip, comprising the above circuit and the memory.
[0005] The above circuits and related chips can reduce the difficulty in implementing circuits containing memory. BRIEF DESCRIPTION OF THE DRAWINGS
[0006] Figure 1 This is a comparative example of the present invention.
[0007] Figure 2 for Figure 1 Schematic diagram of signal transmission of the circuit in the loading phase of scan mode.
[0008] Figure 3 for Figure 1 Schematic diagram of signal transmission of the circuit in the capture phase of scanning mode.
[0009] Figure 4 FIG. 1 is a schematic diagram of a first embodiment of a circuit of the present invention.
[0010] Figure 5 for Figure 4 Schematic diagram of signal transmission of the circuit in the loading phase of scan mode.
[0011] Figure 6 for Figure 4 Schematic diagram of signal transmission of the circuit in the capture phase of scanning mode.
[0012] Figure 7 FIG. 1 is a schematic diagram of a second embodiment of a circuit of the present invention.
[0013] Figure 8 for Figure 7 Schematic diagram of signal transmission of the circuit in the loading phase of scan mode.
[0014] Fig. 9 for Figure 7 Schematic diagram of signal transmission of the circuit in the capture phase of scanning mode. DETAILED DESCRIPTION
[0015] Figure 1 The circuit 100 includes a memory 102. The multiple input terminals of the memory 102 may include multiple data input terminals, multiple address input terminals, and multiple control input terminals. The input terminal I of the memory 102 referred to in the present invention may be any one of them. The multiple output terminals of the memory 102 may include multiple data output terminals. The output terminal O of the memory 102 referred to in the present invention may be any one of them. It should be noted that the circuit 100 can be applied to all input terminals and output terminals of the memory 102. However, for the sake of simplicity, it is not fully described in FIG. Figure 1 .
[0016] The circuit 100 includes scan triggers 104, 106, 114, 118 and 119, which have a data input terminal D, a scan input terminal SI, a clock input terminal CLK, a scan enable terminal SE and an output terminal Q, wherein when the scan enable terminal SE receives a low potential, the data received by the data input terminal D is output from the output terminal Q according to the first clock received by the clock input terminal CLK; when the scan enable terminal SE receives a high potential, the data received by the scan input terminal SI is output from the output terminal Q according to the second clock received by the clock input terminal CLK. All scan triggers in the present invention can be implemented as follows Figure 1As shown in 104, it includes a multiplexer 122 and a general trigger 124, but the present invention is not limited thereto.
[0017] The circuit 100 further includes a built-in self-test circuit 120 for generating a test signal, which is transmitted to the input terminal I of the memory 102 via the multiplexer 108; the output signal of the output terminal O of the memory 102 is returned to the built-in self-test circuit 120 via the multiplexer 116 and the scan trigger 118, and is compared with the preset result to complete the self-test operation of the memory 102. Specifically, the circuit 100 can be operated in the self-test operation or the general operation in the non-scanning mode. In the self-test operation, the control signal BM transmits the output of the scan trigger 106 of the output stage of the built-in self-test circuit 120 to the memory 102; and in the general operation, BM transmits the output of the scan trigger 104 to the memory 102.
[0018] Scan triggers 104 and 106 are the previous scan triggers of the input terminal I of the memory 102; scan triggers 118 and 119 are the next scan triggers of the output terminal O of the memory 102. Since the memory 102 is not included in the scope of the scan test, in the scan mode, the bypass circuit 110 is used in this comparative embodiment to connect the previous scan trigger of the input terminal I of the memory 102 and the next scan trigger of the output terminal O. That is, the bypass circuit 110 is only used in the scan mode.
[0019] The scan mode may have three phases: a load phase, a capture phase, and a load-out phase. In the scan mode, when the control signal SM is at a high level, the multiplexer 116 is controlled to pass the output of the scan flip-flop 114 to the scan flip-flops 118 and 119 . Figure 2 FIG. 1 is a schematic diagram of signal transmission of the circuit 100 in the loading stage. The scan enable terminals SE of the scan flip-flops 104, 106, 114, 118 and 119 are set to a high potential, so that when the test signal is fed from the test machine outside the chip where the circuit 100 is located, it is delivered to the scan flip-flops 104, 106, 114, 118 and 119 via the loading path (thicker line). It should be noted that Figure 2 The serial connection in FIG. 1 is for illustration only. In practice, the order of the scan triggers that the load path passes through may be different, or the scan triggers 104 , 106 , 114 , 118 , and 119 may belong to different load paths.
[0020] Figure 3 FIG. 1 is a schematic diagram of signal transmission of the circuit 100 in the capture phase. The scan enable terminals SE of the scan triggers 104, 106, 114, 118 and 119 are set to a low potential, so that the test signals loaded into the scan triggers 104, 106, 114, 118 and 119 are transmitted along the capture phase. Figure 3 The thicker line in the figure is continuously transmitted to the next level scan trigger. Specifically, when the control signal BM is at a high level, the data outputted from the output terminal Q of the scan trigger 106 is returned to the built-in self-test circuit 120 through the multiplexer 108, the scan trigger 114, the multiplexer 116 and the scan trigger 118 to form a loop; when the control signal BM is at a low level, the data outputted from the output terminal Q of the scan trigger 104 is returned to the built-in self-test circuit 120 through the multiplexer 108, the scan trigger 114, the multiplexer 116 and the scan trigger 118 to form a loop. After a preset period of time, the circuit 100 enters the load-out phase (same as the load-out phase). Figure 2 ), the signals in the scan triggers 104, 106, 114, 118 and 119 are fed to the test machine to be compared with the preset results.
[0021] In order to reflect the actual situation, the scan triggers 104, 106, 114, 118 and 119 work at the first clock in the capture phase, which is the same as the clock used in the general operation. In the load phase and the load-out phase, the scan triggers 104, 106, 114, 118 and 119 work at the second clock, which is supplied by the test machine. Limited by the speed of the machine, the frequency of the second clock is much lower than the first clock. Since the area of the memory 102 in the layout diagram is often not small, the bypass circuit 110 connecting the front and rear stages of the memory 102 has to span a considerable distance, while meeting the operating frequency of the capture phase, which is difficult to layout the wiring.
[0022] Figure 4 Schematic diagram of the first embodiment of the circuit of the present invention. The circuit 400 is arranged on a chip, and has substantially the same structure and operation as the circuit 100, except that the circuit 400 does not include a bypass circuit connecting the previous scan trigger at the input terminal I of the memory 102 and the next scan trigger at the output terminal O, and the built-in self-test circuit 420 and the circuit connection method in the circuit 400 are slightly adjusted. Figure 5 is a schematic diagram of signal transmission of the circuit 400 in the loading stage, and its loading path can be Figure 2 The same or similar reason is as mentioned above, the operating frequency of the loading stage is lower, which will not cause difficulty in winding. The biggest difference caused by removing the bypass circuit is in the capture stage.
[0023] Figure 6Schematic diagram of signal transmission of the circuit 400 in the capture phase. Specifically, in the capture phase of the circuit 400, when the control signal BM is at a high level, the data outputted from the output terminal Q of the scan trigger 106 returns to the data input terminal D of the scan trigger 106 along the multiplexer 108 and the multiplexer 406, forming a loop that does not pass through the scan trigger 118; when the control signal BM is at a low level, the data outputted from the output terminal Q of the scan trigger 104 arrives at the data input terminal D of the scan trigger 106 along the multiplexer 108 and the multiplexer 406, forming a loop that does not pass through the scan trigger 118. The data outputted from the output terminal Q of the scan trigger 118 returns to the data input terminal D of the scan trigger 118 along the NOT gate 408 and the multiplexer 116, forming a loop that does not pass through the scan trigger 104 or 106; the data outputted from the output terminal Q of the scan trigger 119 will not pass through the loop of the scan trigger 104 or 106 either. That is to say, the previous stage scan trigger 104, 106 of the input terminal I and the next stage scan trigger 118, 119 of the output terminal O are in different loops, data are not transmitted to each other, and the distance traversed by the loop of the circuit 400 in the capture stage is much shorter than that of the loop of the circuit 100 in the capture stage, thereby reducing the complexity of the winding and making the area of the circuit 400 smaller than that of the circuit 100.
[0024] The purpose of the NOT gate 408 is to change the signal in the capture phase to increase the test coverage, and it can also be replaced by other logic. The implementation of the multiplexer 406 is shown in the figure but is not limited thereto, and includes an AND gate 402 and an OR gate 404, wherein one of the input terminals of the AND gate 402 is coupled to the output terminal of the multiplexer 108, the other input terminal of the AND gate 402 receives the control signal SM, the output terminal of the AND gate 402 is coupled to one of the input terminals of the OR gate 404, and the output terminal of the OR gate 404 is coupled to the data input terminal D of the scan trigger 106. The implementation of the multiplexer 406 can also be applied to the multiplexers 108 and 116.
[0025] Figure 7 Schematic diagram of a second embodiment of the circuit of the present invention. The circuit 700 is disposed on a chip and has substantially the same architecture and operation as the circuit 400, except that the loop in the capture phase is slightly different.
[0026] Figure 8 is a schematic diagram of signal transmission of the circuit 700 in the loading stage, and its loading path can be Figure 2 and Figure 5 Same or similar.
[0027] Fig. 9Schematic diagram of signal transmission of circuit 700 in the capture phase. Specifically, in the capture phase of circuit 700, when the control signal BM is at a high level, the data outputted from the output terminal Q of the scan trigger 106 reaches the data input terminal D of the scan trigger 104 along the multiplexer 108 and the multiplexer 708, forming a loop that does not pass through the scan trigger 118; when the control signal BM is at a low level, the data outputted from the output terminal Q of the scan trigger 104 returns to the data input terminal D of the scan trigger 104 along the multiplexer 108 and the multiplexer 708, forming a loop that does not pass through the scan trigger 118. The loops of the scan triggers 118 and 119 are the same as Figure 6 same.
[0028] The implementation of the multiplexer 708 may be the same as the multiplexer 406 but is not limited thereto, and includes an AND gate 704 and an OR gate 706, wherein one of the input terminals of the AND gate 704 is coupled to the output terminal of the multiplexer 108, the other input terminal of the AND gate 704 receives the control signal SM, the output terminal of the AND gate 704 is coupled to one of the input terminals of the OR gate 706, and the output terminal of the OR gate 706 is coupled to the data input terminal D of the scan flip-flop 104. The implementation of the multiplexer 406 may also be applied to the multiplexers 108 and 116.
[0029] The above description briefly presents the features of certain embodiments of the present invention, so that those skilled in the art can more fully understand the various forms of the content of the present invention. Those skilled in the art should know that they can easily use the content of the present invention as a basis to design or change other processes and structures to achieve the same purpose and / or the same advantages as the embodiments herein. It should be understood that the steps mentioned in the method flow chart of the present invention, except for those whose order is specifically stated, can be adjusted in sequence according to actual needs, and can even be executed simultaneously or partially simultaneously. In addition, the above modules or method steps can be implemented by hardware, software or firmware according to the needs of the designer. Those skilled in the art should know that these equivalent embodiments still belong to the spirit and scope of the content of the present invention, and they can be changed, replaced and improved in various ways without deviating from the spirit and scope of the content of the present invention.
[0030] Description of Reference Numerals
[0031] 100,400,700:Circuit
[0032] 102: Memory
[0033] 104,106,114,118,119: Scan trigger
[0034] 110: Bypass circuit
[0035] 108,116,122,406,708:Multiplexer
[0036] 402,704: AND gate
[0037] 404,706: OR gate
[0038] 408: NOT Gate
[0039] 120,420: Built-in self-test circuit
[0040] SM, BM: control signal
[0041] 124: General trigger
Claims
1. A circuit coupled to a memory, the circuit comprising: A plurality of scan triggers, each having a data input terminal, a scan input terminal, a clock input terminal, a scan enable terminal and an output terminal, wherein when the scan enable terminal receives a first potential, the data received by the data input terminal is output from the output terminal according to the first clock received by the clock input terminal, and when the scan enable terminal receives a second potential, the data received by the scan input terminal is output from the output terminal according to the second clock received by the clock input terminal, and the plurality of scan triggers include: A first scan trigger, which is a previous stage scan trigger of the input terminal of the memory, and whose output terminal is coupled to the input terminal of the memory; and A second scan trigger, which is a subsequent scan trigger of the output terminal of the memory, and has an input terminal coupled to the output terminal of the memory; Wherein, in the scan mode, the circuit has a loading phase and a capturing phase, in which the scanning enable end of each of the plurality of scan triggers receives the second potential in the loading phase, and the scanning enable end of each of the plurality of scan triggers receives the first potential in the capturing phase; In the loading stage, the data outputted from the output terminal of the first scan trigger reaches the scan input terminal of the second scan trigger through a loading path; and In the capture phase, the data outputted from the output terminal of the first scan trigger returns to the data input terminal of the first scan trigger through a first loop, and the first loop does not pass through the second scan trigger.
2. The circuit as described in claim 1, wherein the circuit further has a load-out stage in the scan mode, in which the scan enable terminal of each of the plurality of scan triggers receives the second potential, and the data output by the output terminal of the first scan trigger reaches the scan input terminal of the second scan trigger through a load path.
3. The circuit of claim 2, wherein in the load-in phase and the load-out phase, the data received at the scan input terminal of the first scan flip-flop is shifted from the first scan flip-flop to the second scan flip-flop according to the second clock.
4. The circuit as claimed in claim 3, wherein the data outputted from the output terminal of the second scan flip-flop returns to the data input terminal of the second scan flip-flop through a second loop, and the second loop does not pass through the first scan flip-flop.
5. The circuit of claim 1 , wherein the plurality of scan flip-flops further comprises a third scan flip-flop, and the circuit further comprises: A first multiplexer is used to selectively couple the output terminal of the first scan trigger or the third scan trigger to the input terminal of the memory. 6 . The circuit of claim 5 , wherein the first multiplexer outputs the output of the first scan flip-flop or the output of the third scan flip-flop according to a first control signal.
7. The circuit of claim 6, wherein during the capture phase, the first loop passes through the first multiplexer.
8. The circuit of claim 7, further comprising a built-in self-test circuit for testing the memory, wherein the third scan flip-flop is located in the built-in self-test circuit.
9. The circuit of claim 7, wherein in the load phase, the load path passes through the third scan flip-flop.
10. The circuit of claim 8, wherein in the capture phase, the data outputted from the output terminal of the third scan flip-flop passes through the first multiplexer to reach the data input terminal of the first scan flip-flop.