A hardware compilation optimization method, system and device for intelligent algorithm

Abstract

The present application provides a hardware compilation optimization method, system and device for intelligent algorithms, which belongs to the technical field of embedded computing. The optimization method specifically includes the following steps: receiving the intelligent algorithm model to be compiled, optimizing the model structure, and converting the optimized model representation into a standard format; analyzing the intelligent algorithm model graph structure to obtain a model data flow graph with hardware parameters; quantifying the model parameters based on the model data flow graph to improve the parallel processing capability and hardware resource utilization of the generated hardware structure; generating the hardware computing structure corresponding to the intelligent algorithm based on the model data flow graph combined with the hardware template; generating a hardware bitstream based on the hardware structure generated by the intelligent algorithm hardware compilation system, and inputting the bitstream into the intelligent algorithm running device. Through the processing scheme of the present application, the intelligent algorithm is compiled so that it can be quickly implemented on the hardware platform.

Description

Technical Field

[0001] The present application relates to the field of embedded computing, and in particular to a hardware compilation optimization method, system and device for intelligent algorithms. Background Art

[0002] With the widespread application of data-driven intelligent algorithms in multiple fields, data-intensive algorithm computing power has become the basis for realizing future machine learning and autonomous systems. However, intelligent algorithms have the characteristics of variable models, complex network structures, and fast update speeds. Designing efficient dedicated chips for each algorithm is too costly and will not be reprogrammable, greatly increasing the development cycle and development difficulty. FPGAs contain a large number of gate-level reconfigurable logic units with high reconfiguration time overhead. There are additional development difficulties and costs in directly implementing intelligent algorithms on FPGAs.

[0003] Therefore, how to achieve fast compilation and efficient implementation of intelligent algorithm hardware accelerators is an urgent problem to be solved. Summary of the invention

[0004] In view of this, the present application provides a hardware compilation optimization method, system and device for intelligent algorithms, which solve the problems in the prior art.

[0005] On the one hand, the present application provides a hardware compilation optimization method for intelligent algorithms using the following technical solutions:

[0006] A hardware compilation optimization method for intelligent algorithms includes the following steps:

[0007] Receive the intelligent algorithm model to be compiled, optimize the model structure, and convert the optimized model representation into a standard format;

[0008] Analyze the intelligent algorithm model graph structure to obtain a model data flow graph with hardware parameters;

[0009] quantifying model parameters based on the model data flow graph to improve the parallel processing capability and hardware resource utilization of the generated hardware structure;

[0010] Generate a hardware computing structure corresponding to the intelligent algorithm based on the model data flow diagram combined with the hardware template;

[0011] A hardware bitstream is generated based on the hardware structure generated by the intelligent algorithm hardware compilation system, and the bitstream is input into the intelligent algorithm running device.

[0012] Optionally, the receiving of the intelligent algorithm model to be compiled, optimizing the model structure, and converting the optimized model representation into a standard format comprises the following steps:

[0013] Based on the framework of the intelligent algorithm model, read the graph structure of the model;

[0014] Adopt model structure optimization algorithm to simplify the model structure while ensuring model performance;

[0015] The graph structure serialization standard is adopted to convert the model graph structure into a standard serialization representation.

[0016] Optionally, the method for simplifying the model structure includes algorithms such as model pruning and knowledge distillation, and the model structure is optimized by cyclically performing training and model structure optimization processes.

[0017] Optionally, the step of converting the model graph structure into a standard serialized representation is as follows:

[0018] Divide nodes into four categories: input, output, operation nodes, and parameters;

[0019] The topological structure of the model graph is realized by saving the previous and next connections of the nodes.

[0020] Optionally, analyzing the standard format of the intelligent algorithm model to obtain a model data flow diagram with hardware parameters includes the following steps:

[0021] Establish a model reasoning framework containing hardware parameters;

[0022] The standard format of the intelligent algorithm is analyzed, and a model data flow diagram with hardware parameters is obtained by corresponding node keywords.

[0023] Optionally, the model parameters are quantized based on the model parameter data flow graph using a dynamic quantization method, analyzing the different weights distributed on each layer of the intelligent algorithm model, and quantizing each layer using a different number of bits.

[0024] Optionally, the generating of the hardware computing structure corresponding to the intelligent algorithm according to the model data flow diagram in combination with the hardware template mainly includes the following steps:

[0025] Determine the control parameters for each node operation and allocate them to on-chip memory;

[0026] Establish a shared unit pool containing model-optimized hardware templates;

[0027] An on-chip network is generated by combining the hardware templates and control parameters of node operations in the shared unit pool.

[0028] Create a controller to manage the timing of each operator.

[0029] Optionally, the model-optimized hardware template includes conventional adders, multipliers, and multipliers that utilize bit-level sparsity of model parameters.

[0030] In the second aspect, the present application provides a hardware compilation system for intelligent algorithms using the following technical solutions:

[0031] A hardware compilation system for intelligent algorithms, including a structure optimization module, a serialization module, a model reloading module, a quantization module and a hardware generation module;

[0032] The structural optimization module is used for optimizing the structure of intelligent algorithm models, and performs training-model pruning in a loop on the training data set, while assisting knowledge distillation, to achieve the optimization of the model structure while ensuring the model performance;

[0033] The serialization module is used to convert the structure-optimized intelligent algorithm model graph structure into a serialized representation, and convert models under multiple frameworks into a unified serialized representation;

[0034] The model reloading module is used to convert the unified serialized model representation into a model data flow graph with hardware parameters;

[0035] The quantization module is used to convert the algorithm model parameter accuracy into 8bit or 16bit by a dynamic quantization method, and save the model parameters to run normally in the generated hardware structure;

[0036] The hardware generation module is used to convert the model data flow graph with hardware parameters into a hardware structure and finally generate a hardware bitstream.

[0037] In a third aspect, the present application provides a device for hardware compilation of intelligent algorithms using the following technical solutions:

[0038] A device for hardware compilation of intelligent algorithms, the device comprising a CPU and an FPGA, and the operation process comprises the following steps:

[0039] Inputting a hardware bitstream into the FPGA;

[0040] Inputting relevant software configuration code into the CPU;

[0041] The input data and the quantized model parameters are written into the specified memory.

[0042] In summary, this application includes the following beneficial technical effects:

[0043] By designing a serialization standard representation, it can accept intelligent algorithms under various frameworks. Combined with existing hardware templates, the operators in the intelligent algorithms can be converted into hardware description languages. This has strong adaptability and greatly shortens the development cycle of accelerated hardware.

[0044] By optimizing the algorithm model structure and parameters in various aspects, combined with the use of hardware templates with sparse weight bits, the generated hardware structure can efficiently implement intelligent algorithms and improve hardware resource utilization. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0046] Figure 1 A flowchart of a compilation optimization method provided in an embodiment of the present application;

[0047] Figure 2 A module description of the compilation system provided in the embodiment of the present application;

[0048] Figure 3 A schematic diagram of the structure of the operating device provided in the embodiment of the present application;

[0049] Figure 4 A schematic diagram of the hardware acceleration structure provided in an embodiment of the present application.

[0050] Explanation of the accompanying drawings: 21, structure optimization module; 22, serialization module; 23, model reloading module; 24, quantization module; 25, hardware generation module; 31, CPU; 32, FPGA. DETAILED DESCRIPTION

[0051] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0052] The following describes the implementation methods of the present application through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0053] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0054] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0055] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects described may be practiced without these specific details.

[0056] The embodiment of the present application provides a hardware compilation optimization method for intelligent algorithms.

[0057] A hardware compilation optimization method for intelligent algorithms, characterized by comprising the following steps:

[0058] Receive the intelligent algorithm model to be compiled, optimize the model structure, and convert the optimized model representation into a standard format.

[0059] Analyze the graph structure of the intelligent algorithm model and obtain the model data flow graph with hardware parameters.

[0060] The model parameters are quantified based on the model data flow graph to improve the parallel processing capability and hardware resource utilization of the generated hardware structure.

[0061] Generate the hardware computing structure corresponding to the intelligent algorithm based on the model data flow diagram and hardware template.

[0062] A hardware bitstream is generated based on the hardware structure generated by the intelligent algorithm hardware compilation system, and the bitstream is input into the intelligent algorithm running device.

[0063] Receiving the intelligent algorithm model to be compiled, optimizing the model structure, and converting the optimized model representation into a standard format includes the following steps:

[0064] Based on the framework of intelligent algorithm model, read the graph structure of the model.

[0065] The model structure optimization algorithm is used to simplify the model structure while ensuring the model performance.

[0066] The graph structure serialization standard is adopted to convert the model graph structure into a standard serialization representation.

[0067] Methods to simplify the model structure include model pruning, knowledge distillation and other algorithms, which optimize the model structure through a cyclic training and model structure optimization process.

[0068] To convert the model graph structure into a standard serialized representation, perform the following steps:

[0069] Nodes are divided into four categories: input, output, operation nodes and parameters.

[0070] The topological structure of the model graph is realized by saving the previous and next connections of the nodes.

[0071] Analyze the standard format of the intelligent algorithm model to obtain the model data flow diagram with hardware parameters, including the following steps:

[0072] Establish a model inference framework containing hardware parameters.

[0073] Analyze the standard format of the intelligent algorithm and obtain the model data flow diagram with hardware parameters by corresponding node keywords.

[0074] The model parameters are quantified based on the model parameter data flow diagram using a dynamic quantization method, analyzing the different weights distributed at each layer of the intelligent algorithm model, and using different bit numbers to quantify each layer.

[0075] The hardware computing structure corresponding to the intelligent algorithm is generated based on the model data flow diagram and the hardware template, which mainly includes the following steps:

[0076] Determine the control parameters for each node operation and allocate them to on-chip memory.

[0077] Create a shared unit pool containing model-optimized hardware templates.

[0078] The on-chip network is generated by combining the hardware templates and control parameters of node operations in the shared unit pool.

[0079] Create a controller to manage the timing of each operator.

[0080] The model-optimized hardware templates include conventional adders, multipliers, and multipliers that exploit the bit-level sparsity of model parameters.

[0081] like Figure 1As shown, the hardware compilation optimization method for intelligent algorithms disclosed in the embodiment of the present application specifically includes:

[0082] S1, receiving the intelligent algorithm model to be compiled, optimizing the model structure, and converting the optimized model representation into a standard format.

[0083] Specifically, the intelligent algorithm model to be compiled includes implementations under multiple frameworks, such as Tensorflow, Pytorch, Caffe, Mxnet, etc. The algorithm model can be directly read using the framework embedded tools; the model structure optimization method includes model pruning and knowledge distillation algorithms. Model pruning is mainly aimed at coarse-grained pruning of model channels. The pruning method for channels can greatly reduce the amount of calculation; knowledge distillation of the model is to effectively reduce the model parameters by designing a teacher-student network. Based on the model structure optimization method, repeated training and structural optimization are performed on the specified data set, which greatly reduces the number of model parameters while ensuring model performance, thereby facilitating the efficient implementation of intelligent algorithms on hardware.

[0084] The purpose of the serialization standard for graph structures is to obtain a unified representation of algorithm models under multiple frameworks for subsequent unified compilation. The serialization method for graph structures, that is, the serialization method for structured data, obtains a model storage representation that is independent of the model framework and language. The specific method is to divide the nodes in the model graph structure into four categories: input, output, parameter, and operation, store them separately in the form of keyword indexes, and record the forward and backward nodes to preserve the topological structure of the model in the serialized storage.

[0085] S2, analyze the intelligent algorithm model graph structure to obtain the model data flow graph with hardware parameters.

[0086] Specifically, for the unified serialization representation of the algorithm model graph structure under various frameworks, the model structure is converted to a model data flow graph with hardware configuration parameters by traversing the operation nodes and using the methods corresponding to the keywords. The model data flow graph with hardware parameters is implemented through a custom model reasoning framework. The custom reasoning framework is similar to Tensorflow and defines node variables, constants, operations, and placeholders. In addition, hardware-related configuration parameters such as register configuration interfaces, bus interfaces, and data bit widths are defined within the nodes. Traverse each node of the model serialization representation and obtain the model data flow graph with hardware parameters by manually setting the keyword corresponding method.

[0087] In addition, the model graph structure conversion includes the fusion operation of operators, which further simplifies the model graph structure and reduces the data transfer loss. For example, the fusion of the convolution layer and the batch normalization layer is realized. The calculation formula of the convolution layer is y＝w*x+b, the calculation formula of the batch normalization layer is Fusion of the two layers yields formula (1), see formula (1):

[0088]

[0089] This is equivalent to modifying the convolution layer. Without increasing the computational complexity of the convolution layer, the batch normalization operation nodes are omitted, and the graph structure of the algorithm model can be optimized.

[0090] S3, quantizes the model parameters based on the model data flow graph to improve the parallel processing capability and hardware resource utilization of the generated hardware structure.

[0091] Specifically, intelligent algorithms are usually accompanied by large memory consumption and high computing costs during operation. Quantizing model parameters can further reduce storage and computing costs. Unlike uniform quantization, which may quickly reduce overall accuracy, dynamic quantization methods can quantize algorithm models in layers. In view of the different weight distribution characteristics of each layer in the model structure, each layer is quantized with a different number of bits. Compared with the uniform quantization method, the model can be further compressed while ensuring that the model accuracy will not decrease rapidly. The model parameters generated by the quantization method need to be saved and wait to be written to the memory.

[0092] S4, based on the model data flow diagram and combined with the hardware template, generate the hardware computing structure corresponding to the intelligent algorithm. Figure 4 As shown, it is a schematic diagram of the hardware structure provided by an embodiment of the present application. Specifically, the nodes of the optimized model data flow graph are traversed, and the corresponding hardware structure is generated according to the data flow in combination with the hardware configuration parameters of the nodes. The model data flow graph is traversed, the control function of each node operation is determined, and allocated to the specified memory. The hardware templates in the arithmetic unit are shared between the nodes, and different specific node operations are implemented in combination with different control parameters, so as to avoid the situation where the hardware structure is greatly expanded as the scale of the algorithm model increases. The on-chip network connects the control parameters in the storage with the shared arithmetic unit pool. The controller manages the timing of each operator and realizes the overall process of the intelligent algorithm. In addition, the hardware structure also includes registers for external control, and external signals are communicated through the AXI bus.

[0093] The hardware template includes a multiplier that exploits bit sparsity. The hardware template converts each input into a list of signed powers of 2, or items, through Booth encoding, and then multiplies and accumulates these items in sequence, making full use of the high bit sparsity of the weight values ​​or activation values ​​of the algorithm model during the reasoning process, greatly reducing the forward reasoning delay.

[0094] In addition, the hardware computation structure is represented by the underlying hardware language, which is used to generate the hardware bitstream.

[0095] S5, generating a hardware bitstream based on the hardware structure generated by the intelligent algorithm hardware compilation system, and inputting the bitstream into the intelligent algorithm running device.

[0096] Specifically, the FPGA-related tool chain is used to convert the hardware structure represented by the underlying hardware language into a hardware bitstream, which is then input into the intelligent algorithm running device. The intelligent algorithm acceleration hardware implementation is completed together with the software-related configuration code, input data, and quantized weights.

[0097] The hardware compilation optimization algorithm for intelligent algorithms provided in the above-mentioned example disclosed in this application is aimed at the flexible and changeable needs of intelligent application scenarios under various frameworks, and an efficient and fast hardware compilation optimization method is proposed. The intelligent algorithm models represented by various frameworks are used, and the corresponding acceleration hardware structure is quickly generated from the algorithm model according to the overall structure of hardware acceleration and the optimization method of software and hardware collaboration. This method aims at the model reasoning acceleration requirements of intelligent algorithms and efficiently realizes model parallel processing and hardware resource utilization.

[0098] The application also discloses a hardware compilation system for intelligent algorithms.

[0099] like Figure 2 As shown, a hardware compilation system for intelligent algorithms is used to integrate and automatically implement hardware compilation optimization methods. The model algorithm to be compiled is input into the system, and after being processed by multiple modules of the compilation system, the hardware structure corresponding to the algorithm and the quantized model parameters can be obtained.

[0100] A hardware compilation system for intelligent algorithms includes a structure optimization module, a serialization module, a model reloading module, a quantization module and a hardware generation module.

[0101] The structure optimization module 21 is used for optimizing the structure of the intelligent algorithm model. It performs training-model pruning in a loop on the training data set and assists in knowledge distillation to achieve the optimization of the model structure while ensuring the model performance.

[0102] The serialization module 22 is connected to the structure optimization module 21, and is used to convert the structurally optimized intelligent algorithm model graph structure into a serialization representation, and convert models under multiple frameworks into a unified serialization representation.

[0103] Specifically, it reads the graph representation of algorithm models under various frameworks, serializes the structured graph model using the node category correspondence method, generates an algorithm model file in a unified format, and saves the internal model topology structure.

[0104] The model reloading module 23 is connected to the serialization module 22 and is used to convert the unified serialization model representation into a model data flow graph with hardware parameters.

[0105] Specifically, the transformation process is to use a reasoning engine with hardware configuration parameters to represent the model graph based on a unified serialized model representation, which is completely decoupled from the algorithm model framework.

[0106] The quantization module 24 is connected to the model reloading module 23 and is used to convert the accuracy of the algorithm model parameters into 8 bits or 16 bits through a dynamic quantization method.

[0107] Specifically, the quantized model parameters need to be saved, and the software configuration code needs to write the model parameters into the specified memory.

[0108] The hardware generation module 25 is connected to the model reloading module 23 and is used to convert the model data flow graph with hardware parameters into a hardware structure and finally generate a hardware bit stream.

[0109] It should be noted that it should be understood that the division of the various modules of the above system is only a division of logical functions. In reality, they can be fully or partially integrated into one physical entity, or they can be physically separated. And these modules can all be implemented in the form of software called by processing elements; they can also be all implemented in the form of hardware; some modules can also be implemented in the form of software called by processing elements, and some modules can be implemented in the form of hardware. For example, the x module can be a separately established processing element, or it can be integrated in a chip of the above device. In addition, it can also be stored in the memory of the above device in the form of program code, and called and executed by a processing element of the above device. The implementation of other modules is similar. In addition, these modules can be fully or partially integrated together, or they can be implemented independently. The processing element here can be an integrated circuit with signal processing capabilities. In the implementation process, each step of the above method or each module above can be completed by an integrated logic circuit of hardware in the processor element or instructions in the form of software.

[0110] The application also discloses a device for hardware compilation of intelligent algorithms.

[0111] like Figure 3 As shown, a device for hardware compilation of intelligent algorithms includes: a CPU (31), an FPGA (32), and a specific use process is as follows:

[0112] Generate a hardware bitstream and input it into the FPGA. Since the generated hardware structure contains registers for external control, the software-related configuration code needs to be input into the CPU. The generated acceleration hardware is externally controlled through the AXI bus. At the same time, the model parameters, input and output, and memory addresses of related intermediate variables are specified, and the reading of input and output is completed.

[0113] In summary, the intelligent algorithm compilation optimization method, system and device of the present application can quickly generate the corresponding hardware acceleration structure by compiling the intelligent algorithm, with high compilation efficiency, greatly simplifying the development process and generating an efficient hardware structure. Therefore, the present application effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0114] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A hardware compilation optimization method for intelligent algorithms, characterized in that: The steps include: Receive the intelligent algorithm model to be compiled, optimize the model structure, and convert the optimized model representation into a standard format; Analyze the intelligent algorithm model graph structure to obtain a model data flow graph with hardware parameters; quantifying model parameters based on the model data flow graph to improve the parallel processing capability and hardware resource utilization of the generated hardware structure; Generate a hardware computing structure corresponding to the intelligent algorithm based on the model data flow diagram combined with the hardware template; Generate a hardware bitstream based on the hardware structure generated by the intelligent algorithm hardware compilation system, and input the bitstream into the intelligent algorithm running device; The receiving of the intelligent algorithm model to be compiled, optimizing the model structure, and converting the optimized model representation into a standard format comprises the following steps: Based on the framework of the intelligent algorithm model, read the graph structure of the model; Adopt model structure optimization algorithm to simplify the model structure while ensuring model performance; Using a graph structure serialization standard, converting the model graph structure into a standard serialization representation; To convert the model graph structure into a standard serialized representation, perform the following steps: Divide nodes into four categories: input, output, operation nodes, and parameters; The topological structure of the model graph is realized by saving the previous and next connections of the nodes.

2. The hardware compilation optimization method for intelligent algorithms according to claim 1, characterized in that: The method for simplifying the model structure includes model pruning and knowledge distillation algorithm, and the model structure is optimized by cyclically performing training and model structure optimization processes.

3. The hardware compilation optimization method for intelligent algorithms according to claim 1, characterized in that: Analyzing the standard format of the intelligent algorithm model to obtain a model data flow diagram with hardware parameters includes the following steps: Establish a model reasoning framework containing hardware parameters; Analyze the standard format of the intelligent algorithm and obtain the model data flow diagram with hardware parameters by corresponding node keywords.

4. The hardware compilation optimization method for intelligent algorithms according to claim 1, characterized in that: The model parameters are quantified based on the model data flow graph using a dynamic quantization method, which analyzes the different weights distributed at each layer of the intelligent algorithm model and uses different bit numbers to quantify each layer.

5. The hardware compilation optimization method for intelligent algorithms according to claim 1, characterized in that: The hardware computing structure corresponding to the intelligent algorithm is generated based on the model data flow diagram and the hardware template, which mainly includes the following steps: Determine the control parameters for each node operation and allocate them to on-chip memory; Establish a shared unit pool containing model-optimized hardware templates; Combining the hardware templates and the control parameters of the node operations in the shared unit pool, generating an on-chip network; Create a controller to manage the timing of each operator.

6. The hardware compilation optimization method for intelligent algorithms according to claim 5, characterized in that: The model-optimized hardware template includes conventional adders, multipliers, and multipliers that utilize bit-level sparsity of model parameters.

7. A hardware compilation system for intelligent algorithms, characterized in that: It includes structure optimization module, serialization module, model reloading module, quantization module and hardware generation module; The structure optimization module is used for optimizing the structure of the intelligent algorithm model. It performs training-model pruning in a loop on the training data set and assists in knowledge distillation. On the premise of ensuring the performance of the model, the model structure is optimized. The structure optimization module reads the graph structure of the model based on the framework of the intelligent algorithm model; adopts the model structure optimization algorithm to simplify the model structure on the premise of ensuring the performance of the model; adopts the graph structure serialization standard to convert the model graph structure into a standard serialization representation; The serialization module is used to convert the structure of the intelligent algorithm model graph after structural optimization into a serialized representation, and convert the models under various frameworks into a unified serialized representation. The serialization module converts the model graph structure into a standard serialized representation by performing the following steps: dividing the nodes into four categories: input, output, operation nodes and parameters; realizing the topological structure of the model graph by saving the front and back connections of the nodes; The model reloading module is used to convert the unified serialized model representation into a model data flow graph with hardware parameters; The quantization module is used to convert the algorithm model parameter accuracy into 8 bits or 16 bits through a dynamic quantization method, and save the model parameters to run normally in the generated hardware structure; The hardware generation module is used to convert the model data flow graph with hardware parameters into a hardware structure and finally generate a hardware bitstream.

8. A device for hardware compilation of intelligent algorithms, characterized in that: The device includes a CPU and an FPGA, and the operation process includes the following steps: Inputting the hardware bitstream generated in any one of claims 1 to 6 into the FPGA; Inputting relevant software configuration code into the CPU; Write the input data and the quantized model parameters in any one of claims 1-6 into the designated memory.

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