Full Coverage Simplified Testing Method for Parallel Bus

Abstract

The full-coverage simplified test method for the parallel bus of the present invention belongs to the field of embedded computers. The method includes mask processing of the parallel bus address and data to form a target address and target data, write / read operations on the target address space of the parallel bus; determining whether the target data is the same as the data read from the target address, if so, the parallel bus test is qualified, if not, the parallel bus test is unqualified. This method first performs mask processing on the parallel bus address and data to form a target address and target data, secondly performs write / read operations on the target address space of the parallel bus, and finally compares the target data and the read data and records the test results.

Description

Technical Field

[0001] The present invention belongs to the technical field of embedded computers, and particularly relates to a full-coverage simplified test method for a parallel bus. Background Art

[0002] With the continuous development of the integration and modularization of embedded computer systems, the integration levels of the whole machine and modules are getting higher and higher. A variety of functional components are cascaded together through multiple types of interfaces, and the parallel bus is one of the commonly used interfaces.

[0003] At present, the parallel bus uses address space coding test to test the bus signals and slave devices. This test method is divided into two ways: full-address coding and data address coding, and it is necessary to perform continuous read / write access operations on the address space, which has the disadvantages of long test time and inability to cover all address signals.

[0004] In view of this, the present invention is specifically proposed. Summary of the Invention

[0005] The purpose of the present invention is to provide a full-coverage simplified test method for a parallel bus to solve the technical problem of low test efficiency of the existing method. There are many technical beneficial effects of the technical solution of this case, as introduced below:

[0006] Provide a full-coverage simplified test method for a parallel bus, which is applicable to the data interaction between the master device and the slave device of the parallel bus, and adopts the parallel bus method. The method includes:

[0007] Mask processing of the parallel bus address and data to form a target address and target data, and write / read operations on the target address space of the parallel bus;

[0008] Judge whether the target data is the same as the data read from the target address. If so, the parallel bus test is qualified; if not, the parallel bus test is unqualified.

[0009] Compared with the prior art, the technical solution provided by the present invention has the following beneficial effects:

[0010] The method provided in this case forms a target address and target data, reads and judges whether the data is consistent to perform the test, avoiding the continuous read / write access operations on the address space required by the traditional method, which may result in long test time and large amount of test data. It can simplify the test and also achieve full coverage of the parallel bus signals. Description of the Drawings

[0011] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0012] Figure 1 is the block diagram of the parallel bus test structure of the embedded data processing module;

[0013] Figure 2 is the flowchart of the parallel bus interface test software. Specific Embodiments

[0014] The following illustrates the embodiments of the present invention through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present invention from the content disclosed in this specification. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. The present invention can also be implemented or applied through other different specific embodiments. The details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention.

[0015] It should be noted that the following describes various aspects of the embodiments within the scope of the appended claims. It should be obvious that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is illustrative only. Based on the present invention, those skilled in the art should understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects described herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using other structures and / or functionality in addition to one or more of the aspects described herein.

[0016] It should also be noted that the drawings provided in the following embodiments only schematically illustrate the basic concept of the present invention. The drawings only show the components related to the present invention and are not drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in its actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0017] In addition, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the aspects can be practiced without these specific details. To enable those skilled in the art to better understand the solution of the present invention, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. The terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, unless otherwise specified, the meaning of "a plurality" is two or more.

[0018] Such as Figure 1 The full-coverage simplified test method for the parallel bus shown is applicable to the data interaction between the parallel bus master device and the slave device and adopts the parallel bus method. The method includes:

[0019] Mask processing of the parallel bus address and data to form a target address and target data, and write / read operations on the target address space of the parallel bus;

[0020] Judge whether the target data is the same as the data read from the target address. If so, the parallel bus test is qualified; if not, the parallel bus test is unqualified.

[0021] Form a target address and target data, and perform data reading and judging whether they are consistent to conduct the test, avoiding the need for continuous read / write access operations to the address space in the traditional method, which has the problems of long test time and large test data volume, and can simplify the test and also achieve full coverage of the parallel bus signals.

[0022] As a specific embodiment provided in this case, the method for mask processing of the parallel bus address and data includes:

[0023] According to the valid address space of the parallel bus and the access data width, perform mask processing to form the same number of target addresses and target numbers. For example, perform mask processing to form 4 target addresses and 4 target data.

[0024] The write / read operations on the target address space are to perform parallel bus write and read operations. The method for judging whether the target data is the same as the data read from the target address includes:

[0025] Write initialization data to 4 target address spaces and then read and record the written data;

[0026] Write target data to the spaces of 4 target addresses and then read and record the written data;

[0027] The comparison between the targeted data and the read data is to compare the actually written data and the expected results according to the corresponding relationship. If they are consistent, the parallel bus test is normal. Specifically:

[0028] Preset 4 mask data for multiplication with AND. The 4 mask data are 0x55555555, 0xAAAAAAAA, 0xFFFFFFFF, and 0x0. The valid address bits are multiplied with AND to form the targeted address, targeted data, and initialization data, covering all address lines and data lines.

[0029] Furthermore, the targeted address space is the targeted registers implemented by 4 FPGAs. The data bit width is the same as the parallel bus data bit width. The access address corresponds one-to-one with the 4 targeted addresses, and only these 4 registers are connected to the parallel bus as slave devices.

[0030] See Figure 1 In the embodiment shown, the embedded data processing module in practical applications adopts the PC8270+FPGA architecture. The memory resources are connected to the 60X bus of the PC8270 processor. The 60X bus is decoded and converted inside the FPGA to form an external parallel bus interface with a data bit width of 16 bits. The address range is:

[0031] 0xF4000000 - 0xF4FFFFFF, with a total storage space of 16MB. The test module uses the FPGA to implement the parallel bus slave device. Four 16-bit targeted registers are designed inside to correspond one-to-one with the 4 targeted addresses, and the control logic uses the valid 23-bit address line signals.

[0032] 2. Software Flow Design

[0033] See Figure 2 , and the software working process is as follows:

[0034] Address line: First step, perform mask processing on the memory access address [23:1] (0 is the lowest address line) (the method is the core): The 32-bit memory access address is AND-operated with special data (0xFFAAAAAA, 0xFF555554, 0xFFFFFFFE, 0xFF000000) to form 4 targeted addresses (A1 - A4): 0xF4AAAAAA, 0xF4555554, 0xF4FFFFFE, and 0xF4000000;

[0035] Data line: Perform mask processing on the 16-bit data: The 16-bit data is AND-operated with special data (0x5555, 0xAAAA, 0xFFFF, and 0x0) to form 4 targeted data (D1 - D4): 0x5555, 0xAAAA, 0xFFFF, and 0x0; Concatenate special data (0x5, 0xA, 0xF, and 0x0) to form the initialization data (D0): 0x5AF0;

[0036] In the second step, first write D0 initialization (for example, the value D0) to the 4 target address spaces, then read the data of the 4 target addresses, record the read values, and store them in registers R1 to R4.

[0037] In the third step, first write the target data D1 - D4 to the 4 target address spaces, then read the data of the 4 target addresses, and record them in R5 - R8.

[0038] In the fourth step, compare R1 - R4 with D0 respectively, and compare R5 - R8 with D1 - D4 respectively, record the test results, and if the results are consistent, the test is qualified.

[0039] The present invention reduces the access times of the parallel bus by performing mask processing on the memory access addresses in the parallel bus, and transfers the data processing to the address processing. In the test, 2 write / read operations are performed on each target address space, and the test is completed by comparing the target data and the read data. This test method is simple to operate, time-consuming, and can cover all parallel bus signals. 2 write / read operations are performed on each target address space in the test, and the test is completed by comparing the target data and the read data. It is simple to operate, time-consuming, and can cover all parallel bus signals.

[0040] The above has introduced the product provided by the present invention in detail. Specific examples are used in this article to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the core idea of the present invention. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of the invention, several improvements and modifications can be made to the invention, and these improvements and modifications also fall within the protection scope of the invention claims.

Claims

1. A full-coverage simplified test method for a parallel bus, applicable to data interaction between a parallel bus master device and a slave device, and using the parallel bus method, is characterized in that, The method includes: Mask processing of the parallel bus address and data to form a target address and target data, write / read operations on the target address space of the parallel bus, and determining whether the target data is the same as the data read from the target address. If so, the parallel bus test is qualified; if not, the parallel bus test is unqualified. Performing mask processing to form 4 of the target addresses and 4 of the target data. The write / read operations on the target address space are parallel bus write and read operations. The method for determining whether the target data is the same as the data read from the target address includes: writing initialization data to the 4 target address spaces and then reading and recording the written data, and writing the target data to the spaces of the 4 target addresses and then reading and recording the written data. The comparison between the target data and the read data is to compare the actually written data with the expected result according to the corresponding relationship. If they are consistent, the parallel bus test is normal. Preset 4 mask data are multiplied by AND, and the 4 mask data are 0x55555555, 0xAAAAAAAA, 0xFFFFFFFF, and 0x0. The valid address bits are multiplied by AND to form the target address, target data, and initialization data, covering all address lines and data lines.

2. The method according to claim 1, characterized in that, The target address space is 4 target registers implemented by FPGAs, the data bit width is the same as the parallel bus data bit width, the access address corresponds one by one to the 4 target addresses, and only these 4 registers are connected to the parallel bus as slave devices.

Images