Ranking memory devices based on performance metrics set based on various timing margin parameters

Abstract

The present disclosure relates to rating memory devices based on performance metrics set based on various timing margin parameters. An operating timing condition associated with a memory device to be installed at a memory subsystem is determined. The memory device can include a cross-point array of non-volatile memory cells. The operating timing condition corresponds to a first operational delay timing margin setting for the cross-point array of non-volatile memory cells. A first set of memory access operations is performed at the cross-point array of non-volatile memory cells according to a second operational delay timing margin setting that is lower than the first operational delay timing margin setting. A first number of errors that occur during performance of the first set of memory access operations is determined. In response to determining that the first number of errors satisfies an error condition, a first quality rating is assigned to the memory device. In response to determining that the first number of errors does not satisfy the error criteria, further testing is performed for the cross-point array of non-volatile memory cells based on one or more power level settings.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to rating memory devices based on performance metrics set with various time tolerance parameters. Background Technology

[0002] A memory subsystem may include one or more memory devices for storing data. These memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory subsystem to store data at memory devices and retrieve data from memory devices. Summary of the Invention

[0003] In one aspect, this disclosure relates to a method comprising: determining operational timing conditions associated with a memory device to be installed at a memory subsystem, the memory device comprising a crosspoint array of non-volatile memory cells, wherein the operational timing conditions correspond to a first operational delay timing tolerance setting of the crosspoint array of non-volatile memory cells; performing a first set of memory access operations at the crosspoint array of non-volatile memory cells according to a second operational delay timing tolerance setting, wherein the second operational delay timing tolerance setting is lower than the first operational delay timing tolerance setting; determining a first number of errors occurring during the execution of the first set of memory access operations; assigning a first quality level to the memory device in response to determining that the first number of errors meets an error criterion; and performing further testing on the crosspoint array of non-volatile memory cells based on one or more power level settings in response to determining that the first number of errors does not meet the error criterion.

[0004] In another aspect, this disclosure relates to a system comprising: a memory device; and processing means coupled to the memory device, the processing means being configured to perform operations including: determining an operational timing condition associated with a set of memory devices, each comprising a cross-point array of non-volatile memory cells and to be mounted at one or more memory subsystems, wherein the operational timing condition corresponds to a first power level setting of the cross-point array of non-volatile memory cells associated with a first timing tolerance; performing a first set of memory access operations at the cross-point array of non-volatile memory cells of each of the set of memory devices according to a second power level setting, wherein the second power level setting is associated with a second timing tolerance less than the first timing tolerance; determining, for each of the set of memory devices, the number of errors occurring during the execution of the first set of memory access operations; identifying one or more memory devices in the set of memory devices associated with a corresponding number of errors satisfying an error criterion; and assigning a first quality level to each of the identified one or more memory devices.

[0005] In another aspect, this disclosure relates to a non-transitory computer-readable storage medium comprising instructions that, when executed by a processing means, cause the processing means to perform operations including: determining an operating timing condition associated with a memory device to be installed at a memory subsystem, the memory device comprising a cross-point array of non-volatile memory cells, wherein the operating timing condition corresponds to a first operating delay timing tolerance setting of the cross-point array of non-volatile memory cells; performing a first set of memory access operations at the cross-point array of non-volatile memory cells according to a second operating delay timing tolerance setting, wherein the second operating delay timing tolerance setting is lower than the first operating delay timing tolerance setting; determining a first number of errors occurring during the execution of the first set of memory access operations; assigning a first quality level to the memory device in response to determining that the first number of errors meets an error criterion; and performing further testing on the cross-point array of non-volatile memory cells based on one or more power level settings in response to determining that the first number of errors does not meet the error criterion. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed descriptions and accompanying drawings of various embodiments of the present disclosure given below. However, the drawings should not be construed as limiting this disclosure to the specific embodiments, but are merely for explanation and understanding.

[0007] Figure 1 An example computing system including a memory subsystem is shown according to some embodiments of the present disclosure.

[0008] Figure 2 An example manufacturing environment according to some embodiments of this disclosure is shown.

[0009] Figure 3 This is a flowchart of an example method for rating a memory device based on a timing tolerance performance metric, according to embodiments of the present disclosure.

[0010] Figure 4 This is a flowchart of another example method for rating memory devices based on timing tolerance performance metrics.

[0011] Figure 5 This is a flowchart of an example method for rating a collection of memory devices based on timing tolerance performance metrics, according to some embodiments of the present disclosure.

[0012] Figure 6 This is a block diagram of an example computer system in which embodiments of the present disclosure may operate. Detailed Implementation

[0013] This disclosure relates to rating memory devices based on performance metrics set with various time tolerance parameters. The memory subsystem can be a memory device, a memory module, or a combination of both. The following is combined with… Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that includes one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0014] The memory subsystem can contain high-density non-volatile memory devices where data retention is required when no power is supplied to the memory device. One example of a non-volatile memory device is a NAND flash memory device. Another example is a three-dimensional cross-point (“3D cross-point”) memory device containing an array of non-volatile memory cells. 3D cross-point memory devices can combine stackable cross-grid data access arrays to perform bit storage based on changes in bulk resistance. The following section combines... Figure 1Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die may consist of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and has various logic states associated with the number of bits being stored. Logic states may be represented by binary values ​​(e.g., “0” and “1”) or combinations of such values.

[0015] Memory devices can consist of bits arranged in a two-dimensional (2D) or three-dimensional (3D) grid. Memory cells are etched onto a silicon wafer in an array of columns (hereinafter also referred to as bit lines (BL)) and rows (hereinafter also referred to as word lines (WL)). A word line can refer to one or more rows of memory cells in a memory device, which are used in conjunction with one or more bit lines to generate the address of each of the memory cells. The intersection of bit lines and word lines constitutes the address of a memory cell. Hereinafter, a block refers to a cell of a memory device used to store data and can contain groups of memory cells, groups of word lines, word lines, or individual memory cells. One or more blocks can be grouped together to form planes of a memory device to allow concurrent operation on each plane. A 3D intersection-based memory device (and its controller) is called a "driver" and has multiple dies layered in multiple planes referred to as "layers" in the memory device.

[0016] The memory subsystem controller can perform memory access operations (e.g., read operations, write operations, etc.) by applying specific voltages to memory cells that store data, in order to access data stored in the memory device. For some types of memory devices, memory access operations (e.g., read operations) can alter the threshold voltage distribution of memory cells, a phenomenon known as the partial write effect. Over time, the partial write effect caused by memory access operations can worsen the threshold voltage distribution of memory cells, and subsequent memory access operations at the same memory cells may have a higher error rate. The threshold voltage distribution may change after data has been programmed into the memory device. For example, at a given voltage level, the impact of memory cell damage may be greater if the memory access operation is performed shortly after the data has been programmed, compared to performing the memory access operation later after the data has been written. As time continues to increase since the data was programmed, the impact of the damage may continue to decrease. Therefore, memory cell damage caused by a specific memory access voltage may differ when the data has been programmed versus when the data is being read.

[0017] The memory subsystem controller can execute memory access operations based on various operation timing conditions to reduce the impact of partial write effects on memory cells. One example of an operation timing condition is the amount of time elapsed between the execution of an initial memory access operation and the time before a subsequent memory access operation can be performed. For instance, after writing data to a memory cell in a memory device, the memory subsystem controller can delay subsequent read operations at that memory cell until the amount of time associated with the operation timing condition has elapsed. This type of delay is called operation-to-operation latency. The amount of time latency between specific memory access operations can be optimized to reduce the number of errors caused by corrupted memory access operations.

[0018] In integrated circuits (ICs), timing tolerance corresponds to the difference between the time a signal arrives at the circuit and the latest time the signal can reach the circuit to function correctly. The size of the timing tolerance for a particular memory device can be directly related to the quality of the components of the memory device. For example, the timing tolerance of a lower-quality memory device can be smaller than that of a higher-quality memory device. Regarding the execution of a memory access operation, the timing tolerance corresponds to a period of time after the initial memory access operation is performed, during which a voltage for subsequent memory access operations is applied to the memory cell according to the operating timing and performance conditions (e.g., efficiency conditions, latency conditions, etc.) for the memory subsystem. The memory subsystem operates according to various timing tolerance parameters set such that the memory subsystem controller applies a voltage for a specific memory access operation to the memory cell within the timing tolerance corresponding to the memory access operation. For example, the timing tolerance for write-to-read latency can be 100 nanoseconds (ns). The write-to-read latency timing tolerance parameter allows the memory subsystem controller to apply a voltage signal for subsequent read operations to the memory cell within a 100 ns timing tolerance associated with the write-to-read latency.

[0019] As described above, the timing tolerance of a lower-quality memory device can be smaller than that of a higher-quality memory device. According to a previous example, the write-to-read latency timing tolerance at a lower-quality memory device can be 90 ns instead of 100 ns. This is referred to as a negative timing tolerance. If the memory subsystem controller operates according to timing tolerance parameters that cause it to apply a voltage for subsequent read operations within a 100 ns timing tolerance, a partial write effect may occur, which could degrade the threshold voltage distribution of the memory cells.

[0020] Advanced memory devices, such as those based on 3D cross-pointing, operate at extremely high speeds and have very precise timing tolerances. As previously described, different dies may have different timing tolerances due to process variations during manufacturing. Furthermore, signal or power inputs to the assembled memory device can cause fluctuations in driver voltage levels, which can exacerbate timing tolerance variations between dies. If the timing tolerance of the memory device becomes negative and the memory subsystem controller drives the memory device at a high frequency, the memory device may malfunction, increasing the error rate associated with the memory device. The memory subsystem controller may perform numerous error correction operations to correct defects at the memory device, leading to a degraded memory subsystem performance. In some cases, negative timing tolerances can cause write / read failures to exceed the capability of error correction codes (ECC) to correct data. In this situation, the memory subsystem reports an uncorrectable error correction code (UECC) event.

[0021] This disclosure addresses the aforementioned and other shortcomings by rating memory devices using performance metrics based on various timing parameter tolerance settings. Test equipment for a manufacturing system can perform tests on each memory device according to various timing tolerance parameter settings (e.g., operation delay timing tolerance settings, power level settings, etc.) and rate each memory device based on its performance during the tests. In some embodiments, the test equipment can measure the performance of the memory device based on the total number of errors detected after performing a set of memory access operations (e.g., the total number of UECC event reports). In response to determining that the number of errors meets an error criterion (e.g., exceeding a threshold number of errors), the test equipment can assign a first quality level to the memory device. In response to determining that the number of errors does not meet the error criterion, the test equipment can perform additional tests on the memory device and assign a second or third quality level to the memory device based on the results of the additional tests.

[0022] The advantages of this disclosure include, but are not limited to, increased overall lifespan of the memory subsystem. By testing memory devices using various timing tolerance parameter settings, the test equipment can more easily identify memory devices containing manufacturing defects, resulting in smaller timing tolerances. Since smaller timing tolerances may lead to a large number of errors during memory access operations at the memory device, the test equipment can assign an appropriate quality level to the device. The assembly equipment of the manufacturing system can assemble the memory subsystem according to the quality level of each device. For example, the assembly equipment of the manufacturing system can use memory device grades to assemble a memory subsystem containing only memory devices assigned to high-quality grades, which may result in a lower overall error rate for the memory subsystem. A lower overall error rate for the memory subsystem reduces the number of error correction operations performed on the memory subsystem and can reduce the possibility of unrecoverable data loss. In another example, the assembly equipment can use memory device quality grades to assemble a memory subsystem containing an equal mixture of memory devices assigned to low-quality grades and memory devices assigned to high-quality grades, which avoids assembling a memory subsystem with a large number of low-quality memory devices. Alternatively or additionally, the test equipment can identify memory devices with smaller timing tolerances that may lead to a large number of errors during operation of the memory subsystem. These identified memory devices can be marked as defective, and the manufacturing system can prevent assembly equipment from including these memory devices in any memory subsystem.

[0023] Figure 1 An example computing system 100 including a memory subsystem 110 is illustrated according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0024] The memory subsystem 110 can be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0025] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., an airplane, drone, train, car or other means of transport), Internet of Things (IoT) enabled device, embedded computer (e.g., an embedded computer contained in a vehicle, industrial equipment or networked business device), or such computing device containing memory and processing power.

[0026] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 An example of a host system 120 coupled to a memory subsystem 110 is shown. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which may be an indirect communication connection or a direct communication connection (e.g., without an intermediate component), whether wired or wireless, and includes connections such as electrical, optical, magnetic, etc.

[0027] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more cache memories, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110, for example, to write data to memory subsystem 110 and read data from memory subsystem 110.

[0028] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)). The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 can further utilize an NVM High Speed ​​(NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for passing control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1Memory subsystem 110 is shown as an example. Generally, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or combinations of communication connections.

[0029] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0030] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory devices, which are crosspoint arrays of non-volatile memory cells. Crosspoint arrays of non-volatile memory can perform bit storage based on variations in volume resistance by combining stackable cross-grid data access arrays. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0031] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the memory device 130 may be grouped into pages that can refer to logical units of the memory device used for storing data. In the case of some types of memory (e.g., NAND), pages may be grouped to form blocks. Some types of memory (e.g., 3D cross-connect) may group pages across the die and channels to form management units (MUs).

[0032] Although non-volatile memory devices, such as 3D cross-point arrays of non-volatile memory cells and NAND flash memory (e.g., 2D NAND, 3D NAND), have been described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0033] The memory subsystem controller 115 (or, for simplicity, controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system having dedicated (i.e., hard-decoded) logic that performs the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0034] The memory subsystem controller 115 may be a processing device that includes one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0035] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The example memory subsystem 110 has been shown to include a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0036] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical MU addresses, physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions to access the memory device 130 and translate responses associated with the memory device 130 into information for the host system 120.

[0037] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache memory or buffer (e.g., DRAM) and an address circuitry (e.g., a row decoder and a column decoder) that can receive and decode addresses from the memory subsystem controller 115 to access the memory device 130.

[0038] In some embodiments, memory device 130 includes a local media controller 135, which operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a native memory device combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0039] In some cases, one or more tests may be performed on memory devices 130 and 140 before they are installed at memory subsystem 110. For example, memory device 130 may be tested at a test facility of a manufacturing system before it is installed at memory subsystem 110. Memory device 130 may be inserted at the test facility. Manufacturing components in the manufacturing environment may perform one or more operations at the memory device inserted at the test facility. Local media controller 135 of memory device 130 may include memory device testing component 113, which may collect test data associated with one or more operations performed at memory device 130. The test data may include any data used to determine the performance of the memory device (e.g., durability, operational error rate, latency, throughput, etc.). For example, the test data may include the number of errors that occurred during one or more operations performed at memory device, the amount of time between instances of starting an operation and instances of completing an operation, etc. In response to collecting the test data, memory device testing component 113 may transfer the test data to the manufacturing component. The following section discusses... Figure 2 Further details regarding the operation of the memory device testing component 113 and the manufacturing component are described.

[0040] Figure 2 An example manufacturing system 200 according to some embodiments of the present disclosure is illustrated. The manufacturing system 200 may include a server 210, a manufacturing apparatus 220, a testing apparatus 230, a client device 240, and a data storage device 250. In some embodiments, each of the server 210, manufacturing apparatus 220, testing apparatus 230, client device 240, and data storage device 250 may be connected via a network 270.

[0041] Server 210 may include manufacturing component 212 configured to facilitate one or more processes at manufacturing system 200. In some embodiments, manufacturing component 212 may include memory subsystem assembly module 214 (referred to herein as assembly module 214), memory device testing module 216 (referred to herein as device testing module 216), and memory device simulation module 218 (referred to herein as device simulation module 218). Assembly module 214 is configured to facilitate the assembly of a memory subsystem, such as memory subsystem 110, at manufacturing equipment 220.

[0042] Such as about Figure 1As described, the memory subsystem 110 may include a memory subsystem controller (e.g., memory subsystem controller 115) and one or more memory devices (e.g., memory devices 130). In some embodiments, the assembly module 214 may select a particular memory device 130 to be installed in the memory subsystem 110 based on a quality level 260 for each memory device 130. The manufacturing component 212 may determine the quality level 260 of each memory device 130 based on measured performance of each memory device 130. The performance of a memory device may refer to the quality of data stored in the memory device 130 (e.g., the number of errors present in the stored data) and / or the efficiency of operations performed at the memory device. In some embodiments, the manufacturing component 212 may measure the performance of the memory device 130 based on the total number of errors detected after performing a set of memory access operations (e.g., the total number of UECC event reports).

[0043] In some embodiments, manufacturing component 212 may measure the performance of memory device 130 based on test data (e.g., test data 256) collected by device testing module 216 for memory device 130. Device testing module 216 may facilitate testing of memory device 130 at test equipment 230. In some embodiments, test equipment 230 may include a memory device test rack containing a plurality of memory device test slots. Memory device 130 may be inserted into a corresponding memory device test slot, and device testing module 216 may perform one or more test operations to be performed at the inserted memory device.

[0044] In some embodiments, the device test module 216 can facilitate testing of the memory device 130 at the test apparatus 230 by executing one or more instructions to perform a set of memory access operations (e.g., write operations, read operations, etc.) according to one or more operation timing conditions 252. The operation timing condition 252 refers to the amount of time between the execution of an initial memory access operation and the possibility of performing a subsequent memory access operation. The operation timing condition 252 may correspond to the length of time of the delay between the initial memory access operation performed at the memory device and subsequent memory access operations, which is referred to as the operation-to-operation delay (e.g., write-to-write delay, write-to-read delay, read-to-read delay, etc.). For example, after writing data to a memory cell of the memory device 130, the memory subsystem controller 115 may delay subsequent read operations at the memory cell until the amount of time associated with the operation timing condition 252 (referred to as the write-to-read delay) has elapsed.

[0045] A timing tolerance corresponds to a time tolerance following the execution of an initial memory access operation, within which a voltage for subsequent memory access operations can be applied to the memory cell according to the operation timing condition 252 for the memory subsystem 110 and other performance conditions (e.g., efficiency conditions, latency conditions, etc.). The memory subsystem 110, including the memory device 130, can operate according to various timing tolerance parameter settings 254. Timing tolerance parameter settings 254 refer to specific settings (e.g., operation delay timing tolerance settings, power level settings, etc.) that cause the processing device to apply a voltage for a specific type of memory access operation within a timing tolerance corresponding to that type of memory access operation. For example, a write-to-read delay timing tolerance setting 254 can cause the memory subsystem controller 115 to apply a read operation voltage within a 100 ns timing tolerance. In another example, a power level setting can cause the processing device to provide a specific power level to the memory device 130 that maintains the timing tolerance of memory access operations performed at the memory device 130.

[0046] Operation timing condition 252 may correspond to a first set of timing tolerance parameter settings, which includes one or more timing tolerance parameter settings 254 optimized to reduce the number of errors occurring during memory access operations. The timing tolerance parameter settings 254 may include at least one of write-to-read latency timing tolerance settings, write-to-read latency timing tolerance settings, read-to-read latency timing tolerance settings, or power level settings. In some embodiments, a user of manufacturing system 200—e.g., an operator, engineer, programmer, etc.—may provide each of the first set of timing tolerance parameter settings 254 for memory device 130 (e.g., via client device 240). In other or similar embodiments, device testing module 216 may perform a series of tests on memory device 130 at test equipment 230 to determine each of the first set of timing tolerance parameter settings.

[0047] In some embodiments, the device test module 216 may obtain target test data 256 before performing tests on a specific memory device 130. For example, the device test module 216 may perform a set of memory access operations on the memory device 130 at the test device 230 according to a first set of timing tolerance parameters. The set of memory access operations may include: a first series of operations, which includes write operations and subsequent write operations on a set of memory cells at the memory device 130; a second series of operations, which includes write operations and subsequent read operations on a set of memory cells at the memory device 130; or a third series of operations, which includes read operations and subsequent read operations on memory cells at the memory device 130.

[0048] Device test module 216 can determine the number of errors that occur during the execution of a set of operations based on a first set of timing tolerance parameters. For example, device test component 113 can detect one or more errors arising from the execution of a set of memory access operations at memory device 130, and can (e.g., via network 270) transmit a message indicating the total number of errors that occurred to device test module 216. In some embodiments, the total number of errors may correspond to the total number of UECC events detected at memory device 130 during the execution of the set of memory access operations. In some embodiments, device test component 113 may not detect any errors arising from the execution of the set of memory operations and transmit a message indicating that no errors were detected to device test module 216. In response to receiving a message from device test component 113, device test module 216 may store the received number of errors or the indication that no errors were detected as target test data 256 at a data storage device. As previously described, each of the first set of timing tolerance parameter settings is optimized to reduce the number of errors that occur during the execution of memory access operations at memory device 130. Assembly module 214 can use target test data 256 as reference data to indicate the number of errors associated with the optimized timing tolerance parameter setting 254 of memory device 130.

[0049] In some embodiments, the device testing module 216 may obtain the target test data 256 by performing a memory access operation on the memory device 130, as previously described. In other or similar embodiments, the device testing module 216 may obtain the target test data 256 without performing a memory access operation on the memory device 130, and alternatively, may receive the target test data 256 from a user of the manufacturing system 200 having a first set of timing tolerance parameter settings. In other or similar embodiments, according to the previously described embodiments, the device testing module 216 may determine the target test data 256 during the execution of a series of tests to determine each of the first set of timing tolerance parameter settings.

[0050] Device test module 216 can test memory device 130 by executing instructions at test device 230 to perform a set of memory access operations at memory device 130, based on a second set of timing tolerance parameters. It should be noted that device test module 216 can execute each set of memory access operations described herein on the same memory device 130 or different memory devices 130. For example, device test module 216 can execute a first set of operations at a first memory device 130 based on a first set of timing tolerance parameters and execute a second set of operations at a second memory device 130 based on a second set of timing tolerance parameters. The set of operations for testing based on the second set of timing tolerance parameters may contain the same operations (or a series of operations) or may contain different operations included in the set of operations for obtaining target test data 256.

[0051] The second set of timing tolerance parameter settings may include at least one setting different from the first set of timing tolerance parameter settings. For example, the second set of timing tolerance parameter settings may include an operation delay timing parameter setting that causes the processing device to apply a voltage for subsequent read operations within a timing tolerance of 95 ns, said timing tolerance being smaller than the 100 ns timing tolerance for the operation delay timing tolerance parameter settings of the first set. In another example, the power level settings of the second set may cause the processing device to provide a smaller power level to the memory device during the execution of the memory access operation set compared to the corresponding power level settings of the first set. The device test module 216 can determine the number of errors that occur during the execution of the memory access operation set based on the second set of test tolerance parameter settings, and can store the received number of errors as test data 256 at the data storage device 250, as previously described.

[0052] In some embodiments, the device test module 216 may perform multiple tests on the memory device 130 based on different sets of test tolerance parameter settings. For example, the device test module may perform an additional set of operations at the memory device 130 based on a third set of test tolerance parameter settings. The third set of test tolerance parameter settings may include at least one timing tolerance parameter setting that is different from the corresponding parameter settings of the first and / or second sets of test tolerance parameter settings. For example, the third set of test tolerance parameter settings may include an operation delay timing tolerance setting that causes the processing device to apply a voltage for a subsequent read operation within a timing tolerance of 90 ns, said timing tolerance being less than the 95 ns timing tolerance setting for the second set of operation delay timing tolerance settings and the 1000 ns timing tolerance setting for the first set of operation delay timing tolerance settings. In other or similar embodiments, the third set of test tolerance parameter settings may include an operation delay timing tolerance setting that causes the processing device to apply a voltage for subsequent read operations within a timing tolerance of 100 ns, but may also include a power level setting that causes the processing device to provide a smaller power level to the memory device than the power level provided during the execution of the operation set according to the first and / or second set of timing tolerance parameter settings. According to the previously described embodiments, the device test module 216 may determine the number of errors that occur during the execution of an additional set of memory access operations and may store the number of errors as test data 258 at the data storage device 250.

[0053] Assembly module 214 can use test data 258 to determine the quality level of a particular memory device 130. For example, assembly module 214 can determine whether the number of errors detected during the execution of a set of memory access operations during testing meets an error criterion. Assembly module 214 can determine that the number of errors meets the error criterion in response to determining that the number of errors reaches or exceeds a threshold number of errors. In some embodiments, the threshold number of errors may correspond to the number of errors detected in target test data 256. In an illustrative example, target test data 256 may include an indication that no errors were detected during the execution of a first set of operations set according to timing tolerance parameters at memory device 130. Test data 258 may include an indication that device test component 113 detected one or more errors after the execution of a second set of operations set according to timing tolerance parameters. Thus, assembly module 214 can determine that the number of errors detected during the execution of the second set of memory access operations exceeds the threshold number of errors.

[0054] In response to determining that the number of errors meets the error criteria, assembly module 214 may assign a low quality level 260 to memory device 130. In some embodiments, in response to determining that the number of errors does not meet the error criteria (e.g., the number of errors does not meet a threshold), assembly module may assign a high quality level 260 to memory device 130. In some embodiments, low quality level 260 may represent memory devices 130, 140 that are of lower quality than memory devices 130 associated with high quality level 260. In some embodiments, assembly module 214 may use additional test data 258 collected by device testing module 216 to determine the quality level 260 of memory device 130. For example, device testing module 216 may perform an additional set of memory access operations at memory devices 130, 140 according to a third set set of timing tolerance parameters, as previously described. In response to determining that the number of errors detected for performing the additional set of memory access operations meets the error criteria, assembly module 214 may assign a medium quality level 260 to memory device 130. In response to determining that the number of errors does not meet the error criteria, assembly module 214 may assign a high quality grade 260 to memory device 130, as previously described.

[0055] In some embodiments, assembly module 214 may generate instructions and transmit these instructions to manufacturing apparatus 220 to install a specific memory device 130 at memory subsystem 110 based on a quality grade 260 of the memory device 130. For example, assembly module 214 may generate instructions that cause manufacturing apparatus 220 to install memory devices 130 with a high quality grade 260 at a specific memory subsystem 110. In another instance, assembly module 214 may generate instructions that cause manufacturing apparatus 220 to install memory devices 130 with a low quality grade 260 and memory devices 130 with a high quality grade 260 in a substantially equal (i.e., 50 / 50) mix at a specific memory subsystem 110. In other or similar embodiments, assembly module 214 may use quality grade 260 to identify memory devices 130 that may be defective and will not be installed at memory subsystem 110. For example, assembly module 214 may generate instructions that manufacturing apparatus 220 will not install any memory device 130 with a low quality grade 260 at memory subsystem 110. In response to generating instructions for installing memory device 130 at memory subsystem 110, assembly module 214 can transmit the instructions to manufacturing equipment 220. Manufacturing equipment 220 can assemble memory subsystem 110 containing specific memory device 130 according to the instructions.

[0056] Figure 3 and 4These are flowcharts of example methods 300, 400 for rating memory devices based on timing tolerance performance metrics according to embodiments of the present disclosure. Figure 5 This is a flowchart of an example method for rating a collection of memory devices based on a timing tolerance performance metric, according to some embodiments of this disclosure. Methods 300, 400, and / or 500 can be executed via processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, through... Figure 2 Manufacturing component 212 performs methods 300, 400, and / or 500. Although shown in a specific order or sequence, the order of processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0057] For reference Figure 3 In operation 310, the processing logic may determine the operating timing conditions associated with the memory device to be installed in the memory subsystem. The memory device may comprise a cross-point array of non-volatile memory cells. In some embodiments, the operating timing conditions may be related to... Figure 2 The described operation timing condition 252 may correspond to a first operation delay timing tolerance parameter setting, which is optimized to reduce the number of errors occurring during memory access operations performed at the cross-point array of non-volatile memory cells. In operation 320, the processing logic may perform a set of memory access operations at the cross-point array of non-volatile memory cells according to a second operation delay timing tolerance parameter setting. In some embodiments, the second operation delay timing tolerance parameter setting may be lower than the first operation delay timing tolerance parameter setting, as previously described. In some embodiments, before performing the set of memory access operations, the processing logic may modify one or more error correction settings of the memory device to correct error correction components, thereby preventing the correction of errors occurring at the cross-point array of non-volatile memory cells during the execution of memory access operations. For example, the processing logic may modify the error correction settings to prevent the memory device from performing redundant disk storage (RAID) error correction operations.

[0058] In operation 330, the processing logic may determine the number of errors that occurred during the execution of the set of memory access operations. For example, the device testing component 113 of the memory device 130 may detect the number of errors that occurred during the execution of the set of memory access operations and transmit a message indicating the number of detected errors to the manufacturing component 212, as previously described. In operation 340, the processing logic may determine whether the number of errors meets an error criterion. In some embodiments, the processing logic may determine whether the number of errors meets the error criterion by determining whether the number of errors exceeds a threshold number of errors. In one embodiment, if the number of errors reaches or exceeds the threshold number of errors, the processing logic may determine that the error criterion is met. If the number of errors does not reach or exceed the threshold number of errors, the processing logic may determine that the error criterion is not met. In response to the processing logic determining that the error criterion is met, method 300 may continue to operation 350, wherein the processing logic may assign a first quality level (e.g., a low quality level) to the memory device. In response to the processing logic determining that the error criterion is not met, method 300 may continue to operation 360, wherein the processing logic may perform further testing of the memory device based on one or more power level settings. Figure 4 Further details are provided regarding testing memory devices based on one or more power level settings.

[0059] Figure 4 This is a flowchart of another example method 400 for rating a memory device based on a timing tolerance performance metric. In some embodiments, processing logic may execute one or more operations of method 400 in response to the completion of one or more operations of method 300. For example, in response to method 300 continuing to operation 360, the processing logic may begin executing one or more operations of method 400 from operation 410 or operation 420. In other or similar embodiments, processing logic may execute one or more operations of method 400 without completing one or more operations of method 300. For example, the processing logic may begin executing one or more operations of 400 from operation 410.

[0060] In operation 410, according to the previously described embodiments, the processing logic may determine an operation timing condition associated with the memory device. The memory device may include a cross-point array of non-volatile memory cells, as previously described. In some embodiments, the operation timing condition may correspond to a power level setting of the cross-point array of non-volatile memory cells associated with a specific timing tolerance. In operation 420, the processing logic may execute a first set of memory access operations at the cross-point array of non-volatile memory cells of the memory device according to a second power level setting. The power level setting may be associated with a second timing tolerance less than the first timing tolerance. In operation 430, according to the previously described embodiments, the processing logic may determine the number of errors that occur during the execution of the set of memory access operations. In operation 440, the processing logic may determine whether the number of errors detected during the execution of the set of memory access operations meets an error criterion. In one embodiment, if the number of errors reaches or exceeds a threshold number of errors, the processing logic may determine that the error criterion is met. If the number of errors does not reach or exceed the threshold number of errors, the processing logic may determine that the error criterion is not met.

[0061] In some embodiments, in response to the processing logic determining that an error criterion is met, the processing logic may assign a first quality level or a second quality level to the memory device. For example, if the processing logic performs the operation of method 400 without performing the operation of method 300 (i.e., not testing the memory device based on the modified operation delay timing tolerance parameter setting), the processing logic may assign a first quality level (e.g., a low quality level) to the memory device in response to determining that an error criterion is met. In such embodiments, according to the previously described embodiments, the processing logic may subsequently perform one or more operations of method 300 (i.e., to test the memory device based on the modified operation delay timing tolerance parameter setting). In other or similar embodiments, method 400 may terminate.

[0062] In another instance, if the processing logic performs the operation of method 400 (i.e., testing the memory device based on the modified delay timing tolerance parameter setting) after executing one or more operations of method 300, then in response to the processing logic determining in operation 440 that the error criterion is met, method 400 may continue to operation 450, where the processing logic assigns a second quality level (e.g., a medium quality level) to the memory device. In response to the processing logic determining that the error criterion is not met, method 400 continues to operation 460, where the processing logic assigns a third quality level (e.g., a high quality level) to the memory device.

[0063] Figure 5 This is a flowchart of an example method 500 for rating a collection of memory devices based on a timing tolerance performance metric, according to some embodiments of this disclosure. It should be noted that, although regarding... Figure 5 The described embodiments relate to testing memory devices based on modified power level settings, but according to the embodiments described herein, processing logic can perform such operations of method 500 to test memory devices based on modified operation delay timing tolerance settings. In operation 510, the processing logic can determine operation timing conditions associated with a set of memory devices to be installed at one or more memory subsystems. Each memory device may comprise a cross-point array of non-volatile memory cells. The operation timing conditions may correspond to a first power level setting of the cross-point array of non-volatile memory cells associated with a first timing tolerance. In operation 520, according to the previously described embodiments, the processing logic can perform a set of memory access operations at each of the memory devices in the set based on a second power level setting. The second power level setting may be associated with a second timing tolerance less than the first timing tolerance. In operation 530, the processing logic can determine the number of errors that occur during the execution of the set of memory access operations for each of the memory devices in the set. In operation 540, the processing logic can identify one or more memory devices in the set of memory devices, each associated with a corresponding number of errors satisfying an error criterion. In some embodiments, the processing logic may determine that the number of errors in a memory device meets an error criterion by determining that the number of errors exceeds a threshold number of errors. In other or similar embodiments, the processing logic may determine that the number of errors in a particular memory device meets the error criterion by determining that the number of errors in a particular memory device is greater than the number of errors in another memory device in the set of memory devices. At operation 550, the processing logic may assign a first quality level to each of the identified one or more memory devices. In some embodiments, the processing logic may identify one or more additional memory devices in the set of memory devices that have a corresponding number of errors that do not meet the error criterion. In such embodiments, according to the previously described embodiments, the processing logic may perform and conduct additional tests on each of the additional memory devices (e.g., perform another set of memory access operations according to a third power level setting or a modified operation delay timing tolerance setting).

[0064] Figure 6 An example machine of computer system 600 is shown, within which a set of instructions can be executed to cause the machine to perform any or more of the methods discussed herein. In some embodiments, computer system 600 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., to execute an operating system to perform operations corresponding to...). Figure 1The device tests the operation of component 113. In other or similar embodiments, the computer system may correspond to the one used to perform manufacturing of components (e.g., Figure 2 The machine is a server operating the manufacturing system (manufacturing component 212). In an alternative embodiment, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a client-server network environment as a server or client machine in a cloud computing infrastructure or environment.

[0065] A machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular telephone, network appliance, server, network router, switch, or bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by said machine. Furthermore, although a single machine is shown, the term "machine" should also be considered to include any set of machines that individually or collectively execute a set of instructions (or multiple sets of instructions) to perform any one or more of the methods discussed herein.

[0066] Example computer system 600 includes processing devices 602 that communicate with each other via bus 630, main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or RDRAM), static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and data storage system 618.

[0067] Processing device 602 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets or a combination of instruction sets. Processing device 602 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. Computer system 600 may further include a network interface device 608 communicating via network 620.

[0068] Data storage system 618 may include machine-readable storage medium 624 (also called computer-readable medium) on which one or more instruction sets or software embodying any one or more of the methods or functions described herein are stored. Instructions 626 may also reside wholly or at least partially within main memory 604 and / or processing device 602 during execution by computer system 600, which also constitute machine-readable storage medium. Machine-readable storage medium 624, data storage system 618, and / or main memory 604 may correspond to... Figure 1 The memory subsystem 110 or Figure 2 Server 210.

[0069] In one embodiment, instruction 626 includes instructions for implementing a component corresponding to a manufacturing component (e.g., Figure 2 The machine-readable storage medium 624 is shown as a single medium in the example embodiment, but the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing a set of instructions executable by a machine, or encoding said set of instructions, and causing a machine to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0070] Some parts of the previously described descriptions have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. Algorithms are, and are generally considered, a self-consistent sequence of operations that produce the desired result. Operations are those that require the physical manipulation of physical quantities. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Sometimes, primarily for general reasons, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, quantities, etc.

[0071] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient notations applied to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate data represented as physical (electronic) quantities in the registers and memories of the computer system and transform said data into other data similarly represented as physical quantities in the memory or registers or other such information storage systems of the computer system.

[0072] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for its intended purpose, or the apparatus may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in computer-readable storage media, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0073] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may be convenient to construct more specialized devices to perform the methods described herein. The structures of various such systems will be presented as set forth in the description below. Furthermore, this disclosure is described without reference to any particular programming language. It will be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0074] This disclosure can be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon that can be used to program a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0075] In the foregoing description, embodiments of the present disclosure have been described with reference to specific exemplary embodiments thereof. It will be apparent that various modifications can be made to the present disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be regarded as illustrative rather than restrictive.

Claims

1. A method for rating a memory device, comprising: determining an operating timing condition associated with a memory device to be installed at a memory sub-system, the memory device comprising a cross-point array of non-volatile memory cells, wherein the operating timing condition corresponds to a first operating delay timing margin setting for the cross-point array of non-volatile memory cells; performing a first set of memory access operations at the cross-point array of non-volatile memory cells according to a second operating delay timing margin setting, wherein the second operating delay timing margin setting is lower than the first operating delay timing margin setting; determining a first number of errors that occurred during performance of the first set of memory access operations; in response to determining that the first number of errors satisfies an error criterion, assigning a first quality rating to the memory device; and in response to determining that the first number of errors does not satisfy the error criterion, performing further testing for the cross-point array of non-volatile memory cells based on one or more power level settings.

2. The method of claim 1, wherein the first operating delay timing margin setting and the second operating delay timing margin setting include at least one of a write-to-write operating delay timing margin setting, a write-to-read operating delay timing margin setting, or a read-to-read operating delay timing margin setting.

3. The method of claim 1, wherein determining the first number of errors that occurred during performance of the first set of memory access operations comprises: receiving one or more uncorrectable error reports during performance of the first set of memory access operations; and counting a number of one or more received uncorrectable error reports.

4. The method of claim 1, wherein the first set of memory access operations comprises at least one of: a first series of operations comprising a write operation and a subsequent write operation, a second series of operations comprising another write operation and a subsequent read operation, or a third series of operations comprising a read operation and another subsequent read operation.

5. The method of claim 1, wherein performing further testing for the cross-point array of non-volatile memory cells based on the one or more power level settings comprises: identifying a first power level setting for the cross-point array of non-volatile memory cells corresponding to the operating timing condition; performing a second set of memory access operations at the cross-point array of non-volatile memory cells according to a second power level setting, wherein the second power level setting is lower than the first power level setting; determining a second number of errors that occurred during performance of the second set of memory access operations; and in response to determining that the second number of errors satisfies the error criterion, assigning a second quality rating to the memory device, wherein the first quality rating corresponds to a lower memory device than a device quality associated with the second quality rating.

6. The method of claim 5, further comprising: performing a third set of memory access operations at the cross-point array of non-volatile memory cells in accordance with a third operational delay timing margin setting before performing further testing of the cross-point array of non-volatile memory cells based on the one or more power level settings, wherein the third operational delay timing margin setting is lower than the second operational delay timing margin setting; determining a third number of errors that occur during performance of the third set of memory access operations; and in response to determining that the third number of errors satisfies the error criterion, assigning a third quality rating to the memory device, wherein the first quality rating corresponds to a lower quality of memory device than a device quality associated with the third quality rating.

7. The method of claim 1, further comprising: prior to performing the first set of memory access operations at the cross-point array of non-volatile memory cells, modifying one or more error correction settings of the memory device to prevent an error correction component from correcting errors that occur at the cross-point array of non-volatile memory cells during the performance of the first set of memory access operations.

8. The method of claim 1, wherein determining that the first number of errors satisfies the error criterion comprises: determining that the first number of errors exceeds a threshold number of errors.

9. A memory system, comprising: a memory device; and a processing device coupled to the memory device, the processing device to perform operations comprising: determining operational timing conditions associated with a set of memory devices each comprising a cross-point array of non-volatile memory cells and to be installed at one or more memory subsystems, wherein the operational timing conditions correspond to first power level settings of the cross-point array of non-volatile memory cells associated with a first timing margin; performing a first set of memory access operations at the cross-point array of non-volatile memory cells of each of the set of memory devices in accordance with second power level settings, wherein the second power level settings are associated with a second timing margin that is less than the first timing margin; determining, for each of the set of memory devices, a number of errors that occur during performance of the first set of memory access operations; identifying one or more memory devices of the set of memory devices each associated with a respective number of errors that satisfies an error criterion; and assigning a first quality rating to each of the identified one or more memory devices.

10. The memory system of claim 9, wherein to determine, for each of the set of memory devices, the number of errors that occur during performance of the first set of memory access operations, the processing device is to: receive one or more uncorrectable error reports during performance of the first set of memory access operations at the cross-point array of non-volatile memory cells of a respective memory device; and compute, for the respective memory device, a number of one or more received uncorrectable error reports.

11. The memory system of claim 9, wherein the first set of memory access operations comprises at least one of: a first series of operations comprising a write operation and a subsequent write operation, a second series of operations comprising another write operation and a subsequent read operation, or a third series of operations comprising a read operation and another subsequent read operation.

12. The memory system of claim 9, wherein the processing device is to perform operations further comprising: identifying one or more additional memory devices in the set of memory devices that each have associated therewith a respective number of errors that does not satisfy the error criterion; and performing a second set of memory access operations at the cross-point array of non-volatile memory cells of each of the identified one or more additional memory devices according to a third power level associated with a third timing margin of the cross-point array of non-volatile memory cells, wherein the third timing margin is less than the second timing margin; determining a second number of errors that occurred during performance of the second set of memory access operations; in response to determining that the second number of errors satisfies the error criterion, assigning at least one of the first quality grade or a second quality grade to each of the identified one or more additional memory devices; and in response to determining that the second number of errors does not satisfy the error criterion, assigning a third quality grade to each of the one or more additional memory devices, wherein the third quality grade corresponds to a device that is higher than a device quality associated with the first quality grade and the second quality grade.

13. The memory system of claim 9, wherein the processing device is to perform operations further comprising: identifying a first operation delay timing margin setting of the cross-point array of non-volatile memory cells that corresponds to the operation timing condition; performing a third set of memory access operations at the cross-point array of non-volatile memory cells of each memory device of the set of memory devices that is associated with a respective number of errors that does not satisfy the error criterion, wherein the third set of memory access operations is performed according to a second operation delay timing margin setting of the cross-point array of non-volatile memory cells that is lower than the first operation delay timing margin setting; determining a third number of errors that occurred during performance of the third set of memory access operations; in response to determining that the third number of errors satisfies the error criterion, assigning at least one of the first quality grade or a second quality grade to each of the identified one or more additional memory devices; and in response to determining that the third number of errors does not satisfy the error criterion, assigning a third quality grade to each of the identified one or more additional memory devices, wherein the third quality grade corresponds to a device that is higher than a device quality associated with the first quality grade and the second quality grade.

14. The memory system of claim 13, wherein the first operational delay timing margin setting and the second operational delay timing margin setting include at least one of a write-to-write operational delay timing margin setting, a write-to-read operational delay timing margin setting, or a read-to-read operational delay timing margin setting.

15. The memory system of claim 9, wherein identifying the one or more memory devices comprises: determining that the respective number of errors associated with each of the one or more memory devices exceeds a threshold number.

16. The memory system of claim 9, wherein identifying the one or more memory devices comprises: determining that the respective number of errors associated with each of the one or more memory devices is greater than the number of errors for each additional memory device in the set of memory devices.

17. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: determining an operational timing condition associated with a memory device to be installed at a memory sub-system, the memory device comprising a cross-point array of non-volatile memory cells, wherein the operational timing condition corresponds to a first operational delay timing margin setting for the cross-point array of non-volatile memory cells; performing a first set of memory access operations at the cross-point array of non-volatile memory cells according to a second operational delay timing margin setting, wherein the second operational delay timing margin setting is lower than the first operational delay timing margin setting; determining a first number of errors that occurred during performance of the first set of memory access operations; in response to determining that the first number of errors satisfies an error criterion, assigning a first quality level to the memory device; and in response to determining that the first number of errors does not satisfy the error criterion, performing further testing for the cross-point array of non-volatile memory cells based on one or more power level settings.

18. The non-transitory computer-readable storage medium of claim 17, wherein the first operational delay timing margin setting and the second operational delay timing margin setting include at least one of a write-to-write operational delay timing margin setting, a write-to-read operational delay timing margin setting, or a read-to-read operational delay timing margin setting.

19. The non-transitory computer-readable storage medium of claim 17, wherein to determine the first number of errors that occurred during performance of the first set of memory access operations, the processing device is to perform operations comprising: receiving one or more uncorrectable error reports during performance of the first set of memory access operations; and counting a number of one or more received uncorrectable error reports.

20. The non-transitory computer readable storage medium of claim 17, wherein the first set of memory access operations comprises at least one of: a first series of operations comprising a write operation and a subsequent write operation, a second series of operations comprising another write operation and a subsequent read operation, or a third series of operations comprising a read operation and another subsequent read operation.

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