Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure, the method comprising: providing a substrate, the substrate comprising a first region and a second region between the first region; forming a pattern definition layer on the substrate; forming a discrete mask layer on the pattern definition layer, the mask layer and the substrate enclosing an opening, the opening of the first region as a first opening, and the opening of the second region as a second opening; forming a filling layer in the second opening; etching the pattern definition layer exposed by the first opening with the mask layer and the filling layer as masks to form a target pattern. In the embodiments of the present application, the filling layer is formed between the mask layers in the second region, and a mask for finally etching the pattern definition layer is obtained, so that the target pattern formed meets the process requirements, and the electrical performance of the semiconductor structure is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure. Background Technology

[0002] Currently, as semiconductor technology advances towards smaller linewidths and higher integration, higher demands are being placed on photolithography processes. Especially when dimensions are reduced to below 28 nanometers, the spacing between patterns becomes increasingly closer. The effects of optical interference and diffraction on adjacent patterns cause optical proximity effects such as line-end shortening, line-end bridging, line width variations, and line corner rounding when transferring patterns from the photomask to the wafer.

[0003] Specifically, in some semiconductor device designs, different parts of the same chip often have densely distributed patterns (dense patterns) and sparsely distributed patterns (iso patterns). When the same chip has both iso and dense pattern regions, the optical proximity effect will cause the linewidths of the same target size in the iso and dense pattern regions to have different actual sizes after being transferred to the wafer, i.e., line width variations defects.

[0004] Typically, when transferring a pattern from a photomask to a wafer, bars are formed between the patterns on the photomask to improve the pattern formation quality. These bars can optimize the density of local patterns, thereby increasing the pattern contrast and improving the pattern formation quality on the wafer. Summary of the Invention

[0005] The problem addressed by the embodiments of the present invention is to provide a method for forming semiconductor structures to improve the electrical performance of devices.

[0006] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first region and a second region located between the first region; forming a pattern definition layer on the substrate; forming discrete mask layers on the pattern definition layer, the mask layers and the substrate forming an opening, the opening in the first region serving as a first opening, and the opening in the second region serving as a second opening; forming a filling layer in the second opening; and etching the pattern definition layer exposed by the first opening using the mask layer and the filling layer as masks to form a target pattern.

[0007] Optionally, in the step of forming discrete mask layers on the pattern definition layer, the direction parallel to the substrate surface and perpendicular to the extension direction of the mask layer is defined as lateral; the step of forming a fill layer in the second opening includes: conformally covering the mask layer and the pattern definition layer exposed by the mask layer with a fill material layer, the thickness of the fill material layer being twice greater than the lateral dimension of the second opening; removing the fill material layer at the bottom of the first opening and the fill material layer at the top of the mask layer, with the remaining fill material layer in the second opening serving as the fill layer.

[0008] Optionally, the filling material layer may be formed using atomic layer deposition or chemical vapor deposition.

[0009] Optionally, a maskless dry etching process is used to remove the filling material layer at the bottom of the first opening and the filling material layer at the top of the mask layer.

[0010] Optionally, in the step of forming a filling layer in the second opening, a filling sidewall is also formed on the sidewall of the first opening; in the step of etching the pattern definition layer exposed by the first opening using the mask layer and the filling layer as masks to form the target pattern, the pattern definition layer is also etched using the filling sidewall as a mask.

[0011] Optionally, in the step of forming discrete mask layers on the pattern definition layer, the number of the second opening is one, or the number of the second opening is multiple.

[0012] Optionally, the step of forming discrete mask layers on the pattern definition layer includes: forming a mask material layer on the pattern definition layer; forming a photoresist material layer on the mask material layer; providing a mask, the mask including a first mask region and a second mask region located between the first mask region, the first mask region having a first pattern and the second mask region having a second pattern; patterning the photoresist material layer according to the mask to form a photoresist layer; etching the mask material layer using the photoresist layer as a mask to form the mask layer, wherein the first opening corresponds to the first pattern and the second opening corresponds to the second pattern.

[0013] Optionally, in the step of providing the mask, the horizontal direction is perpendicular to the extension direction of the second shape, and the horizontal dimension of the second shape is smaller than the horizontal dimension of the first shape.

[0014] Optionally, in the step of providing the mask, the ratio of the lateral dimension of the second graphic to the lateral dimension of the first graphic is one-third to one.

[0015] Optionally, the second graphic is a continuous graphic in the direction of extension of the second graphic.

[0016] Optionally, the extension direction of the first graphic is the same as the extension direction of the second graphic.

[0017] Optionally, the dimension of the first graphic in the extension direction is less than or equal to the dimension of the second graphic in the extension direction.

[0018] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0019] In the semiconductor structure formation method provided by the embodiments of the present invention, a filling layer is formed between the mask layers in the second region, and then the pattern definition layer is etched using the mask layer and the filling layer as masks to form a target pattern. In the embodiments of this application, a filling layer is formed between the mask layers in the second region to obtain a mask for finally etching the pattern definition layer, so that the formed target pattern meets the process requirements and is beneficial to improving the electrical performance of the semiconductor structure.

[0020] In an optional embodiment, the step of forming discrete mask layers on the pattern definition layer includes: forming a mask material layer on the pattern definition layer; forming a photoresist material layer on the mask material layer; providing a mask, the mask including a first mask region and a second mask region located between the first mask region, the first mask region having a first pattern, and the second mask region having a second pattern; patterning the photoresist material layer according to the mask to form a photoresist layer; etching the mask material layer using the photoresist layer as a mask to form a mask layer, wherein the first pattern corresponds to the first opening, and the second pattern corresponds to the second opening. In the photomask provided in this embodiment, the second pattern has a large lateral dimension, with the extension direction perpendicular to the second pattern defined as the lateral direction. This reduces the fabrication difficulty and cost of the photomask, and is beneficial for improving the formation efficiency of the mask layer. Furthermore, during the formation of the photoresist layer based on the photomask, the second pattern can optimize the pattern density of the first pattern and improve its contrast, resulting in lower linewidth roughness and edge roughness on the sidewalls of the photoresist layer. Using the photoresist layer as a mask to etch the mask material layer, the resulting mask layer has lower linewidth roughness and edge roughness on its sidewalls. This results in lower linewidth and edge roughness of the target pattern sidewalls formed by etching the pattern definition layer using the mask layer as a mask. Although the second pattern is transferred to form a second opening in the step of forming the mask layer according to the mask, a mask for finally etching the pattern definition layer can still be obtained by forming a filling layer in the second opening. This ensures that the target pattern formed using the mask layer and the filling layer as masks meets the process requirements. Furthermore, because the linewidth and edge roughness of the second opening sidewalls are lower and the formation quality of the target pattern is better, it is beneficial to improve the electrical performance of the semiconductor structure. Attached Figure Description

[0021] Figures 1 to 4 This is a schematic diagram of the structure corresponding to each step in the first method of forming a semiconductor structure;

[0022] Figure 5 and Figure 6 This is a schematic diagram of the structure corresponding to each step in the second method of forming a semiconductor structure;

[0023] Figure 7 This is a schematic diagram of the mask structure in the third method for forming semiconductor structures;

[0024] Figures 8 to 16 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0025] The devices currently being fabricated still suffer from poor performance. This paper analyzes the reasons for this poor performance by examining a semiconductor structure fabrication method.

[0026] Figures 1 to 4 This is a schematic diagram of the structure corresponding to each step in the first method of forming a semiconductor structure.

[0027] like Figure 1 As shown, a mask 30 is provided, the mask 30 including: a first pattern 1 spaced apart, and the first pattern 1 extending along a first direction x; a second pattern 2 located between the first patterns 1, the second pattern 2 extending along the first direction x, and spaced apart from the first patterns 1 along a second direction y, the second direction y being perpendicular to the first direction x.

[0028] like Figure 2 As shown, a substrate 10 is provided, on which a pattern definition layer 11 is formed, a mask material layer 12 is formed on the pattern definition layer 11, and a photoresist material layer 13 is formed on the mask material layer 12.

[0029] like Figure 3 As shown, the photoresist material layer 13 is exposed according to the photomask 30 to form the photoresist layer 14.

[0030] like Figure 4 As shown, the photoresist layer 14 is used as a mask to etch the mask material layer 12 to form a mask layer 15; the mask layer 15 is used as a mask to etch the pattern definition layer 11 to form a target pattern 16.

[0031] In the photomask 30, the first pattern 1 is used to form the target pattern 16 on the substrate 10, and the second pattern 2 is an auxiliary pattern. During the exposure process of the photoresist material layer 13 to form the photoresist layer 14 according to the photomask 30, under the action of optical proximity correction (OPC), the second pattern 2 is less likely to be transferred into the photoresist layer 14. Furthermore, the second pattern 2 is used to optimize the pattern density of the first pattern 1 and improve the contrast of the first pattern 1, resulting in a smaller line width roughness (LWR) and line edge roughness (LER) on the sidewalls of the formed photoresist layer 14. Correspondingly, when the photoresist layer 14 is used as a mask to etch the mask material layer 12, the line width roughness and line edge roughness of the sidewalls of the formed mask layer 15 are smaller, resulting in a smaller line width roughness (LWR) on the sidewalls of the target pattern 16 formed when the pattern definition layer 11 is etched using the mask layer 15. With lower roughness (LWR) and line edge roughness (LER), the target pattern 16 has better formation quality.

[0032] With the development of semiconductor technology, the integration density of semiconductor structures is becoming increasingly higher. Correspondingly, in the second direction y, the size d of the second pattern 2 (e.g.) Figure 1 As the second pattern 2 becomes smaller, it is easy to form a groove 18 in the photoresist layer 14. During the process of etching the mask material layer 12 with the photoresist 14 as a mask to form the mask layer 15, it is easy to form an interference opening 19 in the mask layer 15. During the process of etching the pattern definition layer 11 with the mask layer 15 as a mask to form the target pattern 16, it is easy to form an interference pattern 17 based on the interference opening 19.

[0033] Figure 5 and Figure 6 This is a schematic diagram of the steps involved in forming the second semiconductor structure. The second semiconductor structure formation method is an improvement on the first semiconductor structure formation method.

[0034] Figure 5The improved photomask 40 has a first pattern 1 and a second pattern 2 both extending along a first direction x, and the second pattern 2 and the first pattern 1 are arranged alternately along a second direction y, which is perpendicular to the first direction x. To prevent the second pattern 2 from easily transferring onto the photoresist layer, the size of the second pattern 2 in the second direction y is reduced (from the size of the dashed line in the figure to the size of the solid line). While this reduces the likelihood of the second pattern 2 transferring onto the photoresist layer during exposure processing of the photoresist material layer using the photomask 40, it also results in a poorer effect on optimizing the pattern density of the first pattern 1. Consequently, the sidewall linewidth roughness and edge roughness of the photoresist layer are relatively large. Consequently, the sidewall linewidth roughness and edge roughness of the mask layer formed using the photoresist layer as a mask are also relatively large, leading to larger sidewall linewidth roughness and edge roughness of the target pattern 26 formed using the mask layer, resulting in poor formation quality of the target pattern 26.

[0035] refer to Figure 7 This is a schematic diagram of the mask structure in the third method for forming a semiconductor structure. The third method for forming a semiconductor structure is an improvement on the first method.

[0036] Figure 7 The improved photomask 50 has a first pattern 8 and a second pattern 9 extending along a first direction x. The second pattern 9 and the first pattern 8 are arranged at intervals along a second direction y, which is perpendicular to the first direction x. To prevent the second pattern 9 from easily transferring to the photoresist layer, the second pattern 9 is interrupted along the first direction x. During the exposure process of the photoresist material layer with the photomask 50 to form the photoresist layer, although the second pattern 9 is not easily transferred to the photoresist layer, it cannot optimize the pattern density of the entire first pattern 8. The sidewall linewidth roughness and line edge roughness of the photoresist layer are relatively large. Correspondingly, the sidewall linewidth roughness and line edge roughness of the mask layer formed with the photoresist layer as a mask are also relatively large, resulting in large linewidth roughness and line edge roughness of the target pattern formed with the mask layer as a mask, and poor formation quality of the target pattern.

[0037] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first region and a second region located between the first region; forming a pattern definition layer on the substrate; forming discrete mask layers on the pattern definition layer, the mask layers and the substrate forming an opening, the opening in the first region serving as a first opening, and the opening in the second region serving as a second opening; forming a filling layer in the second opening; and etching the pattern definition layer exposed by the first opening using the mask layer and the filling layer as masks to form a target pattern.

[0038] In the semiconductor structure formation method provided by the embodiments of the present invention, a filling layer is formed between the mask layers in the second region, and then the pattern definition layer is etched using the mask layer and the filling layer as masks to form a target pattern. In the embodiments of this application, a filling layer is formed between the mask layers in the second region to obtain a mask for finally etching the pattern definition layer, so that the formed target pattern meets the process requirements and is beneficial to improving the electrical performance of the semiconductor structure.

[0039] In an optional embodiment, the step of forming discrete mask layers on the pattern definition layer includes: forming a mask material layer on the pattern definition layer; forming a photoresist material layer on the mask material layer; providing a mask, the mask including a first mask region and a second mask region located between the first mask region, the first mask region having a first pattern, and the second mask region having a second pattern; patterning the photoresist material layer according to the mask to form a photoresist layer; etching the mask material layer using the photoresist layer as a mask to form a mask layer, wherein the first pattern corresponds to the first opening, and the second pattern corresponds to the second opening. In the photomask provided in this embodiment, the second pattern has a large lateral dimension, with the extension direction perpendicular to the second pattern defined as the lateral direction. This reduces the fabrication difficulty and cost of the photomask, and is beneficial for improving the formation efficiency of the mask layer. Furthermore, during the formation of the photoresist layer based on the photomask, the second pattern can optimize the pattern density of the first pattern and improve its contrast, resulting in lower linewidth roughness and edge roughness on the sidewalls of the photoresist layer. Using the photoresist layer as a mask to etch the mask material layer, the resulting mask layer has lower linewidth roughness and edge roughness on its sidewalls. This results in lower linewidth and edge roughness of the target pattern sidewalls formed by etching the pattern definition layer using the mask layer as a mask. Although the second pattern is transferred to form a second opening in the step of forming the mask layer according to the mask, a mask for finally etching the pattern definition layer can still be obtained by forming a filling layer in the second opening. This ensures that the target pattern formed using the mask layer and the filling layer as masks meets the process requirements. Furthermore, because the linewidth and edge roughness of the second opening sidewalls are lower and the formation quality of the target pattern is better, it is beneficial to improve the electrical performance of the semiconductor structure.

[0040] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0041] Figures 8 to 16 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0042] refer to Figure 8 A substrate 100 is provided, the substrate 100 including a first region I and a second region II located between the first region I.

[0043] The substrate 100 provides a process platform for the subsequent formation of the target pattern.

[0044] The first region I prepares for the subsequent formation of the first opening, and the second region II prepares for the subsequent formation of the second opening.

[0045] The substrate 100 can be replaced with the material required for the target pattern according to the process requirements.

[0046] In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate material may also include germanium, silicon carbide, gallium arsenide, or indium gallium nitride. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or the substrate may include one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, boron silicon nitride, and boron silicon carbide. In other embodiments, the substrate material may also be a metal.

[0047] refer to Figure 9 A graphic definition layer 101 is formed on the substrate 100.

[0048] The graphic definition layer 101 prepares for the subsequent formation of the target graphic.

[0049] In this embodiment, the target pattern is used to space adjacent fins. Specifically, the material of the pattern definition layer 101 includes one or more of silicon, silicon germanide, germanium, silicon carbide, gallium arsenide, and indium gallium ionide. In this embodiment, the material of the pattern definition layer 101 includes silicon.

[0050] In this embodiment, selective epitaxy growth (SEG) is used to form the pattern definition layer 101. The thin film obtained by selective epitaxy growth has high purity and few defects, which is beneficial to improving the formation quality of the pattern definition layer 101. When the pattern definition layer 101 is subsequently patterned, the linewidth roughness (LWR) and line edge roughness (LER) of the fin sidewalls are smaller, resulting in better formation quality of the fins and improving the electrical performance of the semiconductor structure.

[0051] In other embodiments, the target pattern can also be used to space adjacent pseudo-gate structures, and the material of the pattern definition layer includes amorphous silicon. Accordingly, the pattern definition layer is formed using a selective epitaxial growth process.

[0052] In other embodiments, the target pattern may also be a trench to be formed into an interconnect structure, and the material of the pattern definition layer is a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9) or an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative permittivity less than 2.6) or other dielectric materials.

[0053] refer to Figures 10 to 13Discrete mask layers 102 (e.g., ...) are formed on the pattern definition layer 101. Figure 13 As shown), the mask layer 102 and the substrate 100 form an opening, and the opening in the first region I serves as the first opening 103 (as shown). Figure 13 As shown), the opening in the second region II serves as the second opening 104 (as shown). Figure 13 (As shown).

[0054] Specifically, the pattern definition layer 101 is formed on the substrate 100, and in the step of forming the mask layer 102, the opening is surrounded by the pattern definition layer 101 and the mask layer 102.

[0055] The mask layer 102 serves as an etching mask for etching the pattern definition layer 101 to form the target pattern; the second opening 104 provides process space for the subsequent formation of the filling layer; the first opening 103 exposes the pattern definition layer 101, preparing for the subsequent etching of the pattern definition layer 101 to form the target pattern.

[0056] The mask layer 102 is made of a material that can act as a mask and is easy to remove, so that damage to the target pattern formed afterward is reduced when the mask layer 102 is removed, which is beneficial to improving the formation quality of the target pattern.

[0057] Specifically, the step of forming a mask layer 102 on the pattern definition layer 101 includes:

[0058] like Figure 10 As shown, a mask material layer 109 is formed on the pattern definition layer 101.

[0059] The mask material layer 109 prepares for the subsequent formation of the mask layer 102.

[0060] In this embodiment, the material of the mask material layer 109 includes one or more of the following: silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, silicon boron nitride, and silicon boron carbide.

[0061] Continue to refer to Figure 10 A photoresist material layer 110 is formed on the mask material layer 109.

[0062] The photoresist material layer 110 is then patterned to form a photoresist layer.

[0063] In this embodiment, the photoresist material layer 110 is formed using a spin-on process.

[0064] It should be noted that the method for forming the semiconductor structure includes: after forming a mask material layer 109, before forming a photoresist material layer 110 on the mask material layer 109, forming an organic material layer (not shown in the figure) and an anti-reflective coating (not shown in the figure) on the mask material layer 109.

[0065] In this embodiment, the organic material layer includes organic materials, such as one or more of the following: ODL (organic dielectric layer), DUO (Deep UV Light Absorbing Oxide), and APF (Advanced Patterning Film).

[0066] Materials used for anti-reflective coatings include DARC (dielectric anti-reflective coating) or BARC (bottom anti-reflective coating).

[0067] like Figure 11 As shown, the method for forming the semiconductor structure further includes: providing a mask 200, the mask 200 including a first mask region i and a second mask region ii located between the first mask region i, the first mask region i having a first pattern 201, and the second mask region ii having a second pattern 202.

[0068] In the mask 200 provided in this application embodiment, the extension direction perpendicular to the second pattern 202 is taken as the lateral direction, and the lateral dimension of the second pattern 202 is relatively large. This reduces the manufacturing difficulty and cost of the mask 200 and is conducive to improving the formation efficiency of the mask 200.

[0069] In the extension direction of the second pattern, the second pattern 202 is a continuous pattern. Compared with the second pattern being a discontinuous pattern in the extension direction of the second pattern, in the subsequent process of patterning the photoresist material layer 110 according to the mask 200 to form a photoresist layer, the second pattern 202 is more likely to optimize the pattern density of the entire first pattern 201, improve the contrast of the first pattern 201, and help reduce the line width roughness and line edge roughness of the subsequently formed photoresist layer sidewalls.

[0070] In this embodiment, mask 200 refers to a layout file designed using EDA tools. Typically, the layout file is a layout file that has passed DRC (design rule check) verification.

[0071] In this embodiment, the file format of the mask 200 is GDS format. In other embodiments, the file format of the layout may also be other formats such as OASIS.

[0072] Subsequently, the mask layer is formed based on the mask 200, wherein the first pattern 201 corresponds to the first opening and the second pattern 202 corresponds to the second opening.

[0073] In this embodiment, the extension direction of the first graphic 201 is the same as the extension direction of the second graphic 202.

[0074] The extension direction of the first pattern 201 is the same as that of the second pattern 202, so the second pattern 202 and the first pattern 201 do not intersect. Subsequently, the photoresist material layer 110 is exposed according to the mask 200 to form the photoresist layer 111. During this process, the second pattern 202 optimizes the pattern density of the first pattern 201 and improves the contrast of the first pattern 201, resulting in a smaller line width roughness and line edge roughness on the sidewalls of the photoresist layer 111. Thus, the mask material layer 109 is etched using the photoresist layer 111 as a mask, resulting in a smaller line width roughness and line edge roughness on the sidewalls of the first opening. This further etches the pattern definition layer 101 exposed by the first opening, resulting in a smaller line width roughness and line edge roughness on the target pattern, and thus a better formation quality of the target pattern.

[0075] In this embodiment, the dimension of the first pattern 201 in the extension direction is less than or equal to the dimension of the second pattern 202 in the extension direction.

[0076] The dimension of the first pattern 201 in the extension direction is less than or equal to the dimension of the second pattern 202 in the extension direction. Therefore, during the exposure process of the photoresist material layer 110 based on the mask 200 to pattern the photoresist material layer 110, the second pattern 202 can optimize the pattern density of the entire first pattern 201 and improve the contrast of the first pattern 201, making the line width roughness and line edge roughness of the sidewall of the photoresist layer 111 smaller. Thus, by etching the mask material layer 109 with the photoresist layer 111 as a mask, the line width roughness and line edge roughness of the first opening sidewall formed are smaller, and then the pattern definition layer 101 exposed by the first opening is etched, resulting in a target pattern with smaller line width roughness and line edge roughness, and the formation quality of the target pattern is better.

[0077] It should be noted that in this embodiment, the number of second patterns 202 between the first patterns 201 is one. In other embodiments, the number of second patterns between the first patterns can also be multiple. Compared with the number of second patterns being one, when the number of multiple second patterns is multiple, the contrast of the first pattern is better during the process of patterning the photoresist material layer according to the mask to form the photoresist layer, thereby the line width roughness and line edge roughness of the formed photoresist layer sidewalls are smaller.

[0078] In the step of providing the mask 200, the lateral direction is perpendicular to the extension direction of the second pattern 202, and the lateral dimension of the second pattern 202 is smaller than the lateral dimension of the first pattern 201. Subsequently, the lateral direction is parallel to the surface of the substrate 100 and perpendicular to the extension direction of the mask layer; correspondingly, the lateral dimension of the second opening is smaller than the lateral dimension of the first opening.

[0079] In the method for forming the semiconductor structure, a filling layer is subsequently formed in the second opening. The step of forming the filling layer includes: conformally covering the mask layer and the pattern definition layer 101 exposed by the mask layer with a filling material layer; removing the filling material layer at the bottom of the first opening and the filling material layer at the top of the mask layer, with the remaining filling material layer in the second opening serving as the filling layer. If the lateral dimension of the second opening is greater than or equal to the lateral dimension of the first opening, when the filling layer is formed in the second opening, the first opening is also filled with a filling material layer. That is, the mask layer, the filling layer, and the filling material layer in the first opening completely cover the pattern definition layer 101, making it impossible to subsequently etch the pattern definition layer 101 using the mask layer and the filling layer as masks to form the target pattern.

[0080] It should be noted that in the step of providing the mask 200, the ratio of the lateral dimension of the second pattern 202 to the lateral dimension of the first pattern 201 should not be too large or too small. If the ratio is too large, during the subsequent exposure processing of the photoresist material layer 110 based on the mask 200 to pattern the photoresist material layer 110, the second pattern 202 will have a significant impact on the first pattern 201, resulting in a large process variation band (PVBand). The second pattern 202 will not significantly improve the contrast of the first pattern 201, resulting in large linewidth roughness and line edge roughness of the photoresist layer sidewalls. Consequently, the linewidth roughness and line edge roughness of the first opening sidewall formed by etching the mask material layer 109 based on the photoresist layer will be large, and the linewidth roughness and line edge roughness of the target pattern sidewall formed by etching the pattern definition layer 101 exposed by the first opening using the mask layer as a mask will be large, resulting in poor formation quality of the target pattern. If the ratio is too small, during the exposure and patterning of the photoresist material layer 110 based on the mask 200, the second pattern 202's effect on optimizing the pattern density of the first pattern is not significant. Consequently, the second pattern 202's effect on improving the contrast of the first pattern 201 is not significant, resulting in large linewidth roughness and line edge roughness on the sidewalls of the photoresist layer. Consequently, the linewidth roughness and line edge roughness of the first opening sidewall formed by etching the mask material layer 109 based on the photoresist layer are also large. Consequently, the linewidth roughness and line edge roughness of the target pattern sidewall formed by subsequently etching the pattern definition layer 101 exposed by the first opening using the mask layer as a mask are also large, resulting in poor formation quality of the target pattern. In this embodiment, in the step of providing the mask 200, the ratio of the lateral dimension of the second pattern 202 to the lateral dimension of the first pattern 201 is one-third to one.

[0081] like Figure 12 As shown, the photoresist material layer 110 is patterned according to the photomask 200 to form a photoresist layer 111.

[0082] In this embodiment of the application, the photoresist material layer 110 is patterned according to the photomask 200 to form the photoresist layer 111. During this process, the second pattern 202 can optimize the pattern density of the first pattern 201 and improve the contrast of the first pattern 201, so that the line width roughness and line edge roughness of the sidewalls of the photoresist layer 111 are smaller. As a result, during the subsequent etching of the mask material layer 109 using the photoresist layer 111 as a mask to form the mask layer, the line width roughness and line edge roughness of the sidewalls of the mask layer are smaller.

[0083] The photoresist layer 111 is used to prepare for the subsequent etching of the mask material layer 109.

[0084] In this embodiment, the photoresist material layer 110 is patterned by exposing the photoresist material layer 110 to the mask 200 to form the photoresist layer 111.

[0085] It should be noted that during the process of patterning the photoresist material layer 110 to form the photoresist layer 111, a first groove 301 is formed based on the first pattern 201, and a second groove 302 is formed based on the second pattern 202. The smaller linewidth roughness and line edge roughness of the sidewalls of the photoresist layer 111 means that the linewidth roughness and line edge roughness of the sidewalls of the first groove 301 and the second groove 302 are smaller. Subsequently, the mask material layer 109 exposed by the first groove 301 is etched to form a first opening, and the mask material layer exposed by the second groove 302 is etched to form a second opening.

[0086] It should be noted that, subsequently, the mask material layer 109 is etched using the photoresist layer 111 as a mask to form a mask layer. Simultaneously, while forming a filling layer in the second opening, a filling sidewall is formed on the sidewall of the mask layer in the first region I. This filling sidewall reduces the lateral dimension of the first opening, resulting in a smaller lateral dimension of the target pattern formed by subsequent etching of the pattern material layer exposed through the first opening. To ensure that the lateral dimension of the final target pattern meets the process requirements, the lateral dimension of the first pattern 201 is slightly larger during the provision of the mask 200.

[0087] like Figure 13 As shown, the photoresist layer 111 is used as a mask to etch the mask material layer 109 to form the mask layer 102. The first opening 103 corresponds to the first pattern 201, and the second opening 104 corresponds to the second pattern 202.

[0088] Although the second pattern 202 is transferred to form the second opening 104 in the step of forming the mask layer 102 according to the mask 200, the mask for finally etching the pattern definition layer 101 can still be obtained by forming a filling layer in the second opening 104, so that the target pattern formed with the mask layer 102 and the filling layer as the mask meets the process requirements. Moreover, because the line width roughness and line edge roughness of the sidewall of the first opening 103 are small, the line width roughness and line edge roughness of the corresponding target pattern sidewall are also small, which is beneficial to improving the electrical performance of the semiconductor structure.

[0089] In this embodiment, the photoresist layer 111 is used as a mask, and a dry etching process is employed to etch the mask material layer 109 to form the mask layer 102. The dry etching process has anisotropic etching characteristics, providing good control over the etching profile. This helps to minimize the linewidth roughness and edge roughness of the sidewalls of the first opening 103, and also improves the removal efficiency of the mask material layer 109. In the step of etching the mask material layer 109 using the dry etching process, the top of the pattern definition layer 101 can be used as the etching stop position, reducing damage to other film layers.

[0090] refer to Figure 14 and Figure 15 A filling layer 105 is formed in the second opening 104.

[0091] A fill layer 105 is formed between the mask layers 102 in the second region II. Subsequently, the pattern definition layer 101 is etched using the mask layers 102 and the fill layer 105 as masks to form the target pattern. Because the linewidth roughness and line edge roughness of the sidewalls of the mask layer 102 are relatively small, the formation quality of the target pattern formed using the mask layers 102 and the fill layer 105 as masks is good, which is beneficial to improving the electrical performance of the semiconductor structure.

[0092] It should be noted that, in the step of forming the filling layer 105 in the second opening 104, a filling sidewall 107 is also formed on the sidewall of the first opening 103.

[0093] In this embodiment, the filler sidewall 107 does not need to be removed. In subsequent processes, the pattern definition layer 101 is etched using the mask layer 102, the filler layer 105, and the filler sidewall 107 as masks to form the target pattern. During the process of providing the mask 200, the lateral dimension of the first pattern 201 is slightly larger, and the lateral dimension of the corresponding first opening 103 is also slightly larger. The filler sidewall 107 serves to reduce the lateral dimension of the first opening 103, so that the final target pattern meets the process requirements.

[0094] Specifically, the step of forming a fill layer 105 between the mask layers 102 in the second region II includes: conformally covering the mask layers 102 and the exposed pattern definition layer 101 of the mask layers 102 with a fill material layer 106, the thickness of the fill material layer 106 being twice greater than the lateral dimension of the second opening 104; removing the fill material layer 106 at the bottom of the first opening 103 and the fill material layer 106 at the top of the mask layers 102, with the remaining fill material layer 106 in the second opening 104 serving as the fill layer 105.

[0095] In this embodiment, the filler material layer 106 is formed using atomic layer deposition (ALD). ALD is a self-limiting reaction process based on atomic layer deposition, resulting in a film with a thickness of a single atom. Because ALD can precisely deposit one atomic layer per cycle, it facilitates precise control over the thickness of the filler material layer 106. Furthermore, the filler material layer 106 prepared by ALD exhibits good bonding strength, consistent film thickness, good compositional uniformity, and good shape retention, which helps improve the density and reduce the porosity of the filler material layer 106. In other embodiments, the filler material layer can also be formed using chemical vapor deposition (CVD).

[0096] In this embodiment, a maskless dry etching process is used to remove the filling material layer 106 at the bottom of the first opening 103 and the filling material layer 106 at the top of the mask layer 102. Using a maskless dry etching process eliminates the need for a photomask, reducing the process cost of forming the filling layer 105. Furthermore, the maskless dry etching process has anisotropic etching characteristics, which helps to ensure complete removal of the filling material layer 106 on the surface of the pattern definition layer 101 and the top of the mask layer 102, while minimizing lateral etching of the filling material layer 106 on the sidewalls of the mask layer 102. Consequently, the formation quality of the filling sidewall 107 is better, and the target pattern formed by etching the pattern definition layer 101 using the filling sidewall 107, the filling layer 105, and the mask layer 102 as masks has better formation quality.

[0097] Specifically, during the process of removing the filler material layer 106 at the bottom of the first opening 103 and the filler material layer 106 at the top of the mask layer 102, the remaining filler material layer 105 located on the sidewall of the mask layer 102 in the first region I serves as the filler sidewall 107.

[0098] refer to Figure 16 Using the mask layer 102 and the fill layer 105 as a mask, the pattern definition layer 101 exposed by the first opening 103 is etched to form the target pattern 108.

[0099] In this embodiment, during the step of forming the target pattern 108, the remaining pattern definition layer 101 serves as the remaining pattern 112, and the target pattern 108 is used to space adjacent remaining patterns 112. Specifically, the remaining pattern 112 is a fin. In other embodiments, the target pattern can also be a pseudo-gate structure. In some other embodiments, the remaining pattern can also be a low-k dielectric material.

[0100] In this embodiment, the pattern definition layer 101 is etched using a dry etching process with the mask layer 102 and the fill layer 105 as masks to form the target pattern 108. The dry etching process has anisotropic etching characteristics, providing good control over the etching profile, which helps ensure that the morphology of the target pattern 108 meets process requirements and also improves the removal efficiency of the pattern definition layer 101. During the etching of the pattern definition layer 101 using the dry etching process, the top of the substrate 100 can be used as the etching stop point to reduce damage to other film layers.

[0101] Specifically, in the step of etching the pattern definition layer 101 using the mask layer 102 and the filling layer 105 as masks to form the target pattern 105, the pattern definition layer 101 is also etched using the filling sidewall 107 as a mask to form the target pattern 108.

[0102] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method of forming a semiconductor structure, characterized by, The method comprises the following steps: providing a substrate, the substrate comprising a first region and a second region between the first region; forming a pattern definition layer on the substrate; forming a discrete mask layer on the pattern definition layer, the mask layer and the substrate forming an opening, the opening in the first region being a first opening, the opening in the second region being a second opening; the step of forming a discrete mask layer on the pattern definition layer comprises: forming a mask material layer on the pattern definition layer; forming a photoresist material layer on the mask material layer; providing a mask plate, the mask plate comprising a first mask region and a second mask region between the first mask region, the first mask region having a first pattern, the second mask region having a second pattern; performing a patterning process on the photoresist material layer according to the mask plate to form a photoresist layer; and etching the mask material layer using the photoresist layer as a mask to form the mask layer, the first opening corresponding to the first pattern, and the second opening corresponding to the second pattern; forming a filling layer in the second opening; etching the pattern definition layer exposed by the first opening using the mask layer and the filling layer as a mask to form a target pattern.

2. The method of forming a semiconductor structure of claim 1, wherein, In the step of forming a discrete mask layer on the pattern definition layer, the direction perpendicular to the extension direction of the mask layer and parallel to the surface of the substrate is the transverse direction; the step of forming a filling layer in the second opening comprises: conformally covering a filling material layer on the mask layer and the pattern definition layer exposed by the mask layer, the thickness of the filling material layer being twice greater than the transverse dimension of the second opening; the filling material layer at the bottom of the first opening and the filling material layer on the top of the mask layer are removed, and the remaining filling material layer in the second opening serves as the filling layer.

3. The method of forming a semiconductor structure of claim 2, wherein The filling material layer is formed by an atomic layer deposition process or a chemical vapor deposition process.

4. The method of forming a semiconductor structure of claim 2, wherein, The filling material layer at the bottom of the first opening and the filling material layer on the top of the mask layer are removed by a maskless dry etching process.

5. The method of forming a semiconductor structure of claim 1, wherein In the step of forming a filling layer in the second opening, a filling side wall is also formed on the sidewall of the first opening; In the step of etching the pattern definition layer exposed by the first opening using the mask layer and the filling layer as a mask to form a target pattern, the filling side wall is also used as a mask to etch the pattern definition layer.

6. The method of forming a semiconductor structure of claim 1, wherein, In the step of forming a discrete mask layer on the pattern definition layer, the number of the second openings is one, or the number of the second openings is multiple.

7. The method of forming a semiconductor structure of claim 1, wherein In the step of providing a mask plate, the direction perpendicular to the extension direction of the second pattern is the transverse direction, and the transverse dimension of the second pattern is smaller than the transverse dimension of the first pattern.

8. The method of forming a semiconductor structure according to claim 1 or 7, wherein In the step of providing a mask plate, the ratio of the transverse dimension of the second pattern to the transverse dimension of the first pattern is one third to one.

9. The method of forming a semiconductor structure of claim 1, wherein, In the extension direction of the second pattern, the second pattern is a continuous pattern.

10. The method of forming a semiconductor structure of claim 1, wherein, The extension direction of the first pattern is the same as the extension direction of the second pattern.

11. The method of forming a semiconductor structure of claim 10, wherein, The dimension of the first pattern in the extension direction is smaller than or equal to the dimension of the second pattern in the extension direction.

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