Method for manufacturing a storage capacitor

Abstract

The present invention provides a method for manufacturing a storage capacitor, comprising: providing a semiconductor substrate; forming a first mask layer; etching the first mask layer to form a first trench; forming a second mask layer on the bottom and sidewalls of the first trench and above the first mask layer, such that a second trench is formed; removing the second mask layer above the first mask layer, the first mask layer, and the second mask layer at the bottom of the second trench; sequentially forming a third mask layer, a fourth mask layer, and a fifth mask layer; grinding and thinning the fourth mask layer and the fifth mask layer until the second mask layer is exposed; removing the second mask layer and the fourth mask layer to form a third trench; using the third mask layer, the fourth mask layer, and the fifth mask layer as a barrier layer to etch the semiconductor substrate to form a fourth trench in the semiconductor substrate; removing the third mask layer, the fourth mask layer, and the fifth mask layer; forming a dielectric layer and a conductive layer, and this method can reduce the process complexity and production cost.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and particularly to a method for manufacturing a storage capacitor. Background Art

[0002] Generally, a unit storage cell of a storage capacitor includes a storage capacitor and a MOS transistor. To increase its storage density, more storage cells need to be integrated per unit area and more information needs to be stored in each unit storage cell. With the improvement of the integration degree of semiconductor technology and the requirements for chip performance, the chip area is continuously reduced. To integrate more storage cells per unit area, the required lithography steps increase, and the requirements for the lithography process become higher and higher, correspondingly increasing the process complexity and production cost.

[0003] Therefore, it is necessary to provide a new method for manufacturing a storage capacitor to improve the above problems existing in the prior art. Summary of the Invention

[0004] The purpose of the present invention is to provide a method for manufacturing a storage capacitor, which can reduce the requirements for the lithography accuracy of a lithography machine on the premise of ensuring the performance of the storage capacitor, thereby reducing the process complexity and production cost.

[0005] To achieve the above purpose, a method for manufacturing a storage capacitor of the present invention includes:

[0006] Providing a semiconductor substrate; forming a first mask layer on the semiconductor substrate; etching the first mask layer to form a first trench; forming a second mask layer on the bottom and side walls of the first trench and above the first mask layer, so as to form a second trench, wherein the groove width and groove depth of the second trench are both smaller than those of the first trench; removing the second mask layer above the first mask layer, the first mask layer, and the second mask layer at the bottom of the second trench; sequentially forming a third mask layer on the remaining second mask layer, a fourth mask layer on the third mask layer, and a fifth mask layer on the fourth mask layer; grinding and thinning the fourth mask layer and the fifth mask layer until the second mask layer is exposed; removing the second mask layer and the fourth mask layer to form a third trench; using the third mask layer, the fourth mask layer, and the fifth mask layer around the third trench as a barrier layer to etch the semiconductor substrate to form a fourth trench in the semiconductor substrate; removing the third mask layer, the fourth mask layer, and the fifth mask layer as the barrier layer above the fourth trench; forming a dielectric layer and a conductive layer on the fourth trench.

[0007] Optionally, forming a dielectric layer and a conductive layer on the fourth trench includes:

[0008] Form an insulating layer on the sidewalls of the fourth trench, the bottom of the fourth trench, and the semiconductor substrate; form a first dielectric layer on the insulating layer; form a first conductive layer on the first dielectric layer; form a second dielectric layer on the first conductive layer; form a second conductive layer on the second dielectric layer.

[0009] Optionally, the method further includes: forming a third dielectric layer on the second conductive layer and performing a planarization process; etching the third dielectric layer to form a via hole to expose the first conductive layer and the second conductive layer.

[0010] Optionally, the method further includes: filling a third conductive layer in the via hole and etching the third conductive layer to complete metal interconnection.

[0011] Optionally, the materials of the first mask layer, the second mask layer, the third mask layer, the fourth mask layer, and the fifth mask layer are all silicon nitride.

[0012] Optionally, the material of the insulating layer is at least one of materials with a dielectric constant greater than 3.9.

[0013] Optionally, the material of the insulating layer includes at least one of zirconium dioxide, aluminum oxide, silicon nitride, hafnium dioxide, yttrium trioxide, silicon dioxide, tantalum pentoxide, lanthanum oxide, and titanium dioxide.

[0014] Optionally, the material of the conductive layer is copper, aluminum, or tungsten.

[0015] The beneficial effect of the manufacturing method of the storage capacitor provided by the present invention is that: the above manufacturing method can complete etching with high lithography accuracy under the production conditions of using ordinary photoresist. The groove width of the finally manufactured trench is relatively narrow, which helps to increase the surface area of the capacitor and improve the capacitance of the storage capacitor. On the premise of ensuring the performance of the storage capacitor, the requirement for the lithography accuracy of the lithography machine is reduced, thereby reducing the process complexity and production cost. Description of the Drawings

[0016] Figure 1 It is a flowchart of a manufacturing method of a storage capacitor provided by the present invention;

[0017] Figure 2 It is a schematic diagram of an intermediate structure of some embodiments of the present invention;

[0018] Figure 3 It is a schematic diagram of an intermediate structure of some other embodiments of the present invention;

[0019] Figures 4A to 4J It is a schematic diagram of an intermediate structure in some other embodiments of the present invention;

[0020] Figure 4K Schematic diagram of a storage capacitor structure provided by the present invention.

[0021] Reference numerals in the figure:

[0022] 01 First trench; 02 Second trench; 03 Third trench; 04 Fourth trench; 05 Through hole; 100 Semiconductor substrate

[0023] 201 First mask layer; 202 Second mask layer; 203 Third mask layer; 204 Fourth mask layer; 205 Fifth mask layer

[0024] 301 Insulating layer; 302 First dielectric layer; 303 First conductive layer; 304 Second dielectric layer; 305 Second conductive layer; 306 Third dielectric layer; 307 Third conductive layer Detailed implementation manners

[0025] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the present invention. Apparently, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein shall have the ordinary meanings understood by those of ordinary skill in the art in the field to which the present invention belongs. The words such as "including" used herein mean that the elements or items appearing before this word cover the elements or items listed after this word and their equivalents, without excluding other elements or items.

[0026] Figure 1 Shows a schematic flowchart of a manufacturing method of a storage capacitor. Figure 2 Each structural diagram in shows a schematic diagram of the phased intermediate structure in each process preparation stage in this example.

[0027] See Figure 1 , the manufacturing method of the storage capacitor provided by the embodiment of the present invention includes the following steps:

[0028] S101, provide a semiconductor substrate 100.

[0029] Exemplarily, as shown in (a) in Figure 2 , the semiconductor substrate 100 may be an N-type or P-type silicon substrate. The material of the semiconductor substrate 100 includes one or more combinations of silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, indium gallium, and the semiconductor substrate 100 may also be a silicon semiconductor substrate on insulator or a germanium semiconductor substrate on insulator.

[0030] S102, form a first mask layer 201 on the semiconductor substrate 100.

[0031] Exemplarily, as Figure 2 shown in (a) of [], the first mask layer 201 can be any one or more of silicon nitride, silicon carbide, silicon oxynitride, or silicon carbonitride.

[0032] S103, etch the first mask layer 201 to form a first trench 01.

[0033] Exemplarily, as Figure 2 shown in (b) of [], by coating photoresist on the first mask layer 201 and then performing patterned etching, the first trench 01 as shown in the figure can be formed. The photoresist used in this step can be a relatively inexpensive photoresist.

[0034] S104, form a second mask layer 202 on the bottom and sidewalls of the first trench 01 and above the first mask layer 201, such that a second trench 02 is formed, and the groove width and groove depth of the second trench 02 are both smaller than those of the first trench 01.

[0035] Exemplarily, as Figure 2 shown in (c) of [], remove the photoresist coated on the first mask layer 201, and then deposit a layer of polysilicon, the second trench 02 as shown in the figure can be formed. The polysilicon can be any one or more of silicon nitride, silicon carbide, silicon oxynitride, or silicon carbonitride. The photoresist used in this step can still be a relatively inexpensive photoresist.

[0036] S105, remove the second mask layer 202 above the first mask layer, the first mask layer 201, and the second mask layer 202 at the bottom of the second trench 02.

[0037] Exemplarily, after one etching, remove the second mask layer 202 above the first mask layer 201 and the second mask layer 202 at the bottom of the second trench 02. After that, the structures of the remaining first mask layer 201 and second mask layer 202 are as Figure 2 shown in (d) of []. After that, further through one more etching, remove the remaining first mask layer 201, and the structure of the remaining second mask layer 202 is as Figure 2 shown in (e) of [].

[0038] S106, sequentially form a third mask layer 203 on the remaining second mask layer 202, a fourth mask layer 204 on the third mask layer 203, and a fifth mask layer 205 on the fourth mask layer 204.

[0039] Exemplarily, as Figure 3As shown in (a) of FIG. 1 , a third mask layer 203 is formed on the semiconductor substrate, and then, further, as shown in FIG. Figure 3 As shown in (b) in FIG. 1 , a fourth mask layer 204 is formed on the surface of the third mask layer 203; then, as shown in FIG. Figure 3 As shown in (c), a fifth mask layer 205 is formed on the surface of the fourth mask layer 204. The third mask layer 203, the fourth mask layer 204 or the fifth mask layer 205 can be polysilicon, which can be any one or more of silicon nitride, silicon carbide, silicon oxynitride or silicon carbonitride.

[0040] S107 , grinding and thinning the fourth mask layer 204 and the fifth mask layer 205 until the second mask layer 202 is exposed.

[0041] For example, Figure 3 The intermediate structure shown in (c) is ground to be thinned to expose the second mask layer 202, as shown in FIG. Figure 3 As shown in (d) in .

[0042] S108 , removing the second mask layer 202 and the fourth mask layer 203 to form a third trench 03 .

[0043] Exemplarily, by wet etching or dry etching, the Figure 3 The entire second mask layer 202 shown in (d) and a portion of the fourth mask layer 203 are formed as shown in FIG. Figure 3 The third groove 03 shown in (e).

[0044] S109 , using the third mask layer 203 , the fourth mask layer 204 , and the fifth mask layer 205 around the third trench 03 as barrier layers, etching the semiconductor substrate 100 to form a fourth trench 04 in the semiconductor substrate 100 .

[0045] For example, the third mask layer 203, the fourth mask layer 204, and the fifth mask layer 205 around the third trench 03 are used as barrier layers. Figure 3 The third trench 03 shown in (e) is patterned and etched, thereby etching a portion of the semiconductor substrate 100, thereby forming a fourth trench 04 in the semiconductor substrate 100, as shown in FIG. Figure 3 As shown in (f) in FIG. 1 , it can be seen from the figure that the width of the fourth trench 04 is relatively narrow, which helps to increase the surface area of ​​the capacitor and improve the capacity of the storage capacitor.

[0046] S110 , removing the third mask layer 203 , the fourth mask layer 204 , and the fifth mask layer 205 which serve as barrier layers above the fourth trench.

[0047] Exemplarily, the intermediate structure after removing the third mask layer 203 as the barrier layer, the fourth mask layer 204, and the fifth mask layer 205 above the fourth trench is as Figure 3 shown in (g) of

[0048] S111, forming a dielectric layer and a conductive layer on the fourth trench.

[0049] This step will be further elaborated in detail below in combination with each process in Figure 4.

[0050] As Figure 4A shown, an insulating layer 301 is formed on the sidewall of the fourth trench 04, the bottom of the fourth trench 04, and the semiconductor substrate 100. The material of the insulating layer is at least one of materials with a dielectric constant greater than 3.9. Optionally, the material of the insulating layer includes at least one of zirconia, alumina, silicon nitride, hafnium dioxide, yttrium trioxide, silicon dioxide, tantalum pentoxide, lanthanum oxide, and titanium dioxide. After that, as Figure 4B shown, a first dielectric layer 302 is formed on the insulating layer; as Figure 4C shown, a first conductive layer 303 is formed on the first dielectric layer 302; as Figure 4D shown, a second dielectric layer 304 is formed on the first conductive layer 303; as Figure 4E shown in (a) of Figure 4E , a second conductive layer 305 is formed on the second dielectric layer 302. Then, by adding one photomask to form a lithography window, the edge part of the second conductive layer 305 is etched away to form an intermediate structure as Figure 4F shown in (b) of Figure 4F shown. As Figure 4G shown, a third dielectric layer 306 is formed on the second conductive layer 305. As Figure 4G shown, by etching the third dielectric layer 306 once to expose the second conductive layer 305 and the second dielectric layer 304, and further etching the Figure 4G shown via hole to expose the first conductive layer 303, a via hole 05 is formed as Figure 4H shown. A third conductive layer 307 is filled in the via hole as Figure 4I shown. As Figure 4J and as Figure 4K shown, by coating photoresist and patterning and etching the third conductive layer 307, the metal interconnection is completed. As can be seen from Figure 4K , the above manufacturing method can complete the self-aligned boundary and expand the two second trenches 02 shown in Figure 2 (c) into nine fourth trenches 04 shown in Figure 4A , realizing the fabrication of multiple sidewall patterns.

[0051] In this embodiment, the second conductive layer 305 is the first electrode plate of the capacitor. The second conductive layer 305 is isolated and insulated from the first conductive layer 303 by the second dielectric layer 304. The first conductive layer 303 and the third conductive layer 307 are electrically connected to jointly form the second electrode plate of the storage capacitor. The third dielectric layer 306 and the second dielectric layer 304 jointly form the dielectric between the electrode plates of the storage capacitor.

[0052] In a possible embodiment, for the first conductive layer 303, the second conductive layer 305 or the third conductive layer 307, the material of the conductive layer is copper, aluminum or tungsten.

[0053] In this embodiment, through the above manufacturing method, etching with high lithography accuracy can be completed under the production conditions using ordinary photoresist. Finally, the groove width of the manufactured groove is relatively narrow, which helps to increase the surface area of the capacitor and improve the capacitance of the storage capacitor. On the premise of ensuring the performance of the storage capacitor, the requirement for the lithography accuracy of the lithography machine is reduced, thereby reducing the process complexity and production cost.

[0054] Although the embodiments of the present invention have been described in detail above, it is obvious to those skilled in the art that various modifications and changes can be made to these embodiments. However, it should be understood that such modifications and changes are all within the scope and spirit of the present invention described in the claims. Moreover, the present invention described herein can have other embodiments and can be implemented or realized in various ways.

Claims

1. A method for manufacturing a storage capacitor, characterized in that, comprising: providing a semiconductor substrate; forming a first mask layer on the semiconductor substrate; etching the first mask layer to form a first trench; forming a second mask layer on the bottom and side walls of the first trench and above the first mask layer, such that a second trench is formed, and the groove width and groove depth of the second trench are both smaller than those of the first trench; removing the second mask layer above the first mask layer, the first mask layer, and the second mask layer at the bottom of the second trench; successively forming a third mask layer on the remaining second mask layer, a fourth mask layer on the third mask layer, and a fifth mask layer on the fourth mask layer; grinding and thinning the fourth mask layer and the fifth mask layer until the second mask layer is exposed; removing the second mask layer and the fourth mask layer to form a third trench; using the third mask layer, the fourth mask layer, and the fifth mask layer around the third trench as a barrier layer, etching the semiconductor substrate to form a fourth trench in the semiconductor substrate; removing the third mask layer, the fourth mask layer, and the fifth mask layer that serve as the barrier layer above the fourth trench; forming a dielectric layer and a conductive layer on the fourth trench.

2. The method according to claim 1, characterized in that, forming a dielectric layer and a conductive layer on the fourth trench includes: forming an insulating layer on the side walls of the fourth trench, the bottom of the fourth trench, and the semiconductor substrate; forming a first dielectric layer on the insulating layer; forming a first conductive layer on the first dielectric layer; forming a second dielectric layer on the first conductive layer; forming a second conductive layer on the second dielectric layer.

3. The method according to claim 2, characterized in that, the method further includes: forming a third dielectric layer on the second conductive layer and performing a planarization process; etching the third dielectric layer to form a via hole to expose the first conductive layer and the second conductive layer.

4. The method according to claim 3, characterized in that, further including: filling a third conductive layer in the via hole and etching the third conductive layer to complete metal interconnection.

5. The method according to any one of claims 1 to 4, characterized in that, further including: the materials of the first mask layer, the second mask layer, the third mask layer, the fourth mask layer, and the fifth mask layer are all silicon nitride.

6. The method according to any one of claims 2 to 4, characterized in that, further including: the material of the insulating layer is at least one of materials with a dielectric constant greater than 3.

9.

7. The method according to any one of claims 2 to 4, characterized in that, the material of the insulating layer includes at least one of zirconium dioxide, aluminum oxide, silicon nitride, hafnium dioxide, yttrium trioxide, silicon dioxide, tantalum pentoxide, lanthanum oxide, titanium dioxide.

8. The method according to any one of claims 2 to 4, characterized in that, the material of the conductive layer is copper, aluminum, or tungsten.

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