Semiconductor Structure and Method for Forming the Same

Abstract

The present application provides a semiconductor structure and a method for forming the same. The semiconductor structure includes: a substrate, the substrate including a stacked first wafer and second wafer and a through-silicon via penetrating the second wafer and electrically connecting a first redistribution layer in the first wafer, a second metal wiring layer being formed in the second wafer; a dielectric layer located on the surface of the second wafer; a second redistribution layer located in the dielectric layer, a first portion of the second redistribution layer being electrically connected to the through-silicon via, a second portion of the second redistribution layer being located above the second metal wiring layer; a second via located below the second portion of the second wiring layer and electrically connecting the second portion of the second redistribution layer, the second via not being directly connected to the second metal wiring layer; and a third via located below the second via and electrically connecting the second metal wiring layer and the second via.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a semiconductor structure and a method for forming the same. Background Art

[0002] Through Silicon Vias (TSVs) can be used to connect wafers in 3D integrated packaging. In some 3D integrated packaging processes, the TSVs are not directly connected to the device layer on the stacked wafers, but redistribution layers (RDLs) and vias are required to connect the TSVs and the devices on the stacked wafers to achieve electrical connection.

[0003] However, in the current TSV process, there is still a problem that the sizes of the redistribution layers and vias are too large, resulting in an overly large overall size of the wafer. Therefore, it is necessary to provide more effective and reliable technical solutions. Summary of the Invention

[0004] This application provides a semiconductor structure and a method for forming the same, which can reduce the sizes of the redistribution layers and vias, and thus reduce the overall size of the wafer.

[0005] One aspect of this application provides a method for forming a semiconductor structure, including: providing a substrate, the substrate including a stacked first wafer and second wafer and a TSV passing through the second wafer and electrically connecting a first redistribution layer in the first wafer, and a second metal wiring layer being formed in the second wafer; forming a dielectric layer on the surface of the TSV and on the surface of the second wafer; forming a first trench in the dielectric layer, a first part of the first trench exposing the TSV, and a second part of the first trench being located above the second metal wiring layer; forming a second trench at the bottom of the second part of the first trench and located above the second metal wiring layer, the second trench not exposing the second metal wiring layer; forming a third trench at the bottom of the second trench and exposing the second metal wiring layer; forming a second redistribution layer in the first trench, a second via in the second trench, and a third via in the third trench.

[0006] In some embodiments of this application, the method for forming the first trench, the second trench, and the third trench includes wet etching or dry etching.

[0007] In some embodiments of this application, the method for forming the second redistribution layer, the second via, and the third via includes: filling a conductive material in the first trench, the second trench, and the third trench; and polishing to remove the conductive material higher than the surface of the first trench.

[0008] In some embodiments of the present application, the size of the third through-hole is smaller than that of the second through-hole.

[0009] In some embodiments of the present application, the first wafer further includes a first metal wiring layer, and the first metal wiring layer is electrically connected to the first redistribution layer through a first through-hole.

[0010] In some embodiments of the present application, the semiconductor structure further includes an intermediate dielectric layer located between the first wafer and the second wafer.

[0011] Another aspect of the present application provides a semiconductor structure, including: a substrate, the substrate includes a stacked first wafer and a second wafer and a silicon through-hole penetrating the second wafer and electrically connecting a first redistribution layer in the first wafer, and a second metal wiring layer is formed in the second wafer; a dielectric layer located on the surface of the second wafer; a second redistribution layer located in the dielectric layer, a first portion of the second redistribution layer is electrically connected to the silicon through-hole, and a second portion of the second redistribution layer is located above the second metal wiring layer; a second through-hole located below the second portion of the second redistribution layer and electrically connecting the second portion of the second redistribution layer, and the second through-hole is not directly connected to the second metal wiring layer; a third through-hole located below the second through-hole and electrically connecting the second metal wiring layer and the second through-hole.

[0012] In some embodiments of the present application, the size of the third through-hole is smaller than that of the second through-hole.

[0013] In some embodiments of the present application, the first wafer further includes a first metal wiring layer, and the first metal wiring layer is electrically connected to the first redistribution layer through a first through-hole.

[0014] In some embodiments of the present application, the semiconductor structure further includes an intermediate dielectric layer located between the first wafer and the second wafer.

[0015] For the semiconductor structure and its forming method according to the present application, the second through-hole and the third through-hole are formed by two etching processes, the sizes of the second through-hole and the third through-hole can be reduced, and thus the overall size of the wafer can be reduced; in addition, since the size of the third through-hole is smaller than that of the second through-hole, the diffusion of the metal material in the second through-hole can be avoided, and the device reliability can be improved. Description of the Drawings

[0016] The following drawings detail the exemplary embodiments disclosed in the present application. Wherein the same reference numerals denote similar structures in several views of the drawings. Those of ordinary skill in the art will understand that these embodiments are non-limiting, exemplary embodiments, and the drawings are for illustrative and descriptive purposes only and are not intended to limit the scope of the present application. Embodiments in other ways may also achieve the inventive intent of the present application. It should be understood that the drawings are not drawn to scale. Among them:

[0017] Figure 1 It is a schematic diagram of a semiconductor structure;

[0018] Figures 2 to 7 It is a schematic diagram of the structures of the respective steps in the method for forming the semiconductor structure according to the embodiment of the present application. Detailed implementation manners

[0019] The following description provides specific application scenarios and requirements of the present application, aiming to enable those skilled in the art to manufacture and use the content of the present application. For those skilled in the art, various partial modifications to the disclosed embodiments are obvious, and the general principles defined here can be applied to other embodiments and applications without departing from the spirit and scope of the present application. Therefore, the present application is not limited to the disclosed embodiments, but to the broadest scope consistent with the claims.

[0020] The technical solution of the present invention will be described in detail below in conjunction with the embodiments and the drawings.

[0021] In some methods for forming semiconductor structures, since the size of the TSV is on the order of several micrometers, the RDL can be manufactured using ordinary copper top metal processes. The vias under the RDL can also use ordinary copper top via processes. However, in actual operation, since the thickness of the film between the RDL and the top metal on the stacked wafers is much thicker, the ordinary copper top via process cannot be used because the TSV process requires such a thick film.

[0022] Figure 1 It is a schematic diagram of a semiconductor structure. As Figure 1 shown, the semiconductor structure includes a substrate 100, the substrate 100 includes a first wafer 110 and a second wafer 120 stacked up and down, an intermediate dielectric layer 130 located between the first wafer 110 and the second wafer 120, and a through-silicon via 140 penetrating through the second wafer 120 and the intermediate dielectric layer 130.

[0023] The first wafer 110 includes a first substrate 111 and a first interlayer dielectric layer 112. A first metal wiring layer 113 is formed in the first interlayer dielectric layer 112 to connect active devices (not shown in the figure) in the first substrate 111. The first metal wiring layer 113 is electrically connected to a first redistribution layer 115 through a first via 114.

[0024] Similarly, the second wafer 120 includes a second substrate 121 and a second interlayer dielectric layer 122. A second metal wiring layer 123 is formed in the second interlayer dielectric layer 122 to connect active devices (not shown in the figure) in the second substrate 121. The second metal wiring layer 123 is electrically connected to a second redistribution layer 125 through a second via 124.

[0025] Figure 1 In the semiconductor structure shown, the first via 114 and the second via 124 are relatively large in size, and the first redistribution layer 115 and the second redistribution layer 125 are also relatively large in size, which will have a great impact on the chip size.

[0026] Therefore, to address the above problems, the present application provides a semiconductor structure and a method for forming the same. By etching twice to form the second via and the third via, the sizes of the second via and the third via can be reduced, thereby reducing the overall size of the wafer. In addition, the size of the third via must be smaller than that of the second via to prevent the diffusion of the metal material in the second via and improve the device reliability.

[0027] An embodiment of the present application provides a method for forming a semiconductor structure, including: providing a substrate, the substrate including a stacked first wafer and second wafer and a through-silicon via penetrating the second wafer and electrically connecting the first redistribution layer in the first wafer, and a second metal wiring layer being formed in the second wafer; forming a dielectric layer on the surface of the through-silicon via and the surface of the second wafer; forming a first trench in the dielectric layer, a first part of the first trench exposing the through-silicon via, and a second part of the first trench being located above the second metal wiring layer; forming a second trench at the bottom of the second part of the first trench and located above the second metal wiring layer, the second trench not exposing the second metal wiring layer; forming a third trench at the bottom of the second trench and exposing the second metal wiring layer; forming a second redistribution layer in the first trench, a second via in the second trench, and a third via in the third trench.

[0028] Figures 2 to 7 It is a schematic structural diagram of each step in the method for forming a semiconductor structure according to an embodiment of the present application. The method for forming a semiconductor structure according to an embodiment of the present application will be described in detail below with reference to the accompanying drawings.

[0029] Refer to Figure 2, a substrate 200 is provided, which includes a stacked first wafer 210 and second wafer 220, and a through-silicon via 240 that penetrates the second wafer 220 and electrically connects a first redistribution layer 215 in the first wafer 210. A second metal wiring layer 223 is formed in the second wafer 220.

[0030] Continue to refer to Figure 2 , the first wafer 210 includes a first substrate 211 and a first interlayer dielectric layer 212. Among them, the material of the first substrate 211 includes (i) elemental semiconductors, such as silicon or germanium, etc.; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide, etc.; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium phosphide arsenide or gallium indium phosphide, etc.; or (iv) a combination of the above. The material of the first interlayer dielectric layer 212 includes silicon oxide or silicon nitride, etc.

[0031] In some embodiments of the present application, the first wafer 210 further includes a first metal wiring layer 213, which is located in the first interlayer dielectric layer 212 and electrically connects active devices (not shown in the figure) in the first substrate 211. The first metal wiring layer 213 is also electrically connected to the first redistribution layer 215 through a first via 214. The material of the first metal wiring layer 213 includes copper or aluminum, etc. The material of the first via 214 includes tungsten or copper, etc. The material of the first redistribution layer 215 includes copper or aluminum, etc.

[0032] The second wafer 220 includes a second substrate 221 and a second interlayer dielectric layer 222. Among them, the material of the second substrate 221 includes (i) elemental semiconductors, such as silicon or germanium, etc.; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide, etc.; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium phosphide arsenide or gallium indium phosphide, etc.; or (iv) a combination of the above. The material of the second interlayer dielectric layer 222 includes silicon oxide or silicon nitride, etc. The second metal wiring layer 223 is located in the second interlayer dielectric layer 222 and electrically connects active devices (not shown in the figure) in the second substrate 221. The material of the second metal wiring layer 223 includes copper or aluminum, etc.

[0033] In some embodiments of the present application, the material of the through-silicon via 240 includes copper or tungsten, etc.

[0034] In some embodiments of the present application, the semiconductor structure further includes an intermediate dielectric layer 230 located between the first wafer 210 and the second wafer 220. The through-silicon via 240 also penetrates the intermediate dielectric layer 230.

[0035] In the 3D packaging process of a semiconductor structure, to electrically connect the stacked first wafer 210 and second wafer 220, it is therefore also necessary to electrically connect the second metal wiring layer 223 to the silicon through hole 240. It should be noted that this application only uses two wafers as an example, and the process of this application can also be applied to the stacking process of more than two wafers.

[0036] Reference Figure 3 , a dielectric layer 250 is formed on the surface of the silicon through hole 240 and the surface of the second wafer 220.

[0037] In some embodiments of the present application, the method of forming the dielectric layer 250 includes a chemical vapor deposition process or a physical vapor deposition process.

[0038] In some embodiments of the present application, the material of the dielectric layer 250 includes silicon oxide, silicon nitride, etc.

[0039] Reference Figure 4 , a first trench 260 is formed in the dielectric layer 250. The first part of the first trench 260 exposes the silicon through hole 240, and the second part of the first trench 260 is located above the second metal wiring layer 223. The first trench 260 is used to form a second redistribution layer, so the size of the first trench 260 matches the size of the second redistribution layer.

[0040] In some embodiments of the present application, the method of forming the first trench 260 includes a lithography process and wet etching or dry etching.

[0041] Reference Figure 5 , a second trench 270 located above the second metal wiring layer 223 is formed at the bottom of the second part of the first trench 260, and the second trench 270 does not expose the second metal wiring layer 223.

[0042] In some embodiments of the present application, the method of forming the second trench 270 includes a lithography process, dry etching, wet etching, etc.

[0043] Reference Figure 6 , a third trench 280 exposing the second metal wiring layer 223 is formed at the bottom of the second trench 270.

[0044] In some embodiments of the present application, the method of forming the third trench 280 includes a lithography process and dry etching or wet etching, etc.

[0045] Compared with Figure 1 the semiconductor structure shown in Figure 1The second through hole 124 in [the previous structure] is formed in one go. A trench is formed through one etching process, and then the trench is filled to form the second through hole 124. In such a process, the size of the formed second through hole 124 is relatively large, increasing the overall size of the chip. In the method for forming the semiconductor structure according to the embodiments of the present application, the second trench 270 and the third trench 280 are formed through two etching processes. The amount of etching each time is smaller, and the sizes of the formed second trench 270 and third trench 280 are smaller, which can reduce the size of the overall wafer and improve device performance. The size includes the diameter (the dimension in the horizontal direction in the drawings).

[0046] In some embodiments of the present application, the size of the chip formed by the method for forming the semiconductor structure according to the present application can be reduced by 20% to 40% compared to the size of a conventional chip.

[0047] It should be noted that the embodiments of the present application only take forming two through holes through two etching processes as an example. In practice, more etching processes can also be carried out, such as three or four etching processes, to form four through holes to electrically connect the second redistribution layer and the second metal wiring layer.

[0048] Reference Figure 7 , a second redistribution layer 226 is formed in the first trench 260, a second through hole 225 is formed in the second trench 270, and a third through hole 224 is formed in the third trench 280.

[0049] In some embodiments of the present application, the method for forming the second redistribution layer 226, the second through hole 225, and the third through hole 224 includes: filling a conductive material in the first trench 260, the second trench 270, and the third trench 280; and polishing to remove the conductive material above the surface of the first trench 260.

[0050] In some embodiments of the present application, the conductive material includes a metal material, such as copper, tungsten, aluminum, etc.

[0051] In some embodiments of the present application, the size of the third through hole 224 is smaller than the size of the second through hole 225. This can prevent the metal material in the second through hole 225 from diffusing into the second interlayer dielectric layer 222 and reduce device performance.

[0052] In the method for forming the semiconductor structure according to the present application, the second through hole and the third through hole are formed through two etching processes, which can reduce the sizes of the second through hole and the third through hole, thereby reducing the overall size of the wafer; in addition, the size of the third through hole is smaller than the size of the second through hole, which can prevent the metal material in the second through hole from diffusing and improve device reliability.

[0053] The embodiments of the present application further provide a semiconductor structure. Reference Figure 7, the semiconductor structure includes: a substrate, the substrate includes a stacked first wafer and second wafer and a through-silicon via that penetrates the second wafer and electrically connects a first redistribution layer in the first wafer, and a second metal wiring layer is formed in the second wafer; a dielectric layer, located on the surface of the second wafer; a second redistribution layer, located in the dielectric layer, a first portion of the second redistribution layer electrically connects the through-silicon via, and a second portion of the second redistribution layer is located above the second metal wiring layer; a second via, located below the second portion of the second redistribution layer and electrically connecting the second portion of the second redistribution layer, and the second via is not directly connected to the second metal wiring layer; a third via, located below the second via and electrically connecting the second metal wiring layer and the second via.

[0054] Reference Figure 7 , the semiconductor structure includes a substrate 200, the substrate 200 includes a stacked first wafer 210 and second wafer 220 and a through-silicon via 240 that penetrates the second wafer 220 and electrically connects a first redistribution layer 215 in the first wafer 210, and a second metal wiring layer 223 is formed in the second wafer 220.

[0055] Continue to refer to Figure 7 , the first wafer 210 includes a first substrate 211 and a first interlayer dielectric layer 212. Among them, the material of the first substrate 211 includes (i) elemental semiconductors, such as silicon or germanium, etc.; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide, etc.; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium phosphide arsenide or gallium indium phosphide, etc.; or (iv) a combination of the above. The material of the first interlayer dielectric layer 212 includes silicon oxide or silicon nitride, etc.

[0056] In some embodiments of the present application, the first wafer 210 further includes a first metal wiring layer 213, located in the first interlayer dielectric layer 212, electrically connecting active devices (not shown in the figure) in the first substrate 211, and the first metal wiring layer 213 is also electrically connected to the first redistribution layer 215 through a first via 214. The material of the first metal wiring layer 213 includes copper or aluminum, etc. The material of the first via 214 includes tungsten or copper, etc. The material of the first redistribution layer 215 includes copper or aluminum, etc.

[0057] The second wafer 220 includes a second substrate 221 and a second interlayer dielectric layer 222. Among them, the material of the second substrate 221 includes (i) elemental semiconductors, such as silicon or germanium, etc.; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide, etc.; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium phosphide arsenide or gallium indium phosphide, etc.; or (iv) a combination of the above. The material of the second interlayer dielectric layer 222 includes silicon oxide or silicon nitride, etc. The second metal wiring layer 223 is located in the second interlayer dielectric layer 222 and is electrically connected to active devices (not shown in the figure) in the second substrate 221. The second metal wiring layer 223 is also electrically connected to the second redistribution layer 226 through a second via 225 and a third via 224. The material of the second metal wiring layer 223 includes copper or aluminum, etc. The material of the second via 225 includes tungsten or copper, etc. The material of the third via 224 includes tungsten or copper, etc. The material of the first redistribution layer 215 includes copper or aluminum, etc.

[0058] In some embodiments of the present application, the material of the silicon via 240 includes copper or tungsten, etc.

[0059] In some embodiments of the present application, the semiconductor structure further includes an intermediate dielectric layer 230 located between the first wafer 210 and the second wafer 220. The silicon via 240 also penetrates through the intermediate dielectric layer 230.

[0060] Continuing to refer to Figure 7 , the dielectric layer 250 is located on the surface of the second wafer 220, and the second redistribution layer 226 is located in the dielectric layer 250.

[0061] In some embodiments of the present application, the material of the dielectric layer 250 includes silicon oxide or silicon nitride, etc.

[0062] In some embodiments of the present application, the size of the third via 224 is smaller than the size of the second via 225. This can prevent the metal material in the second via 225 from diffusing into the second interlayer dielectric layer 222 and reduce the device performance.

[0063] Compared with Figure 1 the semiconductor structure shown in Figure 1The second through-hole 124 in [reference] is formed in one go. A trench is formed through one etching process and then filled to form the second through-hole 124. In such a process, the size of the formed second through-hole 124 is relatively large, increasing the overall size of the chip. In the semiconductor structure described in the embodiments of the present application, the second trench and the third trench are formed through two etching processes. The amount of etching each time is small, and the sizes of the formed second trench and third trench are small. Consequently, the sizes of the formed second through-hole 225 and third through-hole 224 are also small, which can reduce the size of the overall wafer and improve device performance. The size includes the diameter (the dimension in the horizontal direction in the drawings).

[0064] In some embodiments of the present application, the size of the semiconductor structure described in the present application can be reduced by 20% to 40% compared with the size of a conventional semiconductor structure.

[0065] It should be noted that the embodiments of the present application only use two etching processes to form two through-holes as an example. In practice, more etching processes can also be performed, such as three or four etching processes, to form four through-holes for electrically connecting the second redistribution layer and the second metal wiring layer.

[0066] In the semiconductor structure described in the present application, the second through-hole and the third through-hole are formed through two etching processes, which can reduce the sizes of the second through-hole and the third through-hole, and thus reduce the overall thickness of the wafer. In addition, the size of the third through-hole is smaller than that of the second through-hole, which can prevent the diffusion of the metal material in the second through-hole and improve device reliability.

[0067] In summary, after reading the content of the present application, those skilled in the art can understand that the foregoing application content can be presented only by way of example and may not be restrictive. Although not explicitly stated here, those skilled in the art can understand that the present application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of the present application.

[0068] It should be understood that the term "and / or" used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may also be an intermediate element.

[0069] Similarly, it should be understood that when an element such as a layer, a region, or a substrate is referred to as being "on" another element, it can be directly on the other element or there can be intervening elements. In contrast, the term "directly" means that there are no intervening elements. It should also be understood that the terms "comprises," "comprising," "includes," or "including," when used in this application, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0070] It should also be understood that although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element in some embodiments may be referred to as a second element in other embodiments without departing from the teachings of this application. The same reference numerals or the same reference designators represent the same elements throughout the specification.

[0071] In addition, the present application's specification describes exemplary embodiments by reference to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Accordingly, variations from the shapes as illustrated, for example due to manufacturing techniques and / or tolerances, are to be expected. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but should include deviations in shapes resulting from, for example, manufacturing. For example, an etched region shown as rectangular will typically have rounded or curved features. Thus, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shape of the regions of the device nor to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a semiconductor structure, characterized in that Comprising: Providing a substrate, the substrate including a stacked first wafer and second wafer and a through-silicon via that penetrates the second wafer and electrically connects a first redistribution layer in the first wafer, and a second metal wiring layer is formed in the second wafer; Forming a dielectric layer on the surface of the through-silicon via and on the surface of the second wafer; Forming a first trench in the dielectric layer, a first portion of the first trench exposing the through-silicon via, and a second portion of the first trench being located above the second metal wiring layer; Forming a second trench at the bottom of the second portion of the first trench and located above the second metal wiring layer, the second trench not exposing the second metal wiring layer; Forming a third trench at the bottom of the second trench and exposing the second metal wiring layer; Forming a second redistribution layer in the first trench, a second via in the second trench, and a third via in the third trench, the size of the third via being smaller than the size of the second via.

2. The method for forming a semiconductor structure as claimed in claim 1, wherein, The method of forming the first trench, the second trench, and the third trench includes wet etching or dry etching.

3. The method for forming a semiconductor structure as claimed in claim 1, wherein The method of forming the second redistribution layer, the second via, and the third via includes: Filling the first trench, the second trench, and the third trench with a conductive material; Grinding and removing the conductive material higher than the surface of the first trench.

4. The method for forming a semiconductor structure according to claim 1, wherein The first wafer further includes a first metal wiring layer, and the first metal wiring layer is electrically connected to the first redistribution layer through a first via.

5. The method for forming a semiconductor structure according to claim 1, wherein, Also including an intermediate dielectric layer located between the first wafer and the second wafer.

6. A semiconductor structure, characterized in that, Comprising: A substrate, the substrate including a stacked first wafer and second wafer and a through-silicon via that penetrates the second wafer and electrically connects a first redistribution layer in the first wafer, and a second metal wiring layer is formed in the second wafer; A dielectric layer located on the surface of the second wafer; A second redistribution layer located in the dielectric layer, a first portion of the second redistribution layer electrically connecting the through-silicon via, and a second portion of the second redistribution layer being located above the second metal wiring layer; A second via located below the second portion of the second redistribution layer and electrically connecting the second portion of the second redistribution layer, the second via not being directly connected to the second metal wiring layer; A third via located below the second via and electrically connecting the second metal wiring layer and the second via, the size of the third via being smaller than the size of the second via.

7. The semiconductor structure according to claim 6, wherein, The first wafer further includes a first metal wiring layer, and the first metal wiring layer is electrically connected to the first redistribution layer through a first via.

8. The semiconductor structure according to claim 6, wherein Also including an intermediate dielectric layer located between the first wafer and the second wafer.

Images