Memory device with vertical channel transistor and method for manufacturing the same

Abstract

The present invention provides a memory device having vertical channel transistors and a method for manufacturing the same. By forming multiple bit lines around the outer wall of the lower portion of a semiconductor pillar, and forming multiple word lines above the multiple bit lines and around the outer wall of the semiconductor pillar via an intermediate insulating layer, the body of the vertical trench transistor can directly contact the semiconductor substrate, thereby preventing the body of the vertical trench transistor from floating, reducing device size, and improving device reliability. Furthermore, the gate stack structure is formed solely through deposition and etching processes, eliminating the need for photolithography and forming word lines without the aid of a photomask. This simplifies the structure and process, allowing the memory device to be expanded to below 10nm using existing equipment and materials.

Description

Technical Field

[0001] The present invention relates to a semiconductor element and a manufacturing method thereof, and in particular to a memory device having a vertical channel transistor and a manufacturing method thereof. Background Art

[0002] Memory manufacturing technology has recently become a crucial component of the semiconductor industry. Dynamic Random Access Memory (DRAM) is a type of volatile memory composed of multiple memory cells. Each cell is primarily composed of a transistor and a capacitor, and each cell is electrically connected to the other via a word line (WL) and a bit line (BL).

[0003] With the continuous development of semiconductor production, the demand for reducing the size of components has gradually increased. However, the use of 8F 2 or 6F 2 Conventional planar or recessed gate transistors in a cell structure (where 'F' represents a feature size in a memory) have difficulty in realizing miniaturized memory devices with line widths of 40 nm or less. Therefore, memory structures with vertical channel transistors have been proposed in the prior art.

[0004] In a vertical channel transistor, a wraparound gate electrode is formed to surround a semiconductor pillar extending vertically above a semiconductor substrate. Source and drain regions are formed above and below the semiconductor pillar, respectively, to create a vertical channel. This allows the channel length to be maintained even when the transistor area is reduced. Summary of the Invention

[0005] Technical problem to be solved by the invention

[0006] However, in existing memory structures with vertical channel transistors, a buried bit line is usually formed in the semiconductor substrate below the semiconductor pillar, which causes the body of the vertical channel transistor to float and reduces device reliability.

[0007] Furthermore, current memory cell structures have reached the limits of cell reliability, resulting in insufficient process margins and reduced device reliability. Further reducing design rules will incur significant costs.

[0008] The present invention is completed to solve the above problems, and its purpose is to provide a memory with vertical channel transistors and a manufacturing method thereof that can avoid the floating of the main body of the vertical trench transistor, reduce the device size, and improve the device reliability.

[0009] Technical solutions to technical problems

[0010] The present invention provides a memory device having a vertical channel transistor, comprising:

[0011] a plurality of semiconductor pillars extending perpendicularly to a horizontal surface of the semiconductor substrate and arranged in an array in a first direction and in a second direction intersecting the first direction, each semiconductor pillar constituting an active region of a vertical channel transistor;

[0012] a plurality of bit lines extending in parallel along the first direction and formed around outer walls of lower portions of the plurality of semiconductor pillars; and

[0013] A plurality of word lines are extended along the second direction and arranged in parallel. The word lines are formed above the plurality of bit lines and around outer walls of the plurality of semiconductor pillars with an intermediate insulating layer between the word lines and the plurality of bit lines.

[0014] Preferably, the word lines are formed symmetrically with respect to the semiconductor pillars in the first direction.

[0015] Preferably, the intermediate insulating layer is an oxide film.

[0016] Preferably, two adjacent bit lines among the plurality of bit lines are isolated from each other by a trench for device isolation.

[0017] Preferably, two adjacent word lines among the plurality of word lines are isolated from each other by an air gap.

[0018] Preferably, the device further includes a storage element electrically connected to a storage node buried in a storage node hole above the semiconductor pillar and the word line.

[0019] Preferably, the storage element is a capacitor.

[0020] Preferably, the unit configuration size of the semiconductor pillar on the semiconductor substrate is 4F 2 , where F is the feature size in the memory.

[0021] The present invention also provides a method for manufacturing a memory having a vertical channel transistor, which comprises the following steps:

[0022] A process of forming a plurality of semiconductor pillars on a semiconductor substrate, wherein the plurality of semiconductor pillars extend perpendicular to a horizontal surface of the semiconductor substrate and are arranged in an array in a first direction and in a second direction intersecting the first direction;

[0023] forming a plurality of bit lines extending in the first direction and arranged in parallel around outer walls of lower portions of the plurality of semiconductor pillars; and

[0024] A process of forming a plurality of word lines extending in parallel along the second direction above the plurality of bit lines and surrounding outer walls of the plurality of semiconductor pillars with an intermediate insulating layer interposed therebetween.

[0025] Preferably, the process of forming the bit line includes: depositing a first oxide layer on the semiconductor substrate on which the multiple semiconductor pillars are formed, and forming a first nitride layer only on the semiconductor substrate; depositing a second oxide layer; etching the second oxide layer, the first nitride layer and the first oxide layer to form a bit line cut and injecting impurities; removing only the first nitride layer and the first oxide layer of the outer wall surrounding the lower part of the multiple semiconductor pillars; depositing a conductive material and etching to form the bit line.

[0026] Preferably, the process of forming the word line includes: depositing a second nitride layer and a third oxide layer in sequence on the intermediate insulating layer; etching the third oxide layer and the second nitride layer to form a vertical channel transistor cut; removing only the second nitride layer surrounding the outer wall of the multiple semiconductor pillars; and depositing gate electrode material and etching to form the word line.

[0027] Preferably, the conductive material is TiN / W, TaN / W or WN / W.

[0028] Preferably, the gate electrode material is high-K dielectric / TiN / W, high-K dielectric / TaN / W or high-K dielectric / WN / W.

[0029] Effects of the Invention

[0030] According to the memory device having a vertical channel transistor and the manufacturing method thereof of the present invention, a plurality of bit lines are formed around the outer wall of the lower portion of a semiconductor column, and a plurality of word lines are formed above the plurality of bit lines and around the outer wall of the semiconductor column via an intermediate insulating layer, so that the main body of the vertical trench transistor can directly contact the semiconductor substrate, thereby preventing the main body of the vertical trench transistor from floating, reducing the device size, and improving the device reliability.

[0031] In addition, according to the memory with vertical channel transistors and the manufacturing method thereof of the present invention, a gate stack structure is formed only by deposition and etching processes, without the need for photolithography processes, and word lines are formed without the aid of photomasks. The structure and process are relatively simple, so that the memory can be expanded to below 10nm by using existing equipment and materials. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 This is a perspective view schematically showing the structure of a vertical channel transistor in a memory device according to an embodiment of the present invention.

[0033] Figure 2AFIG. 1 is a schematic diagram showing a cross-sectional structure of a memory device having vertical channel transistors according to an embodiment of the present invention.

[0034] Figures 2B to 2D 1 and 2 are top views respectively showing a bit line arrangement, a word line arrangement, and a capacitor arrangement in a memory device having vertical channel transistors according to an embodiment of the present invention.

[0035] Figure 3A and Figure 3B FIG. 1 is a schematic cross-sectional view showing a method for manufacturing a memory device having a vertical channel transistor according to an embodiment of the present invention when forming a semiconductor pillar.

[0036] Figures 4A to 4G It is a schematic cross-sectional structure diagram showing a method of manufacturing a memory device having a vertical channel transistor according to an embodiment of the present invention when forming a bit line.

[0037] Figure 5A and Figure 5B FIG. 1 is a schematic cross-sectional view showing a method for manufacturing a memory device having a vertical channel transistor according to an embodiment of the present invention, when an intermediate insulating layer is formed.

[0038] Figures 6A to 6E It is a schematic diagram showing a cross-sectional structure when forming a vertical channel transistor in a method for manufacturing a memory device having a vertical channel transistor according to an embodiment of the present invention.

[0039] Figure 7 FIG. 1 is a schematic cross-sectional structure diagram showing a method for manufacturing a memory device having a vertical channel transistor according to an embodiment of the present invention when an air gap is formed.

[0040] Figures 8A to 8D FIG. 1 is a schematic diagram showing a cross-sectional structure when forming a storage node in a method for manufacturing a memory device having a vertical channel transistor according to an embodiment of the present invention.

[0041] Figure 9 FIG. 1 is a schematic diagram showing a cross-sectional structure when a capacitor is formed in a method for manufacturing a memory device having a vertical channel transistor according to an embodiment of the present invention. DETAILED DESCRIPTION

[0042] The present invention is described more fully below with reference to the accompanying drawings, in which embodiments of the invention are shown. However, the present invention may be implemented in various ways and should not be limited to the embodiments set forth herein. The sizes and relative sizes of layers and regions may be exaggerated in the drawings for clarity.

[0043] For ease of description, spatially relative terms, such as "below," "beneath," "below," "above," and "upper," may be used herein to describe the relationship of one element or feature relative to another element or feature as shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. For example, if the device in the figures is turned over, an element described as "below" or "beneath" another element or feature would then be oriented "above" the other element or feature.

[0044] Embodiments of the present invention are described herein with reference to cross-sectional and top view illustrations, which are illustrations of the principles of idealized embodiments of the present invention. Therefore, embodiments of the present invention should not be constructed to the specific shapes of the regions described herein, but rather include deviations in shape due to, for example, manufacturing processes. For example, an etched region shown as a rectangle will typically have circular or curved properties. Therefore, the regions illustrated in the figures are schematic in nature and are not intended to limit the scope of the present invention.

[0045] Unless otherwise defined, the terms used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present invention belongs. Terms should be understood to have meanings consistent with their meanings in the context of the relevant technology and should not be understood in an idealized or overly formal sense unless explicitly defined herein.

[0046] Below, refer to Figure 1 、 Figures 2A to 2D The structure of a memory device having vertical channel transistors according to an embodiment of the present invention will be described. In this embodiment, DRAM is used as the memory device for description, but the present invention is not limited thereto and other memory devices may also be used.

[0047] Figure 1 This is a perspective view schematically showing the structure of a vertical channel transistor in a memory device according to an embodiment of the present invention. Figure 2A FIG. 1 is a schematic diagram showing a cross-sectional structure of a memory device having vertical channel transistors according to an embodiment of the present invention. Figures 2B to 2D 1 and 2 are top views respectively showing a bit line arrangement, a word line arrangement, and a capacitor arrangement in a memory device having vertical channel transistors according to an embodiment of the present invention.

[0048] like Figures 2A to 2D As shown, a memory device 1 having vertical channel transistors includes a plurality of semiconductor pillars 10 , a plurality of bit lines 20 , and a plurality of word lines 30 .

[0049] A plurality of semiconductor pillars 10 extend perpendicular to the horizontal surface of semiconductor substrate 11 and are arranged in an array in a first direction and in a second direction intersecting the first direction. Each semiconductor pillar 10 constitutes an active region of a vertical channel transistor. At this point, one of the cell transistors of the DRAM cell is electrically connected to a bit line 20 via semiconductor pillar 10.

[0050] In this embodiment, if Figure 2B As shown, the Y direction is set as the first direction, the X direction is set as the second direction, and the X direction is orthogonal to the Y direction, but the present invention is not limited thereto.

[0051] Figure 2A It is along Figure 2B The cross-sectional view in the X-X' direction. Figure 2A and Figure 2B As shown, a plurality of bit lines 20 extend in parallel along the Y direction as a first direction and are formed around the outer walls of the lower portions of the plurality of semiconductor pillars 10. In addition, two adjacent bit lines 20 are isolated from each other by trenches 201 for device isolation.

[0052] In addition, refer to Figure 2A and Figure 2C Multiple word lines 30 are arranged in parallel, extending along the X direction, which serves as a second direction. They are formed above the multiple bit lines 20, surrounding the outer walls of the multiple semiconductor pillars 10 with an intermediate insulating layer 40 between them. Furthermore, adjacent two of the multiple word lines 30 are isolated from each other by air gaps 301. In the DRAM cell disclosed in the present invention, the word lines 30 are formed without the use of a photomask.

[0053] In addition, if Figure 2C As shown, each word line 30 is preferably formed symmetrically with respect to each semiconductor pillar in the Y direction. The intermediate insulating layer 40 is, for example, an oxide film.

[0054] In addition, if Figure 2A and Figure 2D As shown, above semiconductor pillar 10 and word line 30, another junction of each cell transistor of the DRAM cell is electrically connected to storage element 50 via a storage node formed to be buried in a storage node hole. In this embodiment, storage element 50 is a capacitor.

[0055] According to the memory of this embodiment, the required layout area is significantly reduced and it is possible to manufacture Figure 2D 4F shown 2 A single unit of size. Where F is the feature size in the memory.

[0056] In addition, according to Figures 2A to 2D The memory structure shown in the figure can be obtained Figure 1The vertical channel transistor shown as a unit transistor has a body that can directly contact the semiconductor substrate, thereby preventing the body of the vertical channel transistor from floating, reducing the device size, and improving the device reliability.

[0057] In addition, the present invention also provides a method for manufacturing the above-mentioned memory having vertical channel transistors, which includes the following processes: a process of forming a plurality of semiconductor pillars on a semiconductor substrate, wherein the plurality of semiconductor pillars extend perpendicular to the horizontal surface of the semiconductor substrate and are arranged in an array in a first direction and in a second direction intersecting the first direction; a process of forming a plurality of bit lines extending in parallel along the first direction around the outer walls of the lower portions of the plurality of semiconductor pillars; and a process of forming a plurality of word lines extending in parallel along the second direction around the outer walls of the plurality of semiconductor pillars above the plurality of bit lines with an intermediate insulating layer between the plurality of bit lines.

[0058] Next, referring to FIG. 3 to FIG. Figure 9 , specifically describe the above-mentioned manufacturing method.

[0059] <Formation of Semiconductor Pillars>

[0060] Figure 3A and Figure 3B 1 is a schematic diagram showing a cross-sectional structure of a semiconductor pillar formed in a method for manufacturing a memory device having a vertical channel transistor according to an embodiment of the present invention. In this embodiment, silicon pillars are used as semiconductor pillars for illustration, but the present invention is not limited thereto.

[0061] like Figure 3A As shown in FIG. 1 , a substrate insulating film 12 is deposited and formed on a semiconductor substrate 11 on which a substrate oxide film is formed. At this time, the substrate insulating film 12 may be formed of silicon nitride (SiN) or the like.

[0062] During the formation of silicon pillar arrays, Figure 3B As shown, a separation column is formed in a semiconductor substrate 11 having a substrate insulating film 12 formed thereon. At this point, a process for forming the separation column can be performed using a photomask, a process well known to those skilled in the art, and therefore a detailed description thereof is omitted here. Subsequently, channel impurities are implanted into the surface of the column and the horizontal surface of the semiconductor substrate 11 to form a transistor channel for the cell transistor.

[0063] <Formation of Bit Line>

[0064] Figures 4A to 4G It is a schematic cross-sectional structure diagram showing a method of manufacturing a memory device having a vertical channel transistor according to an embodiment of the present invention when forming a bit line.

[0065] like Figure 4A As shown in the previous Figure 3BA first oxide layer 110 and a first nitride layer 111 are sequentially deposited on the structure. The first nitride layer 111 can be made of an insulating material such as SiN. Conventional etching techniques are used to leave only the first nitride layer 111 on the semiconductor substrate 11. Then, a second oxide layer 112 is deposited as an insulating layer. For example, the oxide and insulating film can be planarized using conventional CMP techniques.

[0066] In the process of forming the bit line, such as Figure 4B As shown in the above Figure 4A At this time, a process for forming the bit line cutout CUT1 can be performed using a photomask, which is well known to those skilled in the art, and therefore a detailed description thereof is omitted here. Figure 4C As shown, N+ impurities are implanted into the surface of the bit line cutout CUT1, and the outer wall surrounding the lower portion of the semiconductor column, ie, the first nitride layer and the first oxide layer at the vertical position, are etched away.

[0067] Then, if Figure 4D As shown in FIG, a conductive material is deposited. As the conductive material to be deposited, for example, TiN / W (titanium nitride / tungsten), TaN / W (tantalum nitride / tungsten) or WN / W (tungsten nitride / tungsten) can be used. Then, as shown in FIG. Figure 4E As shown, the deposited conductive material is etched by conventional etching techniques to form bit lines 20. Such etching techniques are well known in the relevant art, and therefore, a detailed description thereof is omitted here.

[0068] When forming the isolation structure between the bit lines, such as Figure 4F As shown in the above Figure 4E The trench 201 is formed by etching. At this time, an etching technique can be used to perform the process of forming the trench 201. This process is well known to those skilled in the art, so its detailed description is omitted here.

[0069] Then, if Figure 4F As shown, P-type ion impurities such as boron (B) ions and boron fluoride (BF 2 ) ions are implanted into the surface of the trench 201 .

[0070] Then, if Figure 4G As shown, the oxide attached to the silicon pillars is removed by etching. This etching technique is well known in the relevant art, so its detailed description is omitted here.

[0071] <Formation of Intermediate Insulating Layer>

[0072] Figure 5A and Figure 5B FIG. 1 is a schematic cross-sectional view showing a method for manufacturing a memory device having a vertical channel transistor according to an embodiment of the present invention, when an intermediate insulating layer is formed.

[0073] like Figure 5A As shown, an intermediate oxide film is deposited as an intermediate insulating layer and a CMP planarization process is performed. Figure 5B As shown, a certain amount of the intermediate oxide film is removed to obtain the intermediate insulating layer 40 . Figure 5B In the figure, the left side is a cross-sectional view along the X direction, the right side is a cross-sectional view along the Y direction, and the following figures are the same. At this time, etching technology can be used to perform Figure 5B This process is well known to those skilled in the art, so its detailed description is omitted here.

[0074] <Formation of Vertical Channel Transistor>

[0075] Figures 6A to 6E It is a schematic diagram showing a cross-sectional structure when forming a vertical channel transistor in a method for manufacturing a memory device having a vertical channel transistor according to an embodiment of the present invention.

[0076] In the process of forming a vertical channel transistor (VCT), as Figure 6A As shown, in Figure 5B A second nitride layer 113 and a third oxide layer 114 are sequentially deposited on the structure, and a planarization process is performed. The second nitride layer 113 is, for example, SiN, and the third oxide layer 114 is, for example, SiO2.

[0077] Further, if Figure 6B As shown in the above Figure 6A A vertical channel transistor cutout CUT2 is formed in the substrate. At this point, a process for forming the vertical channel transistor cutout CUT2 can be performed using a photomask. This process is well known to those skilled in the art, so a detailed description thereof is omitted here. Subsequently, the vertical channel transistor cutout CUT2 is etched using an etching technique. This process is also well known to those skilled in the art, so a detailed description thereof is omitted here.

[0078] In the process of forming a vertical channel transistor, such as Figure 6C As shown, only the above Figure 6B The outer wall of the plurality of semiconductor pillars is surrounded by the second nitride layer 113 in the middle vertical position. At this time, etching technology can be used to Figure 6C The process is well known to those skilled in the art, so its detailed description is omitted here.

[0079] Then, if Figure 6D As shown, a gate electrode material is deposited. The gate electrode material is, for example, high-K dielectric / TiN / W, high-K dielectric / TaN / W or high-K dielectric / WN / W (where K is a dielectric constant). Figure 6DIn the embodiment of the present invention, the deposited gate electrode material is etched by conventional etching techniques to form word lines 30. Such etching techniques are well known in the relevant art. Therefore, a detailed description thereof is omitted here. Thus, word lines 30 are formed without the aid of a photomask.

[0080] During the formation of the gate electrode, Figure 6E As shown, the deposited gate electrode material is removed and a conventional etching technique is used to form a gate electrode. Such etching technique is well known in the relevant art, so a detailed description thereof is omitted here.

[0081] <Formation of Air Gap>

[0082] Figure 7 FIG. 1 is a schematic cross-sectional structure diagram showing a method for manufacturing a memory device having a vertical channel transistor according to an embodiment of the present invention when an air gap is formed.

[0083] like Figure 7 As shown, in Figure 6E A capping oxide is formed on the structure shown, thereby obtaining an air gap 101 .

[0084] <Formation of Storage Nodes>

[0085] Figures 8A to 8D FIG. 1 is a schematic diagram showing a cross-sectional structure when forming a storage node in a method for manufacturing a memory device having a vertical channel transistor according to an embodiment of the present invention.

[0086] In the process of forming storage nodes, such as Figure 8A As shown, CMP planarization is performed, and the top oxide layer of the silicon pillar is removed to expose the storage node. Further, N+ impurities are implanted on the surface of the storage node to form a storage node junction. Figure 8B As shown, selective epitaxial growth (SEG) is performed to deposit a cobalt silicide (Co-Silicidation: CoSix) layer or an N+ polysilicon layer and CMP planarization is performed to form a storage node.

[0087] In the process of forming storage nodes, such as Figure 8C As shown, an interlayer dielectric (ILD) 115 is deposited and CMP planarization is performed.

[0088] Further, if Figure 8D As shown in the above Figure 8C At this time, a process of forming a storage node can be performed using a photomask. This process is well known to those skilled in the art, so its detailed description is omitted here. Figure 8D As shown, a barrier metal 116 such as TiN, WN, TaN, and W is deposited and CMP planarization is performed.

[0089] <Capacitor Formation>

[0090] Figure 9 FIG. 1 is a schematic diagram showing a cross-sectional structure when a capacitor is formed in a method for manufacturing a memory device having a vertical channel transistor according to an embodiment of the present invention.

[0091] like Figure 9 As shown in the above Figure 8D The capacitor 50 is formed on the formed structure. At this time, a process of forming the capacitor can be performed using a photomask, which is well known to those skilled in the art, and thus a detailed description thereof is omitted here.

[0092] In addition, the capacitor material can be deposited on the side surface of the capacitor. In this case, the formation of the capacitor material can sequentially include: depositing a first electrode material on the side surface of the capacitor, the first electrode material including a conductive material 501A and a dielectric material 501B, and then filling the second electrode material 502, the second electrode material 502 being a conductive material.

[0093] Thus, a memory device having vertical channel transistors according to an embodiment of the present invention is finally formed.

[0094] According to the manufacturing method of the memory with vertical channel transistors of this embodiment, the gate stack structure is formed only by deposition and etching processes, without the need for photolithography process, and word lines are formed without the aid of photomasks. The structure and process are relatively simple, so the memory can be expanded to below 10nm by using existing equipment and materials.

[0095] The present invention has been described in detail, but the above embodiments are merely examples of all embodiments and the present invention is not limited thereto. The present invention can freely combine the various embodiments within the scope of the invention, or modify or omit any constituent elements of the various embodiments.

Claims

1. A method for manufacturing a memory device having a vertical channel transistor, characterized in that: Including the following steps: A process of forming a plurality of semiconductor pillars on a semiconductor substrate, wherein the plurality of semiconductor pillars extend perpendicular to a horizontal surface of the semiconductor substrate and are arranged in an array in a first direction and in a second direction intersecting the first direction; The process of providing a plurality of bit lines extending in parallel along the first direction, wherein each bit line is formed around the outer wall of the lower portion of a plurality of semiconductor pillars arranged in the first direction; and A process of providing a plurality of word lines extending in parallel along the second direction above the plurality of bit lines with an intermediate insulating layer between the plurality of bit lines, wherein each word line is formed around the outer walls of a plurality of semiconductor pillars arranged in the second direction; The process of forming the bit line includes: depositing a first oxide layer on the semiconductor substrate on which the plurality of semiconductor pillars are formed, and forming a first nitride layer only on the semiconductor substrate; depositing a second oxide layer; etching the second oxide layer, the first nitride layer, and the first oxide layer to form a bit line cutout and implanting impurities; removing only the first nitride layer and the first oxide layer surrounding outer walls of lower portions of the plurality of semiconductor pillars; Conductive material is deposited and etched to form the bit lines.

2. The method for manufacturing a memory device having a vertical channel transistor according to claim 1, wherein: The process of forming the word line includes: sequentially depositing a second nitride layer and a third oxide layer on the intermediate insulating layer; etching the third oxide layer and the second nitride layer to form a vertical channel transistor cutout; removing only the second nitride layer surrounding outer walls of the plurality of semiconductor pillars; and Gate electrode material is deposited and etched to form the word lines.

3. The method for manufacturing a memory device having a vertical channel transistor according to claim 1, wherein: The conductive material is TiN / W, TaN / W or WN / W.

4. The method for manufacturing a memory device having a vertical channel transistor according to claim 2, wherein: The gate electrode material is high-K dielectric / TiN / W, high-K dielectric / TaN / W or high-K dielectric / WN / W.

5. A memory device having a vertical channel transistor, characterized in that: The memory is obtained by the manufacturing method according to any one of claims 1 to 4.

6. The memory device having a vertical channel transistor according to claim 5, wherein: The word lines are formed symmetrically with respect to the semiconductor pillars in the first direction.

7. The memory device having a vertical channel transistor according to claim 5, wherein: The intermediate insulating layer is an oxide film.

8. The memory device having a vertical channel transistor according to claim 5, wherein: Two adjacent bit lines among the plurality of bit lines are isolated from each other by a trench for device isolation.

9. The memory device having a vertical channel transistor according to claim 5, wherein: Two adjacent word lines among the plurality of word lines are isolated from each other by an air gap.

10. The memory device having a vertical channel transistor according to claim 5, wherein: Also included is a storage element electrically connected to a storage node buried in a storage node hole over the semiconductor pillar and the word line.

11. The memory device having a vertical channel transistor according to claim 10, wherein: The storage element is a capacitor.

12. The memory device having a vertical channel transistor according to any one of claims 5 to 11, wherein: The unit configuration size of the semiconductor pillar on the semiconductor substrate is 4F 2 , where F is the feature size in the memory.

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