Semiconductor memory element

Abstract

The present invention discloses a semiconductor memory element, comprising a select transistor and a floating gate transistor, disposed on a substrate. The select transistor includes a select gate, a select gate oxide layer, and a drain doping region. The floating gate transistor includes a floating gate, a floating gate oxide layer, a source doping region, a first tunneling region doping under the floating gate, a second tunneling region doping, a first tunneling oxide layer on the first tunneling region doping, and a second tunneling oxide layer on the second tunneling region doping. The floating gate oxide layer is between the first tunneling oxide layer and the second tunneling oxide layer. A lightly doped diffusion region surrounds the source doping region and the second tunneling region doping.

Description

Technical Field

[0001] The present invention relates to a semiconductor memory element, and more particularly to a flash memory element having two tunneling oxide layers disposed between a floating gate and a substrate. Background Art

[0002] Flash memory is a non-volatile memory that can store the information content in the memory even in the absence of an external power supply. In recent years, due to the advantages of repeatable writing and electrical erasability of flash memory, it has been widely used in electronic products such as mobile phones, digital cameras, video players, personal digital assistants (PDAs), or in the developing system-on-a-chip (SOC).

[0003] However, in the current flash memory architecture, only a single-sided tunneling oxide layer is usually used for operations such as writing or erasing. This operation mode not only affects the operation speed of the entire memory, but also easily reduces the endurance and lifespan of the memory. Therefore, how to improve the existing architecture and operation mode to enhance the overall endurance of flash memory has become an important issue today. Summary of the Invention

[0004] The main object of the present invention is to provide an improved non-volatile semiconductor memory element to solve the deficiencies and drawbacks of the prior art.

[0005] The present invention provides a semiconductor memory element, comprising: a substrate having a first conductivity type, wherein the substrate includes a first active region surrounded by a trench isolation region; a select transistor disposed on the first active region, wherein the select transistor includes a select gate, a select gate oxide layer under the select gate, and a drain doping region having a second conductivity type and adjacent to the select gate; a floating gate transistor disposed on the first active region and close to the select transistor, wherein the floating gate transistor includes a floating gate, a floating gate oxide layer under the floating gate, a source doping region having the second conductivity type and adjacent to the floating gate, a first tunneling region doping under the floating gate and between the floating gate oxide layer and the source doping region, a first tunneling oxide layer on the first tunneling region doping, a second tunneling region doping under the floating gate and between the floating gate dielectric layer and the select gate, and a second tunneling oxide layer on the second tunneling region doping; and a lightly doped diffusion region having the second conductivity type, surrounding the source doping region and the second tunneling region doping.

[0006] According to an embodiment of the present invention, the first conductivity type is P-type and the second conductivity type is N-type.

[0007] According to an embodiment of the present invention, the first tunneling region doping and the second tunneling region doping are N + doping regions.

[0008] According to an embodiment of the present invention, the lightly doped diffusion region is N - doping region.

[0009] According to an embodiment of the present invention, the first tunneling region doping is adjacent to the source doping region.

[0010] According to an embodiment of the present invention, the thickness of the select gate oxide layer is less than the thickness of the floating gate oxide layer.

[0011] According to an embodiment of the present invention, the thickness of the floating gate oxide layer is between 200 angstroms and 380 angstroms.

[0012] According to an embodiment of the present invention, the thickness of the select gate oxide layer is between 50 angstroms and 130 angstroms.

[0013] According to an embodiment of the present invention, the first tunneling oxide layer is directly disposed on the first tunneling region doping, and further, the thickness of the first tunneling oxide layer is less than the thickness of the floating gate oxide layer.

[0014] According to an embodiment of the present invention, the second tunneling oxide layer is directly disposed on the doping of the second tunneling region, and further, the thickness of the second tunneling oxide layer is less than the thickness of the floating gate oxide layer.

[0015] According to an embodiment of the present invention, the thicknesses of the first tunneling oxide layer and the second tunneling oxide layer are between 70 angstroms and 95 angstroms.

[0016] According to an embodiment of the present invention, it further includes: a first peripheral gate oxide layer adjacent to the first tunneling oxide layer, wherein the thickness of the first peripheral gate oxide layer is greater than the thickness of the first tunneling oxide layer.

[0017] According to an embodiment of the present invention, the floating gate has a first edge aligned with an outer edge of the first peripheral gate oxide layer.

[0018] According to an embodiment of the present invention, it further includes: a second peripheral gate oxide layer adjacent to the second tunneling oxide layer, wherein the thickness of the second peripheral gate oxide layer is greater than the thickness of the second tunneling oxide layer.

[0019] According to an embodiment of the present invention, the floating gate has a second edge aligned with an outer edge of the second peripheral gate oxide layer.

[0020] According to an embodiment of the present invention, it further includes: a second active region close to the first active region, wherein the first active region is isolated from the second active region by the trench isolation region, and wherein the floating gate extends from the first active region to the second active region; and a control gate doping region having the second conductivity type, disposed in the second active region.

[0021] According to an embodiment of the present invention, the control gate doping region is an N + doping region.

[0022] According to an embodiment of the present invention, the control gate doping region is capacitively coupled to the floating gate.

[0023] According to an embodiment of the present invention, the lightly doped diffusion region surrounds the control gate doping region. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a layout schematic diagram of a semiconductor memory element illustrated by an embodiment of the present invention;

[0025] Figure 2 is Figure 1 a cross-sectional schematic diagram taken along the tangent line I-I' in

[0026] Figure 3 is Figure 1Schematic cross-sectional view taken along the middle tangent II-II’;

[0027] Figure 4 Voltage condition diagrams for write and erase operations.

[0028] Description of main component symbols

[0029] 1 Semiconductor memory element

[0030] 100 Substrate

[0031] 102 Trench isolation region

[0032] AA1 First active region

[0033] AA2 Second active region

[0034] BN1 First tunneling region doping

[0035] BN2 Second tunneling region doping

[0036] CG Control gate doping region

[0037] D Drain doping region

[0038] CN- Lightly doped diffusion region

[0039] FE1 First edge

[0040] FE2 Second edge

[0041] FT Floating gate transistor

[0042] FG Floating gate

[0043] FGD Floating gate oxide layer

[0044] MC1, MC2 Memory cells

[0045] PD1 First peripheral gate oxide layer

[0046] PD2 Second peripheral gate oxide layer

[0047] PE1 Outer edge

[0048] PE2 Outer edge

[0049] S Source doping region

[0050] ST Selection transistor

[0051] SG Selection gate

[0052] SGD Selection gate oxide layer

[0053] SPF Spacer wall

[0054] TD1 First tunneling oxide layer

[0055] TD2 Second tunneling oxide layer Detailed implementation manners

[0056] In the following, details will be described with reference to the accompanying drawings, the content of which also constitutes a part of the detailed description of the specification and is illustrated in a specific example manner for implementing the embodiment. The following embodiments have described sufficient details to enable those of ordinary skill in the art to implement them.

[0057] Of course, other embodiments may also be adopted, or any structural, logical, and electrical changes may be made without departing from the embodiments described herein. Therefore, the following detailed description should not be considered restrictive. Instead, the embodiments included therein will be defined by the appended claims.

[0058] Please refer to Figures 1 to 3 , in which Figure 1 is a layout schematic diagram of the semiconductor memory element 1 illustrated according to an embodiment of the present invention, Figure 2 is a cross-sectional schematic diagram taken along the tangent line I-I' in Figure 1 , Figure 3 is a cross-sectional schematic diagram taken along the tangent line II-II' in Figure 1 . Among them, Figure 1 the semiconductor memory element 1 illustrated therein includes two memory cells MC1 and MC2 that are mirror-symmetrical with respect to the symmetry axis A. In the following embodiments, a single-poly non-volatile memory element is taken as an example for illustration. However, those skilled in the art should understand that the present invention can also be used in other types of semiconductor memory structures, for example, a stack gate type memory (a control gate is stacked on a floating gate).

[0059] As Figures 1 to 3 shown, the semiconductor memory element 1 includes a substrate 100, for example, a silicon substrate, having a first conductivity type, for example, P-type. Among them, the substrate 100 includes a first active region AA1 surrounded by a trench isolation region 102. According to an embodiment of the present invention, the first active region AA1 may be a long strip-shaped region extending along the reference Y axis. According to an embodiment of the present invention, the semiconductor memory element 1 includes a selection transistor ST disposed on the first active region AA1. According to an embodiment of the present invention, the selection transistor ST includes a selection gate SG, a selection gate oxide layer SGD under the selection gate SG, and a drain doping region D adjacent to the selection gate SG. According to an embodiment of the present invention, the drain doping region D has a second conductivity type, for example, N-type.

[0060] According to an embodiment of the present invention, the semiconductor memory element 1 includes a floating gate transistor FT disposed on the first active region AA1 and adjacent to the select transistor ST. According to an embodiment of the present invention, the floating gate transistor FT includes a floating gate FG, a floating gate oxide layer FGD under the floating gate FG, a source doping region S having a second conductivity type (e.g., N-type) and adjacent to the floating gate FG, a first tunneling region doping BN1 under the floating gate FG and between the floating gate oxide layer FGD and the source doping region S, a first tunneling oxide layer TD1 on the first tunneling region doping BN1, a second tunneling region doping BN2 under the floating gate FG and between the floating gate dielectric layer FGD and the select gate SG, and a second tunneling oxide layer TD2 on the second tunneling region doping BN2.

[0061] As Figure 1 shown, the memory cells MC1 and MC2 share the source doping region S. According to an embodiment of the present invention, the first tunneling region doping BN1 is adjacent to the source doping region S and merged into a doping region. According to an embodiment of the present invention, for example, the first tunneling region doping BN1 and the second tunneling region doping BN2 are N + doping regions.

[0062] According to an embodiment of the present invention, the thickness of the select gate oxide layer SGD is less than the thickness of the floating gate oxide layer FGD. According to an embodiment of the present invention, for example, the thickness of the select gate oxide layer SGD is between 50 angstroms and 130 angstroms. According to an embodiment of the present invention, for example, the thickness of the floating gate oxide layer FGD is between 200 angstroms and 380 angstroms.

[0063] According to an embodiment of the present invention, the first tunneling oxide layer TD1 is directly disposed on the first tunneling region doping BN1. According to an embodiment of the present invention, the thickness of the first tunneling oxide layer TD1 is less than the thickness of the floating gate oxide layer FGD. According to an embodiment of the present invention, the second tunneling oxide layer TD2 is directly disposed on the second tunneling region doping BN2. According to an embodiment of the present invention, the thickness of the second tunneling oxide layer TD2 is less than the thickness of the floating gate oxide layer FGD. According to an embodiment of the present invention, for example, the thicknesses of the first tunneling oxide layer TD1 and the second tunneling oxide layer TD2 are between 70 angstroms and 95 angstroms.

[0064] As Figure 2As shown, the semiconductor memory element 1 includes a first peripheral gate oxide layer PD1 adjacent to the first tunneling oxide layer TD1, wherein the thickness of the first peripheral gate oxide layer PD1 is greater than that of the first tunneling oxide layer TD1. According to an embodiment of the present invention, the floating gate FG has a first edge FE1 aligned with an outer edge PE1 of the first peripheral gate oxide layer PD1. The semiconductor memory element 1 includes a second peripheral gate oxide layer PD2 adjacent to the second tunneling oxide layer TD2, wherein the thickness of the second peripheral gate oxide layer PD2 is greater than that of the second tunneling oxide layer TD2. According to an embodiment of the present invention, the floating gate FG has a second edge FE2 aligned with an outer edge PE2 of the second peripheral gate oxide layer. According to an embodiment of the present invention, a spacer SPF, such as a silicon nitride spacer, but not limited thereto, may be provided on the sidewall of the floating gate FG.

[0065] As Figures 1 to 3 shown, the semiconductor memory element 1 further includes a lightly doped diffusion region (cell N-implant) CN- having a second conductivity type (e.g., N-type), surrounding the source doping region S and the second tunneling region doping BN2. According to an embodiment of the present invention, for example, the lightly doped diffusion region CN- may be an N - doped region.

[0066] As Figure 1 and Figure 3 shown, the semiconductor memory element further includes a second active region AA2 close to the first active region AA1. According to an embodiment of the present invention, for example, the second active region AA2 may be a rectangular region with a width greater than that of the first active region in a reference X-axis direction, but not limited thereto. According to an embodiment of the present invention, the first active region AA1 is isolated from the second active region AA2 by a trench isolation region 102. According to an embodiment of the present invention, the floating gate FG extends from the first active region AA1 to the second active region AA2 and is capacitively coupled to a control gate doping region CG having a second conductivity type (e.g., N-type) provided in the second active region AA2. According to an embodiment of the present invention, the control gate doping region may be an N + doped region. According to an embodiment of the present invention, the lightly doped diffusion region CN- surrounds the control gate doping region CG.

[0067] Please refer to Figure 4 , which illustrates the voltage conditions for write and erase operations. Please also refer to Figures 1 to 3 , for example, when operating on the memory cell MC1, a source voltage V S is provided to the source doping region S, a drain voltage V D is provided to the drain doping region D, a control gate voltage V CG is provided to the control gate doping region CG, and a select gate voltage V SGTo the select gate SG. A method for operating the memory cell MC1 mainly utilizes the first tunneling region doped with BN1 and the second tunneling region doped with BN2 in the structure to improve the endurance of the entire device during operations such as writing and erasing, thereby enhancing the performance and lifespan of the device.

[0068] For example, when performing a program operation on a selected memory cell, such as memory cell MC1, as Figure 4 shown, apply a 5-volt voltage (V S = 5V) to the source doping region S, apply a 0-volt voltage (V D = 0V) to the drain doping region D, apply a 7-volt voltage (V SG = 7V) to the select gate SG, and apply a 9.5-volt voltage to the control gate doping region CG, so that electrons pass through the second tunneling oxide layer TD2 and are stored in the floating gate FG to complete the writing operation. For unselected memory cells, a program inhibit operation can be performed. For example, apply a 5-volt voltage (V S = 5V) to the source doping region S, apply a 5-volt voltage (V D = 5V) to the drain doping region D, apply a 7-volt voltage (V SG = 7V) to the select gate SG, and apply a 9.5-volt voltage to the control gate doping region CG to avoid program disturb.

[0069] When performing an erase operation, as Figure 4 shown, apply a 9.5-volt voltage (V S = 9.5V) to the source doping region S, apply a 2-volt voltage (V D = 0V) to the drain doping region D, apply a 0-volt voltage (V SG = 0V) to the select gate SG, and apply a 0-volt voltage to the control gate doping region CG, so that electrons pass through the first tunneling oxide layer TD1 and move out of the floating gate FG to complete the erase operation. The present invention mainly forms two tunneling oxide layers TD1 and TD2 arranged left and right between the floating gate FG and the substrate 100, and utilizes these two tunneling oxide layers TD1 and TD2 to perform operations such as writing and erasing. In this way, not only can the operating speed of the entire memory be improved, but also the endurance and lifespan of the memory can be extended.

[0070] When the storage unit of the present invention performs a write operation, the select gate SG operates at a relatively low voltage (e.g., 7V). Therefore, it is not necessary to fabricate the select gate transistor ST with high-voltage components (e.g., components with an operating voltage higher than 10V), which is more suitable for the embedded application field. The operating voltage of the present invention is relatively low, so it is relatively power-saving. Due to the lightly doped diffusion region CN- and the two tunneling oxide layers TD1 and TD2 disposed directly below the floating gate FG, the reliability and durability can be improved. In addition, the storage unit of the present invention has a small size and requires fewer photomasks, so it has the advantage of low cost.

[0071] The above are only the preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims

1. A semiconductor memory element, characterized in that, Comprising: A substrate having a first conductivity type, wherein the substrate includes a first active region surrounded by a trench isolation region; A select transistor disposed on the first active region, wherein the select transistor includes a select gate, a select gate oxide layer under the select gate, and a drain doping region having a second conductivity type and adjacent to the select gate; A floating gate transistor disposed on the first active region and adjacent to the select transistor, wherein the floating gate transistor includes a floating gate, a floating gate oxide layer under the floating gate, a source doping region having the second conductivity type and adjacent to the floating gate, a first tunneling region doping under the floating gate and between the floating gate oxide layer and the source doping region, a first tunneling oxide layer on the first tunneling region doping, a second tunneling region doping under the floating gate and between the floating gate dielectric layer and the select gate, and a second tunneling oxide layer on the second tunneling region doping; and A lightly doped diffusion region having the second conductivity type, surrounding the source doping region and the first tunneling region doping, wherein the first tunneling region doping is adjacent to the source doping region.

2. The semiconductor memory element according to claim 1, wherein, The first conductivity type is P-type and the second conductivity type is N-type.

3. The semiconductor memory element according to claim 2, wherein, The first tunneling region doping and the second tunneling region doping are N + doped regions.

4. The semiconductor memory device according to claim 1, wherein, The lightly doped diffusion region is an N - doped region.

5. The semiconductor memory element according to claim 1, wherein, The thickness of the select gate oxide layer is less than the thickness of the floating gate oxide layer.

6. The semiconductor memory element according to claim 5, wherein, The thickness of the floating gate oxide layer is between 200 angstroms and 380 angstroms.

7. The semiconductor memory element according to claim 6, wherein, The thickness of the select gate oxide layer is between 50 angstroms and 130 angstroms.

8. The semiconductor memory element according to claim 1, wherein, The first tunneling oxide layer is directly disposed on the first tunneling region doping, and further, the thickness of the first tunneling oxide layer is less than the thickness of the floating gate oxide layer.

9. The semiconductor memory device according to claim 8, wherein, The second tunneling oxide layer is directly disposed on the second tunneling region doping, and further, the thickness of the second tunneling oxide layer is less than the thickness of the floating gate oxide layer.

10. The semiconductor memory element according to claim 9, wherein, The thicknesses of the first tunneling oxide layer and the second tunneling oxide layer are between 70 angstroms and 95 angstroms.

11. The semiconductor memory element according to claim 1, wherein, Further comprising: A first peripheral gate oxide layer adjacent to the first tunneling oxide layer, wherein the thickness of the first peripheral gate oxide layer is greater than the thickness of the first tunneling oxide layer.

12. The semiconductor memory element according to claim 11, wherein, The floating gate has a first edge aligned with the outer edge of the first peripheral gate oxide layer.

13. The semiconductor memory element according to claim 12, wherein, Further comprising: A second peripheral gate oxide layer adjacent to the second tunneling oxide layer, wherein the thickness of the second peripheral gate oxide layer is greater than the thickness of the second tunneling oxide layer.

14. The semiconductor memory element according to claim 13, wherein, The floating gate has a second edge aligned with the outer edge of the second peripheral gate oxide layer.

15. The semiconductor memory element according to claim 1, wherein, Further comprising: A second active region adjacent to the first active region, wherein the first active region is isolated from the second active region by the trench isolation region, and wherein the floating gate extends from the first active region to the second active region; and A control gate doping region having the second conductivity type, disposed in the second active region.

16. The semiconductor memory element according to claim 15, wherein, The control gate doping region is N + doping region.

17. The semiconductor memory element according to claim 15, wherein, The control gate doping region is capacitively coupled to the floating gate.

18. The semiconductor memory element according to claim 15, wherein, The lightly doped diffusion region surrounds the control gate doping region.

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