Semiconductor device including resistive switching layer and method of manufacturing the same

Abstract

The present disclosure provides a semiconductor device including a resistance change layer and a method of manufacturing the same. The semiconductor device includes a substrate and a gate structure disposed above the substrate. The gate structure includes at least one gate electrode layer and at least one interlayer insulation layer alternately stacked above the substrate. The semiconductor device includes a hole pattern above the substrate penetrating the gate structure, and a gate insulation layer, a channel layer, a resistor layer, and a resistance change layer sequentially disposed on a sidewall surface of the gate structure within the hole pattern. Each of the resistor layer and the resistance change layer is disposed opposite the gate insulation layer based on the channel layer.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean application No. 10-2020-0144704, filed on November 2, 2020, with the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure generally relates to a semiconductor device, and more specifically, to a semiconductor device including a resistive switching layer and a method for manufacturing the same. Background Technology

[0004] Recently, semiconductor devices with three-dimensional structures have been developed from planar structures. Three-dimensional semiconductor devices offer advantages in addressing industry demands for reduced design rules and increased integration density. Specifically, research on three-dimensional structures is actively underway in the field of memory devices requiring high integration and large capacity. Summary of the Invention

[0005] A semiconductor device according to embodiments of the present disclosure may include a substrate and a gate structure disposed above the substrate. The gate structure may include at least one gate electrode layer and at least one interlayer insulating layer alternately stacked above the substrate. The semiconductor device may include a hole pattern penetrating the gate structure above the substrate, and a gate insulating layer, a channel layer, a resistor layer, and a resistive switching layer sequentially disposed within the hole pattern on the sidewall surfaces of the gate structure. Each of the resistor layer and the resistive switching layer is disposed opposite to the gate insulating layer based on the channel layer.

[0006] A semiconductor device according to another embodiment of this disclosure may include a substrate and a gate structure disposed above the substrate. The gate structure may include at least one gate electrode layer and at least one interlayer insulating layer alternately stacked above the substrate along a first direction perpendicular to the substrate, and the gate structure may extend in a second direction perpendicular to the first direction. The semiconductor device may include a gate insulating layer, a channel layer, a resistor layer, and a resistive switching layer sequentially disposed above the substrate on the sidewall surface of the gate structure. Each of the resistor layer and the resistive switching layer is disposed opposite to the gate insulating layer based on the channel layer.

[0007] According to another embodiment of this disclosure, a method for manufacturing a semiconductor device is provided. In this method, a substrate may be provided. A gate structure may be formed over the substrate. The gate structure may include at least one gate electrode layer and at least one interlayer insulating layer alternately stacked over the substrate. A hole pattern may be formed to penetrate the gate structure over the substrate. A gate insulating layer, a channel layer, and an oxide reaction layer may be sequentially formed within the hole pattern on the sidewall surface of the gate structure. A reduction reaction layer may be formed on the oxide reaction layer. A resistor layer, a resistive switching layer, and an insulating layer may be formed by reacting the oxide reaction layer with the reduction reaction layer.

[0008] According to another embodiment of this disclosure, a method for manufacturing a semiconductor device is provided. In this method, a substrate may be provided. A gate structure may be formed over the substrate. The gate structure may include at least one gate electrode layer and at least one interlayer insulating layer alternately stacked over the substrate. A hole pattern may be formed to penetrate the gate structure over the substrate. A gate insulating layer and a channel forming layer may be sequentially formed in the hole pattern on the sidewall surface of the gate structure. A reduction reaction layer may be formed on the channel forming layer. A channel layer, a resistor layer, a resistive switching layer, and an insulating layer may be formed by reacting the channel forming layer with the reduction reaction layer.

[0009] According to another embodiment of this disclosure, a method for manufacturing a semiconductor device is provided. In this method, a substrate may be provided. A gate structure may be formed over the substrate and may extend in a direction parallel to the surface of the substrate. The gate structure may include at least one gate electrode layer and at least one interlayer insulating layer alternately stacked in a direction perpendicular to the surface of the substrate. A gate insulating layer, a channel layer, and an oxide reaction layer may be sequentially formed on the sidewall surface of the gate structure over the substrate. A reduction reaction layer may be formed on the oxide reaction layer. A resistor layer, a resistive switching layer, and an insulating layer may be formed by reacting the oxide reaction layer with the reduction reaction layer.

[0010] According to another embodiment of this disclosure, a method for manufacturing a semiconductor device is provided. In this method, a substrate may be provided. A gate structure may be formed over the substrate and may extend in a direction parallel to the surface of the substrate. The gate structure may include at least one gate electrode layer and at least one interlayer insulating layer alternately stacked in a direction perpendicular to the surface of the substrate. A gate insulating layer and a channel forming layer may be sequentially formed over the substrate on the sidewall surface of the gate structure. A reduction reaction layer may be formed on the channel forming layer. A channel layer, a resistor layer, a resistive switching layer, and an insulating layer may be formed by reacting the channel forming layer with the reduction reaction layer. Attached Figure Description

[0011] Figure 1 This is a perspective view schematically illustrating a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 2 yes Figure 1 A plan view of a semiconductor device.

[0013] Figure 3 It is along Figure 1 A cross-sectional view of a semiconductor device taken from line I-I′.

[0014] Figure 4A and Figure 4B This is a view schematically illustrating a method of operating a semiconductor device according to an embodiment of the present disclosure.

[0015] Figure 5 This is a view illustrating the changes in oxygen vacancies in the resistive switching layer of a semiconductor device according to an embodiment of the present disclosure.

[0016] Figure 6A This is a schematic diagram illustrating the IV characteristics of a semiconductor device according to an embodiment of the present disclosure.

[0017] Figure 6B It is a graph comparing the IV characteristics of a conventional semiconductor device with those of a semiconductor device according to embodiments of the present disclosure.

[0018] Figure 6C This is a schematic diagram illustrating a method for implementing multi-level signals in a semiconductor device according to embodiments of the present disclosure.

[0019] Figure 6D This is a graph schematically illustrating a method for controlling the set voltage of a semiconductor device according to an embodiment of the present disclosure.

[0020] Figure 7A and Figure 7B This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0021] Figure 8A and Figure 8B This is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0022] Figure 9 This is a perspective view schematically illustrating a semiconductor device according to another embodiment of the present disclosure.

[0023] Figure 10 yes Figure 9 A plan view of a semiconductor device.

[0024] Figure 11 It is along Figure 9 A cross-sectional view of the semiconductor device taken from line Ⅱ-Ⅱ′.

[0025] Figure 12This is a circuit diagram of a semiconductor device according to an embodiment of the present disclosure.

[0026] Figure 13 This is a perspective view schematically illustrating a semiconductor device according to another embodiment of the present disclosure.

[0027] Figure 14 yes Figure 13 A plan view of a semiconductor device.

[0028] Figure 15A and Figure 15B This is a cross-sectional view schematically illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0029] Figure 16A and Figure 16B This is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0030] Figure 17 This is a perspective view schematically illustrating a semiconductor device according to yet another embodiment of the present disclosure.

[0031] Figure 18 yes Figure 17 A plan view of a semiconductor device.

[0032] Figure 19 It is along Figure 17 A cross-sectional view of the semiconductor device taken from line Ⅲ-Ⅲ′.

[0033] Figure 20 It is along Figure 17 A cross-sectional view of the semiconductor device taken from line IV-IV′. Detailed Implementation

[0034] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the drawings, the dimensions of the various components, such as the width and thickness of the components, are enlarged to clearly illustrate their parts. The terms used herein may correspond to words chosen in consideration of their function in the embodiments, and the meaning of these terms may be interpreted differently by those skilled in the art to which the embodiments pertain. Where there are explicit and detailed definitions, these terms may be interpreted according to those definitions. Unless otherwise defined, the terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which the embodiments pertain.

[0035] Furthermore, unless explicitly used otherwise in the context, the singular form of a word should be understood to include the plural form of that word. It should be understood that the terms “comprising,” “including,” or “having” are intended to specify the presence of a feature, quantity, step, operation, component, element, part, or combination thereof, but are not intended to exclude the presence or possible addition of one or more other features, quantities, steps, operations, components, elements, parts, or combinations thereof.

[0036] In this specification, the phrase "predetermined direction" can refer to a direction that encompasses a direction defined in a coordinate system and the direction opposite to that direction. As an example, in the xyz coordinate system, the x-direction can encompass directions parallel to the x-direction. That is, the x-direction can represent both the direction from the origin 0 along the positive x-axis where the absolute value of the z-axis increases and the direction from the origin 0 along the negative x-axis where the absolute value of the z-axis increases. In the xyz coordinate system, the y-direction and z-direction can both be interpreted in substantially the same way.

[0037] Figure 1 This is a perspective view schematically illustrating a semiconductor device according to an embodiment of the present disclosure. Figure 2 yes Figure 1 A plan view of a semiconductor device. Figure 3 It is along Figure 1 A cross-sectional view of a semiconductor device taken from line I-I′.

[0038] refer to Figures 1 to 3 Semiconductor device 1 includes a substrate 101 and a gate structure 120 disposed above the substrate 101. Furthermore, semiconductor device 1 includes a hole pattern 11 penetrating the gate structure 120 above the substrate 101. Semiconductor device 1 includes a gate insulating layer 130, a channel layer 140, a resistor layer 150, and a resistance changing layer 160, which are sequentially disposed within the hole pattern 11 on the sidewall surface of the gate structure 120. Semiconductor device 1 may also include an insulating layer 170 disposed within the hole pattern 11 to contact the resistance changing layer 160. Additionally, semiconductor device 1 may include a fill layer 180, which is configured to contact the insulating layer 170 and fill the hole pattern 11. Gate structure 120 may include a lower interlayer insulating layer 121, a gate electrode layer 122, and an upper interlayer insulating layer 123.

[0039] refer to Figures 1 to 3The substrate 101 may include a semiconductor material. Specifically, the semiconductor material may include silicon (Si), germanium (Ge), gallium arsenide (GaAs), molybdenum selenide (MoSe2), hafnium selenide (HfSe2), indium selenide (InSe), gallium selenide (GaSe), black phosphorus, indium gallium zinc oxide (IGZO), or combinations of two or more thereof. The semiconductor material may be doped with dopants. As an example, the semiconductor material may be doped with N-type or P-type dopants.

[0040] The substrate insulating layer 102 may be disposed on the substrate 101. The substrate insulating layer 102 may include an insulating material. The insulating material may include, for example, oxides, nitrides, oxynitrides, or combinations of two or more thereof.

[0041] The lower channel contact layer 110 may be disposed on the substrate insulating layer 102. The lower channel contact layer 110 may be electrically connected to one end of the channel layer 140. The lower channel contact layer 110 may be connected to a source line (not shown). The lower channel contact layer 110 may provide a potential of the source line to the channel layer 140. In some embodiments, the source line may be disposed on the gate structure 120. In this case, the source electrode may be electrically connected to the lower channel contact layer 110 through a conductive via that penetrates the gate structure 120 and contacts the lower channel contact layer 110.

[0042] The contact layer 110 below the channel may include a conductive material. The conductive material may include, for example, a doped semiconductor, a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal silicide, or a conductive metal oxide. The conductive material may include, for example, silicon, tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or combinations of two or more thereof, doped with n-type or p-type dopants.

[0043] A gate structure 120 may be disposed on the lower channel contact layer 110. The gate structure 120 may include a lower interlayer insulating layer 121, a gate electrode layer 122, and an upper interlayer insulating layer 123 sequentially disposed above the substrate 101. The lower interlayer insulating layer 121 may be configured to contact the lower channel contact layer 110. The lower interlayer insulating layer 121 may electrically insulate the gate electrode layer 122 and the lower channel contact layer 110 from each other. Similarly, the upper interlayer insulating layer 123 may electrically insulate the gate electrode layer 122 from a conductive layer (not shown) on the upper interlayer insulating layer 123.

[0044] The gate electrode layer 122 may include a conductive material. The conductive material may include, for example, a doped semiconductor, a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal silicide, or a conductive metal oxide. The conductive material may include, for example, silicon (Si), tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or combinations thereof, doped with n-type or p-type dopants. Each of the lower interlayer insulating layer 121 and the upper interlayer insulating layer 123 may include an insulating material. The insulating material may include, for example, oxides, nitrides, oxynitrides, or combinations thereof.

[0045] refer to Figures 1 to 3 A hole pattern 11 penetrating the gate structure 120 is formed on the lower contact layer 110. As an example, the hole pattern 11 can be formed by photolithography and etching processes.

[0046] refer to Figure 1 and Figure 3 Inside the hole pattern 11, a gate insulating layer 130 may be disposed on the sidewall surface of the gate structure 120. The gate insulating layer 130 may be configured to cover the sidewall surface of the gate structure 120. The gate insulating layer 130 may include, for example, oxides, nitrides, oxynitrides, or combinations of two or more thereof.

[0047] Channel layer 140 may be disposed on gate insulating layer 130. One end of channel layer 140 may contact channel under-contact layer 110. Channel layer 140 may include a semiconductor material. Semiconductor materials may include, for example, silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. As another example, semiconductor materials may include 2D semiconductor materials. 2D semiconductor materials may include transition metal dichalcogenide (TMDC) or black phosphorus. Transition metal dichalcogenide may include, for example, molybdenum selenide (MoSe2), hafnium selenide (HfSe2), indium selenide (InSe), gallium selenide (GaSe), etc. Semiconductor materials may include, for example, metal oxides, such as indium gallium zinc oxide (IGZO).

[0048] Resistor layer 150, resistive switching layer 160, and insulating layer 170 may be sequentially disposed on the sidewall surface of channel layer 140. Resistor layer 150 may be configured to cover channel layer 140. Resistor layer 160 may be configured to cover resistor layer 150. Insulating layer 170 may be configured to cover resistive switching layer 160. Each of resistor layer 150, resistive switching layer 160, and insulating layer 170 may be disposed on one side of channel layer 140, opposite to the other side of channel layer 140 that contacts gate insulating layer 130.

[0049] Resistor layer 150 may have a constant or fixed resistivity. While the resistance of resistive switching layer 160 can be changed by applying an external electric field, the resistance of resistor layer 150 may not be changed by applying an external electric field. Resistor layer 150 may comprise an oxide material having a predetermined resistance. The oxide material may include, for example, silicon oxide or aluminum oxide. The oxide material may satisfy the stoichiometric ratio of silicon (Si) to oxygen (O) or the stoichiometric ratio of aluminum (Al) to oxygen (O). That is, compared to resistive switching layer 160, resistor layer 150 may not contain oxygen vacancies, or may have a sufficiently low oxygen vacancy concentration. A sufficiently low oxygen vacancy concentration can refer to a concentration at which a change in the distribution of oxygen vacancies present in resistor layer 150 will not change the resistive state of resistor layer 150. As an example, resistor layer 150 may have a thickness of 1 nm to 5 nm.

[0050] The resistive switching layer 160 can be configured to cover the sidewall surface of the resistor layer 150. The resistive switching layer 160 may include oxygen vacancies that can move along the electric field when an electric field of magnitude greater than or equal to a threshold is applied to the resistive switching layer 160. That is, the electric field can change the distribution of oxygen vacancies in the resistive switching layer 160.

[0051] Depending on the distribution of oxygen vacancies, the resistive switching layer 160 can have different resistance states. As an example, when oxygen vacancies are uniformly distributed in the resistive switching layer 160, the resistive switching layer 160 can maintain a high resistance state. As another example, when oxygen vacancies are densely distributed in one direction under an applied electric field, the resistive switching layer 160 can have a low resistance state, which has a reduced or lower resistance compared to the high resistance state.

[0052] Even after the electric field is removed, the resistive switching layer 160 can non-volatilely retain the resistance state that was changed by the applied electric field. Therefore, the resistive switching layer 160 can be used as a storage layer to store the resistance state as signal information.

[0053] The resistive switching layer 160 may include a metal oxide. The resistive switching layer 160 includes a non-stoichiometric metal oxide. The metal oxide may have a low oxygen content relative to the metal in the metal oxide, meaning the metal oxide may have insufficient oxygen relative to the metal in the metal oxide. Therefore, the metal oxide may have an oxygen vacancy concentration corresponding to the insufficient oxygen content. The metal oxide may include, for example, lithium oxide, titanium oxide, nickel oxide, copper oxide, manganese oxide, hafnium oxide, zirconium oxide, tungsten oxide, niobium oxide, vanadium oxide, or combinations of two or more of these.

[0054] In an embodiment, the resistive switching layer 160 may comprise the same metal oxide as the insulating layer 170. However, the metal oxide of the resistive switching layer 160 may have a lower oxygen content than the metal oxide of the insulating layer 170. Due to the lower oxygen content, the resistive switching layer 160 may have a higher oxygen vacancy concentration than the insulating layer 170.

[0055] In some embodiments, the resistive switching layer 160 may further include impurities that can bind with oxygen. As an example, the impurities may include silicon (Si) or aluminum (Al). Compared to the metal in the metal oxide of the resistive switching layer 160, the impurities may have a greater affinity for oxygen. Therefore, the impurities can reduce the metal oxide of the resistive switching layer 160. By reducing the metal oxide through impurities distributed in the resistive switching layer 160, oxygen vacancies can be generated in the metal oxide. Therefore, the concentration of oxygen vacancies in the resistive switching layer 160 can be further increased.

[0056] The insulating layer 170 may be configured to cover the sidewall surface of the resistive switching layer 160. The insulating layer 170 may have electrical insulating properties. In one embodiment, the insulating layer 170 may comprise the same metal oxide as the resistive switching layer 160. However, the metal oxide of the insulating layer 170 may have a higher oxygen content than the metal oxide of the resistive switching layer 160.

[0057] In one embodiment, compared to the resistive switching layer 160, the insulating layer 170 may have a low oxygen vacancy concentration that does not support changes in the internal resistance state. In one embodiment, the metal oxide of the insulating layer 170 may satisfy the stoichiometric ratio between oxygen and the metal of the metal oxide.

[0058] Refer again Figures 1 to 3 A fill layer 180 may be disposed within the hole pattern 11 in which a gate insulating layer 130, a channel layer 140, a resistor layer 150, a resistive switching layer 160, and an insulating layer 170 are formed. The fill layer 180 may comprise, for example, an oxide, a nitride, an oxynitride, or a combination of two or more of these. The fill layer 180 may contact the insulating layer 170 within the hole pattern 11. Although in Figures 1 to 3 Not shown, but a channel contact layer that contacts one end of channel layer 140 can be disposed outside of hole pattern 11. The channel contact layer can electrically connect channel layer 140 to bit lines (not shown). Although in Figures 1 to 3 Although not shown, bit lines can be arranged on gate structure 120 in the form of a wire pattern and can be electrically connected to the on-channel contact layer. The bit lines can provide the potential of the bit lines to channel layer 140 through the on-channel contact layer.

[0059] In some other embodiments, it is possible to Figures 1 to 3 In the semiconductor device 1, the insulating layer 170 is omitted, and the filling layer 180 can be configured as a contact resistive switching layer 160.

[0060] Figure 4A and Figure 4B This is a schematic view illustrating a method of operating a semiconductor device according to embodiments of the present disclosure. Specifically, Figure 4A yes Figure 1 A schematic diagram of semiconductor device 1 is shown. Figure 3 A portion of the cross-sectional view. Figure 4B This is the circuit diagram of semiconductor device 1. Figure 5 This is a view illustrating the change in oxygen vacancies in the resistive switching layer of a semiconductor device according to an embodiment of the present disclosure.

[0061] Figure 4A yes Figure 4B A schematic diagram of the memory cell MC in the circuit diagram. Figure 4A In this configuration, the end of channel layer 140 contacts the lower channel contact layer 110 and the upper channel contact layer 190. The lower channel contact layer 110 and the upper channel contact layer 190 can be electrically connected to a source line (not shown) and a bit line (not shown), respectively. The source line and bit line can correspond to... Figure 4B The source line SL and the bit line BL. Figure 4A The channel layer 140, the gate insulating layer 130, and the gate electrode layer 122 can constitute Figure 4B A transistor TR has a source S, a drain D, a channel CH, and a gate G. The source S and drain D can be connected to the source line SL and the bit line BL, respectively. Figure 4A The gate electrode layer 122 can correspond to Figure 4B The gate G of the transistor TR is formed in Figure 4A The conductive channels in the channel layer 140 can correspond to Figure 4B The transistor TR has channel CH.

[0062] exist Figure 4A In the middle, the resistor layer 150 with a thickness T150 in the x-direction can correspond to Figure 4B The first fixed resistor R1 and the second fixed resistor R2 are respectively disposed in the first electrical path L1 and the third electrical path L3. Figure 4A In this context, the resistive switching layer 160 with a length L160 in the z-direction can correspond to... Figure 4B The variable resistor VR is located in the second electrical path L2. Figure 4B In this circuit, the first electrical path to the third electrical path L1, L2 and L3 can be connected in parallel with the transistor TR.

[0063] Reference Figure 4A , Figure 4B and Figure 5This describes a method of operating a semiconductor device according to embodiments of the present disclosure. (See also...) Figure 5 The resistive switching layer 160 of the semiconductor device may include oxygen vacancies Ov. As will be described later with reference to FIG. 7, the semiconductor device can be fabricated using a certain amount of oxygen vacancies in the resistive switching layer 160, sufficient to allow a change in resistance state or to allow set and reset operations. Therefore, during the initial operation of the semiconductor device of this disclosure, it is not necessary to perform a formation operation for generating oxygen vacancies. This formation operation may refer to the operation of applying a high electric field to the resistive switching layer to generate oxygen vacancies within the resistive switching layer during conventional resistive switching memory operation, and using the oxygen vacancies generated within the resistive switching layer to change the resistance state of the resistive switching layer to a low resistance state. The oxygen vacancies generated in the resistive switching layer 160 during fabrication are sufficient for subsequent set and reset operations.

[0064] In conventional applications, when a transition metal oxide (TMO) is used in a resistive switching layer, a formation operation is first performed on the TMO during the initial operation of the semiconductor device. This formation operation separates oxygen from the TMO, creating oxygen vacancies within it. Conversely, in embodiments of this disclosure, the resistive switching layer 160 may include a sufficient number of oxygen vacancies for set and reset operations without requiring this formation operation.

[0065] refer to Figure 5 In the initial state S1, oxygen vacancies Ov can be uniformly distributed in the resistive switching layer 160, allowing the resistive switching layer 160 to be in a high-resistance state. Subsequently, a set operation P1 can be performed when a set electric field is applied in the z-direction. As the oxygen vacancies Ov in the resistive switching layer 160 move along the set electric field, the density of oxygen vacancies Ov can locally increase along the direction of the set electric field. As the oxygen vacancies Ov are redistributed more and more densely along the direction of the applied set electric field, the resistance of the resistive switching layer 160 decreases.

[0066] Furthermore, the density of oxygen vacancies Ov in the resistive switching layer 160 along the direction of the set electric field can be increased proportionally to the amplitude of the applied set electric field. As the density of oxygen vacancies Ov increases, the resistance of the resistive switching layer 160 decreases. Therefore, by controlling the oxygen vacancies Ov to have various distribution densities resulting from the applied set electric field, the resistive switching layer 160 can have multiple resistance states. Even after the applied set electric field is removed, the resistive switching layer 160 can maintain any one of the multiple resistance states. Therefore, the resistive switching layer 160 can have multiple levels of resistance states, which can be implemented as signal information.

[0067] refer to Figure 5As a result of the set operation P1, the resistive switching layer 160 transitions to a low-resistance state and remains in this state. Afterwards, a reset operation P2 can be performed when a reset electric field is applied in the opposite direction to the set electric field. During reset operation P2, the density of oxygen vacancies Ov in the resistive switching layer 160 along the direction of the reset electric field decreases. As a result, the resistance state of the resistive switching layer 160 can transition from a low-resistance state to a high-resistance state. After the applied reset electric field is removed, the high-resistance state of the resistive switching layer 160 can be maintained.

[0068] refer to Figure 4B A set operation P1 can be performed by applying a set voltage between the source line SL and the bit line BL when the transistor TR is turned off using the gate G. As an example, applying the set voltage can be performed by applying a positive bias voltage to the bit line BL and grounding the source line SL. Furthermore, because the transistor TR is in the off state when the set voltage is applied, the current generated by the set voltage can flow along the first electrical path L1, the second electrical path L2, and the third electrical path L3, which provide relatively low resistance paths.

[0069] The set voltage creates a set electric field across the variable resistor VR, which can be oriented from the potential line BL to the source line SL. This set electric field can change the resistance state of the variable resistor VR from a high-resistance state to a low-resistance state. As mentioned above, the set electric field can decrease the resistance of the variable resistor VR by increasing the oxygen vacancy density within VR along its direction.

[0070] Alternatively, the reset operation P2 can be performed by applying a reset voltage between the source line SL and the bit line BL when the gate G turns off the transistor TR. As an example, applying the reset voltage can be performed by applying a negative bias voltage to the bit line BL and grounding the source line SL. Since the transistor TR is turned off when the reset voltage is applied, the current generated by the reset voltage can flow along the first electrical path L1, the second electrical path L2, and the third electrical path L3, which maintain relatively low resistance.

[0071] The reset electric field formed by the reset voltage across the variable resistor VR can have a direction from the source line SL to the position line BL. The reset electric field can change the resistance state of the variable resistor VR from a low-resistance state to a high-resistance state. As mentioned above, the reset electric field can increase the resistance of the variable resistor VR by reducing the density of oxygen vacancies inside the variable resistor VR along the direction of the reset electric field.

[0072] Figure 6A This is a schematic diagram illustrating the IV characteristics of a semiconductor device according to an embodiment of the present disclosure. Figure 6BIt is a graph comparing the IV characteristics of a conventional semiconductor device with the IV characteristics of a semiconductor device according to an embodiment of the present disclosure. Figure 6C This is a schematic diagram illustrating a method for implementing multi-level signals in a semiconductor device according to embodiments of the present disclosure. Figure 6D This is a graph schematically illustrating a method for controlling the set voltage of a semiconductor device according to an embodiment of the present disclosure. Figures 6A to 6D The IV characteristics can be referenced above. Figures 1 to 3 The electrical characteristics of semiconductor device 1 are described.

[0073] refer to Figure 6A In the initial high-resistance state, a set operation can be performed by applying a positive voltage. As the voltage increases, the output current can increase along the first portion 601 of curve 60. In the first voltage segment V1 of the first portion 601, where the applied voltage is small, the slope of the IV curve can be relatively small, indicating that the current increases relative to the voltage increase. That is, in the first voltage segment V1, the output current can increase relatively slowly as the voltage increases. In the second voltage segment V2 of the first portion 601, where the applied voltage is sufficiently large, the slope of the IV curve can increase more rapidly as the applied voltage increases. That is, in the second voltage segment V2, the output current can increase relatively rapidly compared to the first voltage segment V1 as the voltage increases.

[0074] In the semiconductor device of this embodiment, the resistance state can gradually switch from a high resistance state to a low resistance state until the applied voltage reaches the set voltage Vset in the second voltage segment V2. For example... Figure 6A As shown, semiconductor device 1 can output a set current Iset in a low-resistance state under a set voltage Vset. Subsequently, when the voltage applied to semiconductor device 1 decreases, the output current can decrease along the second portion 602 of curve 60. After the voltage applied to semiconductor device 1 is removed, semiconductor device 1 can maintain a low-resistance state along the second portion 602, such that when a positive voltage is applied to semiconductor device 1 again, semiconductor device 1 can output a current that increases along the second portion 602.

[0075] refer to Figure 6AIn the initial state of low resistance, a reset operation can be performed by applying a negative voltage. As the absolute value of the voltage increases, the output current can increase along the third part 603 of curve 60. In the third voltage segment V3 of the third part 603, where the applied voltage is very small, the slope of the IV curve (i.e., the current increases with increasing voltage) can be relatively large. That is, semiconductor device 1 can exhibit low resistance characteristics. In the fourth voltage segment V4 where the applied voltage is sufficiently large, the slope of the IV curve can decrease as the applied voltage in the third part 603 increases. That is, in semiconductor device 1, the resistance state can gradually switch from a low resistance state to a high resistance state until the applied voltage reaches the reset voltage Vreset in the fourth voltage segment V4. In other words, the resistance state may not switch from a low resistance state to a high resistance state rapidly. Therefore, the output current in the fourth voltage segment V4 may not decrease rapidly with increasing applied voltage. Semiconductor device 1 can output a reset current Ireset in a high resistance state at the reset voltage Vreset. Subsequently, when the voltage applied to semiconductor device 1 decreases, the output current can decrease along the fourth portion 604 of curve 60. After the voltage applied to semiconductor device 1 is removed, semiconductor device 1 can store a high-resistance state. That is, when a positive voltage is applied to semiconductor device 1 again, semiconductor device 1 can output a current that increases along the first portion 601.

[0076] refer to Figure 6B The diagram illustrates a first curve 60 indicating the electrical characteristics of a semiconductor device according to embodiments of the present disclosure, and second and third curves 70a and 70b indicating the electrical characteristics of a conventional semiconductor device. The first curve 60 may be... Figure 6A Curve 60 has a first portion 601 and a second portion 602. The second curve 70a and the third curve 70b respectively illustrate the IV characteristics of the formation and set operations according to a conventional semiconductor device. A conventional semiconductor device may have the following structure: [The text abruptly ends here, likely due to an incomplete translation or missing information.] Figure 4A The resistor layer 150 is omitted in the semiconductor device 1. That is, the semiconductor device 1 differs from conventional devices in that, in conventional semiconductor devices, the channel layer 140 and the resistive switching layer 160 can be in direct contact with each other. Therefore, in conventional semiconductor devices, in… Figure 4B In the circuit diagram, the first path L1 and the third path L3 can be omitted respectively (see Figure 4B The first fixed resistor R1 and the second fixed resistor R2 are on the circuit.

[0077] refer to Figure 6BWhen a conventional semiconductor device includes a transition metal oxide (TMO) layer as a resistive switching layer, a formation operation needs to be performed before first driving the conventional semiconductor device. This formation operation can be performed by applying a formation voltage Vform-c to the TMO layer to separate oxygen from the TMO, thereby generating oxygen vacancies. These oxygen vacancies are then aligned in the direction of the applied formation voltage to form a conductive filament. Figure 6B As shown, when a positively applied voltage reaches the formation voltage Vform-c, a formation operation can occur. Along... Figure 6B The first part of the second curve 70a, 701, shows a gradually increasing output current that can rapidly increase at the forming voltage Vform-c. This rapidly increasing output current is expressed as... Figure 6B The compliance current Ic in the middle. Thereafter, when the applied voltage is reduced to 0V, the output current can decrease along the second part 702.

[0078] Furthermore, although not shown, in conventional semiconductor devices, a set operation can be performed again after a reset operation that disconnects a portion of the formed conductive wire. For example, in curve 70b, a set operation can be performed by applying a positive voltage in the initial high-resistance state. Because the set operation restores the partially disconnected conductive wire, it can occur at a set voltage Vset-c where the applied voltage is lower than the formation voltage Vform-c. Along Figure 6B The first part 703 of the third curve 70b shows a gradually increasing output current that can rapidly increase from the set voltage Vset-c to the compliance current Ic. Thereafter, when the applied voltage decreases to 0V, the output current can decrease along the second part 704.

[0079] As described above, in conventional semiconductor devices, the forming and setting operations for changing the resistance state from a high-resistance state to a low-resistance state can occur respectively by a rapid increase in the output current at the forming voltage Vform-c and the setting voltage Vset-c. Conversely, in the semiconductor device according to embodiments of this disclosure, the setting operation can occur within a voltage range (for example, in...). Figure 6A (It gradually occurs in the second voltage range V2).

[0080] Furthermore, as described above, in embodiments of this disclosure, when the semiconductor device is manufactured, the resistive switching layer may include a sufficient amount of oxygen vacancies for forming conductive filaments. Therefore, when the semiconductor device is operated, a set operation can be performed immediately without the need for a formation operation to generate oxygen vacancies. In embodiments of this disclosure, a method for manufacturing a semiconductor device in which the resistive switching layer contains a sufficient amount of oxygen vacancies will be described later with reference to FIG7.

[0081] refer to Figure 6CThe semiconductor device according to embodiments of this disclosure can realize multiple different resistance states. (See reference...) Figure 6C As shown in curve 60a, in the initial high-resistance state, when a positive voltage is applied and increased from 0V, the output current can increase along the first part 610. Until the applied voltage reaches the first set voltage Vset1, the resistance state of the semiconductor device can gradually switch from a high-resistance state to a low-resistance state.

[0082] After the applied voltage is increased to the first set voltage Vset1, when the applied voltage is decreased to 0V, the output current can decrease from the first set current Iset1 along the second portion 611. Thereafter, when a positive voltage is applied again and increased from 0V, the output current can increase along the second portion 611. Therefore, the semiconductor device can have current characteristics along the second portion 611. That is, the semiconductor device can maintain a first low-resistance state in a non-volatile manner.

[0083] In another example, after the applied voltage is increased from the initial high-resistance state to the second set voltage Vset2, when the applied voltage decreases to 0V, the output current can decrease from the second set current Iset2 along the third portion 612. Subsequently, when a positive voltage is applied again and increased from 0V, the output current can increase along the third portion 612. Therefore, the semiconductor device can have a current characteristic along the third portion 612. That is, the semiconductor device can non-volatilely maintain the second low-resistance state.

[0084] Similarly, after increasing the applied voltage from the initial high-resistance state to the third set voltage Vset3, when the applied voltage decreases to 0V, the output current can decrease from the third set current Iset3 along the fourth portion 613. Therefore, the semiconductor device can have a current characteristic along the fourth portion 613 and can maintain the third low-resistance state in a non-volatile manner. Furthermore, after increasing the applied voltage to the fourth set voltage Vset4, when the applied voltage decreases to 0V, the output current can decrease from the fourth set current Iset4 along the fifth portion 614. Therefore, the semiconductor device can have a current characteristic along the fifth portion 614 and non-volatilely maintain the fourth low-resistance state.

[0085] refer to Figure 6C As an example, a read operation can be performed by applying a read voltage Va less than the first set voltage Vset1 to the semiconductor device to identify the output currents of the first portion 610 to the fifth portion 614 respectively. As another example, a read operation can be performed by applying a read current Ia less than the first set current Iset1 to the semiconductor device to identify the output voltages V610 to V614 of the first portion 610 to the fifth portion 614 respectively.

[0086] Figure 6D A method for controlling the set voltage according to an embodiment of the present disclosure is shown. (Reference) Figure 6D In the first curve 60 and the second curve 60′, each of the applied voltages can have current characteristics along the first portions 601 and 601′ until reaching the set voltages Vset and Vset′ respectively from an initial high-resistance state, and after reaching the set voltages Vset and Vset′ respectively, can exhibit current characteristics along the second portions 602 and 602′ in a low-resistance state. The set voltage Vset′ of the second curve 60′ can be ΔV larger than the set voltage Vset of the first curve 60.

[0087] According to embodiments of this disclosure, in Figure 4A In a semiconductor device, the amplitude of the set voltage can be controlled by controlling the length L160 of the resistive switching layer 160. As an example, regardless of the resistance state of the resistive switching layer 160, as the length L160 of the resistive switching layer 160 increases, the resistance of the resistive switching layer 160 along the z-direction can increase. Therefore, as the length L160 of the resistive switching layer 160 increases, the amplitude of the set voltage when the resistance of the resistive switching layer 160 transitions from a high resistance state to a low resistance state can increase. Therefore, in the second curve 60′, compared to the first curve 60, the set voltage can shift in the positive voltage direction.

[0088] Furthermore, increasing the amplitude of the set voltage enhances the ability to distinguish multi-level signal information when performing a read operation on the resistive switching layer storing multi-level signal information. (See again...) Figure 6C In one embodiment, the read operation for multi-level signal information can be performed by applying a read current Ia and distinguishing the output voltages V610, V611, V612, V613, and V614 of the first to fifth portions 610, 611, 612, 613, and 614, respectively. (See also...) Figure 6C and Figure 6D ,because Figure 6D The second curve 60' is shifted in the positive voltage direction compared to the first curve 60. Therefore, the semiconductor device corresponding to the second curve 60' can ensure a relatively large voltage gap between multiple output voltages during read operations using the read current. That is, a relatively large voltage margin or window can be ensured to distinguish multiple output voltages from each other. Therefore, compared to the semiconductor device corresponding to the first curve 60, the semiconductor device corresponding to the second curve 60' can distinguish voltages more accurately and superiorly when reading multi-level signal information.

[0089] Figure 7A and Figure 7B This is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. In one embodiment, reference is made to... Figure 7A and Figure 7B The described method can be applied to manufacturing. Figures 1 to 3 Method for semiconductor device 1.

[0090] refer to Figure 7A The substrate insulating layer 102 and the under-channel contact layer 110 can be sequentially formed on the substrate 101. The gate structure 120, including the hole pattern 11, can be formed on the under-channel contact layer 110.

[0091] Subsequently, the gate insulating layer 130, the channel layer 140, the oxidation reaction layer 1510 and the reduction reaction layer 1710 can be sequentially formed on the sidewall surface of the gate structure 120 located inside the hole pattern 11.

[0092] The oxidation reaction layer 1510 may include, for example, silicon (Si) or aluminum (Al). The reduction reaction layer 1710 may include a metal oxide. The metal oxide may include, for example, lithium oxide, titanium oxide, nickel oxide, copper oxide, manganese oxide, hafnium oxide, zirconium oxide, tungsten oxide, niobium oxide, vanadium oxide, or a combination of two or more of these. In this case, the oxygen affinity of the silicon (Si) or aluminum (Al) in the oxidation reaction layer 1510 may be greater than the oxygen affinity of the metal in the metal oxide constituting the reduction reaction layer 1710. In this specification, oxygen affinity may refer to the bonding force between an element and oxygen in an oxide when an element combines with oxygen to form an oxide. As an example, when the oxidation reaction layer 1510 contains silicon and silicon combines with oxygen to form silicon oxide, the oxygen affinity of silicon may refer to the bonding force between silicon and oxygen in silicon oxide. Elements with high oxygen affinity are more likely to combine with oxygen to form oxides compared to elements with low oxygen affinity. Furthermore, compared to oxides containing elements with relatively low oxygen affinity, oxides containing elements with relatively high oxygen affinity are less likely to ionize oxygen by breaking the bonds with the elements in the oxide.

[0093] In embodiments of this disclosure, when the reduction reaction layer 1710 is formed on the oxidation reaction layer 1510, the silicon or aluminum in the oxidation reaction layer 1510 can combine with the oxygen in the metal oxide of the reduction reaction layer 1710 to form silicon oxide or aluminum oxide. As a result, the metal oxide in the reduction reaction layer 1710 can be reduced. In another embodiment, after the reduction reaction layer 1710 is formed on the oxidation reaction layer 1510, an additional heat treatment can promote the redox reaction between the oxidation reaction layer 1510 and the reduction reaction layer 1710. Therefore, as... Figure 7B As shown, the entire oxidation reaction layer ( Figure 7AThe oxide reaction layer 1510 can be oxidized to form a resistor layer 150. In one embodiment, the entire oxide reaction layer 1510 can be effectively oxidized by forming an oxide reaction layer 1510 with a thickness of 1 nm to 5 nm. A portion of the reduction reaction layer 1710, which is reduced by reacting with the oxide reaction layer 1510, may include an oxygen-deficient metal oxide (i.e., a metal oxide with oxygen vacancies). The reduced portion can form a resistive switching layer 160. The portion of the reduction reaction layer 1710 that does not participate in the reaction with the oxide reaction layer 1510 can form an insulating layer 170. Subsequently, the hole pattern 11 can be filled with an insulating material to form a filling layer (not shown). A contact layer (not shown) and a bit line (not shown) on the channel can be formed outside the hole pattern 11. As a result, a reference can be manufactured. Figures 1 to 3 Semiconductor device 1 described.

[0094] In some embodiments, after the redox reaction between the oxide reaction layer 1510 and the reduction reaction layer 1710 is completed, the insulating layer 170 can be removed to expose the resistive switching layer 160. Subsequently, the hole pattern 11 can be filled with an insulating material to form a filling layer (not shown). A contact layer (not shown) and bit lines (not shown) on the channel can be formed outside the hole pattern 11. Therefore, with... Figure 7B The devices shown are different, as Figures 1 to 3 In a modified example of semiconductor device 1, insulating layer 170 is absent and resistive switching layer 160 is in direct contact with filling layer 180.

[0095] In some embodiments, during the formation of the resistive switching layer 160, the resistive switching layer 160 may further include silicon or aluminum diffused from the oxide reaction layer 1510 into the resistive switching layer 160. The diffused silicon or aluminum can further reduce the metal oxide in the resistive switching layer 160. Through the reduction of the metal oxide, the oxygen vacancy concentration in the resistive switching layer 160 can be further increased.

[0096] As described above, a resistive switching layer 160 including oxygen vacancies can be generated through the reaction between the oxidation reaction layer 1510 and the reduction reaction layer 1710. Furthermore, when the resistive switching layer 160 is generated, it can reserve a sufficient amount of oxygen vacancies for the set and reset operations of the semiconductor device. Therefore, according to embodiments of this disclosure, no formation operation is required to operate the semiconductor device.

[0097] Figure 8A and Figure 8B This is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to another embodiment of the present disclosure. In one embodiment, reference is made to... Figure 8A and Figure 8B The described method can be applied to manufacturing. Figures 1 to 3 Method for semiconductor device 1.

[0098] refer to Figure 8A The substrate insulating layer 102 and the under-channel contact layer 110 can be sequentially formed on the substrate 101. The gate structure 120, including the hole pattern 11, can be formed on the under-channel contact layer 110.

[0099] Subsequently, the gate insulating layer 130, the channel forming layer 1410, and the reduction reaction layer 1710 can be sequentially formed on the sidewall surface of the gate structure 120 located inside the hole pattern 11.

[0100] The channel forming layer 1410 may include a semiconductor material. The semiconductor material may include, for example, silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. The reduction reaction layer 1710 may include a metal oxide. The metal oxide may include, for example, lithium oxide, titanium oxide, nickel oxide, copper oxide, manganese oxide, hafnium oxide, zirconium oxide, tungsten oxide, niobium oxide, vanadium oxide, or a combination of two or more of these. The oxygen affinity of the semiconductor material in the channel forming layer 1410 may be greater than the oxygen affinity of the metal in the metal oxide constituting the reduction reaction layer 1710.

[0101] In embodiments of this disclosure, when the reduction reaction layer 1710 is formed on the channel forming layer 1410 comprising silicon (Si), a portion of the channel forming layer 1410 and a portion of the reduction reaction layer 1710 can react with each other. That is, a portion of the channel forming layer 1410 can be oxidized to silicon oxide, while a portion of the reduction reaction layer 1710 can be reduced. In another embodiment, after the reduction reaction layer 1710 is formed on the channel forming layer 1410, a further heat treatment can be performed to promote the redox reaction between the channel forming layer 1410 and the reduction reaction layer 1710.

[0102] As a result, Figure 8B As shown, the oxidized portion of the channel forming layer 1410 can form a resistor layer 150. The unoxidized portion of the channel forming layer 1410 can form a channel layer 140. The portion of the reduction reaction layer 1710 that is reduced by reaction with the channel forming layer 1410 can include an oxygen-depleted metal oxide (i.e., a metal oxide with oxygen vacancies). The reduced portion can form a resistive switching layer 160. The portion of the reduction reaction layer 1710 that does not participate in the redox reaction with the channel forming layer 1410 can be retained to form an insulating layer 170. Subsequently, the hole pattern 11 can be filled with an insulating material to form a filling layer (not shown). As a result, a reference can be manufactured. Figures 1 to 3 Semiconductor device 1 described.

[0103] In some embodiments, after the redox reaction between the channel forming layer 1410 and the reduction reaction layer 1710 is completed, the insulating layer 170 can be removed to expose the resistive switching layer 160. Subsequently, the hole pattern 11 can be filled with an insulating material to form a filling layer (not shown). Therefore, with Figure 8B The devices shown are different, as Figures 1 to 3 A modified example of the semiconductor device 1 can provide a structure in which there is no insulating layer 170 and the resistive switching layer 160 and the filling layer 180 are in direct contact.

[0104] Figure 9 This is a perspective view schematically illustrating a semiconductor device according to another embodiment of the present disclosure. Figure 10 yes Figure 9 A plan view of a semiconductor device. Figure 11 It is along Figure 9 A cross-sectional view of the semiconductor device taken from line II-II′.

[0105] refer to Figures 9 to 11 The semiconductor device 2 may include a substrate 201 and a gate structure 220 disposed on the substrate 201. The semiconductor device 2 may include a first hole pattern 21 and a second hole pattern 22 penetrating the gate structure 220 on the substrate 201. The semiconductor device 2 may include a gate insulating layer 230, a channel layer 240, a resistor layer 250, and a resistive switching layer 260 in each of the first hole pattern 21 and the second hole pattern 22. The semiconductor device 2 may include an insulating layer 270 in each of the first hole pattern 21 and the second hole pattern 22, the insulating layer 270 being configured to contact the resistive switching layer 260. Furthermore, the semiconductor device 2 may also include a fill layer 280, the fill layer 280 being configured to contact the insulating layer 270 and fill the first hole pattern 21 and the second hole pattern 22.

[0106] refer to Figures 9 to 11 A substrate 201 can be provided. The substrate 201 can be used with a reference. Figures 1 to 3 The substrate 101 described in detail is essentially the same.

[0107] A substrate insulating layer 202 may be disposed on the substrate 201. The substrate insulating layer 202 may be disposed with respect to a reference. Figures 1 to 3 The substrate insulating layer 102 described in detail is essentially the same.

[0108] The lower channel contact layer 210 may be disposed on the substrate insulating layer 202. The lower channel contact layer 210 may be electrically connected to an end of the channel layer 240. Although not shown, the lower channel contact layer 210 may be connected to a source line (not shown). The lower channel contact layer 210 may provide the potential of the source line to the channel layer 240. The lower channel contact layer 210 may be connected to a reference... Figures 1 to 3 The contact layer 110 under the channel described in detail is basically the same.

[0109] Gate structure 220 may be disposed on the under-channel contact layer 210. Gate structure 220 may include first to fourth gate electrode layers 222a, 222b, 222c, and 222d, and first to fifth interlayer insulating layers 223a, 223b, 223c, 223d, and 223e, which may be alternately stacked along a first direction perpendicular to substrate 201 (i.e., the z-direction). First interlayer insulating layer 223a may be configured to contact the under-channel contact layer 210. Fifth interlayer insulating layer 223e may be configured as the uppermost layer of gate structure 220. The number of gate electrode layers in gate structure 220 is not limited to four. In some embodiments, the number of gate electrode layers may be different, and the interlayer insulating layers may be arranged in various numbers such that the various numbers of gate electrode layers are insulated from each other along the first direction (i.e., the z-direction).

[0110] The first to fourth gate electrode layers 222a, 222b, 222c, and 222d may include a conductive material. The conductive material may include, for example, a doped semiconductor, a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal silicide, or a conductive metal oxide. The conductive material may include, for example, silicon (Si), tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or combinations thereof, doped with n-type or p-type dopants. Each of the first to fifth interlayer insulating layers 223a, 223b, 223c, 223d, and 223e may include an insulating material. The insulating material may include, for example, an oxide, a nitride, an oxynitride, or combinations thereof.

[0111] refer to Figures 9 to 11 The first hole pattern 21 and the second hole pattern 22 penetrating the gate structure 220 can be formed on the under-channel contact layer 210. In an embodiment, as shown... Figure 10 As shown, the first hole pattern 21 and the second hole pattern 22 can be configured to be spaced apart from each other in a second direction (i.e., the y-direction). As an example, the first hole pattern 21 and the second hole pattern 22 can be formed by photolithography and etching processes. As described later, the semiconductor device 2 may include a first memory cell U21 and a second memory cell U22 that are separated from each other for each of the first hole pattern 21 and the second hole pattern 22. Figure 9 and Figure 10 Two hole patterns are shown, but this disclosure is not limited thereto. The semiconductor device 2 may include a variety of different numbers of hole patterns arranged spaced apart from each other in the x-direction or y-direction.

[0112] refer to Figures 9 to 11 The gate insulating layer 230 can be disposed within the first hole pattern 21 and the second hole pattern 22 on the sidewall surface of the gate structure 220. The gate insulating layer 230 can be configured to cover the sidewall surface of the gate structure 220. The gate insulating layer 230 may include, for example, oxides, nitrides, oxynitrides, or combinations of two or more of these.

[0113] Channel layer 240 can be disposed on the sidewall surface of gate insulating layer 230. The ends of channel layer 240 can be configured to contact channel lower contact layer 210. Channel layer 240 may include a semiconductor material. Channel layer 240 may be formed from materials referenced above. Figures 1 to 3 The channel layer 140 described is formed of essentially the same material.

[0114] Resistor layer 250, resistive switching layer 260, and insulating layer 270 can be sequentially disposed on the sidewall surface of channel layer 240. Resistor layer 250 can be configured to cover channel layer 240. Resistor layer 260 can be configured to cover resistor layer 250. Insulating layer 270 can be configured to cover resistive switching layer 260. Each of resistor layer 250, resistive switching layer 260, and insulating layer 270 can be disposed on one side of channel layer 240, opposite to the other side of channel layer 240 that contacts gate insulating layer 230.

[0115] Resistor layer 250 may have a constant or fixed resistivity. While the resistance of resistive switching layer 260 can be changed by applying an external electric field, the resistance of resistor layer 250 may not be changed by an external electric field. Resistor layer 250 may include an oxide having a predetermined resistance. Compared to resistive switching layer 260, resistor layer 250 may not contain oxygen vacancies or may have a sufficiently low oxygen vacancy concentration. A sufficiently low oxygen vacancy concentration can mean a concentration such that changes in the oxygen vacancy distribution in resistor layer 250 do not cause a change in the resistive state of resistor layer 250. As an example, resistor layer 250 may have a thickness of 1 nm to 5 nm. Resistor layer 250 may be formed by... Figures 1 to 3 The resistor layer 150 described in detail is made of essentially the same material.

[0116] The resistive switching layer 260 can be configured to cover the sidewalls of the resistor layer 250. The resistive switching layer 260 may include oxygen vacancies that can move along the electric field when an electric field of magnitude greater than or equal to a threshold is applied to the resistive switching layer 260. The electric field can alter the distribution of oxygen vacancies in the resistive switching layer 260. Furthermore, the resistive switching layer 260 can have different resistances depending on the distribution of oxygen vacancies. As an example, when oxygen vacancies are uniformly distributed in the resistive switching layer 260, the resistive switching layer 260 can maintain a high-resistance state. As another example, when oxygen vacancies are densely distributed in one direction by the applied electric field, the resistive switching layer 260 can have a lower resistance compared to the high-resistance state.

[0117] Even after the electric field is removed, the resistive switching layer 260 can maintain the resistance state that changed by the applied electric field. Therefore, the resistive switching layer 260 can be used as a storage layer to store the resistance state as signal information in a non-volatile manner. The resistive switching layer 260 can be made of a reference... Figures 1 to 3 The resistive switching layer 160 described in detail is made of essentially the same material.

[0118] In one embodiment, the resistive switching layer 260 may comprise an oxide of the same metal as the insulating layer 270. However, the metal oxide of the resistive switching layer 260 may have a smaller amount of oxygen than the metal oxide of the insulating layer 270. Therefore, the resistive switching layer 260 may have a higher concentration of oxygen vacancies than the insulating layer 270.

[0119] In some embodiments, the resistive switching layer 260 may further include impurities that can bind with oxygen. As an example, the impurities may include silicon (Si) or aluminum (Al). The impurities may have a greater affinity for oxygen than the metal of the metal oxide constituting the resistive switching layer 260. Therefore, the impurities can reduce the metal oxide of the resistive switching layer 260. Through the reduction of the metal oxide, oxygen vacancies can be generated in the metal oxide. As a result, impurities are distributed in the resistive switching layer 260, thereby further increasing the oxygen deficiency in the metal oxide. Therefore, the concentration of oxygen vacancies in the resistive switching layer 260 can be further increased. In one embodiment, impurities can be implanted into the resistive switching layer 160 by a doping method or an ion implantation method. When implanting impurities, the impurity content can be controlled.

[0120] The insulating layer 270 may be configured to cover the sidewall surface of the resistive switching layer 260. The insulating layer 270 may have electrical insulating properties. In one embodiment, the insulating layer 270 may comprise an oxide of the same metal as the resistive switching layer 260. However, the metal oxide of the insulating layer 270 may have a greater amount of oxygen than the metal oxide of the resistive switching layer 260. In one embodiment, the insulating layer 270 may have a lower concentration of oxygen vacancies than the resistive switching layer 260, such that the internal resistance state of the insulating layer 270 remains unchanged. In one embodiment, the metal oxide of the insulating layer 270 may satisfy a stoichiometric ratio between the metal constituting the metal oxide and oxygen.

[0121] Refer again Figures 9 to 11 The filling layer 280 can be disposed inside each of the first hole pattern 21 and the second hole pattern 22, which have a gate insulating layer 230, a channel layer 240, a resistor layer 250, a resistive switching layer 260, and an insulating layer 270. The filling layer 280 can include, for example, oxides, nitrides, oxynitrides, or combinations of two or more of these. The filling layer 280 can contact the insulating layer 270 inside each of the first hole pattern 21 and the second hole pattern 22. Although in Figures 9 to 11 Although not shown, a channel contact layer that contacts the end of channel layer 240 can be disposed outside the first hole pattern 21 and the second hole pattern 22. The channel contact layer can electrically connect channel layer 240 to bit lines (not shown). Although in Figures 9 to 11 Although not shown, the bit lines can be arranged on the gate structure 220 in the form of a wire pattern and can be electrically connected to the on-channel contact layer. The bit lines can provide the bit line potential to the channel layer 240 through the on-channel contact layer.

[0122] In some embodiments, Figures 9 to 11 In the semiconductor device 2, the insulating layer 270 can be omitted. In this case, the filling layer 280 can be set as a contact resistive switching layer 260.

[0123] Figure 12 This is a circuit diagram of a semiconductor device according to an embodiment of the present disclosure. As an example, Figure 12 It can be Figures 9 to 11 A circuit diagram of one of the first memory cell U21 and the second memory cell U22 of the semiconductor device 2 is provided below. In the following description, as an example, the circuit diagram of the first memory cell U21 will be used to illustrate the operation of the semiconductor device. Specifically, Figure 12 The circuit diagram can be included in Figure 11 The first hole pattern 21 contains a gate insulating layer 230, a channel layer 240, a resistor layer 250, a resistive switching layer 260, and first to fourth gate electrode layers 222a, 222b, 222c and 222d.

[0124] refer to Figure 12 The first memory cell U21 may include first memory cells to fourth memory cells MC1, MC2, MC3 and MC4. The first memory cells to fourth memory cells MC1, MC2, MC3 and MC4 may be connected in series between the source line SL and the bit line BL. The first memory cells to fourth memory cells MC1, MC2, MC3 and MC4 may include corresponding transistors TR1, TR2, TR3 and TR4, first fixed resistors R1a, R1b, R1c and R1d, second fixed resistors R2a, R2b, R2c and R2d, and variable resistors VRa, VRb, VRc and VRd, which are connected in parallel with transistors TR1, TR2, TR3 and TR4, respectively.

[0125] Figures 9 to 11 The first to fourth gate electrode layers 222a, 222b, 222c, and 222d can respectively correspond to Figure 12 The first gate electrode to the fourth gate electrode G1, G2, G3 and G4. Figures 9 to 11 The resistor layer 250 can be Figure 12 The first to fourth storage cells MC1, MC2, MC3, and MC4 are respectively equipped with first fixed resistors R1a, R1b, R1c, and R1d and second fixed resistors R2a, R2b, R2c, and R2d. The resistive switching layer 260 can be equipped with variable resistors VRa, VRb, VRc, and VRd for the first to fourth storage cells MC1, MC2, MC3, and MC4.

[0126] In the following text, as an example, reference will be made to Figure 12 Describe the operation method of the third storage unit MC3. The operation methods of the first storage unit MC1, the second storage unit MC2, and the fourth storage unit MC4 are basically the same as those of the third storage unit MC3.

[0127] First, the set operation of the third memory cell MC3 will be described. By controlling the voltages applied to the first to fourth gate electrodes G1, G2, G3, and G4, the third transistor TR3 can be turned off, while the first transistor TR1, the second transistor TR2, and the fourth transistor TR4 can be turned on. Then, a set voltage can be applied between the bit line BL and the source line SL. As an example, the process of applying the set voltage can be performed by applying a positive bias voltage to the bit line BL and grounding the source line SL. The current according to the set voltage can flow from the bit line BL through the channel of the turned-on fourth transistor TR4, then through the second fixed resistor R2c, the variable resistor VRc, and the first fixed resistor R1c connected in parallel with the third transistor TR3, without passing through the channel of the turned-off third transistor TR3. Subsequently, the current can flow through the channels of the turned-on second transistor TR2 and the turned-on first transistor TR1 to reach the source line SL. At this point, as a set electric field is applied between the two ends of the variable resistor VRc of the third storage cell MC3 through which the current flows, the resistance state of the variable resistor VRc can change from a high resistance state to a low resistance state. Even after the set voltage is removed, the variable resistor VRc of the third storage cell MC3 can remain in a low resistance state, allowing the third storage cell MC3 to non-volatilely store the signal information corresponding to the low resistance state.

[0128] Next, the reset operation of the third memory cell MC3 will be described. By controlling the voltages applied to the first to fourth gate electrodes G1, G2, G3, and G4, the third transistor TR3 can be turned off, while the first transistor TR1, the second transistor TR2, and the fourth transistor TR4 can be turned on. A reset voltage can then be applied between the bit line BL and the source line SL. The reset voltage can have the opposite polarity to the set voltage. As an example, the process of applying the reset voltage can be performed by applying a negative bias voltage to the bit line BL and grounding the source line SL.

[0129] The current, generated by the reset voltage, flows from the source line SL through the channels of the first transistor TR1 and the second transistor TR2, both of which are turned on. Subsequently, the current flows through the second fixed resistor R2c, the variable resistor VRc, and the first fixed resistor R1c, all connected in parallel with the third transistor TR3, but not through the channel of the third transistor TR3, which is turned off. Then, the current flows through the channel of the fourth transistor TR4, which is turned on, to the bit line BL. At this point, as a reset electric field is applied between the two ends of the variable resistor VRc in the third memory cell MC3 through which the current flows, the resistance state of the variable resistor VRc changes from a low resistance state to a high resistance state. Even after the reset voltage is removed, the variable resistor VRc in the third memory cell MC3 remains in a high resistance state, allowing the third memory cell MC3 to store the signal information corresponding to the high resistance state in a non-volatile manner.

[0130] Next, the read operation of the third memory cell MC3 will be described. By controlling the voltages applied to the first to fourth gate electrodes G1, G2, G3, and G4, the third transistor TR3 can be turned off, while the first transistor TR1, the second transistor TR2, and the fourth transistor TR4 can be turned on. A read voltage can then be applied between the bit line BL and the source line SL. As an example, the process of applying the read voltage can be performed by applying a positive bias voltage to the bit line BL and grounding the source line SL. The current according to the read voltage can flow from the bit line BL through the channel of the turned-on fourth transistor TR4, then through the second fixed resistor R2c, the variable resistor VRc, and the first fixed resistor R1c connected in parallel with the third transistor TR3, without passing through the channel of the turned-off third transistor TR3. Subsequently, the current can flow through the channels of the turned-on second transistor TR2 and the turned-on first transistor TR1 to reach the source line SL.

[0131] The read voltage can have an absolute value smaller than the set voltage and reset voltage. That is, the read voltage may not change the resistance state of the variable resistor VRc in the third storage cell MC3. By applying the read voltage, the current flowing through the variable resistor VRc in the third storage cell MC3 can have different values ​​depending on the resistance state of the variable resistor VRc. Therefore, the resistance state of the variable resistor VRc in the third storage cell MC3 can be checked by reading the current value, and the signal information stored in the third storage cell MC3 can be read.

[0132] Figure 13 This is a perspective view schematically illustrating a semiconductor device according to another embodiment of the present disclosure. Figure 14 yes Figure 13 A plan view of a semiconductor device.

[0133] refer to Figure 13 and Figure 14 When compared with the above reference Figures 9 to 11 Compared to the described semiconductor device 2, semiconductor device 3 may further include a cell insulating structure 310. Semiconductor device 3 may include first to fourth memory cells U31, U32, U33 and U34 separated from each other by the cell insulating structure 310.

[0134] The unit insulating structure 310 can be disposed above the substrate 201 for connection. Figures 9 to 11 The semiconductor device 2 has a filling layer 280 that can extend in one direction (i.e., the y-direction) and can bisect the first hole pattern 21 and the second hole pattern 22. The unit insulating structure 310 can be divided along a direction spanning the diameter of the first hole pattern 21 and the second hole pattern 22. Figures 9 to 11 The semiconductor device comprises a gate structure 220, a gate insulating layer 230, a channel layer 240, a resistor layer 250, a resistive switching layer 260, and an insulating layer 270.

[0135] That is, the unit insulation structure 310 can Figures 9 to 11 The first memory cell U21 of the semiconductor device 2 is divided into two parts to form Figure 13 and Figure 14 The semiconductor device 3 contains a pair of first memory cells U31 and second memory cells U32. Further, the cell insulation structure 310 can... Figures 9 to 11 The second memory cell U22 of the semiconductor device 2 is divided into two parts to form Figure 13 and Figure 14 The semiconductor device 3 contains a pair of third memory cells U33 and fourth memory cells U34.

[0136] The gate insulating layer 230a, channel layer 240a, resistor layer 250a, resistive switching layer 260a, and insulating layer 270a of the first memory cell U31 can be symmetrical across the cell insulating structure 310 with the gate insulating layer 230b, channel layer 240b, resistor layer 250b, resistive switching layer 260b, and insulating layer 270b of the second memory cell U32. Similarly, the components of the third memory cell U33 and the fourth memory cell U34 can also be symmetrical to each other based on the cell insulating structure 310.

[0137] As mentioned above, in accordance with the above references Figures 9 to 11 Compared to the semiconductor device 2 described, the semiconductor device 3 can double the density of memory cells by using the cell insulation structure 310.

[0138] Figure 15A and Figure 15B This is a cross-sectional view schematically illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Figure 16A and Figure 16B This is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0139] refer to Figure 15A A substrate insulating layer 202 and a lower channel contact layer 210 can be sequentially formed on a substrate 201. A gate structure 220 having a hole pattern 21 can be formed on the lower channel contact layer 210. Subsequently, a gate insulating layer 230, a channel layer 240, an oxide reaction layer 2510, and a reduction reaction layer 2710 can be sequentially formed on the sidewall surface of the gate structure 220 located inside the hole pattern 21. The oxide reaction layer 2510 and the reduction reaction layer 2710 can be compared with those mentioned above. Figure 7A The oxidation reaction layer 1510 and the reduction reaction layer 1710 described are essentially the same.

[0140] When the reduction reaction layer 2710 is formed on the oxidation reaction layer 2510, as mentioned above... Figure 7A and Figure 7B The silicon (Si) or aluminum (Al) in the oxide reaction layer 2510 can combine with oxygen in the reduction reaction layer 2710 to form silicon oxide or aluminum oxide. Therefore, the reduction reaction layer 2710 can be partially reduced. In another embodiment, after the reduction reaction layer 2710 is formed on the oxide reaction layer 2510, further heat treatment can be performed to promote the redox reaction between the oxide reaction layer 2510 and the reduction reaction layer 2710.

[0141] refer to Figure 15B The entire oxidation reaction layer ( Figure 15A 2510 can be oxidized and converted into resistor layer 250. Reduction reaction layer ( Figure 15A A portion of the reduced reaction layer 2710 (2710) that is reduced by reacting with the oxidation reaction layer 2510 can form the resistive switching layer 260. The resistive switching layer 260 may include oxygen vacancies caused by oxygen deficiency. A portion of the reduced reaction layer 2710 that does not participate in the reaction with the oxidation reaction layer 2510 can be retained to form the insulating layer 270. Subsequently, although in Figure 15B Not shown, but the hole pattern 21 can be filled with a fill layer. Subsequently, a channel contact layer and bit lines can be formed on the outside of the hole pattern 21. This can be targeted at... Figure 9 The hole pattern 22 is processed using the method described above. As a result, the above reference can be manufactured. Figures 9 to 11 Semiconductor device 2 as described.

[0142] In some embodiments, after filling the hole pattern 21 with a filler layer, a trench pattern extending in the y-direction across the diameter of the hole pattern 21 can be formed on the under-channel contact layer 210. By filling the trench pattern with an insulating material, a unit insulation structure can be formed. Subsequently, an over-channel contact layer and bit lines can be formed outside the hole pattern 21. As a result, a reference can be manufactured. Figure 13 and Figure 14 Semiconductor device 3 is described.

[0143] In some embodiments, after forming the resistive switching layer 260, the remaining insulating layer 270 can be removed. Subsequently, a filler layer can be used to fill the via pattern 21, and the filler layer can contact the resistive switching layer 260. Then, a channel contact layer and bit lines can be formed on the outside of the via pattern 21. As a result, as referenced above... Figures 9 to 11 The modification of the semiconductor device 2 described herein can be used to manufacture different semiconductor devices in which the insulating layer 270 is omitted.

[0144] In some embodiments, in forming Figure 15A and Figure 15B During the process of constructing the resistive switching layer 260, the resistive switching layer 260 may further include silicon (Si) or aluminum (Al) diffused from the oxide reaction layer 2510 into the resistive switching layer 260. The diffused silicon (Si) or aluminum (Al) can additionally reduce the metal oxide in the resistive switching layer 260. Due to the reduction of the metal oxide, the oxygen vacancy concentration in the resistive switching layer 260 will additionally increase.

[0145] Figure 16A and Figure 16B This is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor device according to another embodiment of the present disclosure. In one embodiment, reference is made to... Figure 16A and Figure 16B The described method can be applied to Figures 9 to 11 Semiconductor devices 2 and Figure 13 and Figure 14 3. Semiconductor devices.

[0146] refer to Figure 16A The substrate insulating layer 202 and the under-channel contact layer 210 can be sequentially formed on the substrate 201. The gate structure 220 having the hole pattern 21 can be formed on the under-channel contact layer 210.

[0147] Subsequently, the gate insulating layer 230, the channel forming layer 2410, and the reduction reaction layer 2710 can be sequentially formed on the sidewall surface of the gate structure 220 located inside the hole pattern 21.

[0148] The channel forming layer 2410 may include a semiconductor material. The configuration of the channel forming layer 2410 can be the same as described above. Figure 8AThe channel forming layer 1410 is configured substantially the same. The reduction reaction layer 2710 may include a metal oxide. The oxygen affinity of the semiconductor material in the channel forming layer 2410 may be greater than the oxygen affinity of the metal in the metal oxide of the reduction reaction layer 2710.

[0149] In embodiments of this disclosure, when the reduction reaction layer 2710 is formed on the channel forming layer 2410 comprising silicon (Si), a portion of the channel forming layer 2410 and a portion of the reduction reaction layer 2710 can react with each other. That is, a portion of the channel forming layer 2410 can be oxidized to silicon oxide, while a portion of the reduction reaction layer 2710 can be reduced. In another embodiment, after the reduction reaction layer 2710 is formed on the channel forming layer 2410, a further heat treatment can be performed to promote the redox reaction between the channel forming layer 2410 and the reduction reaction layer 2710.

[0150] As a result, Figure 16B As shown, the oxidized portion of the channel forming layer 2410 can form a resistor layer 250. The unoxidized portion of the channel forming layer 2410 can form a channel layer 240. The portion of the reduction reaction layer 2710 reduced by reaction with the channel forming layer 2410 can include an oxygen-deficient metal oxide (i.e., a metal oxide with oxygen vacancies). The reduced portion can form a resistive switching layer 260. The portion of the reduction reaction layer 2710 that does not participate in the reaction with the channel forming layer 2410 can be retained to form an insulating layer 270. Subsequently, a filling layer (not shown) can be formed by filling the hole pattern 21 with an insulating material. As a result, a reference can be manufactured. Figures 9 to 11 Semiconductor device 2 as described.

[0151] In some embodiments, after filling the hole pattern 21 with a filler layer, a trench pattern extending in a direction across the diameter of the hole pattern 21 can be formed on the under-channel contact layer 210. A unit insulation structure can be formed by filling the trench pattern with an insulating material. Subsequently, an over-channel contact layer and bit lines can be formed outside the hole pattern 21. As a result, a reference can be manufactured. Figure 13 and Figure 14 Semiconductor device 3 is described.

[0152] Figure 17 This is a perspective view schematically illustrating a semiconductor device according to yet another embodiment of the present disclosure. Figure 18 yes Figure 17 A plan view of a semiconductor device. Figure 19 It is along Figure 17 A cross-sectional view of the semiconductor device taken from line Ⅲ-Ⅲ′. Figure 20 It is along Figure 17 A cross-sectional view of the semiconductor device taken from line IV-IV′.

[0153] refer to Figures 17 to 20 The semiconductor device 4 may include a substrate 201 and a first gate structure 420 and a second gate structure 520 disposed above the substrate 201. The first gate structure 420 and the second gate structure 520 may extend parallel to each other in a second direction (i.e., the y-direction). The semiconductor device 4 may include a gate insulating layer 430, a channel layer 440, a resistor layer 450, a resistive switching layer 460, and an insulating layer 470 sequentially disposed on the sidewall surface of the first gate structure 420 above the substrate 201. Additionally, the semiconductor device 4 may include a gate insulating layer 530, a channel layer 540, a resistor layer 550, a resistive switching layer 560, and an insulating layer 570 sequentially disposed on the sidewall surface of the second gate structure 520 above the substrate 201.

[0154] refer to Figures 17 to 20 The substrate insulating layer 202 and the channel lower contact layer 210 can be sequentially disposed on the substrate 201.

[0155] The first gate structure 420 may be disposed on the lower contact layer 210. The first gate structure 420 may include a first gate electrode layer to a fourth gate electrode layer 422a, 422b, 422c and 422d, and a first interlayer insulating layer to a fifth interlayer insulating layer 423a, 423b, 423c, 423d and 423e, alternately stacked along a first direction (i.e., the z direction) perpendicular to the substrate 201. The first gate structure 420 may extend in a second direction (i.e., the y direction) perpendicular to the first direction (i.e., the z direction).

[0156] Each of the first to fourth gate electrode layers 422a, 422b, 422c, and 422d may include a conductive material. The conductive material of the first to fourth gate electrode layers 422a, 422b, 422c, and 422d may be the same as that referenced above. Figures 9 to 11 The conductive materials of the first to fourth gate electrode layers 222a, 222b, 222c, and 222d of the described semiconductor device 2 are substantially the same. Each of the first to fifth interlayer insulating layers 423a, 423b, 423c, 423d, and 423e may include an insulating material. The insulating materials of the first to fifth interlayer insulating layers 423a, 423b, 423c, 423d, and 423e may be the same as those referenced above. Figures 9 to 11 The insulating materials of the first to fifth interlayer insulating layers 223a, 223b, 223c, 223d and 223e of the semiconductor device 2 described are substantially the same.

[0157] Similarly, the second gate structure 520 may be disposed on the lower contact layer 210. The second gate structure 520 may include a first gate electrode layer to a fourth gate electrode layer 522a, 522b, 522c and 522d and a first interlayer insulating layer to a fifth interlayer insulating layer 523a, 523b, 523c, 523d ​​and 523e, which are alternately stacked along a first direction (i.e., the z direction) perpendicular to the substrate 201. The configuration of the first to fourth gate electrode layers 522a, 522b, 522c and 522d and the first to fifth interlayer insulating layers 523a, 523b, 523c, 523d ​​and 523e of the second gate structure 520 can be substantially the same as the configuration of the first to fourth gate electrode layers 422a, 422b, 422c and 422d and the first to fifth interlayer insulating layers 423a, 423b, 423c, 423d and 423e of the first gate structure 420.

[0158] In some embodiments, the number of gate electrode layers in the first gate structure 420 and the second gate structure 520 may not be limited to four. The gate electrode layers may be arranged in different numbers, and the interlayer insulating layer may insulate the various numbers of gate electrode layers from each other along the first direction (i.e., the z-direction).

[0159] refer to Figures 17 to 20 The gate insulating layer 430, channel layer 440, resistor layer 450, resistive switching layer 460, and insulating layer 470 sequentially disposed on the sidewall surface of the first gate structure 420 on the lower contact layer 210 can be respectively disposed on a plane parallel to the yz plane. Similarly, the gate insulating layer 530, channel layer 540, resistor layer 550, resistive switching layer 560, and insulating layer 570 sequentially disposed on the sidewall surface of the second gate structure 520 on the lower contact layer 210 can be respectively disposed on a plane parallel to the yz plane.

[0160] The material compositions of gate insulating layers 430 and 530, channel layers 440 and 540, resistor layers 450 and 550, resistive switching layers 460 and 560, and insulating layers 470 and 570 can be the same as those referenced above. Figures 9 to 11 The material composition of the gate insulating layer 230, channel layer 240, resistor layer 250, resistive switching layer 260 and insulating layer 270 described are substantially the same.

[0161] The first unit insulating structure 610a and the second unit insulating structure 610b can be disposed on the channel lower contact layer 210. The first unit insulating structure 610a and the second unit insulating structure 610b can be disposed on the substrate 201 and spaced apart from each other along the second direction (i.e., the y-direction). The first unit insulating structure 610a and the second unit insulating structure 610b can extend in a third direction (i.e., the x-direction) perpendicular to the first and second directions to separate or divide each of the gate insulating layers 430 and 530, each of the channel layers 440 and 540, each of the resistor layers 450 and 550, each of the resistive switching layers 460 and 560, and each of the insulating layers 470 and 570 in the second direction (i.e., the y-direction).

[0162] Therefore, the semiconductor device 4 may include a first memory cell to a sixth memory cell U41, U42, U43, U51, U52 and U53 separated from each other by a first unit insulating structure 610a and a second unit insulating structure 610b.

[0163] Although not shown, the first to sixth bit lines are connected to the first to sixth memory cells U41, U42, U43, U51, U52, and U53, respectively. The first to sixth bit lines can be electrically connected to the end of each of the channel layers 440 and 540 of the first to sixth memory cells U41, U42, U43, U51, U52, and U53, respectively. The other end of each of the channel layers 440 and 540 of the first to sixth memory cells U41, U42, U43, U51, U52, and U53 can be electrically connected to the source line via the lower channel contact layer 210.

[0164] The methods for operating the first to sixth memory units U41, U42, U43, U51, U52, and U53 can be the same as those described above. Figures 9 to 11 The operation methods of the first memory cell U21 and the second memory cell U22 of the described semiconductor device are substantially the same. That is, the operation methods of the first to the sixth memory cells U41, U42, U43, U51, U52 and U53 can follow the above-mentioned... Figure 12 The circuit diagram described.

[0165] The manufacturing of semiconductor device 4 can be referenced. Figures 17 to 20The following steps are performed in sequence. Specifically, a substrate insulating layer 202 and a lower channel contact layer 210 may be formed on a substrate 201. A first gate structure 420 and a second gate structure 520 may be formed on the lower channel contact layer 210. In this case, the first gate structure 420 and the second gate structure 520 may extend in a direction parallel to the surface of the substrate 201 (e.g., the y-direction). Furthermore, each of the first gate structure 420 and the second gate structure 520 may include at least one gate electrode layer and an interlayer insulating layer alternately stacked in a direction perpendicular to the surface of the substrate 201 (e.g., the z-direction). Subsequently, gate insulating layers 430 and 530, channel layers 440 and 540, and an oxidation reaction layer may be sequentially formed on the lower channel contact layer 210 and on the sidewall surfaces of each of the first gate structure 420 and the second gate structure 520. A reduction reaction layer may be formed on the oxidation reaction layer. Subsequently, the oxidation reaction layer and the reduction reaction layer can react to form resistor layers 450 and 550, resistive switching layers 460 and 560, and insulating layers 470 and 570.

[0166] The processes for forming gate insulating layers 430 and 530, channel layers 440 and 540, oxide reaction layers and reduction reaction layers, and the processes for forming resistor layers 450 and 550, resistive switching layers 460 and 560 and insulating layers 470 and 570 by reacting the oxide reaction layers and reduction reaction layers can be referenced above. Figure 15A and Figure 15B The corresponding processes of the described manufacturing methods are basically the same.

[0167] Subsequently, the filling layer 480 fills the space between the insulating layers 470 and 570, and can form a first unit insulating structure 610a and a second unit insulating structure 610b.

[0168] In some embodiments, after forming the first gate structure 420 and the second gate structure 520 on the lower contact layer 210, gate insulating layers 430 and 530 and a channel forming layer may be sequentially formed on the sidewall surfaces of each of the first gate structure 420 and the second gate structure 520. Subsequently, a reduction reaction layer may be formed on the channel forming layer. The channel forming layer and the reduction reaction layer may react to form channel layers 440 and 540, resistor layers 450 and 550, resistive switching layers 460 and 560, and insulating layers 470 and 570.

[0169] The processes for forming gate insulating layers 430 and 530, channel forming layers, and reduction reaction layers, as well as the processes for forming channel layers 440 and 540, resistor layers 450 and 550, resistive switching layers 460 and 560, and insulating layers 470 and 570 by reacting the channel forming layers and reduction reaction layers, can be referenced above. Figure 16A and Figure 16BThe corresponding processes of the described manufacturing methods are basically the same.

[0170] According to the various embodiments of this disclosure described above, a semiconductor device can be provided in which a resistive switching layer is disposed adjacent to the channel layer of a transistor. A set voltage and a reset voltage can be applied to both ends of the resistive switching layer by turning the transistor on / off. Furthermore, by controlling the distribution of oxygen vacancies in the resistive switching layer, the resistance state of the resistive switching layer can be reversibly changed between a low resistance state and a high resistance state. Moreover, in the various embodiments of this disclosure, by using a resistor layer adjacent to the resistive switching layer, the resistance state of the resistive switching layer can be gradually switched according to the applied voltage. As a result, the embodiments of this disclosure can provide a semiconductor device capable of effectively storing multiple variable resistance states as signal information in the resistive switching layer.

[0171] Although the embodiments have been described above with reference to the accompanying drawings, those skilled in the art will understand that various modifications and variations can be made to the embodiments disclosed in this application without departing from the spirit of the application as described in the appended claims.

Claims

1. A semiconductor device comprising: a substrate; a gate structure provided above the substrate, the gate structure including at least one gate electrode layer and at least one interlayer insulating layer alternately stacked above the substrate; a hole pattern penetrating the gate structure above the substrate; and a gate insulating layer, a channel layer, a resistor layer, and a resistance variable layer sequentially provided on a sidewall surface of the gate structure within the hole pattern, wherein each of the resistor layer and the resistance variable layer is provided opposite to the gate insulating layer based on the channel layer, wherein the resistor layer has a constant resistivity, includes an oxide material having a predetermined resistance, and wherein the resistance variable layer includes a metal oxide having oxygen vacancies, and the oxygen vacancies are movable under an electric field. The resistance variable layer has a resistance varied according to a distribution of the oxygen vacancies within the resistance variable layer.

2. The semiconductor device of claim 1, wherein, The resistance variable layer includes a non-stoichiometric metal oxide, and the metal oxide has an insufficient amount of oxygen with respect to a metal.

3. The semiconductor device of claim 1, wherein, The metal oxide includes at least one selected from the group consisting of lithium oxide, titanium oxide, nickel oxide, copper oxide, manganese oxide, hafnium oxide, zirconium oxide, tungsten oxide, niobium oxide, and vanadium oxide.

4. The semiconductor device of claim 3, wherein, The resistance variable layer further includes an impurity bonded with oxygen, and the impurity includes silicon (Si) or aluminum (Al).

5. The semiconductor device of claim 4, wherein, The thickness of the resistor layer is 1 nm to 5 nm.

6. The semiconductor device of claim 1, wherein, The resistor layer includes silicon oxide or aluminum oxide.

7. The semiconductor device of claim 1, wherein, 8. The semiconductor device according to claim 1, further comprising: an insulating layer provided to contact the resistance variable layer within the hole pattern; and a filling layer provided to contact the insulating layer and fill the hole pattern. The resistance variable layer and the insulating layer include the same metal oxide, and the metal oxide of the resistance variable layer has a smaller amount of oxygen than the metal oxide of the insulating layer.

10. The semiconductor device according to claim 8, further comprising a cell insulating structure provided above the substrate, the cell insulating structure connected to the filling layer and bisecting the hole pattern, 9. The semiconductor device of claim 8, wherein, the cell insulating structure separating each of the gate structure, the gate insulating layer, the channel layer, the resistor layer, the resistance variable layer, and the insulating layer in a direction across a diameter of the hole pattern. End portions of the channel layer are connected to a source line and a bit line, respectively. wherein 12. A semiconductor device comprising:

11. The semiconductor device of claim 1, wherein, a substrate; a gate structure provided above the substrate, the gate structure including at least one gate electrode layer and at least one interlayer insulating layer alternately stacked above the substrate in a first direction perpendicular to the substrate, and the gate structure extending in a second direction perpendicular to the first direction; and a gate insulating layer, a channel layer, a resistor layer, and a resistance variable layer sequentially provided on a sidewall surface of the gate structure above the substrate, wherein each of the resistor layer and the resistance variable layer is provided opposite to the gate insulating layer based on the channel layer, wherein the resistor layer has a constant resistivity, includes an oxide material having a predetermined resistance, and wherein the resistance variable layer includes a metal oxide having oxygen vacancies, and the oxygen vacancies are movable under an electric field. ​ wherein the resistor layer has a constant resistivity, includes an oxide material having a predetermined resistance, and wherein the resistance variable layer includes a metal oxide having oxygen vacancies, and the oxygen vacancies move along an electric field.

13. The semiconductor device of claim 12, further comprising an insulating layer disposed on the substrate to contact the resistance variable layer.

14. The semiconductor device of claim 13, wherein, The resistance variable layer and the insulating layer include the same metal oxide, and the metal oxide of the resistance variable layer has a smaller amount of oxygen than the metal oxide of the insulating layer.

15. The semiconductor device of claim 14, further comprising a plurality of unit insulating structures disposed above the substrate to be spaced apart from each other in the second direction.

16. The semiconductor device of claim 15, wherein, The plurality of unit insulating structures are disposed to extend in a third direction perpendicular to the first and second directions, and the plurality of unit insulating structures separate each of the gate insulating layer, the channel layer, the resistor layer, the resistance variable layer, and the insulating layer.

17. The semiconductor device of claim 12, wherein, The resistance variable layer has a resistance that varies according to a distribution of oxygen vacancies within the resistance variable layer, and wherein the resistor layer has a fixed resistivity.

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