A three-level driver for driving an IGBT

Abstract

The application discloses a three-level driver for driving an IGBT, comprising a fault latching unit, a logic control unit, a signal logic processing unit and a power output unit; wherein the signal logic processing unit is used for realizing the interlocking, timing control and fault blocking processing of a PWM input signal according to the PWM input signal provided by an external controller and the fault latching signal provided by the logic control unit, and providing the PWM pulse signal obtained after the processing to the logic control unit; the logic control unit is used for generating and outputting a corresponding driving control signal according to the PWM pulse signal provided by the signal logic processing unit and the fault latching signal provided by the fault latching unit; and the power output unit is used for performing power conversion on the driving control signal provided by the logic control unit, generating and outputting a corresponding driving signal, so as to control the turn-on, turn-off and 0-level turn-off functions of the IGBT driven by the three-level driver.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power devices, in particular to a three-level driver for driving IGBT. BACKGROUND

[0002] With the continuous development of high-speed train technology, the requirements for the safety and stability of the train are also getting higher and higher. As an important part of the train power system, the drive circuit of the converter module in the traction converter plays an extremely important role. Compared with the traditional two-level drive circuit, the voltage borne by the three-level drive circuit when the IGBT is turned off is only half of the two-level drive circuit. Moreover, the three-level drive circuit is conducive to suppressing harmonics. Therefore, the three-level drive circuit is superior to the two-level drive circuit in terms of overall power quality of the traction converter, module application environment, and performance in extreme and fault conditions. However, the introduction of three levels increases the complexity of the circuit, and it is relatively complex in control and driving, especially in the timing control of the pulse switch of the inner and outer IGBT tubes. SUMMARY

[0003] In view of the above problems, the present application provides a three-level driver for driving IGBT, which realizes the driving function of IGBT tube and ensures the turn-on and turn-off timing of inner tube IGBT and outer tube IGBT.

[0004] According to a first aspect, the present application provides a three-level driver for driving IGBT, comprising a fault latching unit, a logic control unit, a signal logic processing unit and a power output unit; wherein:

[0005] The fault latching unit is configured to generate and output a fault latching signal that can be timed and locked according to the received various fault signals;

[0006] The first input end of the logic control unit is connected to the output end of the fault latching unit, and the first output end of the logic control unit is connected to the first input end of the signal logic processing unit, and is configured to forward the fault latching signal provided by the fault latching unit to the signal logic processing unit;

[0007] The second input end of the signal logic processing unit is connected to the output end of the external controller, and the first output end of the signal logic processing unit is connected to the second input end of the logic control unit, and is configured to process the interlocking, timing control and fault locking of the PWM input signal according to the PWM input signal provided by the controller and the fault latching signal provided by the logic control unit, and provide the PWM pulse signal obtained after processing to the logic control unit;

[0008] The logic control unit is further configured to generate and output a corresponding driving control signal according to a PWM pulse signal provided by the signal logic processing unit and a fault latch signal provided by the fault latch unit; wherein the PWM pulse signal determines the high and low levels of the driving control signal, and the fault latch signal controls the high and low levels of the driving control signal.

[0009] The power output unit is connected to the second output end of the logic control unit, and is configured to perform power conversion on the driving control signal provided by the logic control unit, to generate and output a corresponding driving signal, so as to control the turn-on, turn-off and 0-level turn-off functions of the IGBT driven by the three-level driver.

[0010] According to some embodiments of the present application, the three-level driver further comprises:

[0011] The signal isolation unit is connected between the signal logic processing unit and the logic control unit, and is configured to realize isolation of the PWM pulse signal and the fault latch signal.

[0012] According to some embodiments of the present application, the three-level driver further comprises:

[0013] The power supply unit is configured to convert an external input power into a driving power used by the three-level driver to drive the IGBT.

[0014] The power supply monitoring unit is connected to the power supply unit, and is configured to monitor the driving power output by the power supply unit, and output a power fault signal when the driving power does not meet a preset power condition.

[0015] The state monitoring unit is configured to acquire a state parameter of the IGBT driven by the three-level driver, and output a state fault signal when the state parameter does not meet a preset state condition.

[0016] Correspondingly, the fault latch unit is connected to the power supply monitoring unit and the state monitoring unit, and is configured to generate and output a timing-locked fault latch signal according to the power fault signal provided by the power supply monitoring unit and the state fault signal provided by the state monitoring unit.

[0017] According to some embodiments of the present application, in the three-level driver, the power supply unit comprises:

[0018] The EMI filtering sub-unit is configured to perform filtering processing on the external input power.

[0019] The auxiliary power supply sub-unit is connected to the EMI filtering unit, and is configured to convert the filtered external input power into an auxiliary power.

[0020] an isolated DC / DC subunit connected to the auxiliary power supply subunit, for realizing isolated conversion of the power supply under the support of the auxiliary power supply, and outputting a driving power source for driving the IGBT of the three-level driver.

[0021] According to some embodiments of the present application, the three-level driver comprises a state monitoring subunit, a setting subunit, a monitoring subunit, and a comparison subunit.

[0022] The setting subunit is configured to set a state parameter threshold value.

[0023] The monitoring subunit is configured to acquire a state parameter of the IGBT driven by the three-level driver.

[0024] The comparison subunit is connected to the setting subunit and the monitoring subunit, and is configured to compare the state parameter with the state parameter threshold value, and determine whether to output a state fault signal according to the comparison result.

[0025] According to some embodiments of the present application, the power supply fault signal comprises an under-voltage fault signal, and the state parameter of the IGBT comprises a gate voltage signal and a gate voltage signal of the IGBT.

[0026] According to some embodiments of the present application, the three-level driver comprises a signal logic processing subunit.

[0027] The fault latch signal comprises a fault latch signal of an inner tube IGBT and a fault latch signal of an outer tube IGBT.

[0028] The PWM input signal comprises an inner tube PWM input signal and an outer tube PWM input signal.

[0029] The PWM pulse signal comprises an inner tube PWM pulse signal and an outer tube PWM pulse signal.

[0030] According to some embodiments of the present application, the signal logic processing subunit comprises a first subunit for realizing signal interlocking, and a second subunit for realizing signal timing control and fault blocking.

[0031] The first subunit comprises a first NAND gate and a second NAND gate, a first input end of the first NAND gate is configured to receive the inner tube PWM input signal, a second input end of the first NAND gate is configured to receive a high level, a first input end of the second NAND gate is connected to an output end of the first NAND gate, and a second input end of the second NAND gate is configured to receive the outer tube PWM input signal.

[0032] The second subunit comprises a fault determination circuit and a third NAND gate and a fourth NAND gate, two input ends of the fault determination circuit are used for receiving fault latching signals of the inner tube IGBT and fault latching signals of the outer tube IGBT, so as to generate and output a fault lock signal when the fault latching signals of the inner tube IGBT and / or the fault latching signals of the outer tube IGBT are received, a first input end of the third NAND gate and a first input end of the fourth NAND gate are used for receiving output signals of the first NAND gate and the second NAND gate after being processed by inversion respectively, and a second input end of the third NAND gate and a second input end of the fourth NAND gate are used for receiving the fault lock signal, so as to output the inner tube PWM pulse signal and the outer tube PWM pulse signal with fault lock function according to the fault lock signal respectively.

[0033] By adjusting the capacitance parameters of the fault lock signal input into the third NAND gate and the fourth NAND gate respectively, the timing control function of locking the outer tube first and then locking the inner tube in the case of fault is realized.

[0034] According to some embodiments of the present application, in the three-level driver, the signal logic processing unit further comprises a first filter circuit and a second filter circuit, the first filter circuit and the second filter circuit are arranged between the first NAND gate and the controller and between the second NAND gate and the controller respectively, and are used for adjusting the inner tube PWM input signal and the outer tube PWM input signal input simultaneously, so that the inner tube PWM input signal is input into the first NAND gate earlier than the outer tube PWM input signal is input into the second NAND gate.

[0035] According to some embodiments of the present application, in the three-level driver, a second output end of the signal logic processing unit is connected with an input end of the controller, and is used for forwarding the fault latching signal provided by the logic control unit to the controller.

[0036] Compared with the prior art, one or more embodiments in the above scheme of the present application can have the following advantages or beneficial effects:

[0037] 1) The technical scheme of the present application realizes the time sequence distinction of the inner tube and the outer tube of the pulse signal in the three-level topology through the signal receiving logic processing circuit, ensures the correctness of the time sequence of the inner tube and the outer tube when the three-level circuit works normally, and provides strong help for the normal work of the IGBT.

[0038] 2) The technical scheme of the present application generates a fault latching signal that can be locked in time based on various types of faults, and feeds back the fault latching signal to an external controller, which can be directly used for upper intelligent control.

[0039] 3) The technical scheme of the present application realizes intelligent monitoring of the IGBT power device, can monitor the change state of each voltage of the IGBT power device in real time, and enhances the reliability and stability of intelligent control.

[0040] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent to those skilled in the art from the description, or can be learned by practice of the present application. The objects and other advantages of the present application can be realized and attained by the structure particularly pointed out in the description and the appended drawings. BRIEF DESCRIPTION OF DRAWINGS

[0041] The scope of the present disclosure can be better understood by reading the detailed description of exemplary embodiments, when considered in connection with the accompanying drawings. The drawings included in the present disclosure are:

[0042] Figure 1 The composition schematic diagram of the three-level driver shown in the embodiment of the present application is shown;

[0043] Figure 2 The schematic diagram of each module in the three-level driver shown in the embodiment of the present application is shown;

[0044] Figure 3 The composition structure schematic diagram of the signal logic processing unit in the three-level driver shown is shown. Figure 1 The composition structure schematic diagram of the signal logic processing unit in the three-level driver shown is shown. DETAILED DESCRIPTION

[0045] In order to make the objects, technical schemes and advantages of the present application more clear, the implementation method of the present application will be described in detail below in combination with the drawings and embodiments, so that the implementation process of how the present application applies technical means to solve technical problems and achieve technical effects can be fully understood and implemented.

[0046] In the following description, many specific details are set forth in order to provide a thorough understanding of the present application, however, the present application can also be implemented in other ways different from those described herein, therefore, the protection scope of the present application is not limited by the specific embodiments disclosed below.

[0047] As Figure 1 shown, the exemplary three-level driver provided by the present embodiment is used to drive IGBT. The driver mainly includes a power supply unit 110, a power supply monitoring unit 120, a state monitoring unit 130, a fault latching unit 140, a signal logic processing unit 150, a signal isolation unit 160, a logic control unit 170, and a power output unit 180. These circuit modules are preferably arranged on a driver circuit board. From the functional point of view, these circuit modules work together to complete three major functions of voltage conversion, drive control and fault monitoring. Among them:

[0048] The power supply unit 110 further comprises an EMI filtering subunit 111, an auxiliary power supply subunit 112 and an isolated DC / DC subunit 113, which are used to filter the external input power supply through the EMI filtering subunit 111 for internal use of the single board of the driving device, and to generate a driving voltage for driving the IGBT on the high-voltage side of the IGBT through the auxiliary power supply subunit 112 and the isolated DC / DC subunit 113.

[0049] The signal logic processing unit 150 completes the conversion of the externally input PWM input signal and the internal and external tube timing fault control, and converts the PWM input signal into a driving control signal on the high-voltage side through the signal isolation unit 160, the logic control unit 170 and the power output unit 180, so as to be used for driving control of the IGBT device.

[0050] The power supply monitoring unit 120 monitors whether the driving voltage output by the power supply unit 110 is normal, the state monitoring unit 130 monitors and judges whether the working state of the IGBT device driven by the driver is normal, and the fault latching unit 140 realizes the fault protection function according to the fault information fed back by the power supply monitoring unit 120 and the state monitoring unit 130.

[0051] As shown in Figure 2 The circuit connection and functional configuration of each unit are described in detail below.

[0052] As described before, in the present embodiment, the power supply unit 110 further comprises an EMI filtering subunit 111, an auxiliary power supply subunit 112 and an isolated DC / DC subunit 113, wherein:

[0053] The EMI filtering subunit 111 is used to filter the externally input power supply.

[0054] The auxiliary power supply subunit 112 is connected to the EMI filtering subunit 111 and is used to convert the externally input power supply after filtering into an auxiliary power supply.

[0055] The isolated DC / DC subunit 113 is connected to the auxiliary power supply subunit 112 and is used to realize the isolated conversion of the power supply under the support of the auxiliary power supply, and to output a driving power supply for driving the IGBT of the three-level driver.

[0056] The power supply monitoring unit 120 is connected to the power supply unit 110 and is used to monitor the driving power supply output by the power supply unit 110, and to output a power supply fault signal when the driving power supply does not meet the preset power supply condition. In actual application, the most common scheme is that the power supply monitoring unit 120 monitors the driving voltage output by the power supply unit 110, and outputs an under-voltage fault signal when the driving voltage is lower than the preset voltage threshold.

[0057] The state monitoring unit 130 further comprises a setting subunit 131, a monitoring subunit 132 and a comparison subunit 133, wherein:

[0058] The setting subunit 131 is configured to set a state parameter threshold value.

[0059] The monitoring subunit 132 is configured to acquire a state parameter of the IGBT driven by the three-level driver.

[0060] The comparison subunit 133 is connected to the setting subunit 131 and the monitoring subunit 132, and is configured to compare the state parameter with the state parameter threshold value, and determine whether to output a state fault signal according to a comparison result.

[0061] In the embodiment, the state parameter of the IGBT at least includes a gate voltage signal and a grid voltage signal of the IGBT. In addition, in the embodiment, since the inner tube IGBT and the outer tube IGBT are driven and monitored at the same time, the acquired state parameter includes a state parameter of the inner tube IGBT and a state parameter of the outer tube IGBT, and the corresponding state fault signal includes two fault signals, i.e., a state fault signal of the inner tube IGBT and a state fault signal of the outer tube IGBT.

[0062] The fault latching unit 140 is connected to the power monitoring unit 120 and the state monitoring unit 130, and is configured to generate and output a timing-locked fault latching signal according to a power fault signal provided by the power monitoring unit 120 and a state fault signal provided by the state monitoring unit.

[0063] The fault latching unit 140 herein is a set of logic digital circuits, which is configured to form and output a timing-locked fault latching signal after comprehensively processing various fault signals (such as an under-voltage fault signal and a state fault signal). It should be noted that, in the embodiment, since the inner tube IGBT and the outer tube IGBT are driven and monitored at the same time, the states of the inner tube IGBT and the outer tube IGBT are independent of each other, and the probabilities of faults are also independent of each other, and the fault latching unit 140 outputs two latching signals, i.e., an inner tube IGBT fault latching signal and an outer tube IGBT fault latching signal.

[0064] The logic control unit 170 comprises a first input end and a second input end, and a first output end and a second output end. In one aspect, the first input end of the logic control unit 170 is connected to the output end of the fault latching unit 140, and the first output end of the logic control unit 170 is connected to the first input end of the signal logic processing unit 150 through the signal isolation unit 160, for forwarding the fault latching signal provided by the fault latching unit 140 to the signal logic processing unit 150; in another aspect, the second input end of the logic control unit 170 is connected to the first output end of the signal logic processing unit 150 through the signal isolation unit 160, and the second output end of the logic control unit 150 is connected to the input end of the power output unit 180, for generating a corresponding drive control signal according to the PWM pulse signal provided by the signal logic processing unit 150 and the fault latching signal provided by the fault latching unit 140, and outputting the drive control signal to the power output unit 180; wherein the PWM pulse signal determines the high and low levels of the drive control signal, and the fault latching signal controls the high and low levels of the drive control signal to be soft-off.

[0065] It should be noted that, in order to simplify, Figure 1 The output end of the fault latching unit 140, the first input end and the second input end and the first output end and the second output end of the signal logic processing unit 150, the input end and the output end of the signal isolation unit 160, the first input end of the logic control unit 170, the first output end of the logic control unit 170, the second input end of the logic control unit 170, the second output end of the logic control unit 170, and the input end and the output end of the power output unit 180 are all indicated by a line, but in fact these lines are used to transmit two-way inner tube signals and outer tube signals. In this regard, the signal isolation unit 160 also comprises two sub-units 161 and 162 for isolating the inner tube signals and the outer tube signals, respectively.

[0066] As mentioned above, the signal logic processing unit 150 also comprises a first input end and a second input end as well as a first output end and a second output end. In one aspect, the first input end of the signal logic processing unit 150 is connected to the first output end of the logic control unit 170, the second input end of the signal logic processing unit 150 is connected to the output end of an external controller (not shown in the figure), and the first output end of the signal logic processing unit 150 is connected to the second input end of the logic control unit 170, for realizing the interlocking, timing control and fault blocking processing of the PWM input signal according to the PWM input signal provided by the controller and the fault latching signal provided by the logic control unit, and providing the PWM pulse signal obtained after the processing to the logic control unit 170. In another aspect, the second output end of the signal logic processing unit 150 is externally connected to the controller, for forwarding the fault latching signal provided by the logic control unit 170 to the controller to feedback the fault information.

[0067] As shown in the figure, in the embodiment, the signal logic processing unit 150 further comprises a first sub-unit 151 for realizing signal interlocking and a second sub-unit 152 for realizing signal timing control and fault blocking; wherein: Figure 3

[0068] The first sub-unit 151 comprises a first NAND gate 1 and a second NAND gate 2, the first input end of the first NAND gate 1 is used for receiving the inner tube PWM input signal, the second input end of the first NAND gate 1 is used for receiving a high level, the first input end of the second NAND gate 2 is connected to the output end of the first NAND gate 1, and the second input end of the second NAND gate 2 is used for receiving the outer tube PWM input signal.

[0069] The second sub-unit 152 comprises a fault third NAND gate 3 and a fourth NAND gate 4 as well as a fault determination circuit 5, the two input ends of the fault determination circuit 5 are used for receiving the fault latching signal of the inner tube IGBT and the fault latching signal of the outer tube IGBT, to generate and output a fault blocking signal when the fault latching signal of the inner tube IGBT and / or the fault latching signal of the outer tube IGBT is received, the first input end of the third NAND gate 3 and the first input end of the fourth NAND gate 4 are respectively used for receiving the output signals of the first NAND gate 1 and the second NAND gate 2 after the inversion processing (for example, by an inverter circuit, not shown in the figure), and the second input end of the third NAND gate 3 and the second input end of the fourth NAND gate 4 are used for receiving the fault blocking signal, to respectively output the inner tube PWM pulse signal and the outer tube PWM pulse signal with the fault blocking function according to the fault blocking signal.

[0070] ​In the embodiment, the timing control function of locking the outer tube first and then the inner tube in failure is realized by adjusting the capacitance parameters of the failure lock signal input to the third and fourth NAND gates 3 and 4, respectively.

[0071] In the embodiment, the signal logic processing unit 140 further comprises a first filter circuit 6 and a second filter circuit 7, which are respectively arranged between the first NAND gate 1 and the controller and between the second NAND gate 2 and the controller, for adjusting the simultaneously input inner tube PWM input signal and outer tube PWM input signal, so that the inner tube PWM input signal is input to the first NAND gate 1 earlier than the outer tube PWM input signal is input to the second NAND gate 2.

[0072] As shown in Figure 3 Based on the above circuit structure, the working mechanism of the signal logic processing unit 140 is as follows:

[0073] The signal logic processing unit realizes the timing control of the PWM signal and completes the failure lock by comprehensively logically processing the PWM input signal and the failure lock signal of the controller, and also outputs the failure lock signal to the controller. Among them, the timing of the inner tube opening first and the outer tube opening later needs to be ensured to ensure that the device will not be damaged due to overvoltage.

[0074] Therefore, the two-way PWM input signal is input to the filter circuit of the signal logic processing unit, and after filtering, it is transmitted to the first subunit. Among them, the filtering parameters of the two filter circuits need to be fine-tuned to ensure that when the inner and outer tube PWM input signals arrive at the same time, the PWM input signal of the inner tube can be input to the corresponding first NAND gate first. The first and second NAND gates realize the timing control of the pulse opening. The specific logic is: when PWM1 and PWM2 are both 0, the outputs of the two NAND gates are both 1; when PWM1 jumps to 1, the output of NAND gate 1 is 0, and the output of NAND gate 2 is 1, at this time PWM2 jumps to 1 again, and the output of NAND gate 2 can only be 0, thereby ensuring the logic of the inner tube opening first; similarly, when PWM2 jumps to 1, because the inner tube pulse PWM1 is not 1, the output logic of NAND gate 1 remains 0, at this time the output of NAND gate 2 maintains 1, thereby ensuring the timing of the outer tube opening later. Then, the output of NAND gate 1 / 2 is inverted to restore the same logic as the external input signal.

[0075] The fault latch signal is input to the signal logic processing unit, and a fault blocking signal is output by the fault judging circuit. When there is no fault, the fault blocking signal is high; when there is a fault, the fault blocking signal is low. The fault blocking signal and the output signal of the first / second NAND gate after being processed by inversion are input to the third / fourth NAND gate again at the same time, at which time, when there is no fault and there is a pulse input, the output of the third / fourth NAND gate is 0; when there is no pulse input, the output of the third / fourth NAND gate is 1; and when there is a fault, the output of the third / fourth NAND gate is 1 regardless of whether there is a pulse input.

[0076] In addition, the capacitance parameter of the fault blocking signal input to the third / fourth NAND gate needs to be adjusted to realize the timing control of blocking the outer tube pulse and then blocking the inner tube pulse when there is a fault.

[0077] Thus, the timing control of the PWM signal and the fault blocking are realized through the above working mechanism.

[0078] As described above, the logic control unit 170 generates corresponding drive control signals according to the PWM pulse signal processed by timing control and fault blocking provided by the signal logic processing unit 150 and the fault latch signal provided by the fault latch unit 140, and outputs the drive control signals to the power output unit 180; the second output end of the logic control unit 170 is used to perform power conversion on the drive control signals provided by the logic control unit 170, generate and output corresponding drive signals to control the IGBT driven by the three-level driver. It should be noted that in this embodiment, since the inner tube IGBT and the outer tube IGBT are driven, the drive control signals and the drive signals each include two drive signals, i.e., the drive control signal for driving the inner tube IGBT and the drive control signal for driving the outer tube IGBT, and the drive signal for driving the inner tube IGBT and the drive signal for driving the outer tube IGBT.

[0079] In addition, the three-level driver described above further includes an external interface 190, which is arranged between the power supply monitoring unit 120, the state monitoring unit 130 and the power output unit 180 and the IGBT power device driven by the three-level driver, and is used to isolate and transmit the drive voltage, the state parameter and the drive control signal. Since it is prior art, it will not be described here.

[0080] The present application realizes the inner and outer tube timing distinction of the pulse signal in the three-level topology through the signal receiving logic processing circuit, and ensures that the inner and outer tube timing will not be wrong when the three-level circuit works normally.

[0081] It should be understood that the disclosed apparatus and methods provided in the several embodiments of the present application can be implemented in other ways. For example, the division of the units is merely illustrative, and the division is merely a logical function division. In actual implementation, another division manner can be used, for example, a plurality of units or components can be combined or integrated into another system, or some features can be omitted or not executed.

[0082] It should be noted that the method of the embodiments of the present application can be executed by a single device, such as a computer or a server. The method of the embodiments of the present application can also be applied to a distributed scenario, and be completed by a plurality of devices cooperating with each other. In the distributed scenario, one of the plurality of devices can only execute one or more steps in the method of the embodiments of the present application, and the plurality of devices can interact with each other to complete the method.

[0083] Any process or method descriptions or any other descriptions provided in the flow diagrams or otherwise described herein can be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps in the process. As would be understood by those of ordinary skill in the art that the scope of the preferred embodiments of the present application encompasses other implementations having fewer than or more than the steps described in the figures and described herein, and that the order of the steps can be changed, including according to the functionality involved, without departing from the scope of the preferred embodiments of the present application.

[0084] It should be understood that various parts of the present application can be realized in hardware, software, firmware or a combination thereof. In the above embodiments, multiple steps or methods can be realized in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if realized in hardware, and as in another embodiment, any of the following technologies known in the art or their combination can be used: discrete logic circuit with logic gates for implementing logical functions on data signals, application specific integrated circuit with suitable combination logic gates, programmable gate array (PGA), field programmable gate array (FPGA), etc.

[0085] Although the disclosed embodiments of the present application are as above, the above description is only to facilitate understanding of the embodiments of the present application, and is not intended to limit the present application. Any person skilled in the art of the present application can make any modification and change in the implementation form and details without departing from the spirit and scope of the present application. The scope of protection of the present application shall be subject to the scope defined by the appended claims.

Claims

1. A three-level driver for driving IGBTs, characterized in that, It includes a fault latch unit, a logic control unit, a signal logic processing unit, and a power output unit; wherein: The fault latch unit is used to generate and output a fault latch signal that can be locked at a time based on the various fault signals received. The logic control unit is used to forward the fault latch signal to the signal logic processing unit; The signal logic processing unit includes a first subunit and a second subunit for implementing signal timing control and fault blocking. It processes the PWM input signal provided by the external controller and the fault latch signal, implements timing control and fault blocking of the PWM input signal, and provides the processed PWM pulse signal to the logic control unit. It is necessary to ensure that the inner transistor turns on first and then turns off, and the outer transistor turns on last and then turns off first. The logic control unit is further configured to generate and output a corresponding drive control signal based on the PWM pulse signal and the fault latch signal; wherein the PWM pulse signal determines the high and low levels of the drive control signal, and the fault latch signal controls the soft shutdown of the high and low levels of the drive control signal. The power output unit is used to control the IGBT driven by the three-level driver; The PWM input signal includes the inner tube PWM input signal and the outer tube PWM input signal; The first sub-unit includes a first NAND gate and a second NAND gate; the first input terminal of the first NAND gate is used to receive the PWM input signal of the inner tube, and the second input terminal is used to receive a high level; the first input terminal of the second NAND gate is connected to the output terminal of the first NAND gate, and the second input terminal is used to receive the PWM input signal of the outer tube. The second subunit includes a fault determination circuit and a third NAND gate and a fourth NAND gate. The two input terminals of the fault determination circuit are used to receive the fault latch signal of the inner IGBT and the fault latch signal of the outer IGBT included in the fault latch signal, so as to generate and output a fault blocking signal when the fault latch signal of the inner IGBT and / or the fault latch signal of the outer IGBT are received. The first input terminal of the third NAND gate and the first input terminal of the fourth NAND gate are respectively used to receive the output signals of the first NAND gate and the second NAND gate after inversion processing. The second input terminal of the third NAND gate and the second input terminal of the fourth NAND gate are used to receive the fault blocking signal, so as to output PWM pulse signals with fault blocking function according to the fault blocking signal. Specifically, by adjusting the capacitor parameters of the fault blocking signal input to the third and fourth NAND gates respectively, a timing control function is achieved to first block the outer tube and then the inner tube when a fault occurs.

2. The three-level driver for driving IGBTs as described in claim 1, characterized in that, Also includes: A signal isolation unit is connected between the signal logic processing unit and the logic control unit to isolate the PWM pulse signal from the fault latch signal.

3. The three-level driver for driving IGBTs as described in claim 1, characterized in that, Also includes: The power supply unit is used to convert the external input power into the driving power used by the three-level driver to drive the IGBT. A power monitoring unit, which is connected to the power supply unit, is used to monitor the drive power output by the power supply unit and output a power fault signal when the drive power fails to meet the preset power conditions. The status monitoring unit is used to acquire the status parameters of the IGBT driven by the three-level driver, and output a status fault signal when the status parameters do not meet the preset status conditions. Accordingly, the fault latching unit is connected to the power monitoring unit and the status monitoring unit, and is used to generate and output a fault latching signal that can be locked at a time based on the power fault signal provided by the power monitoring unit and the status fault signal provided by the status monitoring unit.

4. The three-level driver for driving IGBTs as described in claim 3, characterized in that, The power supply unit includes: The EMI filter subunit is used to filter the external input power supply. An auxiliary power supply unit, which is connected to the EMI filter unit, is used to convert the filtered external input power into an auxiliary power supply. An isolated DC / DC subunit, connected to the auxiliary power supply unit, is used to achieve isolated power conversion with the support of the auxiliary power supply, and outputs the driving power of the three-level driver to drive the IGBT.

5. The three-level driver for driving IGBTs as described in claim 3, characterized in that, The status monitoring unit includes: Set up a sub-unit to set the threshold value of the state parameter; A monitoring subunit is used to acquire the state parameters of the IGBT driven by the three-level driver; The comparison subunit, which connects the setting subunit and the monitoring subunit, is used to compare the state parameter with the state parameter threshold and determine whether to output a state fault signal based on the comparison result.

6. The three-level driver for driving IGBTs as described in any one of claims 3 to 5, characterized in that, The power failure signal includes an undervoltage fault signal; The state parameters of the IGBT include the gate voltage signal and the gate voltage signal.

7. The three-level driver for driving IGBTs as described in claim 1, characterized in that, The signal logic processing unit further includes a first filtering circuit and a second filtering circuit. The first filtering circuit and the second filtering circuit are respectively disposed between the first NAND gate and the controller and between the second NAND gate and the controller, and are used to adjust the simultaneously input inner tube PWM input signal and outer tube PWM input signal to such that the inner tube PWM input signal is input to the first NAND gate earlier than the outer tube PWM input signal is input to the second NAND gate.

8. The three-level driver for driving IGBTs as described in claim 1, characterized in that, The second output terminal of the signal logic processing unit is connected to the input terminal of the controller, and is used to forward the fault latch signal provided by the logic control unit to the controller.

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