A power supply circuit, method, chip and electronic device based on a phase-locked loop

Abstract

The present invention provides a power supply circuit, method, chip and electronic device based on a phase-locked loop. The power supply circuit based on the phase-locked loop includes: a phase-locked loop circuit including a voltage-controlled oscillator; the phase-locked loop circuit outputs, through its output terminal, a control voltage for controlling the voltage-controlled oscillator; a voltage regulator; an input end of the voltage regulator is connected to the output terminal of the phase-locked loop circuit, so that the control voltage output by the phase-locked loop circuit forms a power supply voltage after passing through the voltage regulator; wherein, the power supply voltage is used to supply power to a load circuit, and the load circuit includes at least one logic gate. The power supply circuit based on the phase-locked loop can reduce the timing variation in a digital circuit, which is beneficial to achieving timing convergence.

Description

Technical Field

[0001] The present invention relates to an integrated circuit, and in particular to a power supply circuit, method, chip and electronic equipment based on a phase-locked loop. Background Art

[0002] A digital circuit or digital integrated circuit is a complex circuit composed of many logic gates; compared with an analog circuit, it mainly processes digital signals (i.e., the signal is represented by two states, 0 and 1), so it has a stronger anti-interference ability. Unlike analog circuits, many digital circuits have requirements for timing convergence. However, the inventors have found in actual applications that digital circuits are easily affected by interference factors during the application process and timing changes occur, such as temperature changes, voltage changes, and process angle differences in the circuit. Such timing changes are often difficult to control, which is not conducive to achieving timing convergence of digital circuits. Summary of the invention

[0003] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a power supply circuit, method, chip and electronic device based on a phase-locked loop, so as to solve the problem that the prior art is difficult to achieve timing convergence of digital circuits.

[0004] To achieve the above-mentioned purpose and other related purposes, the first aspect of the present invention provides a power supply circuit based on a phase-locked loop; the power supply circuit based on the phase-locked loop includes: a phase-locked loop circuit, including a voltage-controlled oscillator; the phase-locked loop circuit outputs a control voltage for controlling the voltage-controlled oscillator through its output end; a voltage regulator; its input end is connected to the output end of the phase-locked loop circuit so that the control voltage output by the phase-locked loop circuit forms a power supply voltage after passing through the voltage regulator; wherein the power supply voltage is used to power a load circuit, and the load circuit includes at least one logic gate.

[0005] In an embodiment of the first aspect, the voltage controlled oscillator is a ring oscillator.

[0006] In an embodiment of the first aspect, the ring oscillator includes a ring circuit; the number of inverters in the ring circuit is greater than a threshold.

[0007] In an embodiment of the first aspect, the phase-locked loop-based power supply circuit further includes a low-pass filter; and the output end of the phase-locked loop circuit is connected to the input end of the regulator through the low-pass filter.

[0008] In an embodiment of the first aspect, the phase-locked loop-based power supply circuit further includes a voltage matching circuit; an output end of the phase-locked loop circuit is connected to an input end of the voltage regulator through the voltage matching circuit; the voltage matching circuit is configured to adjust a control voltage output by the phase-locked loop circuit so that the power supply voltage matches the load circuit.

[0009] In an embodiment of the first aspect, the voltage matching circuit includes a bias sub-circuit, a scaling sub-circuit, and / or a limiting sub-circuit.

[0010] A second aspect of the present invention provides a chip; the chip includes the phase-locked loop-based power supply circuit described in the first aspect.

[0011] A third aspect of the present invention provides an electronic device; the electronic device includes the phase-locked loop-based power supply circuit described in the first aspect; a load circuit, electrically connected to an output end of the phase-locked loop-based power supply circuit, and the load circuit includes at least one logic gate.

[0012] In an embodiment of the third aspect, the voltage regulator in the phase-locked loop-based power supply circuit is an on-chip voltage regulator or an off-chip voltage regulator.

[0013] A fourth aspect of the present invention provides a phase-locked loop-based power supply method, applied to a power supply circuit including a phase-locked loop circuit, and the phase-locked loop circuit includes a voltage-controlled oscillator; the phase-locked loop-based power supply method includes: outputting, through an output end of the phase-locked loop circuit, a control voltage for controlling the voltage-controlled oscillator; supplying power to a load circuit by using the control voltage output by the phase-locked loop circuit; wherein the load circuit includes at least one logic gate.

[0014] In an embodiment of the fourth aspect, the voltage-controlled oscillator is a ring oscillator.

[0015] In an embodiment of the fourth aspect, the ring oscillator includes a ring circuit; the number of inverters in the ring circuit is greater than a threshold.

[0016] In an embodiment of the fourth aspect, an implementation method of supplying power to a load circuit by using the control voltage output by the phase-locked loop circuit includes: stabilizing the control voltage output by the phase-locked loop circuit by using a voltage regulator to obtain a power supply voltage; supplying power to the load circuit by using the power supply voltage.

[0017] In an embodiment of the fourth aspect, an implementation method of supplying power to a load circuit by using the control voltage output by the phase-locked loop circuit includes: filtering the control voltage output by the phase-locked loop circuit by using a low-pass filter to obtain a power supply voltage; supplying power to the load circuit by using the power supply voltage.

[0018] In an embodiment of the fourth aspect, an implementation method for supplying power to a load circuit using the control voltage output by the phase-locked loop circuit includes: adjusting the control voltage output by the phase-locked loop circuit using a voltage matching circuit to obtain a power supply voltage matching the load circuit; and supplying power to the load circuit using the power supply voltage.

[0019] In an embodiment of the fourth aspect, the voltage matching circuit includes a bias sub-circuit, a scaling sub-circuit, and / or a limiting sub-circuit.

[0020] As described above, a technical solution of the power supply circuit, method, chip, and electronic device based on a phase-locked loop according to the present invention has the following beneficial effects:

[0021] The power supply circuit based on a phase-locked loop includes a phase-locked loop circuit and a voltage regulator; the phase-locked loop circuit outputs a control voltage for controlling a voltage-controlled oscillator through its output terminal, and this control voltage forms a power supply voltage after passing through the voltage regulator; the power supply voltage can be used to supply power to a load circuit. In the phase-locked loop circuit, since the control voltage of the voltage-controlled oscillator can be adaptively adjusted according to interference factors in the circuit to maintain the frequency stability of the clock signal, therefore, the control voltage of the voltage-controlled oscillator has compensated for the interference factors in the circuit. Further, it can be known that using the power supply voltage formed after this control voltage passes through the voltage regulator to supply power to the load circuit can reduce or even eliminate the influence of interference factors on the timing change of the load circuit, which is beneficial to achieving the timing convergence of digital circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It shows a schematic structural diagram of the power supply circuit based on a phase-locked loop according to the present invention in a specific embodiment.

[0023] Figure 2A It shows a schematic structural diagram of the power supply circuit based on a phase-locked loop according to the present invention in a specific embodiment.

[0024] Figure 2B It shows a schematic structural diagram of the power supply circuit based on a phase-locked loop according to the present invention in a specific embodiment.

[0025] Figure 3A It shows a circuit diagram of a ring oscillator in a specific embodiment of the power supply circuit based on a phase-locked loop according to the present invention.

[0026] Figure 3B It shows a circuit diagram of a ring oscillator in a specific embodiment of the power supply circuit based on a phase-locked loop according to the present invention.

[0027] Figure 4AIt shows a schematic structural diagram of the phase-locked loop-based power supply circuit according to the present invention in a specific embodiment.

[0028] Figure 4B It shows a circuit diagram of the low-pass filter of the phase-locked loop-based power supply circuit according to the present invention in a specific embodiment.

[0029] Figure 5 It shows a schematic structural diagram of the phase-locked loop-based power supply circuit according to the present invention in a specific embodiment.

[0030] Figure 6 It shows a schematic structural diagram of the phase-locked loop-based power supply circuit according to the present invention in a specific embodiment.

[0031] Figure 7 It shows a schematic structural diagram of the phase-locked loop-based power supply circuit according to the present invention in a specific embodiment.

[0032] Figure 8 It shows a schematic structural diagram of the chip according to the present invention in a specific embodiment.

[0033] Figure 9 It shows a flowchart of the phase-locked loop-based power supply method according to the present invention in a specific embodiment.

[0034] Figure 10 It shows a flowchart of step S12 of the phase-locked loop-based power supply method according to the present invention in a specific embodiment.

[0035] Figure 11 It shows another flowchart of step S12 of the phase-locked loop-based power supply method according to the present invention in a specific embodiment.

[0036] Figure 12 It shows yet another flowchart of step S12 of the phase-locked loop-based power supply method according to the present invention in a specific embodiment.

[0037] Figure 13 It shows a flowchart of the phase-locked loop-based power supply method according to the present invention in a specific embodiment.

[0038] Description of component labels

[0039] 1 Phase-locked loop-based power supply circuit

[0040] 11 Phase-locked loop circuit

[0041] 111 Phase detector

[0042] 112 Loop filter

[0043] 113 Voltage-controlled oscillator

[0044] 114 Charge pump

[0045] 115-frequency divider

[0046] 12-voltage regulator

[0047] 13-low-pass filter

[0048] 14-voltage matching circuit

[0049] 2-load circuit

[0050] Steps S11 to S12

[0051] Steps S121a to S122a

[0052] Steps S121b to S122b

[0053] Steps S121c to S122c

[0054] Steps S21 to S25 Specific implementation manners

[0055] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0056] It should be noted that the drawings provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the drawings, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex. In addition, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0057] Digital circuits often contain many logic gates; the component devices of these logic gates, such as CMOS (Complementary Metal Oxide Semiconductor), are susceptible to interference factors and exhibit varying degrees of delay. This delay can cause changes in the timing of digital circuits; for example, circuits that should be synchronous in theory may become asynchronous due to this delay. Among them, the interference factors are, for example, temperature changes, voltage changes, and / or process corner differences of the devices in the circuit. For digital circuits, such timing changes are often caused by multiple logic gates and can occur at any time, so it is often very difficult to control this timing change, and the existence of this timing change poses a great challenge to the timing convergence of digital circuits. Among them, the timing convergence refers to the process of adjusting or modifying the circuit to make the circuit meet the timing requirements.

[0058] To address this problem, the present invention provides a power supply circuit based on a phase-locked loop. The power supply circuit based on a phase-locked loop includes a phase-locked loop circuit and a voltage regulator; the phase-locked loop circuit outputs a control voltage for controlling a voltage-controlled oscillator through its output terminal, and this control voltage forms a power supply voltage after passing through the voltage regulator; the power supply voltage can be used to supply power to a load circuit. In the phase-locked loop circuit, since the control voltage of the voltage-controlled oscillator can be adaptively adjusted according to the interference factors in the circuit to maintain the frequency stability of the clock signal, therefore, the control voltage of the voltage-controlled oscillator has compensated for the interference factors in the circuit. Furthermore, it can be known that using the power supply voltage formed after the control voltage passes through the voltage regulator to supply power to the load circuit can reduce or even eliminate the influence of interference factors on the timing change of the load circuit, which is beneficial to achieving the timing convergence of digital circuits.

[0059] Please refer to Figure 1 , in an embodiment of the present invention, the power supply circuit 1 based on a phase-locked loop includes a phase-locked loop circuit 11 and a voltage regulator 12.

[0060] The phase-locked loop circuit 11 includes a voltage-controlled oscillator (VCO) 113, and the phase-locked loop circuit 11 outputs a control voltage for controlling the voltage-controlled oscillator 113 through its output terminal. Among them, the voltage-controlled oscillator 113 refers to an oscillation circuit whose output frequency has a corresponding relationship with the input control voltage.

[0061] The phase-locked loop circuit 11 is a negative feedback control system that uses the voltage generated by phase synchronization to tune the voltage-controlled oscillator to generate a target frequency, and can achieve automatic tracking of the output signal frequency to the input signal frequency. In this embodiment, the phase-locked loop circuit 11 is used to generate a control voltage that can be automatically adjusted according to interference factors.

[0062] Specifically, the phase-locked loop circuit 11 includes one or more logic gate circuits. The logic gate circuits are affected by interference factors and generate delays, which will cause the output frequency of the phase-locked loop circuit 11 to change. Based on the negative feedback mechanism of the phase-locked loop circuit 11, the phase-locked loop circuit 11 adjusts the control voltage of the voltage-controlled oscillator to ensure that the output frequency of the phase-locked loop circuit 11 remains stable. Therefore, the control voltage of the voltage-controlled oscillator can compensate for the influence generated by the interference factors.

[0063] The input end of the voltage regulator 12 is connected to the output end of the phase-locked loop circuit 11, so that the control voltage output by the phase-locked loop circuit 11 forms a power supply voltage after passing through the voltage regulator 12. Among them, the voltage regulator 12 is used to stabilize the control voltage of the voltage-controlled oscillator, and then obtain a stable power supply voltage; the output end of the phase-locked loop circuit 11 can be directly connected to the input end of the voltage regulator 12, or indirectly connected to the voltage regulator 12 via other circuits. The power supply voltage is used to supply power to the load circuit 2, and the load circuit 2 includes at least one logic gate. The voltage regulator 12 can be an on-chip voltage regulator or an off-chip voltage regulator, where: the on-chip voltage regulator refers to a voltage regulator located on the chip, which is suitable for relatively small chips and is beneficial to improving the volume of the chip; the off-chip voltage regulator refers to a voltage regulator outside the chip, which is suitable for relatively large integrated circuits.

[0064] In a specific application, the load circuit 2 has the same or similar interference factors as the phase-locked loop circuit 11. For example, for the load circuit 2 and the phase-locked loop circuit 11 on the same chip, the logic gate devices included in both often have the same or similar temperature, voltage, and process corner; therefore, the influence of the interference factors on the logic gates in the load circuit 2 is the same or similar to the influence of the interference factors on the logic gates in the phase-locked loop circuit 11. It can be seen that the control voltage of the voltage-controlled oscillator that has been compensated for the interference factors can also compensate for the influence of the interference factors on the load circuit 2 after forming the power supply voltage through the voltage regulator 12.

[0065] As can be seen from the above description, in the PLL-based power supply circuit 1 described in this embodiment, the phase-locked loop circuit 11 outputs a control voltage for controlling the voltage-controlled oscillator through its output terminal, and this control voltage forms a power supply voltage after passing through the voltage regulator 12; the power supply voltage can be used to supply power to the load circuit 2. In the phase-locked loop circuit 11, since the control voltage of the voltage-controlled oscillator can be adaptively adjusted according to the interference factors in the circuit to maintain the frequency stability of the clock signal, therefore, the control voltage of the voltage-controlled oscillator has compensated for the interference factors in the circuit. Further, it can be known that using the power supply voltage formed after the control voltage passes through the voltage regulator to supply power to the load circuit can reduce or even eliminate the influence of interference factors on the timing change of the load circuit, which is beneficial to achieving the timing convergence of digital circuits.

[0066] In addition, in some embodiments, in order to ensure the timing convergence of digital circuits, the power supply voltage of digital circuits is often increased to ensure that the timing of the digital circuit can still be satisfied under the worst operating conditions, that is: in these embodiments, the digital circuit is overdesigned to ensure the timing convergence of the digital circuit. However, digital circuits are not in the worst operating conditions in most cases, so it is unnecessary to provide an excessive power supply voltage to the digital circuit in many cases, which will lead to an increase in energy consumption. Compared with these embodiments, in this embodiment, the power supply voltage formed by stabilizing the control voltage of the voltage-controlled oscillator is used to supply power to the load circuit, and this power supply voltage can change with the change of interference factors in the circuit, so there is no need to always use a large power supply voltage for power supply, which is beneficial to reducing the energy consumption of digital circuits.

[0067] Please refer to Figure 2A , in an embodiment of the present invention, the phase-locked loop circuit 11 includes a phase detector 111, a loop filter 112, and a voltage-controlled oscillator 113. The phase detector 111 is used to detect the phase difference between the reference clock signal and the feedback signal, and generate a pulse width modulation signal proportional to this phase difference. The loop filter 112 has a low-pass characteristic and is used to filter out the high-frequency components of the pulse modulation signal to extract its DC component, and the control voltage of the voltage-controlled oscillator 113 can be obtained according to this DC component. Under the action of the feedback signal and the reference clock, the voltage-controlled oscillator 113 continuously tunes the oscillation frequency of the clock signal and finally maintains dynamic stability. In this embodiment, the signal output by the voltage-controlled oscillator 113 has the same frequency as the reference clock.

[0068] For the phase-locked loop circuit 11 in a stable state, if the logic gates in the phase-locked loop circuit 11 generate a timing change under the action of the interference factor at a certain moment. For example, the interference factor causes an increase in the delay of the logic gates in the phase-locked loop circuit 11. At this time, the frequency of the signal output by the voltage-controlled oscillator 113 will decrease, resulting in a phase difference between this signal and the reference clock. When this signal is input as a feedback signal to the phase detector 111, the phase detector 111 outputs a pulse-width modulation signal proportional to this phase difference. Under the action of this pulse-width modulation signal, the control voltage of the voltage-controlled oscillator 113 gradually increases, and finally makes the frequency of the signal output by the voltage-controlled oscillator 113 the same as that of the reference clock, and the phase-locked loop circuit 11 reaches a stable state again. It can be seen that the control voltage of the voltage-controlled oscillator 113 can automatically compensate for the influence of the interference factor on the timing of the phase-locked loop circuit 11.

[0069] Please refer to Figure 2B , in an embodiment of the present invention, the phase-locked loop circuit 11 includes a phase detector 111, a charge pump 114, a loop filter 112, a voltage-controlled oscillator 113, and a frequency divider 115. Among them, the phase detector 111 is used to detect the phase difference between the reference clock signal and the feedback signal, and generate a pulse-width modulation signal proportional to this phase difference. The charge pump 114 is used to convert the pulse-width modulation signal into a voltage signal, and this voltage signal generates the control voltage of the voltage-controlled oscillator 113 after passing through the loop filter 112. The voltage-controlled oscillator 113 outputs a clock signal under the control of this control voltage, and this clock signal forms the feedback signal after passing through the frequency divider 115. Under the action of the feedback signal and the reference clock, the voltage-controlled oscillator 113 continuously tunes the oscillation frequency of the clock signal and finally maintains dynamic stability. In this embodiment, the frequency of the clock signal output by the voltage-controlled oscillator 113 is an integer multiple of the reference clock frequency. And, in this embodiment, the control voltage of the voltage-controlled oscillator 113 can automatically compensate for the influence of the interference factor on the timing of the phase-locked loop circuit 11. The specific compensation process is similar to that of the phase-locked loop circuit 11 shown in Figure 2A and will not be elaborated here.

[0070] In an embodiment of the present invention, the voltage-controlled oscillator 113 is a ring oscillator. Please refer to Figure 3A and Figure 3B , the ring oscillator includes a ring circuit, and the ring circuit is composed of an odd number of NOT gates connected end to end; among them, the number of NOT gates included in the ring circuit is called the stage number of the ring oscillator; the NOT gates in the ring circuit are, for example, CMOS inverters. In this embodiment, Figure 3A shows an example of directly powering the ring circuit in the ring oscillator with a voltage, Figure 3BAn example is shown where current is converted to voltage to indirectly power the ring circuit in the ring oscillator. Whether it is direct power supply or indirect power supply, the control voltage of the voltage-controlled oscillator can compensate for the influence of the interference factor on the phase-locked loop circuit 11.

[0071] In this embodiment, a ring oscillator is used as the voltage-controlled oscillator 113, which can simplify the structure of the phase-locked loop circuit, broaden the tuning range of the voltage-controlled oscillator, and improve the compatibility between the voltage-controlled oscillator and digital processing.

[0072] In particular, when the ring circuit in the ring oscillator is formed by CMOS inverters, since the CMOS inverter is a type of logic gate and its delay reflects the current voltage, temperature, and process corner; and since the logic gates in the load circuit 2 have the same or similar voltage, temperature, and process corner as the CMOS inverter, therefore, the logic gates in the load circuit 2 have the same or similar delay as the CMOS inverter. When the phase-locked loop circuit 11 forces the period of the ring oscillator to be the same as the period of the target clock by adjusting the control voltage of the ring oscillator, if this control voltage is supplied to other logic gates in the load circuit, the delay of the other logic gates is proportional to the period of the target clock. Therefore, in this embodiment, as long as each stage in the ring oscillator is a CMOS inverter or a device similar to a CMOS logic gate, the delay of the logic gates in the load circuit can track the period of the ring oscillator.

[0073] In addition, the number of stages of the ring oscillator in this embodiment will affect the waveform of its control voltage. Specifically, the fewer the number of stages of the ring oscillator, the closer the waveform of its control voltage is to a ramp wave, such as a sine wave, a triangular wave, etc.; the more the number of stages of the ring oscillator, the more approximate the waveform of its control voltage is to a square wave. For the power supply circuit based on the phase-locked loop, the more the number of stages of the ring oscillator, the stronger its compensation ability for interference factors, and thus it is easier to achieve the timing convergence of the digital circuit. Among them, the compensation ability can be described by the ratio of the maximum delay to the minimum delay of the load circuit; the maximum delay corresponds to a relatively poor operating state of the load circuit, for example, a high-temperature or low-temperature operating state; the minimum delay corresponds to a relatively good operating state of the load circuit, for example, a normal-temperature operating state. In this embodiment, the difference in the compensation ability corresponding to ring oscillators with different numbers of stages is about 1-2%.

[0074] Preferably, the number of inverters in the ring circuit in this embodiment is greater than a threshold value, which can be determined according to actual requirements: when the load circuit has a high requirement for timing convergence, a larger threshold value can be selected, such as 11, 13, etc.; when the load circuit has a low requirement for timing convergence, a smaller threshold value can be selected, such as 3, 5, etc.

[0075] It should be noted that the ring oscillator can be of any number of stages; preferably, the number of stages of the ring oscillator is half or slightly more than half of the timing critical path. Specifically, the period of the ring oscillator includes the rising edge delay and the falling edge delay. Therefore, each stage of the ring oscillator corresponds to two delays (the rising edge delay and the falling edge delay); based on this, it can be known that when the number of stages of the ring oscillator is half or slightly more than half of the timing critical path, the delay of the ring oscillator is basically the same as the delay of the timing critical path, and thus the best match can be provided. Among them, the timing critical path (or called the critical path) refers to the longest path in the timing path. For example, in a digital circuit, there are multiple logical paths from the output end of a device to the input end of another device, and the longest logical path among them is the timing critical path between the above two devices. When optimizing the logical delay of a digital circuit, if all the critical paths in the digital circuit meet the timing requirements, the entire digital circuit achieves timing convergence. Please refer to Figure 4A In an embodiment of the present invention, considering that there may be ripples in the control voltage of the voltage-controlled oscillator, the power supply circuit 1 based on the phase-locked loop in this embodiment further includes a low-pass filter 13. Among them, the output end of the phase-locked loop circuit 11 is connected to the input end 12 of the voltage regulator through the low-pass filter 13, and is used to filter out the high-frequency noise in the control voltage of the voltage-controlled oscillator. Figure 4B Shown is a first-order passive RC low-pass filter that can be used in the present invention, but the low-pass filter applicable to the present invention is not limited to this, and the low-pass filter can be a filter of any order, active or passive.

[0076] In this embodiment, the power supply circuit based on the phase-locked loop includes a low-pass filter, and the low-pass filter can filter out the high-frequency noise in the control voltage of the voltage-controlled oscillator, so that the power supply circuit based on the phase-locked loop can better supply power to the load circuit and will not introduce additional high-frequency noise.

[0077] In a specific application, if the operating frequency of a circuit is low, it will cause the supply voltage to be too low, which in turn will affect the timing convergence of the circuit. For example, if the normal operating frequency of a certain chip is 1 GHz and the supply voltage is 1 V, at this time, the digital circuit can achieve timing convergence at 1 V and 1 GHz; however, in some cases, the operating frequency is reduced to 100 MHz and the supply voltage is reduced to 0.4 V. In this example, although it is completely possible to reduce both the supply voltage and the timing requirements simultaneously in an actual circuit, however, the supply voltage of 0.4 V is relatively rare in an actual circuit and may cause the circuit to malfunction. To address this issue, please refer to Figure 5 In an embodiment of the present invention, the phase-locked loop-based power supply circuit 1 further includes a voltage matching circuit 14; the output end of the phase-locked loop circuit 11 is connected to the input end 12 of the voltage regulator through the voltage matching circuit 14. Specifically, the voltage matching circuit 14 may be a biasing sub-circuit, a scaling sub-circuit, and / or a limiting sub-circuit. Among them, the biasing sub-circuit is a positive biasing adder for increasing the control voltage of the voltage-controlled oscillator; the scaling sub-circuit is used to amplify the control voltage of the voltage-controlled oscillator; the limiting sub-circuit is used to limit the control voltage of the voltage-controlled oscillator to be greater than a certain set value. The biasing sub-circuit, the scaling sub-circuit, and the limiting sub-circuit will reduce the compensation effect of the control voltage of the voltage-controlled oscillator on interference factors, but can ensure that the circuit achieves timing convergence to the greatest extent possible. In a specific application, the voltage matching circuit can be designed according to the actual requirements of the circuit to minimize the adverse impact of the voltage matching circuit on the compensation effect while meeting the timing convergence of the circuit.

[0078] According to the above description, in this embodiment, by configuring the voltage matching circuit in the phase-locked loop-based power supply circuit, by sacrificing a small part of the compensation effect of the control voltage of the voltage-controlled oscillator on interference factors, it is possible to ensure that the circuit achieves timing convergence to the greatest extent possible.

[0079] It should be noted that the voltage matching circuit in this embodiment may be any one or a combination of the biasing sub-circuit, the scaling sub-circuit, and / or the limiting sub-circuit. Through the voltage matching circuit, some additional timing margins can be provided for the digital circuit to ensure the matching between the phase-locked loop-based power supply circuit and the load circuit.

[0080] In an embodiment of the present invention, each stage in the voltage-controlled oscillator has a time delay similar to that of the logic gate of the load circuit. During the operation of the digital circuit, the voltage-controlled oscillator operates at the highest frequency and provides the main clock for the digital circuit. In addition, the voltage regulator in this embodiment can be compensated and calibrated. Specifically, the offset of the voltage regulator can be calibrated after each power-on or can be calibrated once before leaving the factory. For the latter case, the calibration code of the voltage regulator can be stored in the non-volatile memory for reading and used for calibration after power-on.

[0081] Please refer to Figure 6 , in an embodiment of the present invention, the phase-locked loop-based power supply circuit 1 includes: a phase-locked loop circuit 11, a low-pass filter 13, a voltage matching circuit 14, and a voltage regulator 12. Among them, the phase-locked loop circuit 11 includes a phase detector 111, a charge pump 114, a loop filter 112, a voltage-controlled oscillator 113, and a frequency divider 115.

[0082] In the phase-locked loop circuit 11, the inputs of the phase detector 111 are respectively a reference clock signal and a feedback signal output by the frequency divider 115. The phase detector 111 is used to detect the phase difference between the reference clock signal and the feedback signal and generate a pulse width modulation signal proportional to the phase difference. The output end of the phase detector 111 is connected to the input end of the charge pump 114, and the charge pump 114 is used to convert the pulse width modulation signal into a voltage signal. The output end of the charge pump 114 is connected to the input end of the loop filter 112, and the loop filter 112 is used to filter the voltage signal output by the charge pump 114 and generate the control voltage of the loop filter 112. The output end of the loop filter 112 corresponds to the output end of the phase-locked loop circuit 11 and also corresponds to the control end of the voltage-controlled oscillator 113. The output end of the voltage-controlled oscillator 113 is connected to the input end of the frequency divider 115, and the voltage-controlled oscillator 113 is used to generate a clock signal with a specific frequency according to the control voltage of the voltage-controlled oscillator. The frequency divider 115 is used to divide the clock signal to obtain the feedback signal.

[0083] The phase-locked loop circuit 11 outputs the control voltage of the voltage-controlled oscillator 113 through its output end. This control voltage is subjected to low-pass filtering by the low-pass filter 13 and adjusted by the voltage matching circuit 14 and then reaches the input end of the voltage regulator 12. The voltage regulator 12 stabilizes this control voltage to form a supply voltage, and the supply voltage can be used to supply power to the load circuit 2; among them, the load circuit 2 includes at least one logic gate.

[0084] Preferably, the voltage-controlled oscillator 113 is a ring oscillator, and the ring oscillator includes a ring circuit composed of a plurality of NOT gates. Further preferably, the ring circuit is composed of an odd number of CMOS inverters connected end to end in sequence.

[0085] Please refer to Figure 7 , in another embodiment of the present invention, the phase-locked loop-based power supply circuit 1 includes: a phase-locked loop circuit 11, a low-pass filter 13, and a voltage regulator 12. Among them, the phase-locked loop circuit 11 includes a phase detector 111, a charge pump 114, a loop filter 112, a voltage-controlled oscillator 113, and a frequency divider 115. This phase-locked loop circuit 11 is similar in structure and function to Figure 6 the phase-locked loop circuit shown, and will not be elaborated here too much.

[0086] Based on the above description of the phase-locked loop-based power supply circuit, the present invention also provides a chip. Please refer to Figure 8 , the chip includes at least some of the devices in the phase-locked loop-based power supply circuit of the present invention. For example, the chip may include the entire phase-locked loop-based power supply circuit, or may only include the phase-locked loop circuit in the phase-locked loop-based power supply circuit. The chip can be represented as a salable active device formed by packaging the phase-locked loop-based power supply circuit manufactured on a wafer using semiconductor technology; or represented as a salable active device formed by packaging the phase-locked loop-based power supply circuit using PCB packaging technology.

[0087] Based on the above description of the phase-locked loop-based power supply circuit, the present invention also provides an electronic device. The electronic device includes the phase-locked loop-based power supply circuit of the present invention and includes a load circuit. Among them, the load circuit includes at least one logic gate, and the load circuit is electrically connected to the output terminal of the phase-locked loop-based power supply circuit. The phase-locked loop-based power supply circuit supplies power to the load circuit using the supply voltage at its output terminal.

[0088] In an embodiment of the present invention, the voltage regulator is an on-chip voltage regulator or an off-chip voltage regulator. Among them, the on-chip voltage regulator refers to a voltage regulator located on the chip, which is suitable for relatively small chips and is beneficial to improving the volume of the chip; the off-chip voltage regulator refers to a voltage regulator outside the chip, which is suitable for relatively large integrated circuits.

[0089] Based on the above description of the phase-locked loop-based power supply circuit, the present invention also provides a phase-locked loop-based power supply method. In an embodiment of the present invention, the flowchart of the phase-locked loop-based power supply method is as shown in Figure 9 , this method can be applied to a power supply circuit including a phase-locked loop circuit. For example, this method can be performed by Figure 1 , 2A, implemented by the phase-locked loop-based power supply circuit shown in 2B, 4A, 5, 6, or 7. Specifically, the phase-locked loop-based power supply method includes:

[0090] S11, output a control voltage for controlling the voltage-controlled oscillator through the output terminal of the phase-locked loop circuit.

[0091] S12, supply power to the load circuit using the control voltage output by the phase-locked loop circuit; wherein, the load circuit includes at least one logic gate. This method uses the control voltage output by the phase-locked loop circuit to supply power to the load circuit, which can reduce or even eliminate the influence of interference factors on the timing change of the load circuit, and is beneficial to achieving the timing convergence of digital circuits.

[0092] In an embodiment of the present invention, the phase-locked loop circuit includes a phase detector, a loop filter, and a voltage-controlled oscillator.

[0093] In an embodiment of the present invention, the phase-locked loop circuit includes a phase detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a frequency divider.

[0094] In an embodiment of the present invention, the voltage-controlled oscillator is a ring oscillator. The ring oscillator includes a ring circuit formed by connecting an odd number of NOT gates end to end.

[0095] Preferably, the number of inverters in the ring circuit of this embodiment is greater than a threshold. This threshold can be determined according to actual needs: when the load circuit has high requirements for timing, a larger threshold can be selected, such as 11, 13, etc.; when the load circuit has low requirements for timing, a smaller threshold can be selected, such as 3, 5, etc.

[0096] Please refer to Figure 10 , in an embodiment of the present invention, using the control voltage output by the phase-locked loop circuit to supply power to the load circuit includes:

[0097] S121a, regulate the control voltage output by the phase-locked loop circuit using a voltage regulator to obtain a supply voltage.

[0098] S122a, supply power to the load circuit using the supply voltage.

[0099] Please refer to Figure 11 , in an embodiment of the present invention, considering that there may be ripples in the control voltage of the voltage-controlled oscillator, in this embodiment, using the control voltage output by the phase-locked loop circuit to supply power to the load circuit includes:

[0100] S121b, filter the control voltage output by the phase-locked loop circuit using a low-pass filter to obtain the supply voltage. In this step, the high-frequency noise in the control voltage of the voltage-controlled oscillator can be filtered out by using the low-pass filter.

[0101] S122b, supply the load circuit with the supply voltage.

[0102] In an embodiment of the present invention, considering that in specific applications, there may be a mismatch between the requirements of the load circuit 2 for the supply voltage and the supply voltage provided by the voltage regulator 12. For example, the load circuit 2 requires a voltage of 9V, while the voltage regulator 12 can only provide a voltage of 0.9V. This mismatch will make it difficult for the phase-locked loop-based power supply circuit 1 to supply power to the load circuit 2. To address this issue, please refer to Figure 12 , in this embodiment, an implementation method for supplying power to the load circuit using the control voltage output by the phase-locked loop circuit includes:

[0103] S121c, adjust the control voltage output by the phase-locked loop circuit using a voltage matching circuit to obtain a supply voltage that matches the load circuit. The voltage matching circuit includes a biasing sub-circuit, a scaling sub-circuit, and / or a limiting sub-circuit. Among them, the biasing sub-circuit includes a positive biasing sub-circuit and a negative biasing sub-circuit.

[0104] S122c, supply the load circuit with the supply voltage.

[0105] In this embodiment, the voltage matching circuit can provide some additional timing margins for the digital circuit to ensure the matching between the phase-locked loop-based power supply circuit and the load circuit. Figure 13 The flowchart of the phase-locked loop-based power supply method of the present invention in another specific embodiment is shown. This method can be applied to a power supply circuit including a phase-locked loop circuit. For example, this method can be executed by Figure 5 , 6 or the phase-locked loop-based power supply circuit shown in 7. Specifically, the phase-locked loop-based power supply method includes:

[0106] S21, output the control voltage for controlling the voltage-controlled oscillator through the output terminal of the phase-locked loop circuit. Preferably, the voltage-controlled oscillator is a ring oscillator, and the ring oscillator includes a plurality of CMOS inverters.

[0107] S22, filter the control voltage output by the phase-locked loop circuit using a low-pass filter to reduce the ripple in the control voltage output by the phase-locked loop circuit.

[0108] S23. Adjust the control voltage output by the phase-locked loop circuit by using a voltage matching circuit so that the control voltage of the voltage-controlled oscillator matches the requirements of the load circuit. The voltage matching circuit includes a bias sub-circuit, a scaling sub-circuit, and / or a limiting sub-circuit.

[0109] S24. Stabilize the control voltage output by the phase-locked loop circuit by using a voltage regulator to obtain a supply voltage. The supply voltage can be used to supply power to the load circuit.

[0110] S25. Supply power to the load circuit by using the supply voltage.

[0111] The protection scope of the power supply method based on a phase-locked loop according to the present invention is not limited to the execution order of the steps listed in this embodiment. Any solution achieved by adding or deleting steps of the prior art and replacing steps according to the principle of the present invention is included in the protection scope of the present invention.

[0112] The present invention further provides a power supply circuit based on a phase-locked loop. The power supply circuit based on a phase-locked loop can implement the power supply method based on a phase-locked loop according to the present invention. However, the implementation device of the power supply method based on a phase-locked loop according to the present invention includes but is not limited to the structure of the power supply circuit based on a phase-locked loop listed in this embodiment. Any structural deformation and replacement of the prior art made according to the principle of the present invention are included in the protection scope of the present invention.

[0113] The integrated circuit industry has optimized the timing of digital circuits. One challenge in digital circuit design is timing convergence under all operating conditions. In some embodiments, to cover the worst-case scenario, these embodiments tend to increase the supply voltage of the digital circuit, which results in an increase in the power consumption of the digital circuit. The phase-locked loop-based power supply circuit described in the present invention utilizes a phase-locked loop circuit to output a control voltage for controlling the voltage-controlled oscillator, and obtains a supply voltage based on this control voltage to supply power to the load circuit. At the same time, with the continuous improvement of integration, the phase-locked loop has become a basic component of large-scale integrated circuits. In specific applications, it is a common practice in the art to generate the clock with the highest frequency across the chip through the phase-locked loop and provide this clock to the digital circuit. Therefore, the present invention combines the phase-locked loop with the power supply circuit, enabling the phase-locked loop-based power supply circuit to reduce the impact of interference factors such as temperature changes, voltage changes, and process corner differences on the timing of the digital circuit, and being beneficial to reducing the power consumption of the digital circuit. In addition, the phase-locked loop-based power supply circuit described in this embodiment further includes a voltage regulator, which can fill the gap between the power supply required by the load circuit and the logic gates it contains and the control voltage of the voltage-controlled oscillator. It can be seen that the phase-locked loop-based power supply circuit described in the present invention can reduce the timing variation in the digital circuit and lower the power consumption without increasing the chip size. The phase-locked loop-based power supply circuit is an open-loop circuit, which can avoid glitches caused by the adjustment timing and adjustment.

[0114] In summary, the present invention effectively overcomes various drawbacks in the prior art and has high industrial utilization value.

[0115] The above embodiments are only illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A power supply circuit based on a phase-locked loop, characterized in that, The PLL-based power supply circuit includes: A phase-locked loop (PLL) circuit, including a loop filter and a voltage-controlled oscillator (VCO). The loop filter generates a control voltage for controlling the VCO and outputs the control voltage to the VCO and the output terminal of the PLL circuit; A voltage regulator, whose input terminal is connected to the output terminal of the PLL circuit, so that the control voltage output by the PLL circuit forms a power supply voltage after passing through the voltage regulator; Wherein, the power supply voltage is used to supply power to a load circuit, and the load circuit includes at least one logic gate.

2. The power supply circuit based on a phase-locked loop according to claim 1, characterized in that: The VCO is a ring oscillator.

3. The power supply circuit based on a phase-locked loop according to claim 2, wherein: The ring oscillator includes a ring circuit, and the number of inverters in the ring circuit is greater than a threshold.

4. The power supply circuit based on a phase-locked loop according to claim 1, wherein: The PLL-based power supply circuit further includes a low-pass filter; the output terminal of the PLL circuit is connected to the input terminal of the voltage regulator through the low-pass filter.

5. The PLL-based power supply circuit according to claim 1, wherein: The PLL-based power supply circuit further includes a voltage matching circuit; The output terminal of the PLL circuit is connected to the input terminal of the voltage regulator through the voltage matching circuit; The voltage matching circuit is used to adjust the control voltage output by the PLL circuit so that the power supply voltage matches the load circuit.

6. The power supply circuit based on a phase-locked loop according to claim 5, wherein: The voltage matching circuit includes a bias sub-circuit, a scaling sub-circuit, and / or a limiting sub-circuit.

7. A chip, characterized in that: The chip includes the PLL-based power supply circuit according to any one of claims 1 to 6.

8. An electronic device, characterized in that, The electronic device includes: The PLL-based power supply circuit according to any one of claims 1 to 6; A load circuit, electrically connected to the output terminal of the PLL-based power supply circuit, and the load circuit includes at least one logic gate.

9. The electronic device according to claim 8, wherein: The voltage regulator in the PLL-based power supply circuit is an on-chip voltage regulator or an off-chip voltage regulator.

10. A power supply method based on a phase-locked loop, characterized in that, Applied to a power supply circuit including a PLL circuit, and the PLL circuit includes a loop filter and a VCO. The PLL-based power supply method includes: Generating a control voltage for controlling the VCO through the loop filter and outputting the control voltage to the VCO and the output terminal of the PLL circuit; Using the control voltage output by the PLL circuit to supply power to a load circuit, wherein the load circuit includes at least one logic gate.

11. The power supply method based on a phase-locked loop according to claim 10, characterized in that: The VCO is a ring oscillator.

12. The power supply method based on a phase-locked loop according to claim 11, wherein: The ring oscillator includes a ring circuit, and the number of inverters in the ring circuit is greater than a threshold.

13. The power supply method based on a phase-locked loop according to claim 10, wherein Using the control voltage output by the PLL circuit to supply power to a load circuit includes: Using a voltage regulator to regulate the control voltage output by the PLL circuit to obtain a power supply voltage; Using the power supply voltage to supply power to the load circuit.

14. The power supply method based on a phase-locked loop according to claim 10, wherein Using the control voltage output by the PLL circuit to supply power to a load circuit includes: Using a low-pass filter to filter the control voltage output by the PLL circuit to obtain a power supply voltage; Using the power supply voltage to supply power to the load circuit.

15. The power supply method based on a phase-locked loop according to claim 10, wherein Using the control voltage output by the PLL circuit to supply power to a load circuit includes: A voltage matching circuit is used to adjust the control voltage output by the phase-locked loop circuit to obtain a power supply voltage matching the load circuit; The load circuit is powered by using the power supply voltage.

16. The power supply method based on a phase-locked loop according to claim 15, characterized in that: The voltage matching circuit includes a bias sub-circuit, a scaling sub-circuit, and / or a limiting sub-circuit.

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