Integrated inductor-capacitor oscillator and method thereof

Abstract

An integrated oscillator includes: a first inductor arranged in a first loop and a second inductor arranged in a second loop; a first capacitor arranged between two ends of the first loop; a second capacitor arranged between two ends of the second loop; a third inductor, a fourth inductor, a third capacitor and a fourth capacitor, all arranged in the first loop; and a cross-coupled transistor pair, used to electrically couple two ends of the first loop and two ends of the second loop. With respect to a symmetry plane, the overall structure of the integrated oscillator is substantially symmetrical.

Description

Technical Field

[0001] The present disclosure relates generally to an inductor-capacitor (LC) oscillator, and more particularly to an LC oscillator with reduced phase noise. Background Art

[0002] like Figure 1 As shown, an inductor capacitor (LC) oscillator 100 includes a first LC cavity 110, an interleaved coupling pair 120 and a second LC cavity 130. The first LC cavity 110 includes an inductor 111 and a capacitor 112, which are used to resonate at a resonant frequency. The interleaved coupling pair 120 includes two NMOS (N-channel metal oxide semiconductor) transistors 121 and 122, and is configured in an interleaved coupling form. The second LC cavity 130 includes an inductor 131 and a capacitor 132, which are used to resonate at twice the resonant frequency of the first LC cavity 100. A center tap of the first inductor 111 is connected to a power supply node "VDD". The first LC cavity 110 determines an oscillation frequency, which is approximately equal to the resonant frequency. The interleaved coupling pair 120 provides a regeneration function to compensate for an ohmic loss of the first LC cavity 110 and maintain the oscillation. The second LC cavity 130 is used to provide a source degeneration of the interleaved coupling pair 120 to suppress a phase noise of the LC oscillator 100 caused by an up-conversion of a flicker noise of the interleaved coupling pair 120. The LC oscillator 100 is well known in the art and will not be described in detail herein.

[0003] One solution that has attracted attention is that the LC oscillator 100 is integrated on a silicon substrate through a complementary metal oxide semiconductor (CMOS) process. This requires that the LC oscillator 100 be compact in layout and have a low phase noise; it also requires that the magnetic coupling between the LC oscillator 100 and other circuits that coexist on the silicon substrate can be reduced.

[0004] What is needed in the art is an integrated LC oscillator that is compact in layout and has a low phase noise while mitigating magnetic coupling with other circuits that coexist on the same silicon substrate. Summary of the invention

[0005] In one embodiment of the present disclosure, an integrated oscillator includes: a first inductor, which is arranged into a first loop from a first end to a second end, and the first loop is substantially symmetrical with respect to a symmetry plane; a second inductor, which is arranged into a second loop from a third end to a fourth end, the third end is connected to the first end, and the fourth end is connected to the second end, and the second loop is substantially symmetrical with respect to the symmetry plane; a third inductor, which is arranged into a counterclockwise spiral shape, the third inductor of the counterclockwise spiral shape is located in the first loop and is located on one side of the symmetry plane; a fourth inductor, which is arranged into a clockwise spiral shape, the fourth inductor of the clockwise spiral shape is arranged in a clockwise spiral shape, an inductor located in the first loop, the fourth inductor being a mirror image of the third inductor with respect to the symmetry plane; a grounding strip arranged along the symmetry plane to provide a common termination point for the third inductor and the fourth inductor; a first capacitor arranged between the first end and the second end; a second capacitor arranged between the third end and the fourth end; a third capacitor arranged between the third inductor and the grounding strip; a fourth capacitor arranged between the fourth inductor and the grounding strip, the fourth capacitor being a mirror image of the third capacitor with respect to the symmetry plane; and an interlaced coupling transistor pair for electrically interlacingly coupling the first end and the second end.

[0006] In one embodiment of the present disclosure, a method for integrating an oscillator includes: with respect to a symmetry plane, arranging a first inductor in a substantially symmetrical manner to form a first loop from a first end to a second end; with respect to the symmetry plane, arranging a second inductor in a substantially symmetrical manner to form a second loop from a third end to a fourth end, the third end being connected to the first end, and the fourth end being connected to the second end; arranging a third inductor in a counterclockwise spiral shape, the counterclockwise spiral third inductor being located in the first loop and on one side of the symmetry plane; arranging a fourth inductor in a clockwise spiral shape; The fourth inductor of the clockwise spiral shape is located in the first loop, and with respect to the symmetry plane, the fourth inductor is a mirror image of the third inductor; a grounding strip is arranged along the symmetry plane to provide a common termination point for the third inductor and the fourth inductor; a first capacitor is arranged between the first end and the second end; a second capacitor is arranged between the third end and the fourth end; a third capacitor is arranged between the third inductor and the grounding strip; a fourth capacitor is arranged between the fourth inductor and the grounding strip; and an interlaced coupling transistor pair is arranged to electrically interlace the first end and the second end.

[0007] The features, implementation and technical effects of the present invention are described in detail below with reference to the accompanying drawings as preferred embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A schematic diagram showing an LC oscillator;

[0009] Figure 2A A schematic diagram showing an integrated LC oscillator according to an embodiment of the present disclosure;

[0010] Figure 2B show Figure 2A A top view of the layout of the integrated LC oscillator; and

[0011] Figure 3 A flow chart of a method is shown according to the present disclosure.

[0012] Explanation of symbols

[0013] 100: LC Oscillator

[0014] 110: First LC cavity

[0015] 120: Staggered coupling pairs

[0016] 130: Second LC cavity

[0017] 111: Inductor

[0018] 112: Capacitor

[0019] 121: NMOS transistor

[0020] 122: NMOS transistor

[0021] 131: Inductor

[0022] 132: Capacitor

[0023] V DD : Power supply node

[0024] 200: LC Oscillator

[0025] 201: First node

[0026] 202: Second node

[0027] 203: Third Node

[0028] 220: Staggered coupling pairs

[0029] L1: First inductor

[0030] L2: Second inductor

[0031] L3: The third inductor

[0032] L4: The fourth inductor

[0033] C1: First capacitor

[0034] C2: Second capacitor

[0035] C3: The third capacitor

[0036] C4: The fourth capacitor

[0037] M1: First NMOS transistor

[0038] M2: Second NMOS transistor

[0039] V DD : Power supply node

[0040] k 13 :First mutual coupling

[0041] k 14 :Second mutual coupling

[0042] B200: Instructions Block

[0043] UTM: Extra Thick Metal

[0044] RDL: Heavy Distribution Layer

[0045] F1~F8: Finger

[0046] S1: First Strip

[0047] v1_1, v1_2, v1_3, v1_4: the first set of through holes

[0048] S2: Second strip

[0049] v2_1, v2_2, v2_3, v2_4: the second set of through holes

[0050] L3_1: First winding coil

[0051] L3_2: Second winding coil

[0052] L3_V: Through hole

[0053] L4_1: The third winding coil

[0054] L4_2: The fourth winding coil

[0055] L4_V: Through hole

[0056] M1n2: Area

[0057] C1_1, C1_2, C1_3, C1_4, C1_5, C1_6: capacitance of the first capacitor C1

[0058] C2_1, C2_2, C2_3, C2_4, C2_5, C2_6: capacitance of the second capacitor C2

[0059] GND: Ground bar

[0060] P200: Symmetry plane

[0061] CT1: First center tap position

[0062] CT2: Second center tap position

[0063] 300: Flowchart

[0064] 310~390: Steps DETAILED DESCRIPTION

[0065] The present disclosure relates to an inductor-capacitor (LC) oscillator. Although the present specification discloses a plurality of embodiments of the present disclosure which may be considered as preferred examples for implementing the present invention, the present invention may be implemented in a variety of ways, and is not limited to the specific examples described below, nor is it limited to the specific ways used to implement the technical features of the specific examples. In other cases, known details are not shown or described to avoid obstructing the presentation of the present disclosure.

[0066] Those skilled in the art may understand the terms and basic concepts related to microelectronics used in the present disclosure, such as "voltage", "current", "oscillator", "frequency", "resonance", "power supply", "CMOS (complementary metal oxide semiconductor)", "NMOS (N-channel metal oxide semiconductor)", "inductor", "capacitor", "via", "cross couple", and "coil". Such terms are used in articles on microelectronics, and the concepts related thereto are obvious to those skilled in the art, so their details are not repeated here.

[0067] A person skilled in the art can recognize a capacitor symbol, an inductor symbol, a mutual inductive coupling symbol, and can recognize an NMOS transistor symbol, and can recognize its "source", "gate" and "drain" terminals. A person skilled in the art can understand that a diagram of a circuit contains components such as capacitors, inductors, NMOS transistors, etc., and does not need redundant descriptions to indicate how a component in the diagram is connected to another component.

[0068] The present disclosure is expressed in terms of engineering concepts. For example, with respect to two variables X and Y, when it is mentioned that "X is equal to Y", it means "X is approximately equal to Y", that is, "the difference between X and Y is less than a specific engineering error"; when it is mentioned that "X is zero", it means "X is approximately zero", that is, "X is less than a specific engineering error"; when it is mentioned that "X is substantially smaller than Y", it means "X is negligible with respect to Y", that is, "the ratio between X and Y is less than an engineering error, so X is negligible compared to Y".

[0069] A power supply node is a circuit node at a voltage that is approximately equal to a power supply voltage that is above zero but may have a small high-frequency fluctuation. A ground node is a circuit node at a voltage that is approximately zero but may have a small high-frequency fluctuation.

[0070] Throughout this disclosure, “V DD ” indicates a power supply node. In the present disclosure, according to the context that is obvious to those skilled in the art, sometimes V DD Refers to the power supply node V DD For example, it is obvious that when we say “V DD ” is 0.7V, we are expressing that the power supply node V DD The voltage level is 0.7V.

[0071] A circuit is a collection of transistors, resistors, inductors, capacitors, and / or other electronic devices interconnected in a specific manner to achieve a specific function.

[0072] An inductor comprises a conductive path, usually implemented by a metal wire (or trace), which allows a current to flow and induces a magnetic field. An inductor is usually implemented by a metal wire (or trace) configured in a loop topology with two open ends, the two open ends including a first end and a second end, wherein a current can flow from the first end to the second end. A coil is an inductor comprising a metal wire (or trace) configured in a multi-turn spiral topology.

[0073] A CMOS process technology allows the integration of multiple transistors, capacitors, and inductors, which are laid out in a multi-layer structure and interconnected using metal traces and inter-metal-layer vias. One of the purposes of the present disclosure is to use a CMOS process technology to integrate an LC oscillator with a compact layout area while achieving a low-noise technical effect. A multi-layer structure of a CMOS technology includes a polysilicon layer and multiple metal layers, and the multiple metal layers include an ultra-thick metal (UTM) layer, a re-distribution layer (RDL), and multiple lower metal layers. For example, a 28-nanometer 1P7M (a polysilicon layer, a UTM layer, six lower metal layers, and an RDL in a multi-layer structure) CMOS technology is used, but this is not an implementation limitation of the present invention.

[0074] According to one embodiment of the present invention, Figure 2A FIG. 2 is a schematic diagram of an LC oscillator 200. The LC oscillator 200 is integrated and fabricated on a silicon substrate using a 28 nanometer (28nm) 1P7M CMOS technology. The above-mentioned method is only an example as described above and is not a limitation of the present invention. The LC oscillator 200 includes: a first inductor L1, a second inductor L2, a third inductor L3, a fourth inductor L4, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, and an interleaved coupling pair 220 including a first NMOS transistor M1 and a second NMOS transistor M2. A center tap of the first inductor L1 is connected to the power supply node “V DD ”, as a non-limiting example, V DD There is a first mutual coupling between the first inductor L1 and the third inductor L3, with k 13 There is a second mutual coupling between the first inductor L1 and the fourth inductor L4, with k 14 In terms of function, the LC oscillator 200 is similar to Figure 1 The first inductor L1 and the second inductor L2 are both placed between a first node 201 and a second node 202, so they are connected in parallel and together realize a single inductor like Figure 1 The first capacitor C1 and the second capacitor C2 are both placed between the first node 201 and the second node 202, so they are connected in parallel and together realize the function of a single capacitor as Figure 1The third inductor L3 and the fourth inductor L4 are both placed between a third node 203 and a ground node, so they are connected in parallel and together realize the function of a single inductor as Figure 1 The third capacitor C3 and the second capacitor C4 are both placed at the third node 203 and the ground node, and together realize the function of a single capacitor as Figure 1 The interleaved coupling pair 220 realizes Figure 1 The staggered coupling pairs 120 have the function of.

[0075] In short, the inductor 111 is divided into two parallel inductors L1 and L2, and the inductor 131 is divided into two parallel inductors L3 and L4. The advantages of the above approach are described below. In addition, the LC oscillator 200 and Figure 1 A major difference between the LC oscillator 100 and the first mutual coupling k 13 (between the first inductor L1 and the third inductor L3) and the second mutual coupling k 14 (between the first inductor L1 and the fourth inductor L4). In one embodiment, the first inductor L1 is the same as the second inductor L2, the first capacitor C1 is the same as the second capacitor C2, the third capacitor C3 is the same as the fourth capacitor C4, and the third inductor L3 is the same as the fourth inductor L4. The first mutual coupling k 13 The second mutual coupling k 14 They are identical in magnitude but opposite in sign.

[0076] For the purpose of compact layout, the first inductor L1, the third inductor L3 and the fourth inductor L4 are arranged in close proximity, so the first mutual coupling k 13 The second mutual coupling k 14 However, based on the first mutual coupling k 13 The second mutual coupling k 14 are equal in magnitude but opposite in sign, the effect of this first mutual coupling k 13 This cancels out the second mutual coupling k 14 In this way, the effects of strong mutual coupling caused by a compact layout can be mitigated.

[0077] Figure 2BA top view of the layout of the LC oscillator 200 is shown. An illustration is shown in block B200. The first inductor L1 is arranged on the UTM layer in a loop form with two interdigitated multi-finger ends, including a first multi-finger end and a second multi-finger end, the first multi-finger end including fingers F1 and F3, and the second multi-finger end including fingers F2 and F4. The second inductor L2 is arranged on the UTM layer in a loop form with two interdigitated multi-finger ends, including a third multi-finger end and a fourth multi-finger end, the third multi-finger end including fingers F5 and F7, and the fourth multi-finger end including fingers F6 and F8. The first multi-finger end is electrically connected to the third multi-finger end and effectively embodying the first node 201. The second multi-finger end is electrically connected to the fourth multi-finger end and effectively embodying the second node 202. In another embodiment, the LC inductor further comprises: a first strip S1 arranged on the RDL, and a first set of vias including v1_1, v1_2, v1_3 and v1_4, the vias are used to connect fingers F1, F3, F5 and F7, so they are electrically short-circuited and jointly realize the first node 201 in a distributed manner; a second strip S2 arranged on the RDL, and a second set of vias including v2_1, v2_2, v2_3 and v2_4, the vias are used to connect fingers F2, F4, F6 and F8, so they are electrically short-circuited and jointly realize the second node 202 in a distributed manner. The third inductor L3 and the fourth inductor L4 are arranged in the loop of the first inductor L1. The third inductor L3 includes a first winding coil L3_1 arranged on the UTM layer, and includes a second winding coil L3_2 arranged on the RDL, wherein the first winding coil L3_1 and the second winding coil L3_2 are arranged in a spiral form, and spiral in a counterclockwise direction, and are connected through a through hole L3_V. The fourth inductor L4 includes a third winding coil L4_1 arranged on the UTM layer, and includes a fourth winding coil L4_2 arranged on the RDL, wherein the third winding coil L4_1 and the fourth winding coil L4_2 are arranged in a spiral form, and spiral in a clockwise direction, and are connected through a through hole L4_V.

[0078] The first NMOS transistor M1 and the second NMOS transistor M2 are arranged in an area marked as M1n2. The first capacitor C1 is implemented in a distributed manner and includes capacitors C1_1, C1_2, C1_3, C1_4, C1_5 and C1_6. The second capacitor C2 is also implemented in a distributed manner and includes capacitors C2_1, C2_2, C2_3, C2_4, C2_5 and C2_6. Capacitors C1_1 and C1_2 are placed between fingers F1 and F2. Capacitors C1_3 and C1_4 are placed between fingers F2 and F3. Capacitors C1_5 and C1_6 are placed between fingers F3 and F4. Capacitors C2_1 and C2_2 are placed between fingers F5 and F6. Capacitors C2_3 and C2_4 are placed between fingers F6 and F7. Capacitors C2_5 and C2_6 are placed between fingers F7 and F8. A ground strip labeled “GND” is arranged on the UTM layer to provide a common termination for the third inductor L3 and the fourth inductor L4 and realize a ground node. It is worth noting that the third inductor L3 and the fourth inductor L4 are also connected to the third node 203. Figure 2A and Figure 2B shown.

[0079] For a plane of symmetry P200, the third inductor L3 and the fourth inductor L4 are mirror images of each other. It is worth noting that from the top view, the symmetry plane P200 looks like a line. The ground strip GND is laid out along the symmetry plane P200. For the symmetry plane P200, the first inductor L1 and the second inductor L2 are substantially symmetrical. Based on the symmetry, the current flowing from the third node 203 to the third inductor L3 is the same as the current flowing from the third node 203 to the fourth inductor L4, but the two currents spiral in opposite directions: the former is in a counterclockwise direction, and the latter is in a clockwise direction. Therefore, the mutual coupling (i.e., k) between the second inductor L3 and the first inductor L1 is 13 ) and the mutual coupling between the fourth inductor L4 and the first inductor L1 (ie: k 14 ) will be the same in magnitude but opposite in sign. By the above method, the net effect of a strong magnetic coupling caused by arranging the third inductor L3 and the fourth inductor L4 in a close proximity manner in the first inductor L1 is zero.

[0080] In one embodiment, Figure 2BEach capacitor (ie, C1_1, C1_2, etc.) is a metal-oxide-metal (MOM) capacitor, which includes multiple interdigitated fingers in the lower metal layers and is accompanied by multiple vias. MOM capacitors are prior art and will not be described in detail here.

[0081] An advantage of dividing the inductor 111 into parallel inductors L1 and L2 is that a first current of L1 flowing from the first multi-finger to the second multi-finger in a clockwise manner is always accompanied by a second current of L2 flowing from the third multi-finger to the fourth multi-finger in a counterclockwise manner, so that the magnetic field excited by the first current and the magnetic field excited by the second current form a closed loop, so that a magnetic flux can be confined. Undesired magnetic coupling between the LC oscillator 200 and any other circuits coexisting on the same silicon substrate can be effectively mitigated.

[0082] One advantage of splitting the inductor 131 into parallel inductors L3 and L4 is that L3 and L4 can be placed inside the loop of L1, which enables a compact layout while avoiding undesired net coupling with L1, thanks to the symmetry in the layout, which enables the magnetic coupling between L1 and L3 to cancel the magnetic coupling between L1 and L4.

[0083] The LC oscillator 200 can have a low phase noise thanks to the source degeneration provided by the inductors L3 , L4 and the capacitors C3 , C4 , just like the source degeneration provided by the inductor 131 and the capacitor 132 in the LC oscillator 100 .

[0084] like Figure 2B As shown, a first central tap position CT1 is marked at a midpoint of the first inductor L1 on the symmetry plane P200, and a second central tap position CT2 is marked at a midpoint of the second inductor L2 on the symmetry plane P200. Figure 2A As shown, the power supply node "V DD ” Connect the center tap of the first inductor L1 (ie: Figure 2B In an alternative embodiment (not shown in Figure 2A ), the power supply node “V DD ” Connect the center tap of the second inductor L2 (ie: Figure 2B In another alternative embodiment, the power supply node “V DD” is connected to the central tap of the first inductor L1 and is also connected to the central tap of the second inductor L2.

[0085] The first inductor L1 has two multi-finger ends (i.e., the first multi-finger end and the second multi-finger end) that are interdigitated with each other; this enables the first capacitor C1 to be arranged between the two multi-finger ends in a distributed manner, forming a compact layout area, while part of the layout area of ​​the first inductor is reused to arrange the first capacitor. The above approach also applies to the second inductor L2 and the second capacitor C2. Although the multi-finger form is helpful, it is not a necessary condition for implementing the present invention.

[0086] like Figure 3 As shown in the flowchart 300, according to an embodiment of the present disclosure, the method of integrating an oscillator includes: (step 310) for a symmetry plane, a first inductor is arranged in a substantially symmetrical manner to form a first loop from a first end to a second end; (step 320) for the symmetry plane, a second inductor is arranged in a substantially symmetrical manner to form a second loop from a third end to a fourth end, the third end is connected to the first end, and the fourth end is connected to the second end; (step 330) a third inductor is arranged in a counterclockwise spiral shape, the third inductor of the counterclockwise spiral shape is located in the first loop and is on one side of the symmetry plane; (step 340) a fourth inductor is arranged in a clockwise spiral shape, the fourth inductor of the clockwise spiral shape is arranged in a clockwise spiral shape, The inductor is located in the first loop, and the fourth inductor is a mirror image of the third inductor for the symmetry plane; (step 350) a grounding strip is arranged along the symmetry plane to provide a common termination point for the third inductor and the fourth inductor; (step 360) a first capacitor is arranged between the first end and the second end; (step 370) a second capacitor is arranged between the third end and the fourth end; (step 380) a third capacitor is arranged between the third inductor and the grounding strip, and a fourth capacitor is arranged between the fourth inductor and the grounding strip, and the fourth capacitor is a mirror image of the third capacitor for the symmetry plane; and (step 390) an interlaced coupling transistor pair is arranged to electrically interlace the first end and the second end.

[0087] Although the embodiments of the present invention are described above, these embodiments are not intended to limit the present invention. Those skilled in the art may make changes to the technical features of the present invention based on the explicit or implicit contents of the present invention. All these changes may fall within the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be subject to that defined by the claims of this specification.

Claims

1. An integrated oscillator comprising: a first inductor arranged as a first loop from a first end to a second end, wherein the first loop is symmetrical with respect to a symmetry plane; a second inductor arranged into a second loop from a third end to a fourth end, wherein the third end is connected to the first end, and the fourth end is connected to the second end, and the second loop is symmetrical with respect to the symmetry plane; a third inductor arranged in a counterclockwise spiral shape, the third inductor in the counterclockwise spiral shape being located in the first loop and on one side of the symmetry plane; a fourth inductor arranged in a clockwise spiral shape, the fourth inductor in the clockwise spiral shape being located in the first loop, and being a mirror image of the third inductor with respect to the symmetry plane; a ground bar arranged along the symmetry plane to provide a common termination point for the third inductor and the fourth inductor; A first capacitor arranged between the first end and the second end; a second capacitor disposed between the third terminal and the fourth terminal; a third capacitor disposed between the third inductor and the ground bar; a fourth capacitor disposed between the fourth inductor and the grounding strip, wherein the fourth capacitor is a mirror image of the third capacitor with respect to the symmetry plane; and A cross-coupled transistor pair is used to electrically cross-couple the first end and the second end.

2. An integrated oscillator as described in claim 1, wherein the first end is in a multi-finger form, including a first group of fingers; the second end is in a multi-finger form, including a second group of fingers, and the second group of fingers are interlaced with the first group of fingers; the third end is in a multi-finger form, including a third group of fingers; the fourth end is in a multi-finger form, including a fourth group of fingers, and the fourth group of fingers are interlaced with the third group of fingers; the first group of fingers, the second group of fingers, the third group of fingers and the fourth group of fingers are all perpendicular to the symmetry plane.

3. The integrated oscillator of claim 2, wherein the first capacitor is arranged between the first group of fingers and the second group of fingers in a distributed manner, and the second capacitor is arranged between the third group of fingers and the fourth group of fingers in a distributed manner.

4. The integrated oscillator as claimed in claim 2, further comprising: a first connecting strip and a first set of through holes, used to electrically short-circuit the first set of fingers and the third set of fingers; and a second connecting strip and a second set of through holes, used to electrically short-circuit the second set of fingers and the fourth set of fingers.

5. The integrated oscillator as described in claim 1 is integrated on a silicon substrate through a complementary metal oxide semiconductor process and includes a multi-layer planar structure, which includes an ultra-thick metal layer, a redistribution layer, multiple underlying metal layers and multiple through-hole layers, and the multiple through-hole layers are used to provide electrical connections between metal layers. 6 . The integrated oscillator as claimed in claim 5 , wherein the first inductor is disposed on the ultra-thick metal layer. 7 . The integrated oscillator as claimed in claim 5 , wherein the second inductor is disposed on the ultra-thick metal layer.

8. An integrated oscillator as described in claim 5, wherein the third inductor comprises: a first winding coil arranged on the ultra-thick metal layer; a second winding coil arranged on the redistribution layer; and a through hole located between the ultra-thick metal layer and the redistribution layer for electrically connecting the first winding coil and the second winding coil. 9 . The integrated oscillator as claimed in claim 1 , wherein a center tap of the first inductor is located on the symmetry plane and is electrically connected to a power supply node. 10 . The integrated oscillator as claimed in claim 1 , wherein a center tap of the second inductor is located on the symmetry plane and is electrically connected to a power supply node.

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