Multi-chip stacking package and manufacturing method

Abstract

A multi-chip stacking package and a manufacturing method, relating to the field of chip technology, can solve the stress concentration problem of multi-chips, and can stack more layers of chips. The multi-chip stacking package comprises: a first chip (101) and a second chip (102) stacked along a first direction, wherein a first conductive through hole (31) is opened in the first chip (101) along the first direction, and a second conductive through hole (32) is opened in the second chip (102) along the first direction; a first rewiring layer (21) is arranged between the first chip (101) and the second chip (102), and the two sides of the first rewiring layer (21) are respectively fixed to the surface of the first chip (101) and the surface of the second chip (102), wherein the first conductive through hole (31) and the second conductive through hole (32) are connected through the first rewiring layer (21), and the first conductive through hole (31) and the second conductive through hole (32) are staggered. The multi-chip stacking package and the manufacturing method are used for manufacturing chips.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a multi-chip stacking package and a manufacturing method. Background Art

[0002] With the advancement of the electronic communications industry and the advent of the 5G (5th Generation) era, the booming development of technology products such as the Internet of Things (IoT) and Artificial Intelligence (AI), people's requirements for rapid information transmission capabilities are constantly increasing, and chip architecture is also developing along with the new market. The general chip architecture is a flat layout on the circuit board, which occupies a large area and requires many interfaces.

[0003] In the related art, there is a high bandwidth memory (HBM) technology that can stack and package multiple chips. The multi-chip stacking package made by it can meet the needs of multi-user, high throughput, low latency, and high-density equipment. The advanced chip architecture can improve the integration while making the bandwidth no longer restricted by the number of interconnected pins. In the multi-chip stacking package in the related art, in order to interconnect multiple chips, it is necessary to make TSV (Through Silicon Via) in the chip. The principle is to drill holes on the silicon wafer by etching or laser, and then fill them with conductive materials such as copper, polysilicon, tungsten and other materials. When multiple chips are stacked, the interconnection of TSV is used to achieve interconnection between multiple chips.

[0004] However, in the actual application of multi-chip stacking packaging in related technologies, the metal material at the TSV will produce creep after a period of time (solids deform over time under constant external forces), and the superposition of creep between multiple layers will cause stress concentration in the vertical direction, resulting in defects such as cracking. In particular, the creep effect is multiplied when three or more layers of chips are stacked. Summary of the invention

[0005] The embodiments of the present application provide a multi-chip stacking package and a manufacturing method, which can solve the stress concentration problem of multiple chips and can stack more layers of chips.

[0006] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0007] In a first aspect, the present application provides a multi-chip stack package, comprising:

[0008] A first chip and a second chip are stacked along a first direction, wherein a first conductive through hole is opened in the first chip along the first direction, and a second conductive through hole is opened in the second chip along the first direction;

[0009] A first rewiring layer is arranged between the first chip and the second chip, and two sides of the first rewiring layer are respectively fixed to the surface of the first chip and the surface of the second chip, wherein the first conductive via and the second conductive via are connected through the first rewiring layer, and the first conductive via and the second conductive via are staggered.

[0010] The multi-chip stacking package provided by the present application includes multiple chips, that is, at least two chips. Therefore, taking the connection between the first chip and the second chip as an example, since the first conductive vias and the second conductive vias are staggered, the metal creep in the first conductive vias and the metal creep in the second conductive vias will not be superimposed, which can reduce the impact of the metal creep, and the deformable amounts between the chips will not be superimposed, which can solve the stress concentration problem of multiple chips and allow stacking of more layers of chips.

[0011] In a first achievable manner of the first aspect, a plurality of first conductive through holes are provided in the first chip, and the plurality of first conductive through holes are arranged evenly at intervals; a plurality of second conductive through holes are provided in the second chip, and the plurality of second conductive through holes are arranged evenly at intervals. A plurality of conductive through holes on each chip can be provided as needed, and the layout of the plurality of conductive through holes can be evenly spaced. The plurality of first conductive through holes are evenly spaced and the plurality of second conductive through holes are evenly spaced, so that the stress generated by creep deformation is evenly dispersed on each chip, which is more helpful to reduce the influence of metal creep on the entire stacked package, and the even distribution facilitates layout.

[0012] When there are multiple first conductive vias and multiple second conductive vias, as long as one first conductive via is staggered with one second conductive via, the influence of metal creep on the overall structure can be reduced. Therefore, all first conductive vias and all second conductive vias can be staggered, or some first conductive vias and some second conductive vias can be staggered, and another part of first conductive vias and another part of second conductive vias can be arranged correspondingly.

[0013] In a second achievable manner of the first aspect, a third chip is further included, the first chip, the second chip and the third chip are stacked in sequence along the first direction, a third conductive via is provided in the third chip along the first direction, a second rewiring layer is provided between the second chip and the third chip, and both sides of the second rewiring layer are respectively fixed to the surface of the second chip and the surface of the third chip, the second conductive via and the third conductive via are connected through the second rewiring layer, and the second conductive via and the third conductive via are staggered. After including the first chip, the second chip and the third chip, the second conductive via on the second chip and the third conductive via on the third chip are staggered.

[0014] In the above-mentioned achievable manner, the conductive vias of adjacent chips can be staggered, thereby reducing the influence of metal creep on the overall structure. Of course, for chips that are not in adjacent layers, their conductive vias can also be staggered, further reducing the influence of metal creep on the overall structure. For example, in a third achievable manner of the first aspect, the first conductive via and the third conductive via are staggered.

[0015] In addition, all the conductive through holes in the chips of all layers of the multi-layer chip can also be staggered, which is more conducive to reducing the influence of stress concentration. However, such a setting has great limitations on the structural design. Generally, by ensuring that the conductive through holes of two adjacent chips are staggered, it can be ensured that the problem of interlayer cracking caused by stress concentration is not easily generated. It should be noted that since there are many structures inside the chip itself, the position where the conductive through holes may be arranged only occupies an area of ​​the chip. Therefore, the conductive through holes in the above implementation are evenly spaced, which means that the conductive through holes are spaced within the range of their position that can be set (that is, within an area of ​​the chip where the conductive through holes can be arranged).

[0016] In a fourth achievable manner of the first aspect, the first rewiring layer is made of a soft material. The rewiring layer made of a soft material can absorb the stress of the multi-chip stacking package and is more conducive to the stacking of multiple layers of chips. The soft material can be aluminum. Of course, when a second rewiring layer is provided, the second rewiring layer can also be made of a soft material.

[0017] In a fifth achievable manner of the first aspect, the first rewiring layer includes a first part of the first rewiring layer disposed on the side of the first chip facing the second chip, and a second part of the first rewiring layer disposed on the side of the second chip facing the first chip, a first bonding portion is disposed in the first part of the first rewiring layer, a second bonding portion is disposed in the second part of the first rewiring layer, and the first rewiring layer portion and the second rewiring layer portion are bonded by the first bonding portion and the second bonding portion. The connection between multiple chips can be connected in the form of bumps (μbumps in the related art, i.e. microbumps, are bumps with relatively small diameters and heights), or can be connected by bonding (Bonding, a technique of directly bonding two homogeneous or heterogeneous semiconductor materials with clean surfaces and atomically flat surfaces after surface cleaning and activation treatment, and bonding under certain conditions, and bonding the wafers into one body through van der Waals forces, molecular forces, or even atomic forces). In comparison, the bonding portion used in the bonding method is much lower than the height of the bumps, so the thickness of the overall structure can be reduced by using the bonding method. In addition, before the first chip and the second chip are bonded, the first bonding part and the second bonding part need to be prepared respectively, and the bonding parts need to rely on the rewiring layer. Therefore, generally, there are rewiring layers on the opposite surfaces of the first chip and the second chip, that is, the first rewiring layer between the first chip and the second chip actually has two layers in the process, which are respectively referred to as the first rewiring layer part arranged on the side of the first chip facing the second chip, and the second rewiring layer part arranged on the second chip facing the first chip.

[0018] It should be noted that the use of bumps to connect individual chips can achieve multi-layer chip stacking. If multiple chips are connected by hybrid bonding, the hybrid bonding method cannot achieve a multi-layer chip stacking structure due to the creep effect of the metal in the silicon vias of the adjacent chips. The silicon vias of adjacent chips in the present application are staggered, and the creep effects between the chips will not be superimposed, so the chips can be connected by bonding.

[0019] In a sixth achievable manner of the first aspect, the first bonding portion is a plurality of first bonding portions, the second bonding portion is a plurality of second bonding portions, and the plurality of first bonding portions and the plurality of second bonding portions are arranged in a one-to-one correspondence. In addition, after the plurality of bonding portions are arranged, the spacing between the plurality of bonding portions can also be smaller than the spacing between the bumps, which can facilitate layout, and more lines of information transmission can be performed between chips to achieve more functions.

[0020] In a seventh achievable manner of the first aspect, the thickness of the bonding portion along the first direction is 2 microns. Generally, in the bump method, the thickness of the bump is generally 20 microns, so the bonding method can significantly reduce the thickness of the entire structure compared to the bump method.

[0021] In an eighth achievable manner of the first aspect, the spacing between the multiple bonding portions on each rewiring layer is 5 microns. Generally, in the bump method, the spacing between the multiple bumps is generally more than 20 microns. Therefore, the bonding method has a smaller spacing between structures than the bump method, and more circuits can be arranged to transmit more information and realize more functions.

[0022] In a ninth achievable manner of the first aspect, the first chip and the second chip include a passive layer and an active layer, respectively, and the passive layer of the first chip is electrically connected to the active layer of the second chip through a first rewiring layer. In the multi-chip stacking package of the present application, the stacking of multiple chips can be F2B (Face to Back, face-to-back bonding) or F2F (Face to Face, face-to-face bonding), wherein the face is the front side, the back is the back side, the front side is the active side of the chip, that is, one side of the active layer, and the back side is the other side of the chip, that is, one side of the passive layer. Compared with F2F, F2F will make the interface leads of the bottom chip difficult. Therefore, the F2B method is generally used to realize the stacking of multiple chips, that is, the passive layer of the first chip is electrically connected to the active layer of the second chip through the first rewiring layer.

[0023] In a tenth achievable manner of the first aspect, it further includes a third redistribution layer disposed on one side of the active layer of the first chip, and the third redistribution layer is connected to other substrates or circuit boards through a plurality of solder balls.

[0024] In a second aspect, an embodiment of the present application provides a method for manufacturing a multi-chip stack package, comprising:

[0025] A first conductive through hole is opened along a first direction on the first chip, and a first portion of a first rewiring layer is prepared on a surface of one side of the first chip, and the first conductive through hole is connected and conducted with the first portion of the first rewiring layer;

[0026] A second conductive through hole is opened on the second chip along the first direction, and a second portion of the first redistribution layer is prepared on a surface of one side of the second chip, and the second conductive through hole is connected and conducted with the second portion of the first redistribution layer;

[0027] The first part of the first rewiring layer and the second part of the first rewiring layer are fixedly connected and conducted to form a first rewiring layer between the first chip and the second chip, the first chip and the second chip are fixed, and the first conductive via and the second conductive via are staggered.

[0028] The manufacturing method of the multi-chip stacking package provided in the embodiment of the present application can reduce the influence of metal creep because the first conductive through hole and the second conductive through hole are staggered after the first chip and the second chip are fixed. The deformable variables between the chips will not be superimposed, thereby solving the stress concentration problem of multiple chips and allowing more layers of chips to be stacked.

[0029] In a first possible implementation of the second aspect, the method further includes:

[0030] A first portion of a second rewiring layer is prepared on a surface of the second chip which is away from the first chip, and a second conductive through hole is connected to the first portion of the second rewiring layer;

[0031] A third conductive through hole is opened on the third chip along the first direction, and a second portion of a second redistribution layer is prepared on a surface of one side of the third chip, and the third conductive through hole is connected and conducted with the second portion of the second redistribution layer;

[0032] The first part of the second rewiring layer and the second part of the second rewiring layer are fixedly connected and conducted to form a second rewiring layer between the second chip and the third chip, the second chip and the third chip are fixed, and the second conductive via and the third conductive via are staggered.

[0033] After the multi-chip stacking package includes the first chip, the second chip and the third chip, the second chip is fixed to the third chip, and the second conductive through hole on the second chip and the third conductive through hole on the third chip are staggered, which can also reduce the impact of metal creep on the overall structure.

[0034] In a second implementation manner of the second aspect, the step of fixedly connecting and conducting the first portion of the first re-wiring layer and the second portion of the first re-wiring layer comprises:

[0035] forming a first bonding portion in a first portion of a first redistribution layer;

[0036] forming a second bonding portion in the first redistribution layer second portion;

[0037] The first bonding portion and the second bonding portion are bonded to each other so that the first portion of the first re-wiring layer and the second portion of the first re-wiring layer are fixedly connected and conductive.

[0038] The first chip and the second chip are fixed with the first redistribution layer, and the method of bumps or bonding can be adopted. In comparison, the bonding part adopted by the bonding method has a much lower height than that of the bumps. Therefore, the bonding method can reduce the thickness of the overall structure.

[0039] In a third implementation manner of the second aspect, the first chip and the second chip include a passive layer and an active layer respectively, and the manufacturing method further includes:

[0040] The passive layer of the first chip is electrically connected to the active layer of the second chip.

[0041] In a fourth possible implementation of the second aspect, the manufacturing method further includes:

[0042] forming a third redistribution layer on one side of the active layer of the first chip;

[0043] A plurality of solder balls are formed on the third redistribution layer.

[0044] A plurality of solder balls are used for connecting the multi-chip stack package with other substrates or circuit boards.

[0045] In a fifth implementation manner of the second aspect, before the step of fixedly connecting and conducting the first portion of the first re-wiring layer and the second portion of the first re-wiring layer, the manufacturing method further includes:

[0046] A third rewiring layer is prepared on a surface of the first chip on one side away from the first portion of the first rewiring layer, and the first conductive via is connected to the third rewiring layer;

[0047] A wafer carrier layer is bonded outside the third redistribution layer of the first chip.

[0048] When the first chip and the second chip are fixed, since the chip itself is thin and difficult to clamp, a carrier sheet, i.e., a wafer carrier layer, can be temporarily bonded on the first chip, and the chip can be easily operated by clamping the wafer carrier layer. In addition, after the corresponding operation is completed, the wafer carrier layer can be retained, thinned, or removed. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 is a cross-sectional view of a multi-chip stack package;

[0050] Figure 2 A cross-sectional view of a multi-chip stack package provided for an embodiment of the application;

[0051] Figure 3 A cross-sectional view of staggered arrangement of conductive vias in a multi-chip stack package provided in an embodiment of the application;

[0052] Figure 4 A schematic cross-sectional view of a plane perpendicular to a first direction in which conductive through holes of a multi-chip stack package provided in an embodiment of the application are staggered;

[0053] Figure 5 One of the processes of the first embodiment of the method for manufacturing a multi-chip stack package provided in the application embodiment;

[0054] Figure 6The second process of the first embodiment of the method for manufacturing a multi-chip stack package provided in the application embodiment;

[0055] Figure 7 The third process of the first embodiment of the method for manufacturing a multi-chip stack package provided in the application embodiment;

[0056] Figure 8 The fourth process of the first embodiment of the method for manufacturing a multi-chip stack package provided in the application embodiment;

[0057] Fig. 9 Process 5 of the first embodiment of the method for manufacturing a multi-chip stack package provided in the application embodiment;

[0058] Fig.10 One of the processes of the second embodiment of the method for manufacturing a multi-chip stack package provided in the application embodiment;

[0059] Fig.11 The second process of the second embodiment of the method for manufacturing a multi-chip stack package provided in the application embodiment;

[0060] Fig.12 The third process of the second embodiment of the method for manufacturing a multi-chip stack package provided in the application embodiment;

[0061] Fig.13 The fourth process of the second embodiment of the method for manufacturing a multi-chip stack package provided in the application embodiment;

[0062] Fig.14 One of the processes of the third embodiment of the method for manufacturing a multi-chip stack package provided in the application embodiment;

[0063] Fig.15 The second process of the third embodiment of the method for manufacturing a multi-chip stack package provided in the application embodiment;

[0064] Fig.16 The third process of the third embodiment of the method for manufacturing a multi-chip stack package provided in the application embodiment;

[0065] Fig.17 The fourth step of the third embodiment of the method for manufacturing a multi-chip stack package provided in the application embodiment;

[0066] Fig.18 The fifth step of the third embodiment of the method for manufacturing a multi-chip stack package provided in the application embodiment;

[0067] Fig.19 Process 6 of the third embodiment of the method for manufacturing a multi-chip stack package provided in the application embodiment;

[0068] Fig. 20 This is process seven of the third embodiment of the method for manufacturing a multi-chip stack package provided in the application embodiment.

[0069] Reference numerals:

[0070] 01-chip; 011-passive layer; 012-active layer; 013-rewiring layer; 014-conductive via; 02-bump; 03-solder ball; 1-chip; 101-first chip; 102-second chip; 103-third chip; 104-fourth chip; 105-fifth chip; 11-passive layer; 12-active layer; 2-rewiring layer; 21-first rewiring layer; 211-first part of first rewiring layer; 212-second part of first rewiring layer; 2 2-second rewiring layer; 221-first part of second rewiring layer; 222-second part of second rewiring layer; 23-third rewiring layer; 3-conductive via; 31-first conductive via; 32-second conductive via; 33-third conductive via; 4-bonding part; 41-first bonding part; 42-second bonding part; 5-solder ball; 6-wafer carrier layer; 61-first wafer carrier layer; 62-second wafer carrier layer; 63-third wafer carrier layer; 7-bonding film layer 7. DETAILED DESCRIPTION

[0071] Reference Figure 1 , is a schematic diagram of a cross-sectional structure after multiple chips are stacked by means of bumps. Chip 01 includes a passive layer 011 and an active layer 012. The passive layer 011 contains a wafer, and the active layer 012 contains the wiring and devices of the chip. In addition, in order to fix the multiple chips 01, a redistribution layer 013 (RDL) is provided on the surface of the chip 01. The redistribution layer 013 can re-layout the wiring of the chip 01, and facilitate the preparation of other required structures on the redistribution layer 013. The scheme adopted in the figure is to set bumps 02 on the redistribution layer 013, and use the bumps 02 to connect the conductive through holes 014 of adjacent chips 01, thereby ensuring the interconnection between multiple chips 014. A plurality of solder balls 03 are provided on one side of the stacked multiple chips.

[0072] When stacking multiple chips, bonding can also be used. Bonding is a technology that directly combines two homogeneous or heterogeneous semiconductor materials with clean and atomically flat surfaces under certain conditions after surface cleaning and activation, and bonds the chips together through van der Waals forces, molecular forces, and even atomic forces.

[0073] In addition, in the production of chips, a temporary bonding method is also used, that is, it is necessary to first bond a carrier to the chip as a support, and then debond and remove the carrier after the required operation is completed. Specifically, as people's requirements for electronic products develop in the direction of miniaturization, electronic chips are also developing in the direction of becoming thinner and thinner. However, if the thickness of the silicon wafer is to be thinned to 100 microns or less, it is very easy to break, or the wafer will be bent and deformed due to stress when the wafer is processed, and it is impossible to directly process such ultra-thin wafers. Therefore, in order to process such ultra-thin wafers, it is necessary to temporarily bond such ultra-thin wafers with a carrier first. After bonding, the wafer and the carrier are bonded together, and the wafer can be thinned, TSV is manufactured, the rewiring layer is manufactured, and internal interconnections are formed. Then the wafer is separated from the carrier, and the thinned wafer is cleaned, cut, and other processes are performed to complete the processing of such ultra-thin wafers. The wafer bonding method currently used in the industry is generally to apply bonding glue between the carrier and the wafer, and then use a bonding machine to bond the carrier and the wafer together. Wafer debonding refers to separating the bonded carrier and wafer. There are generally the following methods for debonding the above-mentioned temporarily bonded wafers: the first is to use a solvent to dissolve the bonding glue from the edge of the bonded carrier and wafer, and the second is to use thermal shear separation. In the first method, the solvent slowly dissolves the bonding glue from the edge where the wafer and the carrier are combined. The time for the solvent to reach the center of the wafer is too long, and the separation efficiency is too low. In addition, direct separation of the carrier from the wafer requires a special carrier to fix the wafer to prevent the wafer and the carrier from mixing during separation. The process is cumbersome and the cost is high. The second method requires special equipment for thermal shearing, which is costly, and the wafer is easily damaged during shearing, and the success rate is low.

[0074] Refer to Figure 1 In the multi-chip stacking package, on the one hand, since the silicon through vias 014 between adjacent chips 01 are set correspondingly, the metal in the silicon through vias 014 will be greatly deformed after a long period of creep. In this way, the corresponding silicon through vias 014 will multiply the deformation, resulting in stress concentration of the overall structure, and the problem of interlayer fracture may occur; on the other hand, since the chips 01 are connected by bumps 02, the thickness of the overall structure is relatively thick. In the production process of multi-chip stacking package of related technology, each production layer of chips 01 requires temporary bonding of a carrier, and the production process is bound to be complicated.

[0075] The present application provides a multi-chip stacking package, such as Figure 2 and Figure 3 As shown, Figure 2 This is a cross-sectional view of a multi-chip stack package. Figure 3A cross-sectional view of a staggered arrangement of conductive vias for a multi-chip stack package, including:

[0076] A first chip 101 and a second chip 102 are stacked along a first direction, wherein a first conductive via 31 is opened in the first chip 101 along the first direction, and a second conductive via 32 is opened in the second chip 102 along the first direction;

[0077] The first rewiring layer 21 is arranged between the first chip 101 and the second chip 102, and the two sides of the first rewiring layer 21 are respectively fixed to the surface of the first chip 101 and the surface of the second chip 102, wherein the first conductive via 31 and the second conductive via 32 are connected through the first rewiring layer 21, and the first conductive via 31 and the second conductive via 32 are staggered.

[0078] The multi-chip stacking structure provided by the present application includes multiple chips 1, that is, at least two chips. Therefore, taking the connection between the first chip 101 and the second chip 102 as an example, the first chip 101 and the second chip 102 are stacked along the first direction, and the first chip 101 and the second chip 102 are connected and fixed by the first rewiring layer 21 to stack the first chip 101 and the second chip 102; the first conductive via 31 arranged on the first chip 101 and the second conductive via 32 arranged on the second chip 102 are connected through the first rewiring layer 21, and the first conductive via 31 and the second conductive via 32 are staggered. Since the first conductive via 31 and the second conductive via 32 are staggered, the metal creep in the first conductive via 31 and the metal creep in the second conductive via 32 will not be superimposed, which can reduce the influence of the metal creep, and the deformable amount between the chips 1 will not be superimposed, which can solve the stress concentration problem of multiple chips 1, and more layers of chips 1 can be stacked.

[0079] It should be noted that in the multi-chip stacking package, Figure 2 and Figure 3 The main structures include: chip 1, redistribution layer 2 and conductive via 3, etc. For the convenience of description, the first chip (marked as 101) and the second chip (marked as 102) are taken as examples to illustrate the connection structure between adjacent chips 1.

[0080] The conductive via is a via disposed in the chip 1 for conducting electricity to adjacent chips 1. It can be a through silicon via (TSV) or a through hole made of other materials. The through hole can be filled with conductive material to ensure the conductive function. Figure 2 , the first direction refers to the direction along the normal line of chip 1.

[0081] Reference Figure 2 and Figure 3, multiple conductive through holes 3 on each chip 1 can be provided as needed, and the layout of multiple conductive through holes 3 can be evenly spaced. Taking the first chip 101 and the second chip 102 as an example, the first chip 101 is provided with multiple first conductive through holes 31, and the multiple first conductive through holes 31 are evenly spaced; the second chip 102 is provided with multiple second conductive through holes 32, and the multiple second conductive through holes 32 are evenly spaced. The multiple first conductive through holes 31 are evenly spaced and the multiple second conductive through holes 32 are evenly spaced, which evenly disperses the stress generated by creep deformation on each chip 1, which is more helpful to reduce the influence of metal creep on the entire stacked package, and the even distribution facilitates layout.

[0082] When there are multiple first conductive vias 31 and second conductive vias 32, the influence of metal creep on the overall structure can be reduced as long as one first conductive via 31 is staggered with one second conductive via 32. Therefore, all first conductive vias 31 and all second conductive vias 32 may be staggered, or a part of the first conductive vias 31 and a part of the second conductive vias 32 may be staggered, and another part of the first conductive vias 31 and another part of the second conductive vias 32 may be arranged correspondingly.

[0083] After the first conductive via 31 and the second conductive via 32 are staggered, the influence of metal creep on the overall structure can be reduced. In actual stacking packaging, the embodiment of the present application can stack and package multiple chips, for example, 3, 4, 5, 6, 7 or even 8. For example, a third chip 103 is also included, the first chip 102, the second chip 102 and the third chip 103 are stacked in sequence along the first direction, a third conductive via 33 is opened in the third chip 103 along the first direction, a second rewiring layer 22 is provided between the second chip 102 and the third chip 103, and the two sides of the second rewiring layer 22 are respectively fixed to the surface of the second chip 102 and the surface of the third chip 103, the second conductive via 32 and the third conductive via 33 are connected through the second rewiring layer 22, and the second conductive via 32 and the third conductive via 33 are staggered. After the first chip 101 , the second chip 102 and the third chip 103 are included, the second conductive vias 32 on the second chip 102 and the third conductive vias 33 on the third chip 103 are staggered.

[0084] In the above-mentioned achievable manner, the conductive vias 3 of adjacent chips 1 can be staggered, thereby reducing the influence of metal creep on the overall structure. Of course, for chips 1 that are not adjacent layers, their conductive vias 3 can also be staggered, further reducing the influence of metal creep on the overall structure. For example, referring to Figure 2 and Figure 3 , the first conductive via 31 and the third conductive via 33 are staggered.

[0085] Reference Figure 2 , Figure 3 and Figure 4 In adjacent chips 1, the positions of all conductive through holes 3 will not overlap, that is, they are staggered, and further, they can be evenly spaced. It should be noted that for ease of understanding, Figure 3 is a cross-sectional view of a plane extending along a first direction, Figure 4 It is a cross-sectional schematic diagram along a plane perpendicular to the first direction, and for the convenience of observation, the conductive through holes 3 of two adjacent chips 1 are drawn out (only the conductive through hole 3 of one of the chips 1 can be seen in the cross section of the actual object), which are the first conductive through hole 31 and the second conductive through hole 32. It can be clearly seen that the first conductive through hole 31 and the second conductive through hole 32 respectively located on the two adjacent chips 1 are staggered and can be evenly spaced.

[0086] In addition, all the conductive vias 3 in the chip 1 of all layers of the multi-layer chip 1 can also be staggered, which is more conducive to reducing the influence of stress concentration. However, such a setting has great limitations on the structural design. Generally, by ensuring that the conductive vias 3 of two adjacent chips 1 are staggered, it can be ensured that the problem of interlayer cracking caused by stress concentration is not easily generated. It should be noted that, since there are many structures inside the chip 1 itself, the position where the conductive vias 3 are arranged may only occupy an area of ​​the chip 1. Therefore, the conductive vias 3 in the above implementation are evenly spaced, which means that the conductive vias 3 are spaced within the range of their position that can be set (that is, within an area of ​​the chip 1 where the conductive vias 3 can be arranged).

[0087] The rewiring layer 2 is made of a soft material. The rewiring layer 2 made of a soft material can absorb the stress of the stacking structure of the multi-chip 1, which is more conducive to the stacking of the multi-layer chip 1. The soft material can be aluminum. That is, when the first rewiring layer 21 and the second rewiring layer 22 are provided, the first rewiring layer 21 and the second rewiring layer 22 can be made of a soft material.

[0088] The connection between the multiple chips 1 can be connected in the form of bumps (μbumps in the related technology, i.e. micro bumps, are bumps with relatively small diameter and height) or bonding (Bonding, a technology that directly bonds two homogeneous or heterogeneous semiconductor materials with clean and atomically flat surfaces under certain conditions after surface cleaning and activation treatment, and bonds the chips together through van der Waals forces, molecular forces, or even atomic forces.) In comparison, the bonding part used in the bonding method is much lower than the height of the bumps, so the bonding method can reduce the thickness of the overall structure. Figure 2As shown, a bonding portion 4 is provided on the rewiring layer 2 of adjacent chips 1, and the rewiring layer 2 can conduct the bonding portion 4 connected thereon with the conductive through-hole 3, and the bonding portion 4 leaks out of the outer surface of the rewiring layer 2, and the two adjacent chips 1 are bonded and connected via the bonding portion 4, and the rewiring layer 2 can conduct the bonding portion 4 connected thereon with the conductive through-hole 3.

[0089] Taking the connection between the first chip 101 and the second chip 102 as an example, before bonding, the first chip 101 and the second chip 102 need to prepare the first bonding part 41 and the second bonding part 42 respectively, and the bonding part 4 needs to rely on the rewiring layer 2. Therefore, during the manufacturing process, the first chip 101 and the second chip 102 have rewiring layers 2 on the opposite surfaces, that is, the first rewiring layer 21 between the first chip 101 and the second chip 102 actually has two layers during the process, which are respectively referred to as the first rewiring layer part 211 arranged on the side of the first chip 101 facing the second chip 102, and the second rewiring layer part 212 arranged on the second chip 102 facing the first chip 101. Figure 2 The first rewiring layer 21 includes a first rewiring layer first part 211 arranged on the side of the first chip 101 facing the second chip 102, and a first rewiring layer second part 212 arranged on the side of the second chip 102 facing the first chip 101. The first rewiring layer first part 211 is provided with a first bonding part 41, and the first rewiring layer second part 212 is provided with a second bonding part 42. The first rewiring layer first part 211 and the first rewiring layer second part 212 are bonded by the first bonding part 41 and the second bonding part 42.

[0090] It should be noted that by connecting each chip 1 by means of bumps, multi-layer chip stacking can be achieved. If multiple chips are connected by hybrid bonding, the metal creep effect in the conductive vias 3 of the adjacent chips 1 makes it impossible to achieve a multi-layer chip stacking structure by hybrid bonding. However, the conductive vias 3 of the adjacent chips 1 of the present application are staggered, and the creep effects of the chips 1 will not be superimposed, so the chips 1 can be connected by bonding. In addition, the bonding method between multiple chips is hybrid bonding.

[0091] In addition, after multiple bonding parts 4 are provided, the spacing between the multiple bonding parts 4 can also be smaller than the spacing between the bumps, which can facilitate layout, and more lines of information transmission can be carried out between the chips 1 to achieve more functions. Figure 2As shown, each rewiring layer 2 is provided with a plurality of bonding portions 4, and the bonding portions 4 of two adjacent chips 1 are arranged in a one-to-one correspondence. Taking the first chip 101 and the second chip 102 as an example, the first bonding portion 14 is a plurality of first bonding portions 41, and the second bonding portion 42 is a plurality of second bonding portions 42, and the plurality of first bonding portions 41 and the plurality of second bonding portions 42 are arranged in a one-to-one correspondence.

[0092] Generally, the thickness of the bonding portion 4 along the first direction is 2 micrometers. In the bump method, the thickness of the bump is generally 20 micrometers. Therefore, the bonding method can significantly reduce the thickness of the entire structure compared to the bump method.

[0093] Generally, the spacing between the multiple bonding parts 4 on each rewiring layer 2 is 5 microns. In the bump method, the spacing between the multiple bumps is generally more than 20 microns. Therefore, the bonding method has a smaller spacing between structures than the bump method, and more circuits can be arranged to transmit more information and realize more functions.

[0094] In the multi-chip stacking structure of the present application, the stacking of multiple chips 1 can be F2B (Face to Back) or F2F (Face to Face), where the face is the front side and the back is the back side. The front side is the active side of the chip 1, one side of the active layer 12, and the back side is the other side of the chip 1, one side of the passive layer 11. Compared with F2F, F2B will make the interface lead of the bottom chip 1 difficult. Therefore, F2B is generally used to achieve the stacking of multiple chips 1. Figure 2 The first chip 101 and the second chip 103 include a passive layer 11 and an active layer 12 , respectively. The passive layer 11 of the first chip 101 and the active layer 12 of the second chip 102 are electrically connected via a first redistribution layer 21 .

[0095] In order to facilitate the connection with other external substrates or circuit boards after multi-chip stacking packaging, it is necessary to set up corresponding access port structures, such as Figure 2 As shown, it also includes a third redistribution layer 23 arranged on one side of the active layer of the first chip 101. The third redistribution layer 23 is connected to other substrates or circuit boards through multiple solder balls 5. Furthermore, the multi-chip stacking package can be connected to other external substrates or circuit boards through multiple solder balls 5.

[0096] The present application also provides a method for manufacturing a multi-chip stack package, including:

[0097] Reference Figure 2 and Figure 3, opening a first conductive through hole 31 along a first direction on the first chip 101, and preparing a first redistribution layer first portion 211 on a side surface of the first chip 101, and connecting the first conductive through hole 31 to the first redistribution layer first portion 211;

[0098] A second conductive via 32 is opened on the second chip 102 along the first direction, and a first redistribution layer second portion 212 is prepared on a side surface of the second chip 102, and the second conductive via 32 is connected to the first redistribution layer second portion 212 for conduction;

[0099] The first redistribution layer first portion 211 and the first redistribution layer second portion 212 are fixedly connected and conducted to form a first redistribution layer 21 between the first chip 101 and the second chip 102, fix the first chip 101 and the second chip 102, and stagger the first conductive via 31 and the second conductive via 32.

[0100] The manufacturing method of the multi-chip stacking package provided in the embodiment of the present application is that after the first chip 101 and the second chip 102 are fixed, the first conductive through hole 31 and the second conductive through hole 32 are staggered. Therefore, the influence of metal creep can be reduced, and the deformable variables between the chips 1 will not be superimposed, thereby solving the stress concentration problem of multiple chips and allowing more layers of chips to be stacked.

[0101] Reference Figure 2 In some embodiments, the method for manufacturing a multi-chip stack package further includes:

[0102] A second redistribution layer first portion 221 is prepared on a surface of the second chip 102 which is away from the first chip 101, and the second conductive via 32 is connected to the second redistribution layer first portion 221;

[0103] A third conductive through hole 33 is opened on the third chip 103 along the first direction, and a second redistribution layer second portion 222 is prepared on one side surface of the third chip 103, and the third conductive through hole 33 is connected to the second redistribution layer second portion 222 for conduction;

[0104] The second redistribution layer first portion 221 and the second redistribution layer second portion 222 are fixedly connected and conducted, so that a second redistribution layer 22 is formed between the second chip 102 and the third chip 103, the second chip 102 and the third chip 103 are fixed, and the second conductive via 32 and the third conductive via 33 are staggered.

[0105] After the multi-chip stacking package includes the first chip 101, the second chip 102 and the third chip 103, the second chip 102 is fixed to the third chip 103, and the second conductive through hole 32 on the second chip 102 and the third conductive through hole 33 on the third chip 103 are staggered, which can also reduce the impact of metal creep on the overall structure.

[0106] It should be noted that, refer to Figure 2 The first direction refers to the direction along the normal line of the chip 1 , and the normal lines of the first chip 101 , the second chip 102 , and the third chip 103 are in the same direction after being stacked.

[0107] Reference Figure 2 In some embodiments, the step of fixing and connecting the first re-wiring layer first portion 211 and the first re-wiring layer second portion 212 includes:

[0108] forming a first bonding portion 41 in the first redistribution layer first portion 211;

[0109] forming a second bonding portion 42 in the first redistribution layer second portion 212;

[0110] The first bonding portion 41 and the second bonding portion 42 are bonded to each other, so that the first redistribution layer first portion 211 and the first redistribution layer second portion 212 are fixedly connected and conductive.

[0111] The first chip 101 and the second chip 102 are fixed by the first redistribution layer 21, and the method of bumping or bonding can be adopted. In comparison, the height of the bonding part adopted by the bonding method is much lower than that of the bumping. Therefore, the thickness of the overall structure can be reduced by adopting the bonding method.

[0112] Similarly, refer to Figure 2 The step of fixing and connecting the first part 221 of the second re-wiring layer and the second part 222 of the second re-wiring layer may also include preparing a bonding part 4 on the first part 221 of the second re-wiring layer and the second part 222 of the second re-wiring layer, respectively, and then bonding the two bonding parts 4 to form the second re-wiring layer 22, and fixing the second chip 102 and the third chip 103.

[0113] Reference Figure 2 In some embodiments, the first chip 101 and the second chip 102 include a passive layer 11 and an active layer 12 respectively, and the manufacturing method further includes:

[0114] The passive layer 11 of the first chip 101 is electrically connected to the active layer 12 of the second chip 102 .

[0115] Reference Figure 2In some embodiments, the manufacturing method further comprises:

[0116] A third redistribution layer 23 is formed on one side of the active layer 12 of the first chip 101;

[0117] A plurality of solder balls 5 are formed on the third redistribution layer 23 .

[0118] The formed multiple solder balls 5 can be used for connecting a multi-chip stack package with other substrates or circuit boards.

[0119] In some embodiments, reference Figure 2 Before the step of fixing and connecting the first re-wiring layer first portion 211 and the first re-wiring layer second portion 212, the manufacturing method further includes:

[0120] A third rewiring layer 23 is prepared on a surface of the first chip 101 which is away from the first part 211 of the first rewiring layer, and the first conductive via 31 is connected to the third rewiring layer 23;

[0121] The wafer carrier layer 6 is bonded to the outer side of the third redistribution layer 23 of the first chip 101 .

[0122] When the first chip 101 and the second chip 102 are fixed, since the chip 1 is relatively thin and is not easy to grasp and prepare during production and preparation, a wafer carrier layer 6 can be bonded to the outside of the rewiring layer 2 of the chip 1. The wafer carrier layer 6 is used to carry the chip 1. By clamping and fixing the wafer carrier layer 6, the chip 1 can be smoothly produced and the specific structure prepared (for example, preparing the rewiring layer 2, the conductive through-hole 3 and the grinding chip 1, etc.). After the preparation is completed, the wafer carrier layer 6 can be retained or removed (it can be removed by grinding or hot melting, etc.).

[0123] It should be noted that the bonding method between multiple chips 1 is hybrid bonding. During the chip manufacturing process, due to the thin thickness of the chip 1, a carrier needs to be temporarily bonded to facilitate the manufacture of the structure on the chip 1. The carrier can be called a wafer carrier layer 6. The wafer carrier layer 6 can be bonded to the corresponding chip by silicon fusion bonding, and finally the wafer carrier layer 6 can be removed by grinding; or, the wafer carrier layer 6 can be bonded to the corresponding chip by temporary bonding (using bonding glue, with a bonding film layer), and finally the wafer carrier layer 6 can be removed by hot melting.

[0124] The manufacturing method of the embodiment of the present application, when manufacturing a multi-chip stack package, has multiple implementation methods for the preparation between the specific multiple chips 1, and for example, there may be the following specific steps:

[0125] In a first specific embodiment, when manufacturing a multi-chip stack package, a wafer carrier layer 6 may be temporarily bonded to the bottom chip 1, and the chips 1 of other layers are sequentially stacked and bonded to the chip 1. Specifically, the chip 1 includes at least one chip 1 located in the middle layer and two chips 1 located in the edge layer, and each chip 1 includes a passive layer 11 and an active layer 12 fixed together. The method includes:

[0126] Bonding a wafer carrier layer 6 to the outer side of the active layer 12 of the first chip 1 located at the edge layer;

[0127] A conductive through hole 3 is opened on the first chip 1 located at the edge layer, and the passive layer 11 of the first chip 1 located at the edge layer is bonded to the active layer 12 of the chip 1 located at the middle layer;

[0128] A conductive through hole 3 is provided on the passive layer 11 of the chip 1 located in the middle layer, and the passive layer 11 of the chip 1 located in the middle layer is bonded to the active layer 12 of the second chip 1 located in the edge layer;

[0129] The wafer carrier layer 6 of the first chip 1 located at the edge layer is removed, and the solder ball 5 is prepared. It should be noted that in the first specific embodiment, the wafer carrier layer 6 can be bonded and then the conductive via 3 can be made; or the conductive via 3 can be made first and then the wafer carrier layer 6 can be bonded. In addition, the bonded wafer carrier layer 6 can be bonded to the corresponding chip by fusion bonding, and finally the wafer carrier layer 6 can be removed by grinding; or, the wafer carrier layer 6 can be bonded to the corresponding chip by temporary bonding (using bonding glue, with a bonding film layer), and finally the wafer carrier layer 6 can be removed by hot melting.

[0130] Taking four chips 1 as an example, the four chips 1 are respectively a first chip 101, a second chip 102, a third chip 103 and a fourth chip 104, the manufacturing steps are specifically described:

[0131] like Figure 5 As shown, a third rewiring layer 23 is prepared on the outside of the active layer 12 of the first chip 101, and a wafer carrier layer 6 is bonded on the outside of the third rewiring layer 23;

[0132] like Figure 6 As shown, a first conductive via 3 is opened from the outside of the passive layer 11 of the first chip 101, a first redistribution layer first portion 211 is prepared on the outside of the passive layer 11 of the first chip 101, and a first bonding portion 41 is prepared in the first redistribution layer first portion 211;

[0133] Prepare a first redistribution layer second portion 212 on the outer side of the active layer 12 of the second chip 102, and prepare a second bonding portion 42 in the first redistribution layer second portion 212;

[0134] like Figure 7 and Figure 8 As shown, the first bonding portion 41 on the outer side of the passive layer 11 of the first chip 101 is bonded to the second bonding portion 42 on the outer side of the active layer 12 of the second chip 102;

[0135] Repeat the above steps, refer to Fig. 9 , bonding the second chip 102 and the third chip 103;

[0136] Repeat the above steps, refer to Fig. 9 , bonding the third chip 103 and the fourth chip 104;

[0137] Finally, refer to Figure 2 , remove the wafer carrier layer 6 outside the third redistribution layer 23 of the first chip 101 , and prepare solder balls 5 .

[0138] It should be noted that the wafer carrier layer 6 can be removed by grinding. In addition, the wafer carrier layer 6 can be retained, ground thin or completely removed as needed.

[0139] In the first specific embodiment, it is only necessary to temporarily bond a wafer carrier layer 6 to the bottom layer chip 1, and unlike the related art, it is not necessary to temporarily bond a carrier when each adjacent chip 1 is connected. Comparatively speaking, the manufacturing method is simple.

[0140] In a second specific embodiment, when manufacturing a plurality of chip stacking structures, when two adjacent layers of chips 1 are bonded, a wafer carrier layer 6 is temporarily bonded to one of them, and necessary rewiring layers 2 and conductive vias 3 are prepared, and then the wafer carrier layer 6 is debonded and removed, and two adjacent chips 1 are bonded, and so on, until all chips are stacked. Specifically, the chip 1 includes at least one chip 1 located in the middle layer and two chips 1 located in the edge layer, and each chip 1 includes a passive layer 11 and an active layer 12 fixed together, and the method includes:

[0141] A conductive through hole 3 is opened on the chip 1 located in the middle layer, and a wafer carrier layer 6 is bonded to the outer side of the active layer 12 of the chip 1 located in the middle layer;

[0142] Bonding the active layer 12 of the first chip 1 located at the edge layer and the passive layer 11 of the chip 1 located at the middle layer;

[0143] Debonding the wafer carrier layer 6 outside the active layer 12 of the chip 1 located in the middle layer;

[0144] A conductive through hole 3 is opened on the second chip 1 located at the edge layer, and a wafer carrier layer 6 is bonded to the outer side of the active layer 12 of the second chip 1 located at the edge layer;

[0145] Bonding the active layer 12 of the chip 1 located in the middle layer and the passive layer 11 of the second chip 1 located in the edge layer;

[0146] The wafer carrier layer 6 outside the active layer 11 of the second chip 1 located in the edge layer is debonded and solder balls are prepared.

[0147] Taking four chips 1 as an example, the four chips 1 are respectively a first chip 101, a second chip 102, a third chip 103 and a fourth chip 104, the manufacturing steps are specifically described:

[0148] like Fig.10 As shown, a first redistribution layer first portion 211 is prepared on the outer side of the active layer 12 of the first chip 101, and a first bonding portion 41 is prepared in the first redistribution layer first portion 211;

[0149] like Fig.11 As shown, a second conductive through hole 32 is opened from the active layer 12 of the second chip 102 without penetrating the passive layer 11, and a portion of the second rewiring layer 22 is prepared on the outer side of the active layer 12 of the second chip 102; the second rewiring layer 22 is temporarily bonded to the wafer carrier layer 6; the second rewiring layer 22 is temporarily bonded to the wafer carrier layer 6, and the bonding connection can be carried out by fusion bonding, refer to Fig.11 A bonding film layer (film) 7 is provided between the second rewiring layer 22 and the wafer carrier layer 6, and the second rewiring layer 22 and the wafer carrier layer 6 are bonded together through the bonding film layer 7;

[0150] Next, the outer side of the passive layer 11 of the second chip 102 is processed to expose the conductive via 3 of the second chip 102; the BVR process, i.e., Back side via reveal, is used this time to thin the target wafer and expose the copper in the TSV to connect with the back RDL prepared later. The process includes silicon grinding, silicon chemical mechanical polishing, silicon dry etching, insulating layer chemical vapor deposition, and chemical mechanical polishing of the insulating layer and copper;

[0151] Then, if Fig.12 As shown, a first redistribution layer second portion 212 is prepared outside the passive layer 11 of the second chip 102, and a second bonding portion 42 is prepared inside the first redistribution layer second portion 212;

[0152] Bonding the first bonding portion 41 on the outer side of the active layer 12 of the first chip 101 and the second bonding portion 42 on the outer side of the passive layer 11 of the second chip 102;

[0153] Then, the wafer carrier layer 6 outside the active layer 12 of the second chip 102 is debonded, and a bonding portion 4 (here, the bonding portion 4 to be bonded to the third chip 103 ) is prepared;

[0154] Similar to the bonding process of the first chip 101 and the second chip 102, the second chip 102 and the third chip, and the third chip and the fourth chip are bonded in sequence. Fig.13 As shown, finally, the wafer carrier layer 6 on the outer side 12 of the active layer of the fourth chip 104 is debonded, and a rewiring layer 2 is prepared, and solder balls 5 are prepared on the outer side of the rewiring layer 2 to complete the multi-chip stacking package. It should be noted that the wafer carrier layer 6 can be retained, thinned or completely removed as needed.

[0155] In a third specific embodiment, the chip 1 includes a first chip 101, a second chip 102, a third chip 103, a fourth chip 104 and a fifth chip 105, and the method includes the following steps:

[0156] Bonding a first wafer carrier layer 61 on the outer side of the active layer 12 of the first chip 101;

[0157] A first conductive through hole 31 is formed on the first chip 101;

[0158] Bonding the passive layer 11 of the first chip 101 to the active layer 12 of the second chip 102;

[0159] Opening a second conductive via 32 on the second chip 102;

[0160] Bonding a second wafer carrier layer 62 to the outer side of the active layer 12 of the third chip 103;

[0161] A third conductive through hole 33 is formed on the third chip 103;

[0162] Bonding the passive layer 11 of the third chip 103 to the active layer 12 of the fourth chip 104;

[0163] The second wafer carrier layer 62 on the active layer 12 side of the third chip 103 is removed, and the third wafer carrier layer 63 is bonded on the passive layer 11 side of the fourth chip 104;

[0164] Bonding the passive layer 11 of the second chip 102 to the active layer 12 of the third chip 103;

[0165] Debonding the third wafer carrier layer 63 on one side of the passive layer 11 of the fourth chip 104;

[0166] The first wafer carrier layer 61 on the active layer 12 side of the first chip 101 is debonded and solder balls are prepared.

[0167] The detailed steps are as follows:

[0168] like Fig.14 As shown, a third rewiring layer 23 is prepared on the outside of the active layer 12 of the first chip 101, and a first wafer carrier layer 61 is bonded on the outside of the third rewiring layer 23;

[0169] A first conductive via 31 is opened from one side of the passive layer 11 of the first chip 101, and a first redistribution layer first portion 211 is prepared, and a first bonding portion 41 is prepared in the first redistribution layer first portion 211;

[0170] Prepare a first redistribution layer second portion 212 outside the active layer 12 of the second chip 102, and prepare a second bonding portion 42 on the first redistribution layer second portion 212;

[0171] like Fig.15 As shown, the first bonding portion 41 on the passive layer 11 side of the first chip 101 is bonded to the second bonding portion 42 on the active layer 12 side of the second chip 102; Fig.16 As shown, similar to the bonding process of the first chip 101 and the second chip 102, the third chip 103 and the fourth chip 104 are bonded and connected, wherein the second wafer carrier layer 62 is bonded to the outer side of the active layer 12 of the third chip 103;

[0172] At this time, in the structure after the first chip 101 and the second chip 102 are bonded, the first wafer carrier layer 61 is at the bottom, and in the structure after the third chip 103 and the fourth chip 104 are bonded, the second wafer carrier layer 62 is also at the bottom. The second wafer carrier layer 62 needs to be removed before the four chips 1 can be bonded together. During the operation, the structure after the third chip 103 and the fourth chip 104 are bonded needs to be clamped and placed above the second chip 102 for bonding. Since the thickness of the chip 1 is very thin, the structure after the third chip 103 and the fourth chip 104 are bonded has only two layers, which cannot be clamped and is difficult to operate. Therefore, after removing the second wafer carrier layer 62, it is necessary to bond a third wafer carrier layer 63 on the other side of the structure to serve as a carrier for clamping, that is, as shown in FIG. Fig.17 As shown, the second wafer carrier layer 62 on the active layer 12 side of the third chip 103 is removed, and the third wafer carrier layer 63 is bonded on the passive layer 11 side of the fourth chip 104;

[0173] Then, if Fig.18As shown, the bonding portion 4 on the passive layer 11 side of the second chip 102 is bonded to the bonding portion 4 on the active layer 12 side of the third chip 103; then, the third wafer carrier layer 63 on the passive layer 11 side of the fourth chip 104 is debonded, and the stacking of the first chip 101, the second chip 102, the third chip 103 and the fourth chip 104 is completed;

[0174] Next, prepare to bond the fifth chip 105 to the fourth chip 104, open a conductive through hole 3 from the passive layer 11 side of the fourth chip 104, prepare a rewiring layer 2, and prepare a bonding portion 4 on the rewiring layer 2; prepare a rewiring layer 2 and a bonding portion 4 on the active layer 12 of the fifth chip 105;

[0175] like Fig.19 As shown, the bonding portion 4 on the passive layer 11 side of the fourth chip 104 is bonded to the bonding portion 4 on the active layer 12 side of the fifth chip 105;

[0176] Finally, the first wafer carrier layer 61 on the active layer 12 side of the first chip 101 is debonded; and solder balls 5 are prepared outside the redistribution layer 2 on the active layer 12 side of the first chip 101 .

[0177] It should be noted that the above scheme is to first bond the first chip 101 and the second chip 102 to form an accessory, then bond the third chip 103 and the fourth chip 104 to form an accessory, then bond the first chip 101, the second chip 102, the third chip 103 and the fourth chip 104 together, and finally bond the fifth chip 105. There may also be other ways, for example, first bond the first chip 101 and the second chip 102 to form an accessory, then bond the third chip 103 and the fourth chip 104 to form an accessory, then bond the fifth chip 105 to the third chip 103 and the fourth chip 104 to form an accessory, and finally bond all the chips 1 together to complete the stacking process.

[0178] Specifically, the first chip 101 and the second chip 102 are bonded, and the third chip 103 and the fourth chip 104 are bonded, which is consistent with the above solution. Fig.14 , Fig.15 and Fig.16 , then, including the following steps: refer to Fig. 20 , a conductive through hole 3 is opened from one side of the passive layer 11 of the fourth chip 104, and a rewiring layer 2 is prepared, and a bonding portion 4 is prepared on the rewiring layer 2; a rewiring layer 2 and a bonding portion 4 are prepared on the active layer 12 of the fifth chip 105; the bonding portion 4 on one side of the passive layer 11 of the fourth chip 104 is bonded to the bonding portion 4 on one side of the active layer 12 of the fifth chip 105;

[0179] Finally, refer to Fig.19, debonding the first wafer carrier layer 61 on the active layer 12 side of the first chip 101 ; and preparing solder balls 5 outside the redistribution layer 2 on the active layer 12 side of the first chip 101 .

[0180] It should be noted that in the process of bonding the fifth chip 105 to the third chip 103 and the fourth chip 104 to form an accessory, there is no need to temporarily re-bond the third wafer carrier layer 63 as in the above implementation method. It is only necessary to directly remove the second wafer carrier layer 62. This is because the accessory formed by the fifth chip 105 being bonded to the third chip 103 and the fourth chip 104 is a three-layer chip 1 structure. In actual production, its thickness is sufficient to support the clamping operation.

[0181] In the third specific embodiment, corresponding to the chip 1 stacking structure with more than four layers, the 2+3 parallel process implementation process can reduce the number of thermal process experiences, reduce the size of the chip being ground off, and increase the number of effective wafers.

[0182] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A multi-chip stack package, characterized in that: include: A first chip and a second chip stacked along a first direction, the first chip and the second chip respectively comprising a passive layer and an active layer, wherein a first conductive through hole is opened in the first chip along the first direction, a second conductive through hole is opened in the second chip along the first direction, the first conductive through hole penetrates the passive layer and the active layer of the first chip, and the second conductive through hole penetrates the passive layer and the active layer of the second chip; A first rewiring layer is arranged between the first chip and the second chip, and two sides of the first rewiring layer are respectively fixed to the surface of the first chip and the surface of the second chip, wherein the first conductive via and the second conductive via are connected through the first rewiring layer, and the first conductive via and the second conductive via are staggered; a plurality of first conductive vias are arranged in the first chip, and the plurality of first conductive vias are evenly spaced; a plurality of second conductive vias are arranged in the second chip, and the plurality of second conductive vias are evenly spaced.

2. The multi-chip stack package according to claim 1, wherein: It also includes a third chip, wherein the first chip, the second chip and the third chip are stacked in sequence along the first direction, a third conductive via is opened in the third chip along the first direction, a second redistribution layer is provided between the second chip and the third chip, and two sides of the second redistribution layer are respectively fixed to the surface of the second chip and the surface of the third chip, the second conductive via and the third conductive via are connected through the second redistribution layer, and the second conductive via and the third conductive via are staggered.

3. The multi-chip stack package according to claim 2, wherein: The first conductive via and the third conductive via are staggered.

4. The multi-chip stack package according to claim 1, wherein: The first redistribution layer is made of soft material.

5. The multi-chip stack package according to claim 1 or 2, characterized in that: The first rewiring layer includes a first rewiring layer first part arranged on the side of the first chip facing the second chip, and a first rewiring layer second part arranged on the side of the second chip facing the first chip, a first bonding portion is arranged in the first rewiring layer first part, a second bonding portion is arranged in the first rewiring layer second part, and the first rewiring layer first part and the first rewiring layer second part are bonded through the first bonding portion and the second bonding portion.

6. The multi-chip stack package according to claim 5, characterized in that: The first bonding portion is a plurality of first bonding portions, and the second bonding portion is a plurality of second bonding portions, and the plurality of first bonding portions and the plurality of second bonding portions are arranged in a one-to-one correspondence.

7. The multi-chip stack package according to claim 1 or 2, characterized in that: The passive layer of the first chip and the active layer of the second chip are electrically connected through the first redistribution layer.

8. The multi-chip stack package according to claim 7, wherein: It also includes a third rewiring layer disposed on one side of the active layer of the first chip, and the third rewiring layer is connected to other substrates or circuit boards through a plurality of solder balls.

9. A method for manufacturing a multi-chip stack package, characterized in that: include: A first conductive through hole is opened along a first direction on a first chip, and a first portion of a first rewiring layer is prepared on a surface of one side of the first chip, and the first conductive through hole is connected and conducted with the first portion of the first rewiring layer; wherein the first chip comprises a passive layer and an active layer, and the first conductive through hole penetrates the passive layer and the active layer of the first chip; A second conductive through hole is opened on the second chip along the first direction, and a second part of the first rewiring layer is prepared on a side surface of the second chip, and the second conductive through hole is connected and conducted with the second part of the first rewiring layer; wherein the second chip comprises a passive layer and an active layer, and the first conductive through hole penetrates the passive layer and the active layer of the second chip; The first portion of the first rewiring layer and the second portion of the first rewiring layer are fixedly connected and conducted, so that a first rewiring layer is formed between the first chip and the second chip, the first chip and the second chip are fixed, and the first conductive via and the second conductive via are staggered; The first chip is provided with a plurality of first conductive through holes, which are evenly spaced apart; the second chip is provided with a plurality of second conductive through holes, which are evenly spaced apart.

10. The manufacturing method according to claim 9, characterized in that: Also includes: A first portion of a second rewiring layer is prepared on a surface of the second chip which is away from the first chip, and the second conductive via is connected to the first portion of the second rewiring layer; A third conductive through hole is opened on the third chip along the first direction, and a second portion of a second redistribution layer is prepared on a surface of one side of the third chip, and the third conductive through hole is connected and conducted with the second portion of the second redistribution layer; The first part of the first rewiring layer and the second part of the first rewiring layer are fixedly connected and conducted to form a second rewiring layer between the second chip and the third chip, the second chip and the third chip are fixed, and the second conductive via and the third conductive via are staggered.

11. The production method according to claim 9 or 10, characterized in that: The step of fixing and connecting the first portion of the first re-wiring layer and the second portion of the first re-wiring layer comprises: forming a first bonding portion in the first portion of the first redistribution layer; forming a second bonding portion in the first redistribution layer second portion; The first bonding portion and the second bonding portion are bonded to each other so that the first portion of the first re-wiring layer and the second portion of the first re-wiring layer are fixedly connected and conductive.

12. The production method according to claim 9 or 10, characterized in that: The production method further comprises: The passive layer of the first chip is electrically connected to the active layer of the second chip.

13. The manufacturing method according to claim 12, characterized in that: The production method further comprises: forming a third redistribution layer on one side of the active layer of the first chip; A plurality of solder balls are formed on the third redistribution layer.

14. The production method according to claim 9 or 10, characterized in that: Before the step of fixing and connecting the first portion of the first re-wiring layer and the second portion of the first re-wiring layer, the manufacturing method further includes: A third rewiring layer is prepared on a surface of the first chip on one side away from the first portion of the first rewiring layer, and the first conductive via is connected to the third rewiring layer; A wafer carrier layer is bonded outside the third redistribution layer of the first chip.

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