Semiconductor devices

Abstract

To prevent overheating of the power semiconductor components and errors in overcurrent detection notifications to the upper control device, a pulse generation circuit (40) generates a pulse when an input signal (IN) indicating the conduction of the power semiconductor components is received. A gate latch circuit (50) receives this pulse and maintains the overcurrent detection state of the overcurrent detection circuit (160). An overcurrent mode switching circuit (60) switches the signal (signal) generated by the oscillation signal generation circuit (30) when the input signal (IN) is received and the overcurrent detection state is in progress to either an inverted or non-inverted signal (signal0), and outputs a signal (signal1) obtained by inverting the signal (signal). In a timing determination circuit (70), a signal (output) that periodically turns on the power semiconductor components is output based on the signal (signal0) obtained by frequency division and the signal (signal1).

Description

Technical Field

[0001] The present invention relates to a semiconductor device having a power semiconductor element as a voltage-driven power control element and a circuit for driving and protecting the power semiconductor element. Background Technology

[0002] Automobiles are equipped with numerous semiconductor devices that control the switching of loads such as motors. Such automotive semiconductor devices utilize IPS (Intelligent Power Switches), which integrate the power semiconductor elements supplying the load and their control circuitry onto a single chip. Especially in automotive electrical applications, high-side IPS are typically used between the power source and the load, prioritizing safety during load maintenance.

[0003] In semiconductor products used in the automotive industry, a design that ensures no damage under any circumstances is required. In high-side IPS, if the load becomes overcurrent-prone, excessive current exceeding the normal operating current can potentially cause failure of power semiconductor components and surrounding circuitry.

[0004] A technique is proposed that, in the event of an overcurrent condition, controls the current by limiting it or adjusts the overcurrent detection threshold for limiting it (for example, see Patent Document 1). In particular, the overcurrent protection circuit of Patent Document 1 provides a technique that balances ensuring the instantaneous current during normal operation with overcurrent protection corresponding to the load.

[0005] Next, the specific operation of a typical high-side IPS and a high-side IPS when detecting an overcurrent condition will be described, although the overcurrent protection circuit differs from that in Patent Document 1. This typical high-side IPS is based on the configuration described in Non-Patent Document 1.

[0006] Figure 9 This diagram illustrates an example of the configuration of an existing IPS. Figure 10 This is a block diagram illustrating an example of the function of a logic circuit during overcurrent detection. Figure 11 This is a diagram illustrating an example of a timing-determining circuit. Figure 12 This is a timing diagram that determines the first action of the circuit at any given moment. Figure 12 (A) shows the detection of overcurrent during conduction. Figure 12 (B) shows the state when the overcurrent detection occurs before the conduction operation. Figure 13 This is the waveform of the first action when overcurrent is detected. Figure 13 (A) shows the detection of overcurrent during conduction. Figure 13 (B) indicates the state of overcurrent detection before the conduction operation. Figure 14 The timing diagram for the second action of the circuit is determined at a specific moment. Figure 14 (A) shows the detection of overcurrent during conduction. Figure 14 (B) indicates the state of overcurrent detection before the conduction operation. Figure 15 This is the waveform diagram of the second action example when overcurrent is detected. Figure 15 (A) shows the detection of overcurrent during conduction. Figure 15 (B) shows the state when in overcurrent detection before the conduction operation. It should be noted that, in Figure 9 In the description, the terminal name and the voltage, signal, etc. at that terminal are sometimes represented by the same symbol.

[0007] like Figure 9 As shown, the existing IPS100 includes a main MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) 110, logic circuitry 120, and drive circuitry 130. It should be noted that the main MOSFET 110 is sometimes configured as a circuit combining an IGBT (Insulated Gate Bipolar Transistor), which serves as a voltage-driven power control element, with a FWD (Free Wheeling Diode). The IPS100 also includes: a low-voltage detection circuit 140, a short-circuit detection circuit 150, an overcurrent detection circuit 160, an overheat detection circuit 170, an N-channel MOSFET 180, a constant current circuit 182, an operational amplifier 190, and gain setting resistors 191, 192, 193, and 194.

[0008] The IPS100 has the following terminals: IN, VCC, OUT, IN+, IN-, AMP, and GND. The IN and AMP terminals of the IPS100 are connected to a microcomputer 200, which acts as a host control device. The microcomputer 200 generates a signal to turn the main MOSFET 110 on / off based on the load current received from the AMP terminal of the IPS100 and supplies this signal to the IN terminal of the IPS100. In the illustrated example, the signal to turn on the main MOSFET 110 has a potential of 5 volts (V), and the signal to turn off the main MOSFET 110 has a potential of 0V.

[0009] The IN terminal of IPS100 is connected to the input terminal of logic circuit 120. The output terminal of logic circuit 120 is connected to the input terminal of drive circuit 130 with level shifting function. The output terminal of drive circuit 130 is connected to the gate terminal of main MOSFET 110. The drain terminal of main MOSFET 110 is connected to VCC terminal, which is connected to the positive terminal of power supply 210. The negative terminal of power supply 210 is connected to reference potential (GND). The source terminal of main MOSFET 110 is connected to OUT terminal, which is connected to one terminal of load 220. The other terminal of load 220 is connected to one terminal of shunt resistor 230, which is connected to reference potential. One terminal of shunt resistor 230 is also connected to the IN+ terminal of IPS100, and the other terminal is also connected to the IN- terminal. The GND terminal of IPS100 is connected to reference potential.

[0010] The VCC terminal of IPS100 is connected to the input terminal of low-voltage detection circuit 140, and the output terminal of low-voltage detection circuit 140 is connected to logic circuit 120. The VCC terminal of IPS100 is connected to one input terminal of short-circuit detection circuit 150, the other input terminal of short-circuit detection circuit 150 is connected to the OUT terminal, and the output terminal of short-circuit detection circuit 150 is connected to logic circuit 120. The VCC terminal of IPS100 is connected to the drain terminal of MOSFET180, and the gate terminal of MOSFET180 is connected to the output terminal of drive circuit 130. The source terminal of MOSFET180 is connected to one terminal of constant current circuit 182 and one input terminal of overcurrent detection circuit 160, the other input terminal of overcurrent detection circuit 160 is connected to the OUT terminal, and the output terminal of overcurrent detection circuit 160 is connected to logic circuit 120. The output terminal of overheat detection circuit 170 is connected to logic circuit 120. The IN+ terminal of IPS100 is connected to one terminal of gain setting resistor 191. The other terminal of gain setting resistor 191 is connected to one terminal of gain setting resistor 192 and the non-inverting input terminal of operational amplifier 190. The other terminal of gain setting resistor 192 is connected to the GND terminal. The IN- terminal of IPS100 is connected to one terminal of gain setting resistor 193. The other terminal of gain setting resistor 193 is connected to one terminal of gain setting resistor 194 and the inverting input terminal of operational amplifier 190. The output terminal of operational amplifier 190 is connected to the other terminal of gain setting resistor 194 and the AMP terminal of IPS100.

[0011] The low-voltage detection circuit 140 monitors whether the voltage VCC at the VCC terminal is above a predetermined voltage that enables the IPS100 to operate. If the voltage VCC is lower than the predetermined voltage, it notifies the logic circuit 120 of the abnormal drop in voltage VCC. When notified of the abnormal drop in voltage VCC, the logic circuit 120 outputs a signal to the drive circuit 130 to stop the operation of the main MOSFET 110 and MOSFET 180, so that the IPS100 does not perform abnormal operation.

[0012] When the main MOSFET 110 is turned on, the short-circuit detection circuit 150 detects a short circuit in the load 220 based on the voltage difference between the VCC terminal and the OUT terminal. Upon detecting a short circuit in the load 220, the short-circuit detection circuit 150 notifies the logic circuit 120. The logic circuit 120, upon receiving the notification, outputs a signal to the drive circuit 130 that lowers the gate voltages of the main MOSFET 110 and MOSFET 180.

[0013] The overcurrent detection circuit 160 allows a constant current to flow through the constant current circuit 182 when MOSFET 180 is turned on. Overcurrent is detected based on the potential difference caused by the on-resistance of the main MOSFETs 110 and 180 when they are turned on. Upon detecting an overcurrent condition in the load 220, the overcurrent detection circuit 160 notifies the logic circuit 120. Upon being notified of the overcurrent condition in the load 220, the logic circuit 120 stops the operation of the main MOSFETs 110 and 180 and controls them to periodically turn on only for short periods. This control of periodically turning on the main MOSFETs 110 and 180 only for short periods is used to detect whether the load 220 returns to its normal state after an overcurrent is detected. During this operation, the logic circuit 120 outputs a signal to stop the operation of the main MOSFETs 110 and 180. It should be noted that the threshold for the load current that the overcurrent detection circuit 160 determines as an overcurrent is lower than the threshold for the load current that the short-circuit detection circuit 150 determines as a short circuit.

[0014] The overheat detection circuit 170 detects the temperature of the main MOSFET 110 or IPS 100. If the temperature of the main MOSFET 110 or IPS 100 reaches a predetermined temperature, it notifies the logic circuit 120 of the overheat condition. When notified of the overheat condition, the logic circuit 120 outputs a signal to the drive circuit 130 to stop the operation of the main MOSFET 110 and MOSFET 180 in order to prevent IPS 100 from malfunctioning.

[0015] Operational amplifier 190 and gain-setting resistors 191, 192, 193, and 194 constitute a current detection circuit that detects the value of the current flowing through load 220 and notifies the microcomputer 200 of it. The current flowing through load 220 is converted into a voltage through shunt resistor 230, and operational amplifier 190 amplifies this voltage and supplies it to the AMP terminal. The gain of operational amplifier 190 is then set by gain-setting resistors 191, 192, 193, and 194.

[0016] like Figure 10 As shown in the overcurrent detection function, the logic circuit 120 includes an input circuit 121, an oscillation signal generation circuit 122, and a timing determination circuit 123. The input circuit 121 receives the input signal IN received at the IN terminal, which turns the main MOSFET 110 on / off. The output terminal of the input circuit 121 is connected to the first input terminal of the oscillation signal generation circuit 122, and the second input terminal of the oscillation signal generation circuit 122 is connected to the output terminal of the overcurrent detection circuit 160. The output terminal of the oscillation signal generation circuit 122 is connected to the input terminal of the timing determination circuit 123.

[0017] Input circuit 121 shapes the waveform of the received input signal IN and supplies it to oscillation signal generation circuit 122. When input circuit 121 is receiving the input signal IN that turns on the main MOSFET 110, oscillation signal generation circuit 122 receives an overcurrent detection signal from overcurrent detection circuit 160, generates an oscillation signal signal1 and provides this generated signal1 to timing determination circuit 123. Alternatively, when oscillation signal generation circuit 122 is receiving an overcurrent detection signal from overcurrent detection circuit 160, and input circuit 121 receives the input signal IN that turns on the main MOSFET 110, it generates an oscillation signal signal1 and provides this generated signal1 to timing determination circuit 123. Timing determination circuit 123 outputs a signal output based on signal1, which determines the timing at which the main MOSFET 110 is periodically turned on only for a short period of time.

[0018] like Figure 11As shown, the timing determination circuit 123 includes T flip-flops TFF1, TFF2, and TFF3, NOR circuits NOR1 and NOR2, and NAND circuit NAND1. The input terminals of the timing determination circuit 123 receiving the signal signal1 are connected to the input terminals of T flip-flops TFF1 and one input terminal of the NOR circuit NOR1. The output terminal of T flip-flops TFF1 is connected to the input terminals of T flip-flops TFF2 and the other input terminal of the NOR circuit NOR1. The output terminal of T flip-flops TFF2 is connected to the input terminals of T flip-flops TFF3 and one input terminal of the NOR circuit NOR2. The output terminal of T flip-flops TFF3 is connected to the other input terminal of the NOR circuit NOR2. The output terminal of the NOR circuit NOR1 is connected to one input terminal of the NAND circuit NAND1, and the output terminal of the NOR circuit NOR2 is connected to the other input terminal of the NAND circuit NAND1. The output terminal of the NAND circuit NAND1 constitutes the output terminal of the timing determination circuit 123.

[0019] When the timing circuit 123 receives signal1 from the oscillation signal generation circuit 122, it sequentially divides signal1 by a down-counting circuit composed of three T flip-flops TFF1, TFF2, and TFF3. Specifically, TFF1 outputs signal2, which doubles the period of signal1; TFF2 outputs signal3, which doubles the period of signal2; and TFF3 outputs signal4, which doubles the period of signal3. The NOR circuit NOR1 receives signals1 and signal2, and outputs a high (H) level signal when both are low (L) levels. The NOR circuit NOR2 receives signals3 and signal4, and outputs an H level signal when both are low (L) levels. The NAND circuit NAND1 outputs a low (L) level signal only when it receives an H level signal from the NOR circuits NOR1 and NOR2. Therefore, the timing determination circuit 123 has the function of outputting an L-level signal output when all signals signal1, signal2, signal3, and signal4 are at L level. During the period when overcurrent is detected, this L-level signal output is logically inverted when it is input to the drive circuit 130, becoming a signal that causes the main MOSFET 110 to be periodically turned on only for a short time.

[0020] The timing determination circuit 123 described above operates based on the signal signal1 supplied from the oscillation signal generation circuit 122. However, the generation time of the signal signal1 sometimes varies depending on the overcurrent detection signal or the input signal IN from the overcurrent detection circuit 160. That is, the oscillation signal generation circuit 122 may set the signal signal1 to rise synchronously with the overcurrent detection signal or the input signal IN (first operation example) or set the signal signal1 to rise with a delay of half a cycle from the input of the overcurrent detection signal or the input signal IN (second operation example). First, the operation of the timing determination circuit 123 and the IPS 100 in the first operation example will be explained.

[0021] Figure 12 (A) and Figure 13 (A) shows the case where the overcurrent detection time of the overcurrent detection circuit 160 is the input signal IN. It should be noted that in... Figure 12 In (A), from top to bottom, the input signal IN, the overcurrent detection state of the overcurrent detection circuit 160, signals signal1, signal2, signal3, signal4, and the output signal of the timing determination circuit 123 are shown respectively. Figure 13 (A) shows, from top to bottom, the input signal IN, the output signal OUT of the OUT terminal, the load current IL, and the signal AMP of the AMP terminal.

[0022] First, such as Figure 12 As shown in (A), when the main MOSFET 110 is turned on by an input signal IN at level H, the overcurrent detection circuit 160 has not yet detected an overcurrent state, and therefore outputs a signal at level L. At this time, the oscillation signal generation circuit 122 outputs a signal at level L, signal1, and the T flip-flops TFF1, TFF2, and TFF3 of the constant determination circuit 123 are in the reset state, and therefore output signals at level L, signal2, signal3, and signal4. Therefore, the constant determination circuit 123 outputs a signal at level L, and the drive circuit 130 maintains the output of the signal that turns on the main MOSFET 110.

[0023] When the main MOSFET110 is turned on, such as Figure 13 As shown in (A), the output signal OUT is output at the OUT terminal. This initiates the flow of load current IL through the load 220, and the signal AMP at the AMP terminal becomes a signal waveform corresponding to the load current IL.

[0024] Next, during the conduction of the main MOSFET 110, if the overcurrent detection circuit 160 detects an overcurrent condition and outputs an H-level overcurrent detection signal, the oscillation signal generation circuit 122 outputs a signal signal1 that rises synchronously with the rise of the H-level signal. In the timing determination circuit 123, due to the input of the H-level signal signal1, the other signals signal2, signal3, and signal4 also become H-level. Thus, the timing determination circuit 123 outputs an H-level signal output.

[0025] If the overcurrent detection circuit 160 detects an overcurrent, then as follows Figure 13 As shown in (A), the main MOSFET 110 is turned off, therefore, the output signal OUT at the OUT terminal drops to approximately 0V. Consequently, the load current IL flowing through the load 220 decreases, and the signal AMP at the AMP terminal also decreases accordingly. At this time, the load current IL does not decrease immediately, therefore the signal AMP at the AMP terminal also decreases to approximately 0V with a delay compared to the overcurrent detection. Therefore, the microcomputer 200 will know that the overcurrent detection circuit 160 has detected an overcurrent with a delay compared to the actual overcurrent detection.

[0026] If the overcurrent detection circuit 160 detects an overcurrent, the oscillation signal generation circuit 122 and the timing determination circuit 123 will operate to periodically output a signal. That is, as... Figure 12 As shown in (A), signal signal1 is sequentially frequency-divided. During the effective output range where all signals signal1, signal2, signal3, and signal4 are at low level, signal output becomes low level. Whenever this low-level signal is output, main MOSFET 110 is turned on, thus outputting the output signal OUT at the OUT terminal, during which load current IL flows. Therefore, IPS 100 periodically checks whether the state of load 220 returns to normal after overcurrent detection.

[0027] exist Figure 13 In the example shown in (A), the overcurrent condition of load 220 has been resolved when the third output signal has been output since the overcurrent detection. In this case, normal power is resumed to load 220. At this time, after the overcurrent recovery delay, a signal AMP of the magnitude corresponding to the load current IL is output at the AMP terminal.

[0028] Finally, if the input signal IN becomes low, the main MOSFET 110 turns off, and therefore the output signal OUT at the OUT terminal drops to approximately 0V. Consequently, the load current IL of the load 220 begins to decrease, and the signal AMP at the AMP terminal also begins to decrease.

[0029] Next, according to Figure 12 (B) and Figure 13 Section (B) explains the case where the overcurrent detection time of the overcurrent detection circuit 160 is before the input signal IN. It should be noted that... Figure 12 In (B), from top to bottom, the input signal IN, the overcurrent detection status of the overcurrent detection circuit 160, signals signal1, signal2, signal3, signal4, and the output signal of the timing determination circuit 123 are shown respectively. Figure 13 (B) shows, from top to bottom, the input signal IN, the output signal OUT of the OUT terminal, the load current IL, and the signal AMP of the AMP terminal.

[0030] If an H-level input signal IN is received while the output is in a state of overcurrent detection, the oscillation signal generation circuit 122 outputs a signal signal1 that rises at the moment the input signal IN is received. After outputting the H-level signal signal1, the timing determination circuit 123 performs... Figure 12 The same action as in case (A).

[0031] If an input signal IN of level H is received while an overcurrent is detected, then as follows: Figure 13 As shown in (B), firstly, the main MOSFET 110 is turned on, outputting the output signal OUT at the OUT terminal. At this time, the load current IL begins to flow through the load 220, and the signal AMP at the AMP terminal also outputs a signal AMP of the magnitude corresponding to the load current IL.

[0032] Upon receiving the H-level input signal IN, the system is already in overcurrent detection mode. Therefore, immediately after this moment, the main MOSFET 110 turns off, and the output signal OUT at the OUT terminal drops to approximately 0V. Following this, the load current IL immediately decreases, and the signal AMP at the AMP terminal also immediately decreases. When the signal AMP drops to approximately 0V, the microcomputer 200 learns, with a delay compared to the moment the H-level input signal IN was received, that the overcurrent detection circuit 160 has detected an overcurrent.

[0033] During the subsequent reception of the H-level input signal IN, a periodic signal output is used to check whether the overcurrent state of load 220 has returned to normal, and the operation after the overcurrent of load 220 is released is also included. Figure 13 The situation is the same as shown in (A).

[0034] Next, the operation of the timing determination circuit 123 and IPS100 in the second operation example where the oscillation signal generation circuit 122 sets the signal signal1 to rise for half a cycle after the overcurrent detection or the input signal IN will be explained.

[0035] Figure 14 (A) and Figure 15 (A) shows the case where the overcurrent detection time of the overcurrent detection circuit 160 is the input signal IN. It should be noted that in... Figure 14 In (A), from top to bottom, the input signal IN, the overcurrent detection state of the overcurrent detection circuit 160, signals signal1, signal2, signal3, signal4, and the output signal of the timing determination circuit 123 are shown respectively. Figure 15 (A) shows, from top to bottom, the input signal IN, the output signal OUT of the OUT terminal, the load current IL, and the signal AMP of the AMP terminal.

[0036] First, such as Figure 14 As shown in (A), when the main MOSFET 110 is turned on by an input signal IN of level H, the overcurrent detection circuit 160 has not yet detected an overcurrent state, and therefore outputs a signal of level L. At this time, the oscillation signal generation circuit 122 outputs a signal of level L signal1, the timing determination circuit 123 outputs a signal of level L output, and the drive circuit 130 outputs a signal to turn on the main MOSFET 110.

[0037] At this time, as Figure 15 As shown in (A), since the main MOSFET 110 is turned on, the output signal OUT is output at the OUT terminal. As a result, the load current IL begins to flow through the load 220, and the signal AMP at the AMP terminal becomes a signal waveform corresponding to the load current IL.

[0038] Next, if the overcurrent detection circuit 160 detects an overcurrent state and outputs an H-level overcurrent detection signal, the oscillation signal generation circuit 122 outputs a signal signal1 that rises with a half-cycle delay from the rise of the H-level overcurrent detection signal. After outputting the H-level signal signal1, the oscillation signal generation circuit performs... Figure 12 (A) and Figure 13The first action example shown in (A) is the same action.

[0039] Next, according to Figure 14 (B) and Figure 15 (B) explains the case where the overcurrent detection time of the overcurrent detection circuit 160 is before the input signal IN. It should be noted that in... Figure 14 In (B), from top to bottom, the input signal IN, the overcurrent detection status of the overcurrent detection circuit 160, signals signal1, signal2, signal3, signal4, and the output signal of the timing determination circuit 123 are shown respectively. Figure 15 (B) shows, from top to bottom, the input signal IN, the output signal OUT of the OUT terminal, the load current IL, and the signal AMP of the AMP terminal.

[0040] If an input signal IN at level H is received while the overcurrent detection signal is being output, the oscillation signal generation circuit 122 generates a signal signal1 starting at level L from the moment the input signal IN is received. Therefore, signal signal1 rises to level H after half a cycle. During the period prior to this, the signal output of the constant-time determination circuit 123 is valid, and the main MOSFET 110 is turned on. After signal signal1 first reaches level H, [further steps are taken]. Figure 14 (A) and Figure 15 The same action as in case (A).

[0041] It should be noted that, in Figure 12 and Figure 14 In the diagram, when the input signal IN is at level L, the signal output is shown as level H. This is achieved through a circuit (not shown) that makes the signal output level H when the input signal IN is at level L.

[0042] Existing technical documents

[0043] Patent documents

[0044] Patent Document 1: International Publication No. 2017 / 187785

[0045] Non-patent literature

[0046] Non-Patent Literature 1: Sho Nakagawa, Takashi Oe, and Motomitsu Iwamoto, “Single-Chip Linear Control IPS “F5106H””, Fuji Electric Technical Bulletin, December 30, 2013, Vol. 86, No. 4, pp. 43-46 Summary of the Invention

[0047] Technical issues

[0048] However, in the first example of operation, especially in the case where overcurrent is detected before the input signal IN is received, such as Figure 13 As shown in (B), the main MOSFET 110 immediately turns on and off after receiving the H-level input signal IN. Therefore, the signal AMP at the AMP terminal has a short width, so the microcomputer 200 receiving the AMP signal may not only fail to detect the load current IL caused by the indication of the main MOSFET 110's on-state operation, but also fail to know that an overcurrent has been detected. On the other hand, in the second operating example, if an overcurrent is detected after the input signal IN is received, such as... Figure 15 As shown in (A), there is a period during which current flows further from the state where the normal load current is flowing. Therefore, the main MOSFET 110 is prone to overheating, which may lead to failure.

[0049] The present invention was made in view of this, and its object is to provide a semiconductor device in which the main power semiconductor element is unlikely to become overheated and the overcurrent detection notification to the upper control device is error-free.

[0050] Technical solution

[0051] In order to solve the above-mentioned problems, one aspect of the present invention provides a semiconductor device comprising: a power semiconductor element, an overcurrent detection circuit, and a logic circuit having the function of outputting a turn-off signal to the power semiconductor element when an overcurrent is detected by the overcurrent detection circuit. The logic circuit of the semiconductor device includes a pulse generation circuit that generates and outputs a pulse when an input signal instructing the power semiconductor element to turn on is input. During the period of the output pulse, when an overcurrent is detected by the overcurrent detection circuit, a signal instructing the power semiconductor element to turn on is output during a predetermined period after the overcurrent is detected.

[0052] Technical effect

[0053] If the semiconductor device configured as described above detects an overcurrent while the power semiconductor element is conducting, it immediately shuts off the power semiconductor element, thus preventing the power semiconductor element from overheating. Furthermore, if an overcurrent is detected at least during the period of the pulse output by the pulse generation circuit, by outputting a conduction signal to the power semiconductor element for a predetermined period, the duration of the overcurrent detection notification to the upper control device can be sufficiently ensured, preventing notification errors.

[0054] The above and other objects, features and advantages of the present invention will become clear from the accompanying drawings, which illustrate preferred embodiments of the invention by way of example, and the following description in connection with them. Attached Figure Description

[0055] Figure 1 This is a block diagram illustrating an example of the configuration of the logic circuit of the high-side IPS of the present invention.

[0056] Figure 2 This is a circuit diagram showing an example of an input circuit and a pulse generation circuit.

[0057] Figure 3 This is a circuit diagram showing an example of a gated latch circuit.

[0058] Figure 4 This is a circuit diagram showing an example of an overcurrent mode switching circuit.

[0059] Figure 5 This is a circuit diagram illustrating an example of a timing-determining circuit.

[0060] Figure 6 This is a timing diagram showing the operation of the logic circuit when it enters the overcurrent detection state after receiving an input signal.

[0061] Figure 7 This is a timing diagram showing the operation of a logic circuit when it enters an overcurrent detection state before receiving an input signal.

[0062] Figure 8 This is a timing diagram showing the operation of the logic circuit when it enters an overcurrent detection state during the output pulse of the pulse generation circuit.

[0063] Figure 9 This is a diagram showing an example of the configuration of an existing IPS.

[0064] Figure 10 This is a block diagram illustrating an example of the function of a logic circuit during overcurrent detection.

[0065] Figure 11 This is a diagram illustrating an example of a timing-determining circuit.

[0066] Figure 12 This is a timing diagram that determines the first action of the circuit at any given moment. Figure 12 (A) shows a timing diagram of an example of determining the first operation of a circuit when an overcurrent is detected during conduction. Figure 12 (B) shows a timing diagram of an example of determining the first operation of the circuit when it is in the overcurrent detection state before the conduction operation.

[0067] Figure 13 This is the waveform of the first action when overcurrent is detected. Figure 13 (A) shows the waveform of the first action example when overcurrent is detected during the conduction operation. Figure 13 (B) shows the waveform of the first action example when the device is in the overcurrent detection state before the conduction action.

[0068] Figure 14 The timing diagram for the second action of the circuit is determined at a specific moment. Figure 14 (A) shows a timing diagram of an example of the second operation of the circuit that determines the moment when an overcurrent is detected during the conduction operation. Figure 14 (B) shows a timing diagram of the second operation example of the circuit that determines the timing of the overcurrent detection state before the conduction operation.

[0069] Figure 15 This is the waveform diagram of the second action example when overcurrent is detected. Figure 15 (A) shows a waveform diagram of a second operation example when overcurrent is detected during the conduction operation. Figure 15 (B) shows a waveform diagram of the second operation example when the device is in the overcurrent detection state before the conduction operation.

[0070] Symbol Explanation

[0071] 10: Logic Circuits

[0072] 20: Input Circuit

[0073] 21: Schmitt trigger circuit

[0074] 30: Oscillation signal generation circuit

[0075] 40: Pulse generation circuit

[0076] 41, 42, 43: MOSFET

[0077] 44: Capacitor

[0078] 50: Gate latch circuit

[0079] 60: Overcurrent mode switching circuit

[0080] 61, 62: Transmission Gate

[0081] 70: Timing Determining Circuit

[0082] 160: Overcurrent detection circuit

[0083] INV11, INV12, INV13, INV14, INV15, INV16, INV17: Inverting circuit

[0084] NAND11, NAND12, NAND13, NAND14, NAND15, NAND16, NAND17: NAND circuits

[0085] NOR11, NOR12: NOR circuit

[0086] TFF11, TFF12, TFF13: T flip-flops Detailed Implementation

[0087] The following description, using an application to a high-side IPS as an example, details the embodiments of the present invention with reference to the accompanying drawings. It should be noted that the basic structure of a high-side IPS is similar to... Figure 9 The basic structure described herein is the same; therefore, the description of other constituent elements besides the logic circuit, which is a characteristic part of this invention, is sometimes referred to... Figure 9 .

[0088] Figure 1 This is a block diagram illustrating an example of the configuration of the logic circuit of the high-side IPS of the present invention. Figure 2 This is a circuit diagram showing an example of an input circuit and a pulse generation circuit. Figure 3 This is a circuit diagram illustrating an example of a gated latch circuit. Figure 4 This is a circuit diagram illustrating an example of an overcurrent mode switching circuit. Figure 5 This is a circuit diagram illustrating an example of a timing-determining circuit. It should be noted that in the description of the accompanying drawings, the terminal names and the voltage, signal, etc., at those terminals sometimes use the same symbols.

[0089] like Figure 1 As shown, the logic circuit 10 of the high-side IPS of the present invention includes an input circuit 20, an oscillation signal generation circuit 30, a pulse generation circuit 40, a gate latch circuit 50, an overcurrent mode switching circuit 60, and a timing determination circuit 70.

[0090] The input terminals of input circuit 20 are connected to the IN terminal of the high-side IPS. The output terminals of input circuit 20 are connected to the first input terminal of oscillation signal generation circuit 30 and the input terminal of pulse generation circuit 40, respectively. The second input terminal of oscillation signal generation circuit 30 is connected to the output terminal of overcurrent detection circuit 160. The output terminal of pulse generation circuit 40 is connected to the enable terminal of gate latch circuit 50. Another input terminal of gate latch circuit 50 is connected to the output terminal of overcurrent detection circuit 160, and the output terminal of gate latch circuit 50 is connected to the input terminal for switching signal input of overcurrent mode switching circuit 60. In addition, the input terminal for oscillation signal input of overcurrent mode switching circuit 60 is connected to the output terminal of oscillation signal generation circuit 30. The output terminal of overcurrent mode switching circuit 60 is connected to the input terminal of timing determination circuit 70. Timing determination circuit 70 is configured to also receive the first overcurrent detection signal OCDS1 output by overcurrent detection circuit 160.

[0091] like Figure 2As shown, the input circuit 20 includes a non-inverting Schmitt trigger circuit 21. The input terminal of the Schmitt trigger circuit 21 is connected to the IN terminal of the high-side IPS, and the output terminal of the Schmitt trigger circuit 21 is connected to the input terminal of the pulse generation circuit 40. The input circuit 20 is capable of shaping the waveform of the noisy input signal IN supplied from the microcomputer 200.

[0092] The pulse generation circuit 40 includes inverting circuits INV11, INV12, and INV13, a NAND circuit NAND11, a P-channel MOSFET 41, N-channel MOSFETs 42 and 43, and a capacitor 44. It should be noted that MOSFET 42 is a depletion-mode MOSFET.

[0093] The input terminal of pulse generation circuit 40 is connected to the input terminal of inverter circuit INV11 and one input terminal of NAND circuit NAND11. The output terminal of inverter circuit INV11 is connected to the gate terminals of MOSFETs 41 and 43. The source terminal of MOSFET 41 is connected to the power supply line, and the source terminal of MOSFET 43 is connected to ground. The drain terminal of MOSFET 41 is connected to the drain terminal of MOSFET 42. The gate and source terminals of MOSFET 42 are connected to the drain terminal of MOSFET 43, one terminal of capacitor 44, and the input terminal of inverter circuit INV12. The other terminal of capacitor 44 is connected to ground. The output terminal of inverter circuit INV12 is connected to the other input terminal of NAND circuit NAND11, and the output terminal of NAND circuit NAND11 is connected to the input terminal of inverter circuit INV13. The output terminal of inverter circuit INV13 constitutes the output terminal of pulse generation circuit 40.

[0094] If the pulse generation circuit 40 receives an L-level input signal at its input terminal, the L-level input signal is inverted to an H-level signal by the inverter circuit INV11. As a result, an H-level gate voltage is applied to the gate terminals of MOSFETs 41 and 43, MOSFET 41 is turned off, and MOSFET 43 is turned on. Therefore, the charge of capacitor 44 is discharged through MOSFET 43. At this time, the inverter circuit INV12 outputs an H-level signal and applies it to another input terminal of the NAND circuit NAND11, where an L-level input signal is applied to one input terminal of the NAND circuit NAND11. Therefore, the NAND circuit NAND11 outputs an H-level signal, which is inverted to an L-level signal by the inverter circuit INV13 and supplied to the output terminal of the pulse generation circuit 40.

[0095] Furthermore, if the pulse generation circuit 40 receives an H-level input signal at its input terminals, this H-level input signal is inverted to an L-level signal by the inverter circuit INV11. Consequently, an L-level gate voltage is applied to the gate terminals of MOSFETs 41 and 43, turning MOSFET 41 on and turning off MOSFET 43. At this time, a constant current flows through the depletion-type MOSFET 42 when the gate-source voltage is 0V, charging capacitor 44. At the start of charging, the voltage of capacitor 44 has not reached the threshold voltage of the inverter circuit INV12; therefore, the inverter circuit INV12 outputs an H-level signal. Therefore, the NAND circuit NAND11 outputs an L-level signal because H-level signals are applied to both input terminals. This L-level signal is inverted to an H-level signal by the inverter circuit INV13 and supplied to the output terminal of the pulse generation circuit 40.

[0096] Subsequently, if the charging voltage of capacitor 44, which is charged by MOSFET 42 with a constant current, reaches the threshold voltage of inverter circuit INV12, inverter circuit INV12 outputs an L-level signal. Therefore, NAND circuit NAND11 outputs an H-level signal because its other input terminal becomes L-level. This H-level signal is inverted to L-level by inverter circuit INV13 and supplied to the output terminal of pulse generation circuit 40.

[0097] That is, when the pulse generation circuit 40 receives the input signal IN indicating the conduction of the main MOSFET 110 at the IN terminal, it generates and outputs a pulse of H level with a fixed duration determined by the depletion-type MOSFET 42, capacitor 44 and inverting circuit INV12.

[0098] like Figure 3As shown, the gated latch circuit 50 includes NAND12 and NAND13 forming gate circuits, and NAND14 and NAND15 forming latch circuits. One input terminal of NAND12 is connected to the set terminal S of the gated latch circuit 50, one input terminal of NAND13 is connected to the reset terminal R of the gated latch circuit 50, and the other input terminal of NAND12 and NAND13 is connected to the enable terminal E of the gated latch circuit 50. The output terminal of NAND12 is connected to one input terminal of NAND14, and the output terminal of NAND13 is connected to one input terminal of NAND15. The other input terminal of NAND14 is connected to the output terminal of NAND15, and the other input terminal of NAND15 is connected to the output terminal of NAND14. The output terminal of NAND14 is connected to the output terminal Q of the gate latch circuit 50, and the output terminal of NAND15 is connected to the inverted output terminal NQ of the gate latch circuit 50.

[0099] The first overcurrent detection signal OCDS1 of the overcurrent detection circuit 160 is input to the set terminal S of the gate latch circuit 50, and the second overcurrent detection signal OCDS2 of the overcurrent detection circuit 160 is input to the reset terminal R of the gate latch circuit 50. In this embodiment, the first overcurrent detection signal OCDS1 is a signal that becomes level H when the overcurrent detection circuit 160 detects an overcurrent, and the second overcurrent detection signal OCDS2 is a signal obtained by inverting the first overcurrent detection signal OCDS1. The enable terminal E of the gate latch circuit 50 is connected to the output terminal of the pulse generation circuit 40.

[0100] When the gated latch circuit 50 receives a high-level pulse from the pulse generation circuit 40 at the enable terminal E, it latches the first overcurrent detection signal OCDS1 at the set terminal S and the second overcurrent detection signal OCDS2 at the reset terminal R, maintaining the overcurrent detection state of the overcurrent detection circuit 160. When not in the overcurrent detection state, the overcurrent detection circuit 160 outputs the low-level first overcurrent detection signal OCDS1 and the high-level second overcurrent detection signal OCDS2. Furthermore, when in the overcurrent detection state, the overcurrent detection circuit 160 outputs the high-level first overcurrent detection signal OCDS1 and the low-level second overcurrent detection signal OCDS2.

[0101] When the gated latch circuit 50 receives a pulse of level H and is not in an overcurrent detection state, it maintains the first overcurrent detection signal OCDS1 of level L and outputs the first switching signal SWS1 of level L at the output terminal Q, and maintains the second overcurrent detection signal OCDS2 of level H and outputs the second switching signal SWS2 of level H at the inverting output terminal NQ. Conversely, when the gated latch circuit 50 receives a pulse of level H and is in an overcurrent detection state, it maintains the first overcurrent detection signal OCDS1 of level H and outputs the first switching signal SWS1 of level H at the output terminal Q, and maintains the second overcurrent detection signal OCDS2 of level L and outputs the second switching signal SWS2 of level L at the inverting output terminal NQ.

[0102] like Figure 4 As shown, the overcurrent mode switching circuit 60 includes inverting circuits INV14, INV15, and INV16, and transmission gates 61 and 62 constituting a switching circuit. The overcurrent mode switching circuit 60 has an input terminal for receiving a signal signal generated by the oscillation signal generation circuit 30, and input terminals for receiving a first switching signal SWS1 and a second switching signal SWS2 output by the gate latch circuit 50. The overcurrent mode switching circuit 60 also has output terminals for outputting signals signal0 and signal1 generated based on signal signal.

[0103] The input terminal of signal 'signal' is connected to the first terminal of transmission gate 61 and the input terminal of inverting circuit INV14. The output terminal of inverting circuit INV14 is connected to the first terminal of transmission gate 62 and the output terminal of signal 'signal'1. The second terminals of transmission gate 61 and 62 are connected to the input terminals of inverting circuit INV15. The output terminal of inverting circuit INV15 is connected to the input terminal of inverting circuit INV16, and the output terminal of inverting circuit INV16 is connected to the output terminal of signal 'signal0'. The input terminal receiving the first switching signal SWS1 is connected to the inverting control terminal of transmission gate 61 and the control terminal of transmission gate 62. The input terminal receiving the second switching signal SWS2 is connected to the control terminal of transmission gate 61 and the inverting control terminal of transmission gate 62.

[0104] When the overcurrent detection circuit 160 is not in the overcurrent detection state, the first switching signal SWS1 received from the gated latch circuit 50 is at level L, and the second switching signal SWS2 is at level H. At this time, in the overcurrent mode switching circuit 60, transmission gate 61 is turned on, and transmission gate 62 is turned off. Therefore, the signal signal generated when the input signal IN is received passes through transmission gate 61 and the inverting circuits INV15 and INV16, outputting a signal signal0 with the same phase as signal signal1. At this time, since signal signal1 also passes through the inverting circuit INV14, the phase of signal signal1 is opposite to the phase of signal signal1.

[0105] On the other hand, when the overcurrent detection circuit 160 is in the overcurrent detection state, the first switching signal SWS1 received from the gate latch circuit 50 is at level H, and the second switching signal SWS2 is at level L. Therefore, transmission gate 61 is not conducting, and transmission gate 62 is conducting. Here, if the input signal IN is received and the signal signal is received from the oscillation signal generation circuit 30, the signal obtained by inverting the signal signal is output as signal signal0 and signal signal1.

[0106] like Figure 5As shown, the timing determination circuit 70 includes T flip-flops TFF11, TFF12, TFF13, NOR circuits NOR11, NOR12, NAND circuits NAND16, NAND17, and an inverting circuit INV17. The input terminal of the received signal signal0 is connected to the input terminal of T flip-flop TFF11; the input terminal of the received signal signal1 is connected to one input terminal of the NOR circuit NOR11; and the input terminal of the received first overcurrent detection signal OCDS1 is connected to one input terminal of the NAND circuit NAND17. The output terminal of T flip-flop TFF11 is connected to the input terminal of T flip-flop TFF12 and another input terminal of the NOR circuit NOR11. The output terminal of T flip-flop TFF12 is connected to the input terminal of T flip-flop TFF13 and one input terminal of the NOR circuit NOR12. The output terminal of T flip-flop TFF13 is connected to the other input terminal of the NOR circuit NOR12. The output terminal of the NOR11 circuit is connected to one input terminal of the NAND16 circuit, and the output terminal of the NOR12 circuit is connected to the other input terminal of the NAND16 circuit. The output terminal of the NAND16 circuit is connected to the other input terminal of the NAND17 circuit, and the output terminal of the NAND17 circuit is connected to the input terminal of the inverting circuit INV17. The output terminal of the inverting circuit INV17 constitutes the output terminal of the timing determination circuit 70. It should be noted that the NOR11, NOR12, and NAND16 circuits constitute the first logic operation circuit, and the NAND17 circuit and the inverting circuit INV17 constitute the second logic operation circuit.

[0107] When the timing determination circuit 70 receives signal 0 from the overcurrent mode switching circuit 60, it sequentially divides signal 0 using a down-counter circuit composed of three-stage T flip-flops TFF11, TFF12, and TFF13. Specifically, TFF11 outputs signal 2, which doubles the period of signal 0; TFF12 outputs signal 3, which doubles the period of signal 2; and TFF13 outputs signal 4, which doubles the period of signal 3. The NOR circuit NOR11 receives signals 1 and 2, and outputs a high-level signal when both are at low (L) levels. The NOR circuit NOR12 receives signals 3 and 4, and outputs a high-level signal when both are at low (L) levels. The NAND circuit NAND16 only outputs a low-level signal (consistency signal) when it receives a high-level signal from either NOR11 or NOR12. The L-level signal output by the NAND16 NAND circuit becomes the signal that causes the main MOSFET110 to periodically turn on only for a short period of time.

[0108] However, after receiving an H-level input signal IN immediately after the overcurrent detection circuit 160 has not detected an overcurrent, the signal signal1 remains at the H level. Therefore, the NAND circuit NAND16 outputs an H-level signal. Thus, despite receiving an H-level input signal IN, the NAND circuit NAND16 cannot output an L-level signal to turn on the main MOSFET 110.

[0109] Therefore, the timing determination circuit 70 sets the NAND circuit NAND17 and the inverter circuit INV17. When the overcurrent detection circuit 160 does not detect overcurrent, it outputs a low-level signal that turns on the main MOSFET 110 synchronously with the input signal IN. That is, the output signal of the NAND circuit NAND16 and the first overcurrent detection signal OCDS1 are input to the NAND circuit NAND17. When the first overcurrent detection signal OCDS1 (low level, indicating no overcurrent detection) is input, the NAND circuit NAND17 outputs a high-level signal regardless of the logic level of the output signal of the NAND circuit NAND16, and the inverter circuit INV17 outputs a low-level signal output. That is, the NAND circuit NAND17 becomes valid when the NAND circuit NAND16 outputs a consistent signal or the first overcurrent detection signal OCDS1 is low level, and the main MOSFET 110 turns on only during this valid output range.

[0110] Next, refer to Figures 6 to 8 The operation of logic circuit 10 is explained.

[0111] Figure 6 This is a timing diagram showing the operation of the logic circuit when it enters the overcurrent detection state after receiving an input signal. Figure 7 This is a timing diagram showing the operation of the logic circuit when it enters the overcurrent detection state before receiving the input signal. Figure 8 This is a timing diagram illustrating the operation of the logic circuit when it enters an overcurrent detection state during the output pulse of the pulse generation circuit. It should be noted that... Figures 6 to 8 The following signals are shown from top to bottom: input signal IN, pulse generation circuit output, first overcurrent detection signal OCDS1, second overcurrent detection signal OCDS2, first switching signal SWS1, second switching signal SWS2, signal signal, signal signal0, signal signal1, signal signal2, signal signal3, signal signal4, and signal output.

[0112] First, such as Figure 6As shown, if an H-level input signal IN is received, the pulse generation circuit 40 generates a pulse that rises synchronously with the rise of the input signal IN. At this time, the overcurrent detection circuit 160 does not detect overcurrent, therefore, it outputs an L-level first overcurrent detection signal OCDS1 and an H-level second overcurrent detection signal OCDS2.

[0113] If the gated latch circuit 50 receives a pulse from the pulse generation circuit 40, it latches the first overcurrent detection signal OCDS1 and the second overcurrent detection signal OCDS2. The gated latch circuit 50 outputs the low level of the latched first overcurrent detection signal OCDS1 as the first switching signal SWS1, and outputs the high level of the latched second overcurrent detection signal OCDS2 as the second switching signal SWS2.

[0114] The overcurrent mode switching circuit 60 sets the transmission gate 61 to the on state and the transmission gate 62 to the off state according to the first switching signal SWS1 and the second switching signal SWS2.

[0115] Subsequently, if the overcurrent detection circuit 160 detects an overcurrent, the first overcurrent detection signal OCDS1 becomes H level, and the second overcurrent detection signal OCDS2 becomes L level. However, at this time, pulse generation has ended, the gate latch circuit 50 is in a disabled state, and its state remains unchanged. Therefore, the logic levels of the first switching signal SWS1 and the second switching signal SWS2 also remain unchanged.

[0116] Since the overcurrent detection circuit 160 detects an overcurrent, the oscillation signal generation circuit 30 outputs a signal signal that rises synchronously with the rise of the first overcurrent detection signal OCDS1. At this time, the overcurrent mode switching circuit 60 does not switch the overcurrent mode; therefore, the signal signal passes through transmission gate 61 and inverting circuits INV15 and INV16, becoming a signal signal0 with the same phase as the signal signal, and is output. Furthermore, the signal signal passes through inverting circuit INV14, becoming a signal signal1 with the opposite phase as the signal signal, and is output.

[0117] In the timing determination circuit 70, if signals signal0 and signal1 of level H are received, the NAND circuit NAND16 outputs a signal of level H. At this time, since the first overcurrent detection signal OCDS1 is of level H, the NAND circuit NAND17 outputs a signal of level L, and the inverter circuit INV17 outputs a signal of level H.

[0118] Subsequently, in the timing determination circuit 70, signal 0 is received, and signals 2, 3, and 4 are generated sequentially. Furthermore, whenever a consistent signal is output from the NAND circuit NAND 16, the output of NAND 16 becomes low (L), therefore, the output of NAND 17 becomes high (H), and the inverter circuit INV 17 outputs a low-level signal. The main MOSFET 110 is turned on only during the active output range when this signal output is low (L).

[0119] Thus, when an input signal IN is input, if an overcurrent detection state is reached, the effective output range of the signal output will be immediately terminated at that moment. Therefore, the main MOSFET110 can be safely protected against overheating caused by overcurrent.

[0120] Next, as Figure 7 As shown, when the input signal IN is at level L, if the overcurrent detection circuit 160 detects an overcurrent, the overcurrent detection circuit 160 outputs a first overcurrent detection signal OCDS1 at level H and a second overcurrent detection signal OCDS2 at level L.

[0121] Subsequently, if an input signal IN of level H is received, the pulse generation circuit 40 generates a pulse that rises synchronously with the rise of the input signal IN and supplies it to the gate latch circuit 50.

[0122] If the gated latch circuit 50 receives a pulse from the pulse generation circuit 40, it latches the first overcurrent detection signal OCDS1 and the second overcurrent detection signal OCDS2. The gated latch circuit 50 outputs the high level of the latched first overcurrent detection signal OCDS1 as the first switching signal SWS1, and outputs the low level of the latched second overcurrent detection signal OCDS2 as the second switching signal SWS2.

[0123] The overcurrent mode switching circuit 60 sets transmission gate 61 to a non-conducting state and transmission gate 62 to a conducting state based on the first switching signal SWS1 and the second switching signal SWS2. Therefore, the signal signal, generated synchronously with the rise of the input signal IN, passes through the inverting circuit INV14, transmission gate 62, and inverting circuits INV15 and INV16 to become signal signal0. Furthermore, signal signal passes through the inverting circuit INV14 to become signal signal1. The phases of signal signal0 and signal signal1 are opposite to the phase of signal signal1.

[0124] In the timing determination circuit 70, when signal 0 is received, since signals 1, 2, 3, and 4 are at low level, the NAND circuit NAND 16 outputs a signal at low level. Therefore, the NAND circuit NAND 17 outputs a signal at high level, and the inverter circuit INV 17 outputs a signal at low level, and the main MOSFET 110 is turned on only during the effective range of this output.

[0125] Subsequently, the down-counter circuit generates signals signal2, signal3, and signal4 sequentially, with a delay of half a cycle compared to signal1. Whenever the NAND flash circuit NAND16 outputs a signal of L level, the main MOSFET110 is turned on.

[0126] Thus, when in overcurrent detection mode, if an input signal IN is received, the counting start time of the counter circuit used to generate the output signal is delayed by half a cycle of the signal signal. Therefore, from the moment the input signal IN is received, the effective output interval of the output signal is reliably set to half a cycle of the signal signal, thus ensuring sufficient time for receiving the AMP signal during overcurrent detection.

[0127] It should be noted that the effective output interval when the input signal IN is received, i.e., the period of half a cycle of the signal signal output by the oscillation signal generation circuit 30, is preferably longer than or equal to the period during which the pulse generation circuit 40 outputs a pulse. Therefore, regardless of whether an overcurrent is detected at the time the input signal IN is received, the logic circuit 10 outputs the turn-on signal of the main MOSFET 110 during at least the period during which the pulse generation circuit 40 outputs a pulse.

[0128] Next, as Figure 8 As shown, if an H-level input signal IN is received, the pulse generation circuit 40 outputs a pulse. At this time, the overcurrent detection circuit 160 does not detect an overcurrent, therefore, it outputs an L-level first overcurrent detection signal OCDS1. Therefore, in the timing determination circuit 70, since the NAND circuit NAND17 receives the L-level first overcurrent detection signal OCDS1, the NAND circuit NAND17 outputs an H-level signal, and the inverting circuit INV17 outputs an L-level signal output.

[0129] If the overcurrent detection circuit 160 detects an overcurrent during the output pulse of the pulse generation circuit 40, then in the overcurrent detection circuit 160, the first overcurrent detection signal OCDS1 becomes H level and the second overcurrent detection signal OCDS2 becomes L level.

[0130] At this time, the gated latch circuit 50 still receives pulses from the pulse generation circuit 40, and therefore latches the first overcurrent detection signal OCDS1 and the second overcurrent detection signal OCDS2, whose logic levels have changed. The gated latch circuit 50 outputs the H level of the latched first overcurrent detection signal OCDS1 as the first switching signal SWS1, and outputs the L level of the latched second overcurrent detection signal OCDS2 as the second switching signal SWS2.

[0131] The overcurrent mode switching circuit 60 sets transmission gate 61 to a non-conducting state and transmission gate 62 to a conducting state based on the first switching signal SWS1 and the second switching signal SWS2. Therefore, the signal signal, generated synchronously with the rise of the first overcurrent detection signal OCDS1, passes through the inverting circuit INV14, transmission gate 62, and inverting circuits INV15 and INV16 to become signal signal0. Additionally, signal signal passes through the inverting circuit INV14 to become signal signal1. The phases of signals signal0 and signal signal1 are opposite to the phase of signal signal1.

[0132] In the timing determination circuit 70, immediately after receiving the high-level input signal IN, the first overcurrent detection signal OCDS1 becomes low-level. Therefore, the NAND circuit NAND17 outputs a high-level signal, and the inverting circuit INV17 outputs a low-level signal output. After the overcurrent detection circuit 160 detects an overcurrent, and the first overcurrent detection signal OCDS1 becomes high-level, the signal signal output by the oscillation signal generation circuit 30 becomes high-level. Consequently, signals signal0, signal1, signal2, signal3, and signal4 all become low-level. Therefore, the NAND circuit NAND16 outputs a low-level signal, so the NAND circuit NAND17 outputs a high-level signal, and the inverting circuit INV17 continues to output a low-level signal output.

[0133] Subsequently, if the output valid interval is passed with a delay of half a cycle compared to signal signal, the down-counter circuit sequentially generates signals signal2, signal3, and signal4. Whenever the NAND16 outputs a signal of the same level as L, the output valid interval becomes valid, and the main MOSFET110 turns on.

[0134] Thus, in the timing determination circuit 70, when the overcurrent detection circuit 160 detects an overcurrent, the counter circuit begins counting by delaying the signal by half a cycle from that moment. During the period before counting begins, the effective output interval is extended, thereby ensuring sufficient time for the microcomputer 200 to receive the signal AMP upon overcurrent detection.

[0135] It should be noted that, in Figures 6 to 8 In the diagram, when the input signal IN is at level L, the signal output is shown as level H. This is achieved through a circuit (not shown) that makes the signal output level H when the input signal IN is at level L.

[0136] In the above embodiments, the oscillation signal generation circuit 30 uses a signal signal that rises when both the input signal IN and the first overcurrent detection signal OCDS1 are at level H, but it is not limited to this. For example, it can generate a signal signal that starts from level L when both the input signal IN and the first overcurrent detection signal OCDS1 are at level H, and in the overcurrent mode switching circuit 60, the input positions of the first switching signal SWS1 and the second switching signal SWS2 are compared with... Figure 4 The configuration can be changed compared to the previous configuration. Furthermore, in the timing determination circuit 70, the counter circuit is composed of three-stage T flip-flops TFF11, TFF12, and TFF13, but is not limited to this number of stages. Alternatively, a MOSFET connected to a resistor and diode can be used instead of the MOSFET42 in the pulse generation circuit 40. Furthermore, a NOR circuit can be used instead of a NAND circuit. Additionally, the gate latch circuit 50 is composed of a NAND circuit, but can also be configured to use a NOR circuit.

[0137] The above only illustrates the principles of the present invention. Those skilled in the art can make numerous modifications and alterations. The present invention is not limited to the correct structures and applications shown and described above; all corresponding modifications and equivalents are considered to be within the scope of the invention based on the claims and their equivalents.

Claims

1. A semiconductor device, characterized in that, The system includes a power semiconductor element, an overcurrent detection circuit, and a logic circuit that outputs a shutdown signal to the power semiconductor element when the overcurrent detection circuit detects an overcurrent. The logic circuit includes: A pulse generation circuit that generates and outputs a pulse when an input signal indicating the conduction operation of the power semiconductor element is input; as well as An oscillation signal generation circuit generates an oscillation signal when simultaneously inputting an input signal indicating the conduction of the power semiconductor and an overcurrent detection signal from the overcurrent detection circuit. When the overcurrent detection circuit detects an overcurrent during the output of the pulse, the logic circuit outputs a signal indicating the conduction of the power semiconductor element during half a cycle of the oscillation signal after the overcurrent is detected.

2. A semiconductor device, characterized in that, The system includes a power semiconductor element, an overcurrent detection circuit, and a logic circuit that outputs a shutdown signal to the power semiconductor element when the overcurrent detection circuit detects an overcurrent. The logic circuit includes a pulse generation circuit that generates and outputs a pulse when an input signal instructing the power semiconductor element to conduct is input. When the overcurrent detection circuit continuously detects an overcurrent before the pulse is output, the logic circuit outputs a signal indicating the conduction of the power semiconductor element during a predetermined period after the pulse is output.

3. The semiconductor device according to claim 2, characterized in that, Even if the overcurrent is detected, a turn-on signal is output to the power semiconductor element at least during the period when the pulse is output by the pulse generation circuit.

4. A semiconductor device, characterized in that, The system includes a power semiconductor element, an overcurrent detection circuit, and a logic circuit that, when the overcurrent detection circuit detects an overcurrent, periodically turns on the power semiconductor element only for a short period of time. The logic circuit includes: An oscillation signal generation circuit generates an oscillation signal when simultaneously receiving an input signal indicating the conduction action of the power semiconductor element and an overcurrent detection signal from the overcurrent detection circuit. A pulse generation circuit generates a pulse when the input signal is input; A gated latch circuit maintains the overcurrent detection state of the overcurrent detection circuit when the pulse is input; An overcurrent mode switching circuit outputs a counter input signal and an inverted signal obtained by inverting the oscillation signal. The counter input signal is a signal obtained by switching the oscillation signal generated by the oscillation signal generation circuit to inverted or non-inverted according to the overcurrent detection state maintained by the gate latch circuit. as well as The timing determination circuit divides the input signal of the counter into multiple frequency division signals, and outputs an output signal that causes the power semiconductor element to conduct periodically according to the inversion signal and the frequency division signals.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that, The pulse generation circuit generates a pulse that lasts for a fixed duration only when the input signal is input.

6. The semiconductor device according to claim 4, characterized in that, The gated latch circuit has a gate circuit that acquires the overcurrent detection state of the overcurrent detection circuit when the pulse is input, and a latch circuit that holds the overcurrent detection state acquired by the gate circuit. The gated latch circuit outputs a switching signal that causes the overcurrent mode switching circuit to switch the oscillation signal to inverted or non-inverted based on the holding state of the latch circuit.

7. The semiconductor device according to claim 6, characterized in that, The overcurrent mode switching circuit has the following features: An inverting circuit outputs the inverted signal obtained by reversing the oscillation signal; and The switching circuit selects either the oscillation signal or the inverting signal based on the switching signal output by the gate latch circuit and sets it as the input signal of the counter.

8. The semiconductor device according to claim 7, characterized in that, The switching circuit is composed of transmission gates.

9. The semiconductor device according to claim 4, characterized in that, The timing determination circuit has the following characteristics: The counter circuit divides the frequency of the counter input signal; and The logic operation circuit outputs the output signal when the logic states of the inverted signal and the frequency division signal are completely consistent.

10. The semiconductor device according to claim 4, characterized in that, The timing determination circuit has the following characteristics: The counter circuit divides the frequency of the counter input signal; The first logic operation circuit outputs a consistent signal when the logic states of the inverted signal and the frequency division signal are completely consistent. as well as The second logic operation circuit receives the overcurrent detection signal and the consistency signal, and when the overcurrent detection circuit does not detect overcurrent when the input signal is input, outputs the output signal synchronized with the input signal.

11. The semiconductor device according to claim 9 or 10, characterized in that, The counter circuit is composed of multiple T flip-flops.

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