Memory device and initialization method thereof

Abstract

The invention provides a memory device and an initialization method thereof. The initialization method comprises powering on the memory device to provide an internal voltage to a memory array; and after the internal voltage is stabilized, refreshing all storage cells.

Description

Technical Field

[0001] The invention relates to a method for operating a memory, and in particular to a memory device and an initialization method thereof. Background Art

[0002] With the rapid development of technology today, semiconductor memory is widely used in electronic devices. For applications that require high speed and large amounts of data storage, dynamic random access memory (DRAM) is the most commonly used solution.

[0003] There are multiple storage cells in the dynamic random access memory. Figure 1 It is a circuit diagram of an existing storage unit. Figure 1 As shown, the memory cell 100 includes an N-type memory transistor ST. The drain of the memory transistor ST is coupled to the bit line BL. The gate of the memory transistor ST is coupled to the word line WL. The source of the memory transistor ST is coupled to one end of the storage capacitor Ccell. The other end of the one end of the storage capacitor Ccell is coupled to the plate PLT. The node between the memory transistor ST and the storage capacitor Ccell is called a storage node SN.

[0004] When the dynamic random access memory is initialized, the potentials of the word line WL, the bit line BL and the plate PLT are all 0 volts at the beginning, the storage transistor ST will not be turned on, and the storage node ST is in a floating state. After the power-on operation, the potentials of the bit line BL and the plate PLT will be pulled up to half of the operating voltage VDD. Since the storage transistor ST is not turned on, the storage node SN will be slightly lower than half of the operating voltage VDD due to the coupling force from the plate PLT. In this way, when the storage transistor ST is turned on for the first time through the bit line WL, the interference (noise) from the cell plate PLT will become larger, and the potential of the storage node SN will be offset, resulting in a decrease in the reading and writing speed, and an increase in the chance of data reading and writing errors. Summary of the invention

[0005] The invention provides a memory device and an initialization method thereof, which automatically performs a refreshing operation on all storage units after completing a power-on operation.

[0006] The initialization method of the memory device of the present invention comprises: performing a power-on operation on the memory device to provide an internal voltage to the memory array; and performing a refresh operation on all storage cells after the internal voltage is stabilized.

[0007] In one embodiment of the present invention, the above-mentioned step of performing a refresh operation on all memory cells includes: setting the bit line corresponding to each memory cell at an initial voltage; turning off the turned-on access transistor after the corresponding access transistor is turned on for a setting time through the word line corresponding to the row address; incrementing the row address; determining whether the row address exceeds a critical value; and when the row address exceeds the critical value, ending the short burst refresh operation.

[0008] The memory device of the present invention comprises a memory array having a plurality of memory cells and a memory controller. The memory controller is coupled to the memory array. When a power-on operation is performed, the memory controller provides an internal voltage to the memory array. After the internal voltage is stable, the memory controller performs a refresh operation on all memory cells.

[0009] In one embodiment of the present invention, each of the above-mentioned memory cells includes an access transistor. When performing a short burst refresh operation, the memory controller sets the bit line corresponding to each memory cell at an initial voltage, and after turning on the corresponding access transistor for a setting time through a word line corresponding to a row address, turns off the turned-on access transistor. The memory controller increments the row address and determines whether the row address exceeds a critical value. When the row address exceeds the critical value, the memory controller ends the short burst refresh operation.

[0010] Based on the above, each time after a power-on operation, the memory device of the present invention can first perform a refresh operation on all memory cells to actively fix the storage nodes to the correct potential. Thus, even when the memory device is used for the first time after a power-on operation, the potential of the storage nodes will not shift, thereby avoiding the undesirable phenomenon of a decrease in read / write speed and data read / write errors. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a circuit diagram of an existing storage unit;

[0012] Figure 2 is a circuit diagram of a memory device according to an embodiment of the present invention;

[0013] Figure 3 is a flow chart of a method for initializing a memory device according to an embodiment of the present invention;

[0014] Figure 4 is a flow chart of a short burst refresh operation according to an embodiment of the present invention. DETAILED DESCRIPTION

[0015] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0016] Please refer to the following Figure 2 , Figure 2 2 is a circuit diagram of a memory device according to an embodiment of the present invention. The memory device 200 includes a memory array 210 and a memory controller 220. The memory array 210 is, for example, a memory array of a dynamic random access memory. Figure 1 As shown, the memory array 210 includes memory cells 230_1-230_m*n. Each memory cell 230_1-230_m*n includes an N-type storage transistor ST and a storage capacitor Ccell. The storage transistor ST of each memory cell 230_1-230_m*n is coupled to the bit lines BL1-BLm and the word lines WL1-WLn. Figure 1 As shown, the gates of the storage transistors ST of the storage cells 230_1 to 230_m are coupled to the word line WL1, the drains of the storage transistors ST of the storage cells 230_1 to 230_m are respectively coupled to the bit lines BL1 to BLm, the gates of the storage transistors ST of the storage cells 230_m+1 to 230_2m are coupled to the word line WL2, the drains of the storage transistors ST of the storage cells 230_m+1 to 230_2m are respectively coupled to the bit lines BL1 to BLm, and so on. m and n are positive integers greater than 2. In one embodiment, m is, for example, 16K, and n is, for example, 2K, but the numbers are not used to limit the present invention.

[0017] Taking the memory cell 230_1 as an example, in the memory cell 230_1, the drain of the memory transistor ST is coupled to the bit line BL1. The gate of the memory transistor ST is coupled to the word line WL1. The source of the memory transistor ST is coupled to one end of the storage capacitor Ccell. The other end of the storage capacitor Ccell is coupled to the plate PLT.

[0018] The memory controller 220 is coupled to the memory array 210. The memory controller 220 is used to perform write operations, read operations, refresh operations, verification operations and similar operations on the memory array 210. The memory controller 220 can be a processor with computing capabilities. Alternatively, the memory controller 220 can be designed using a hardware description language (HDL) or any other digital circuit design method known to those skilled in the art, and can be implemented as a hardware circuit by means of a field programmable gate array (FPGA), a complex programmable logic device (CPLD) or an application-specific integrated circuit (ASIC).

[0019] Figure 3 is a flowchart of a method for initializing a memory device according to an embodiment of the present invention. Figure 2 and Figure 3 The method of this embodiment is applicable to the memory device 200 described above, and the following is combined with Figure 2 The various components of the memory device 200 are used to illustrate the detailed process of the method of this embodiment.

[0020] In step S310, the memory device 200 is powered on to provide an internal voltage Vin to the memory array 210 through the memory controller 220. The internal voltage Vin (actually including a plurality of voltages) provided by the memory controller 220 can enable the memory cells 230_1-230_m*n of the memory array 210 to start operating to perform various operations.

[0021] Next, in step S320 , after the internal voltage Vin is stabilized, the memory controller 220 performs a refresh operation on all the memory cells 230_1 ˜ 230_m*n.

[0022] For example, the memory controller 220 performs a short burst refresh operation on all the memory cells 230_1 ˜ 230_m*n. Figure 4 is a flow chart of a short burst refresh operation according to an embodiment of the present invention. Figure 2 and Figure 4 The method of this embodiment is applicable to the memory device 200 described above, and the following is combined with Figure 2 The various components of the memory device 200 are used to illustrate the detailed process of the method of this embodiment.

[0023] In step S410 , the memory controller 220 sets the bit lines BL1 ˜BLm corresponding to each memory cell 230_1 ˜ 230 — m*n at an initial voltage, such as 0 volt.

[0024] Next, in step S420, after the access transistors ST in the memory cells 230_1 to 230_m are turned on for a setting time through the word line WL1 corresponding to the row address RADS, the memory controller 220 turns off the turned-on access transistors ST in the memory cells 230_1 to 230_m through the word line WL1. Specifically, at the beginning, the row address RADS corresponds to the word line WL1, and during the period when the access transistors ST in the memory cells 230_1 to 230_m are turned on, the memory controller 220 can refresh the values ​​stored in the memory cells 230_1 to 230_m through the potentials of the bit lines BL1 to BLm. The setting time is, for example, 10 nanoseconds. In this way, the storage nodes SN in the memory cells 230_1 to 230_m will be fixed at an appropriate potential without causing deviation.

[0025] Next, in step S430, the memory controller 220 may increment the row address RADS (row address RADS+1). Furthermore, in step S440, the memory controller 220 may determine whether the incremented row address RADS exceeds a critical value. In this embodiment, the critical value is, for example, the value of the row address corresponding to the last word line WLn in the memory array 210.

[0026] When the row address RADS does not exceed the critical value, it indicates that there are still memory cells that have not been refreshed. The memory controller 220 returns to step S420 and continues to repeat steps S420 and S430. At this time, the incremented row address RADS becomes corresponding to the word line WL2, and the refresh object becomes the memory cell 230_m+1 to 230_2m controlled by the word line WL2, and so on, until the row address RADS increases to exceed the critical value.

[0027] When the row address RADS exceeds the critical value, it indicates that all the memory cells 230_1 ˜ 230_m*n have been refreshed. Finally, in step S450 , the memory controller 220 ends the short burst refresh operation.

[0028] It should be noted that, although the memory controller 220 performs a short burst refresh operation on all the memory cells 230_1 to 230_m*n in this embodiment, the present invention is not limited thereto. In other embodiments, the memory controller 220 may also perform a standard burst refresh operation similar to that used by a general refresh command on the memory cells 230_1 to 230_m*n.

[0029] In summary, whenever an electronic device equipped with a dynamic random access memory is powered on and powered on, the memory device of the present invention can first perform a refresh operation on all memory cells to actively fix the storage nodes in the memory cells to the correct potential. Thus, even when the memory device is used for the first time after the power-on operation, the potential of the storage node will not be offset, thereby avoiding the undesirable phenomenon of reduced read and write speed and data read and write errors.

[0030] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for initializing a memory device, wherein the memory device comprises a memory array having a plurality of storage units, wherein the initialization method comprises: Performing a power-on operation on the memory device to provide an internal voltage to the memory array; as well as After the internal voltage is stabilized, a short burst refresh operation is performed on all the memory cells. Each of the memory cells comprises an access transistor, and the step of performing the short burst refresh operation on all the memory cells comprises: Setting the bit line corresponding to each of the memory cells at an initial voltage; After the corresponding access transistor is turned on for a setting time by a word line corresponding to a row address, turning off the turned-on access transistor; Incrementing the row address; determining whether the row address exceeds a critical value; and When the row address exceeds the critical value, the short burst refresh operation is terminated.

2. The method for initializing a memory device according to claim 1, wherein after the step of determining whether the row address exceeds the critical value, the method further comprises: When the row address does not exceed the critical value, the turning on step and the increasing step are repeated until the row address exceeds the critical value. 3 . The memory device initialization method according to claim 1 , wherein the setup time is 10 nanoseconds. 4 . The memory device initialization method according to claim 1 , wherein the initial voltage is 0 volt.

5. A memory device, characterized in that: include: A memory array having a plurality of storage cells; as well as A memory controller is coupled to the memory array and provides an internal voltage to the memory array when a power-on operation is performed. After the internal voltage is stabilized, the memory controller performs a short burst refresh operation on all the storage cells. Each of the memory cells comprises an access transistor, When performing the short burst refresh operation, the memory controller sets the bit line corresponding to each memory cell at an initial voltage, and turns off the turned-on access transistor after turning on the corresponding access transistor for a setting time through the word line corresponding to the row address. The memory controller increments the row address and determines whether the row address exceeds a critical value. When the row address exceeds the critical value, the memory controller ends the short burst refresh operation. 6 . The memory device according to claim 5 , wherein when the row address does not exceed the critical value, the memory controller repeats the turning on step and the incrementing step until the row address exceeds the critical value. The memory device of claim 5 , wherein the setup time is 10 nanoseconds. The memory device according to claim 5 , wherein the initial voltage is 0 volts.

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