Error correction code poisoning of a memory device and associated methods and systems

Abstract

This application relates to error correction code poisoning in memory devices and associated methods and systems. Memory devices, systems including memory devices, and methods of operating memory devices are described, where the memory devices are configured to poison data based on an indication provided by a host device coupled with the memory device. The indication can include which bit(s) to poison (invert) in which phase of performing a write or read operation. In some embodiments, the memory device can invert one or more bits according to the indication and then correct one or more errors associated with inverting the one or more bits to verify its on-die ECC functionality. In some embodiments, the memory device can provide the host device with poisoned data including one or more bits inverted according to the indication, so that the host device can test system-level ECC functionality using the poisoned data.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to memory devices, and more particularly to error correction code poisoning of memory devices and associated methods and systems. BACKGROUND

[0002] Memory devices are widely used to store information related to various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Memory devices are frequently provided as internal, semiconductor integrated circuits and / or external removable devices in computers or other electronic devices. There are many different types of memory, including volatile and non-volatile memory. Volatile memory, including random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), and the like, requires a source of applied power to maintain its data. In contrast, non-volatile memory can retain its stored data even when an external power supply is not present. Non-volatile memory can be used in various technologies, including flash memory (e.g., NAND and NOR), phase change memory (PCM), ferroelectric random access memory (FeRAM), resistive random access memory (RRAM), and magnetic random access memory (MRAM), among others. Improving memory devices can generally include increasing memory cell density, improving read / write speeds or otherwise reducing operational latency, increasing reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs, among other metrics. SUMMARY

[0003] According to one embodiment of the present disclosure, a method is provided. The method includes receiving, at a memory device, a command from a host device coupled with the memory device, the command directed to a first set of data; generating, from the first set of data, a second set of data including one or more bits inverted based on one or more bit positions indicated to the memory device; detecting one or more errors in the second set of data based at least in part on the one or more inverted bits; correcting the one or more errors in the second set of data to generate a third set of data comprising bits matching the first set of data; and transmitting the third set of data generated from the second set of data and comprising bits matching the first set of data to the host device.

[0004] According to another embodiment of the present disclosure, a method is provided. The method includes receiving, at a memory device, a command from a host device coupled with the memory device, the command directed to a first set of data; inverting one or more bits of the first set of data based on one or more bit positions indicated to the memory device by the host device using one or more registers of the memory device, one or more commands used to program the one or more registers of the memory device, or both; and transmitting the first set of data with the one or more inverted bits to the host device.

[0005] According to yet another embodiment of the present disclosure, an apparatus is provided. The apparatus includes a memory array and peripheral circuitry coupled with the memory array. Configured to: receive a command from a host device coupled with the apparatus, the command directed to a first data set; generate a second data set including one or more bits inverted based on one or more bit positions indicated to the apparatus from the first data set; detect one or more errors in the second data set based at least in part on the one or more inverted bits; correct the one or more errors in the second data set to generate a third data set comprising bits matching the first data set; and transmit the third data set generated from the second data set and comprising bits matching the first data set to the host device. BRIEF DESCRIPTION OF DRAWINGS

[0006] The present disclosure will become more fully understood from the detailed description given hereinbelow and the accompanying drawings, wherein like elements are represented by like reference numerals, and wherein: the components in the figures are not necessarily to scale. It is intended that the specification be considered exemplary of the principles of the application, and that the application be limited only by the claims.

[0007] Figure 1 is a block diagram schematically illustrating a memory device supporting embodiments of the present technology.

[0008] Figures 2A to 2D is a block diagram schematically illustrating a memory device according to embodiments of the present technology.

[0009] Figure 3 is a block diagram of a system having a memory device configured according to embodiments of the present technology.

[0010] Figure 4 and 5 is a flow diagram illustrating a method of operating a memory device according to embodiments of the present technology. DETAILED DESCRIPTION

[0011] Methods, systems, and devices for memory devices (e.g., DRAM) that provide for error correction code poisoning are disclosed. As memory cells are scaled to increase memory density and storage capacity of memory devices, meeting various reliability standards for memory devices becomes increasingly challenging. Error checking and correction functionality using error correction codes (ECC) can help circumvent certain reliability issues. In some embodiments, a memory device includes ECC circuitry (which can be referred to as an ECC engine, module, block, etc.). For example, ECC circuitry included in a memory device (“on-die ECC circuitry”) can detect and correct at least one error in data (e.g., a valid logic state of “1” is flipped to an invalid logic state of “0” or vice versa). Additionally or alternatively, the ECC circuitry can detect two or more errors in data. In some embodiments, a host device (e.g., a memory controller) coupled with the memory device includes ECC circuitry external to the memory device (e.g., system-level ECC functionality). It would be desirable to be able to test the on-die ECC circuitry and / or the system-level ECC functionality to confirm proper operation of the ECC circuitry.

[0012] In some embodiments, on-die ECC circuitry of a memory device can be configured to correct at least one error to improve data integrity within the memory device. For example, the on-die ECC circuitry can use data including a first number of bits (e.g., 128 data bits) to compute / calculate an ECC parity code including a second number of bits (e.g., 8 bits), which can be referred to as ECC check bits or ECC parity bits. The combination of the first and second number of bits (e.g., 136 bits including 128 data bits plus 8 ECC check bits) can be referred to as a codeword including a third number of bits (e.g., 136 bits).

[0013] During a write operation, after receiving a write command that provides data and an address within a memory array of the memory device, the memory device can use the data (e.g., 128 bits of data) to compute a set of ECC check bits (e.g., 8 bits, a first check bit group), and then write a codeword (e.g., 136 bits including the data and the ECC check bits) to the address within the memory array. During a read operation, the memory device can attempt to detect and / or correct at least one error before transferring the data (e.g., 128 bits of data) to the memory controller. In some embodiments, the memory device reads a codeword from the address, and computes another set of ECC check bits (e.g., 8 bits, a second check bit group) from the data read from the address. Subsequently, the memory device can compare the first ECC check bit group read from the address (which was written to the address in response to the write command) with the second ECC check bit group computed from the data read from the address, such that the memory device can detect and / or correct at least one error in the data.

[0014] On-die ECC circuitry can be tested in various ways under manufacturing environments. For example, data can be written to a memory array with the on-die ECC circuitry disabled (e.g., via a test mode), and then read from the memory array with the ECC circuitry enabled, or vice versa. In other examples, with the on-die ECC circuitry enabled, valid data can be written to and then read back from the memory array. Subsequently, poisoned data (e.g., one or more data bits intentionally inverted or flipped, one or more errors injected into the data) can be written and then read back to verify on-die ECC circuitry functionality. However, once the memory device is implemented in a system, the system (e.g., a host device, a memory controller) can not have access to test modes and / or manipulate data by injecting errors to test on-die ECC functionality. Additionally or alternatively, the ability to provide poisoned data to the host device can be required to test system-level ECC functionality.

[0015] Several embodiments of the present technology are directed to poisoning (e.g., inverting, flipping, modifying, corrupting, etc.) one or more bits of data within a memory device included in a system. Such poisoning of data can facilitate confirming functionality of on-die ECC circuitry and / or providing (outputting) poisoned data for testing system-level ECC functionality. In this regard, the present technology allows a host device of a system to control which bits to invert (poison) in conjunction with a memory device coupled thereto during a write or read operation. In some embodiments, the host device can access one or more mode registers of the memory device to indicate which bit or bits to poison (program) when performing an access command (e.g., a write command, a read command). Additionally or alternatively, the host device can transmit one or more commands (e.g., a multi-purpose command (MPC), a mode register write (MRW) command) configured to program a register to provide such an indication to the memory device.

[0016] Reference is made to Figure 1 A memory device supporting embodiments of the present technology is described. Reference is made to Figures 2A to 2D A more detailed description of a memory device supporting embodiments of the present technology is provided. Reference is made to Figure 3 A memory system including a memory device according to embodiments of the present technology is described. Reference is made to Figure 4 and 5 A method of operating a memory device according to embodiments of the present technology is described.

[0017] Figure 1 is a block diagram schematically illustrating a memory device 100 according to embodiments of the present technology. The memory device 100 can include an array of memory cells, such as a memory array 150. The memory array 150 can include a plurality of memory banks (e.g., memory banks 0-15 in the example of Figure 1 Each of the plurality of word lines can be coupled with a corresponding word line driver (WL driver) configured to control a voltage of the word line during a memory operation.

[0018] The memory cells can include any of several different memory media types, including capacitive, phase change, magnetoresistive, ferroelectric, etc. In some embodiments, a portion of the memory array 150 can be configured to store ECC parity bits (ECC check bits). Selection of the word lines WL can be performed by the row decoder 140, and selection of the bit lines BL can be performed by the column decoder 145. Sense amplifiers (SAMP) can be provided for corresponding bit lines BL and connected to at least one respective local I / O line pair (LIOT / B), which in turn can be coupled to at least one respective main I / O line pair (MIOT / B) via a transfer gate (TG), which can act as a switch. The memory array 150 can also include plate lines and corresponding circuitry for managing its operation.

[0019] The memory device 100 can employ a plurality of external terminals including command and address terminals coupled to a command bus and an address bus to receive command signals CMD and address signals ADDR, respectively. The memory device can also include a chip select terminal for receiving a chip select signal CS, clock terminals for receiving a clock signal CK and CKF, data clock terminals for receiving data clock signals WCK and WCKF, data terminals DQ, RDQS, DBI (for data bus inversion function), and DMI (for data mask inversion function), power supply terminals VDD, VSS, and VDDQ.

[0020] Address signals and bank address signals can be supplied externally to the command and address terminals. The address signals and bank address signals supplied to the address terminals can be passed to the address decoder 110 via the command / address input circuit 105. The address decoder 110 can receive the address signals and supply a decoded row address signal (XADD) to the row decoder 140 (which can be referred to as a row driver) and a decoded column address signal (YADD) to the column decoder 145 (which can be referred to as a column driver). The address decoder 110 can also receive the bank address portion of the ADDR input and supply a decoded bank address signal (BADD) and bank address signal to both the row decoder 140 and the column decoder 145.

[0021] Command signals CMD, address signals ADDR, and chip select signals CS can be supplied from a memory controller to the command and address terminals. The command signals can represent various memory commands from the memory controller (e.g., refresh commands, activate commands, precharge commands, access commands which can include read commands and write commands). The chip select signal CS can be used to select the memory device 100 to respond to the commands and addresses provided to the command and address terminals. When an active CS signal is provided to the memory device 100, the commands and addresses can be decoded and memory operations can be performed. The command signals CMD can be provided as internal command signals ICMD to the command decoder 115 via the command / address input circuit 105.

[0022] The command decoder 115 can include circuitry to decode internal command signals ICM to generate various internal signals and commands used to perform memory operations, e.g., row command signals to select a word line and column command signals to select a bit line. Other examples of memory operations that the memory device 100 can perform based on decoding the internal command signals ICM include a refresh command (e.g., to refresh all charges stored in individual memory cells of the memory array 150), an activate command (e.g., to activate a row in a particular bank, in some cases for a subsequent access operation), or a precharge command (e.g., to deactivate an activated row in a particular bank). The internal command signals can also include output and input activate commands, such as a timing command CMDCK Figure 1 (not shown in FIG. 1).

[0023] In some embodiments, the command decoder 115 can further include one or more registers 118 to track various counts and / or values (e.g., a count of refresh commands received by the memory device 100 or self-refresh operations performed by the memory device 100) and / or to store various operating conditions of the memory device 100 to perform certain functions, features, and modes (or test modes). Thus, in some embodiments, the registers 118 (or a subset of the registers 118) can be referred to as mode registers. Additionally or alternatively, the memory device 100 can include the registers 118 as a separate component outside of the command decoder 115. In some embodiments, the registers 118 can include a multipurpose register (MPR) configured to write and / or read specialized data to and from the memory device 100.

[0024] When a read command is issued to a bank having an open row and a column address is timely supplied as part of the read command, read data can be read from the memory cells in the memory array 150 specified by the row address (which can have been provided as part of an activate command identifying the open row) and the column address. The read command can be received by the command decoder 115, which can provide internal commands to the input / output circuitry 160 so that read data can be output from the data terminals DQ, RDQS, DBI, and DMI via the read / write amplifiers 155 and the input / output circuitry 160 according to the RDQS clock signal. The read data can be provided at a time defined by read latency information RL, which can be programmable in the memory device 100, e.g., in a mode register (e.g., the registers 118). The read latency information RL can be defined in terms of clock cycles of the CK clock signal. For example, the read latency information RL can be a number of clock cycles of the CK signal after a read command is received by the memory device 100 when the associated read data is provided.

[0025] When a write command is issued to a bank with an open row and the column address is supplied in time as part of the write command, write data can be supplied to the data terminals DQ, DBI, and DMI in accordance with the WCK and WCKF clock signals. The write command can be received by the command decoder 115, which can provide an internal command to the input / output circuit 160 so that the write data can be received by a data receiver in the input / output circuit 160 and supplied to the memory array 150 via the input / output circuit 160 and the read / write amplifiers 155. The write data can be written into the memory cells specified by the row and column addresses. The write data can be supplied to the data terminals at a time defined by the write latency WL information. The write latency WL information can be programmed in the memory device 100, for example, in a mode register (e.g., register 118). The write latency WL information can be defined in terms of clock cycles of the CK clock signal. For example, the write latency information WL can be a number of clock cycles of the CK signal after a write command is received by the memory device 100 when the associated write data is received.

[0026] The power supply terminals can be supplied with power supply potentials VDD and VSS. These power supply potentials VDD and VSS can be supplied to the internal voltage generator circuit 170. The internal voltage generator circuit 170 can generate various internal potentials VPP, VOD, VARY, VPERI, etc. based on the power supply potentials VDD and VSS. The internal potential VPP can be used in the row decoder 140, the internal potentials VOD and VARY can be used in the sense amplifiers included in the memory array 150, and the internal potential VPERI can be used in many other circuit blocks.

[0027] The power supply terminals can be supplied with power supply potentials VDD and VSS. These power supply potentials VDD and VSS can be supplied to the internal voltage generator circuit 170. The internal voltage generator circuit 170 can generate various internal potentials VPP, VOD, VARY, VPERI, etc. based on the power supply potentials VDD and VSS. The internal potential VPP can be used in the row decoder 140, the internal potentials VOD and VARY can be used in the sense amplifiers included in the memory array 150, and the internal potential VPERI can be used in many other circuit blocks.

[0028] An external clock signal and a complementary external clock signal can be supplied to the clock terminal and the data clock terminal. The external clock signals CK, CKF, WCK, and WCKF can be supplied to the clock input circuit 120. The CK and CKF signals can be complementary, and the WCK and WCKF signals can also be complementary. The complementary clock signals can have both opposing clock levels and transitions between opposing clock levels. For example, when the clock signal is at a low clock level, the complementary clock signal is at a high clock level, and when the clock signal is at a high clock level, the complementary clock signal is at a low clock level. Furthermore, when the clock signal transitions from a low clock level to a high clock level, the complementary clock signal transitions from a high clock level to a low clock level, and when the clock signal transitions from a high clock level to a low clock level, the complementary clock signal transitions from a low clock level to a high clock level.

[0029] The input buffer included in the clock input circuit 120 can receive an external clock signal. For example, when enabled by the CKE signal from the command decoder 115, the input buffer can receive the CK and CKF signals, as well as the WCK and WCKF signals. The clock input circuit 120 can receive the external clock signal to generate an internal clock signal ICLK. The internal clock signal ICLK can be supplied to the internal clock circuit 130. The internal clock circuit 130 can provide various phase- and frequency-controlled internal clock signals based on the received internal clock signal ICLK and the clock enable signal CKE from the command decoder 115.

[0030] For example, the internal clock circuit 130 may include a clock path ( ) that receives the internal clock signal ICLK and provides various clock signals to the command decoder 115. Figure 1 (not shown). The internal clock circuit 130 may further provide an input / output (IO) clock signal. The IO clock signal may be supplied to the input / output circuit 160 and may be used as a timing signal for determining the output timing of read data and the input timing of write data. The IO clock signal may be provided at multiple clock frequencies, so that data can be output from and input to the memory device 100 at different data rates. When high memory speed is desired, a higher clock frequency may be desirable. When lower power consumption is desired, a lower clock frequency may be desirable. The internal clock signal ICLK may also be supplied to the timing generator 135, and thus various internal clock signals may be generated.

[0031] The memory device 100 can be connected to any of a number of electronic devices, or components thereof, that are capable of using memory to store information temporarily or permanently, using the memory. For example, a host device of the memory device 100 can be a computing device such as a desktop or portable computer, a server, a handheld device (e.g., a mobile phone, a tablet computer, a digital reader, a digital media player), or some component thereof (e.g., a central processing unit, a co-processor, a dedicated memory controller, etc.). The host device can be a networking device (e.g., a switch, a router, etc.) or a recorder of digital images, audio, and / or video, a vehicle, an appliance, a toy, or any of a number of other products. In one embodiment, the host device can be directly connected to the memory device 100, but in other embodiments, the host device can be indirectly connected to the memory device (e.g., via a network connection or through an intermediary device).

[0032] In some embodiments, the memory device 100 includes on-die ECC circuitry (not shown). During a write operation, the on-die ECC circuitry can use data provided to the memory device 100 (e.g., external data) to compute a first set of ECC check bits to generate a codeword that includes the data and the first set of ECC check bits. The memory device 100 then writes the codeword to the memory array 150 to complete the write operation. During a read operation, the on-die ECC circuitry can read the codeword to compute a second set of ECC check bits using data read from the memory array 150 (e.g., external data) so that the on-die ECC circuitry can compare the first set of ECC check bits to the second set of ECC check bits. In this way, the on-die ECC circuitry can detect and / or correct one or more errors in the data read from the memory array 150.

[0033] In some embodiments, memory device 100 can receive a command directed to a first set of data from a host device coupled with memory device 100. The first set of data can refer to external data provided by the host (if the command corresponds to a write command) or external data written into memory array 150 (if the command corresponds to a read command). Memory device 100 can generate a second set of data from the first set of data, where the second set of data includes one or more inverted (e.g., corrupted, poisoned) bits corresponding to one or more bit locations that the host device has indicated to memory device 100 (e.g., via a multi-purpose command, an MRW command, or any command that writes a register 118 of memory device 100). The second set of data can refer to a codeword generated based on the external data (if the command corresponds to a write command) or a codeword read from the memory array (if the command corresponds to a read command). Subsequently, memory device 100, in conjunction with on-die ECC circuitry, can detect one or more errors based on the one or more inverted bits in the second set of data. Subsequently, memory device 100, in conjunction with on-die ECC circuitry, can correct the one or more errors, thereby generating a first set of data that removes the poison, and transmit the first set of data to the host device. In this way, the host device can test the on-die ECC circuitry to confirm its functionality by controlling which bits are poisoned during a write operation or a read operation and receiving non-poisoned data from memory device 100.

[0034] Figure 2A To illustratively show a block diagram 201 of a memory device 205 (which can be an example of or include aspects of memory device 100) in accordance with an embodiment of the present technology. FIG. 201 depicts a host device 270 (e.g., a memory controller) coupled with memory device 205. Memory device 205 can include peripheral circuitry 215 coupled with a memory array 210 (which can be an example of or include aspects of memory array 150), a register 220 (which can be an example of or include aspects of register 118), an ECC circuit 225, a command decoder 230 (which can be an example of or include aspects of command decoder 115), I / O circuitry 235 (which can be an example of or include aspects of input / output circuitry 160), and the like.

[0035] FIG. 201 further illustrates various channels (buses, paths) that carry different signals (e.g., command signals, data signals). For example, FIG. 201 depicts a command / address bus 240 (which can include reference Figure 1Aspects of the described CMD, ADDR, and CS), the host device 270 can transmit various commands (e.g., access commands, multi-purpose commands, MRW commands) to the memory device 205 over the command / address bus 240. Additionally, the host device 270 can transmit and / or receive data over the input / output (I / O) bus 245 (which can include the data terminals DQ and data clock terminals DQ described with reference to Figure 1 Aspects of the described data terminals DQ and data clock terminals), the host device 270 can transmit and / or receive data. For a write operation, the diagram 201 illustrates a data path 250 before the ECC circuit 225 and a data path 255 after the ECC circuit 225. Further, for a read operation, the diagram 201 illustrates a data path 260 before the ECC circuit 225 and a data path 265 after the ECC circuit 225.

[0036] The register 220 can be configured to include one or more bit positions based on an indication from the host device 270. In this regard, the host device 270 can pre-determine one or more bit positions and access the memory device 205 to program the register 220 so that the host device 270 can test functionality of the ECC circuit 225 or can cause the memory device 205 to provide (output) poisoned data to the host device to test system-level ECC functionality. The indication from the host device 270 can include a phase of operation in which poisoning can occur, for example, during a write operation before or after the ECC circuit 225, during a read operation before or after the ECC circuit 225. Although the diagram 201 depicts the register 220 as a single block, the register 220 can include multiple registers (e.g., a mode register, a multi-purpose register).

[0037] The host device 270 can provide the indication to the memory device 205 by transmitting one or more commands (e.g., multi-purpose commands, MRW commands) to program the register 220. Accordingly, the command decoder 230 can be configured to determine one or more bit positions (and a phase of operation in which poisoning occurs) pre-determined by the host device 270 based on one or more multi-purpose commands (and / or one or more MRW commands) transmitted from the host device via the command / address bus 240. In some embodiments, the host device 270 can provide the indication to the memory device 205 by programming the register 220 and transmitting one or more multi-purpose commands (and / or one or more MRW commands).

[0038] During a write operation, ECC circuitry 225 can be configured to use data provided to memory device 205 (e.g., external data) to compute a first set of ECC check bits to produce a codeword including the data and the first set of ECC check bits. During a read operation, ECC circuitry 225 can read the codeword from memory array 210 to compute a second set of ECC check bits using data read from memory array 210 (e.g., external data) such that ECC circuitry 225 can compare the first set of ECC check bits to the second set of ECC check bits. In this way, on-die ECC circuitry can detect and / or correct one or more errors in data read from memory array 210.

[0039] In some cases, host device 270 can test memory device 205 to confirm (validate) on-die ECC functionality by a write command followed by a read command. For example, host device 270 can instruct memory device 205 to invert (poison, corrupt) one or more bit locations during a write operation. As described above, prior to transmission of the write command, host device 270 can access register 220 (e.g., through peripheral circuitry 215) to program the one or more bit locations to invert during the write operation. In some embodiments, host device 270 can transmit one or more multi-purpose commands (and / or one or more MRW commands) prior to transmission of the write command to instruct the one or more bit locations. In this way, host device 270 can control (specify) memory device 205 as to which bits to invert with respect to a write operation that memory device 205 is to perform in response to receiving a write command that provides data (external data) and an address to write the data to memory array 210.

[0040] In some embodiments, peripheral circuitry 215 can receive a write command from host device 270 directed to external data (e.g., a first set of data, 128 bits of external data over I / O bus 245). Peripheral circuitry 215 can introduce the external data onto data path 250 in conjunction with I / O circuitry 235. ECC circuitry 225 can use the external data to compute a first set of ECC check bits to produce a codeword including the external data and the first set of ECC check bits. Peripheral circuitry 215 can invert (poison, corrupt) one or more bits of the codeword corresponding to one or more bit locations that have been instructed by host device 270 to memory device 205. In this way, peripheral circuitry 215 can “poison” the codeword (e.g., produce a second set of data including one or more inverted bits) in accordance with the instruction provided by host device 270. Figure 201 illustrates the poisoning with an arrow 275 on data path 255. As a result of the poisoning, data path 255 carries the “poisoned” codeword such that peripheral circuitry 215 can write the “poisoned” codeword to an address of memory array 210.

[0041] Subsequently, the host device 270 can transmit a read command including the address of the memory array 210 to the memory device 205. The peripheral circuitry 215 can read the "poisoned" codeword from the memory array 210. As a result of reading the "poisoned" codeword, the data path 260 provides the "poisoned" codeword to the ECC circuit 225. The peripheral circuitry 215 in conjunction with the ECC circuit 225 can detect one or more errors in the "poisoned" codeword (e.g., the second set of data including one or more inverted bits). In some embodiments, the ECC circuit 225 can use the codeword read from the memory array 210 (e.g., the outer data portion of the codeword) to compute a second set of ECC check bits and compare the second set of ECC check bits of the codeword to the first set of ECC check bits. The peripheral circuitry 215 in conjunction with the ECC circuit 225 can correct one or more errors from the "poisoned" codeword. In this way, the peripheral circuitry 215 can generate the outer data from the "poisoned" codeword read from the memory array 210. As a result of correcting one or more errors from the "poisoned" codeword, the data path 265 can provide the I / O circuit 235 with the outer data that the host device 270 had intended to write, despite the poisoning of the outer data, e.g., the data transmitted to the host device 270 via the data path 265 includes bits that match the data received from the host device 270 via the data path 250. Subsequently, the peripheral circuitry 215 can transmit the outer data back to the host device 270 over the I / O bus 245. In this way, the host device 270 can confirm (validate) the on-die ECC functionality.

[0042] Figure 2B is a block diagram 202 schematically illustrating the memory device 205. The diagram 202 describes that the host device 270 can test the memory device 205 to confirm (validate) on-die ECC functionality by a read command. As described herein, the host device 270 can have instructed the memory device 205 to invert (poison, corrupt) one or more bit positions during a read operation, e.g., by programming the register 220, by transmitting an MPC (and / or MRW command) to the memory device 205, or both. Thus, in response to receiving a read command to read data from an address of the memory array 210, the host device 270 can control (specify) the memory device 205 as to which bits to invert (poison, corrupt) with respect to the read operation that the memory device 205 will perform.

[0043] In some embodiments, peripheral circuitry 215 can receive a read command directed to data (e.g., a first set of data, 128 bits of data) written in an address of memory array 210 (e.g., over command / address bus 240). In this regard, host device 270 can have written a codeword associated with the data to the address, e.g., a codeword including the data and a first set of ECC check bits computed using the data. Accordingly, peripheral circuitry 215 can read the codeword from the address and invert (poison, corrupt) one or more bits of the codeword read from memory array 210, e.g., one or more bits of the data read from memory array 210, where the one or more bits correspond to one or more bit positions that have been indicated by host device 270 to memory device 205. In this way, peripheral circuitry 215 can “poison” the codeword (e.g., generate a second set of data including one or more inverted bits) according to the indication provided by host device 270. Figure 202 illustrates the poisoning with arrows 275 labeled on data path 260. As a result of the poisoning, data path 260 carries the “poisoned” codeword such that ECC circuit 225 receives the “poisoned” codeword.

[0044] ECC circuit 225 can use the “poisoned” codeword (e.g., using the data including one or more inverted bits) to compute a second set of ECC check bits. Further, ECC circuit 225 can compare the first set of ECC check bits to the second set of ECC check bits. In this way, ECC circuit 225 can detect one or more errors in the “poisoned” codeword and correct the one or more errors from the “poisoned” codeword. As a result of correcting the one or more errors from the “poisoned” codeword, data path 265 can provide the data written in memory array 210 to I / O circuit 235, despite the poisoning of the data read from memory array 210. Subsequently, peripheral circuitry 215 can transmit the data to host device 270 over I / O bus 245. In this way, host device 270 can confirm (validate) on-die ECC functionality.

[0045] Figure 2Cis a block diagram 203 schematically illustrating the memory device 205. The diagram 203 describes that the host device 270 can cause the memory device 205 to poison external data during a write operation such that the host device 270 can receive the poisoned external data from the memory device 205. In this way, the host device 270 can test (validate, confirm) system-level ECC functionality using the poisoned data received from the memory device 205. As described herein, the host device 270 can have instructed the memory device 205 to invert (poison, corrupt) one or more bit positions during a write operation, e.g., by programming the register 220, by transmitting an MPC (and / or MRW command) to the memory device 205, or both. Thus, in response to receiving a write command that provides external data and an address of the memory array 210 to write the external data, the host device 270 can control (specify) the memory device 205 as to which bits to invert during the write operation that the memory device 205 will perform.

[0046] In some embodiments, the peripheral circuitry 215 can receive a write command from the host device 270 directed to external data (e.g., a first set of data, 128 bits of external data over the I / O bus 245) (e.g., over the command / address bus 240). The peripheral circuitry 215 can introduce the first set of data onto the data path 250 in conjunction with the I / O circuitry 235. The peripheral circuitry 215 can invert one or more bits of the external data corresponding to one or more bit positions that have been indicated by the host device 270 to the memory device 205. In this way, the peripheral circuitry 215 can “cause” the external data to be “poisoned” in accordance with the indication provided by the host device 270. The diagram 203 illustrates the poisoning with an arrow 275 on the data path 250. As a result of the poisoning, the data path 250 provides the “poisoned” external data to the ECC circuitry 225. The ECC circuitry 225 can compute a first set of ECC check bits using the “poisoned” external data to generate a codeword that includes the “poisoned” external data and the first set of ECC check bits. The peripheral circuitry 215 can write the codeword to an address of the memory array 210, where the address is included in the write command.

[0047] Subsequently, host device 270 can transmit a read command including an address of memory array 210 to memory device 205. Peripheral circuitry 215 can read the codeword from memory array 210. As a result of reading the codeword, data path 260 provides ECC circuit 225 with the codeword including the “poisoned” external data and the first set of ECC check bits. ECC circuit 225 can compute a second set of ECC check bits using the “poisoned” external data read from memory array 210. Further, ECC circuit 225 can compare the first set of ECC check bits read from memory array 210 with the second set of ECC check bits. As both the first set of ECC check bits and the second set of ECC check bits are computed from the “poisoned” external data, ECC circuit 225 can not detect any errors in the “poisoned” external data read from memory array 210. Accordingly, data path 265 can provide the “poisoned” external data to I / O circuit 235. Peripheral circuitry 215 can transmit the “poisoned” external data to host device 270 over I / O bus 245. In this way, host device 270 can receive the “poisoned” data from memory device 205 such that host device 270 can confirm (validate, verify) system-level ECC functionality using the “poisoned” data.

[0048] Figure 2D FIG. 204 is a block diagram 204 schematically illustrating memory device 205. FIG. 204 describes that host device 270 can cause memory device 205 to poison data during a read operation such that host device 270 can receive poisoned data from memory device 205. In this way, host device 270 can test (confirm, validate) system-level ECC functionality using the poisoned data received from memory device 205. As described herein, host device 270 can have instructed memory device 205 to invert (poison, corrupt) one or more bit positions during a read operation, e.g., by programming register 220, by transmitting an MPC (and / or MRW command) to memory device 205, or both. Accordingly, in response to receiving a read command providing an address of memory array 210, host device 270 can control (specify) memory device 205 as to which bits to invert during a read operation that memory device 205 is to perform.

[0049] In some embodiments, the peripheral circuitry 215 can receive a read command (e.g., over the command / address bus 240) directed to data (e.g., a first set of data, 128 bits of data) written to an address of the memory array 210. In this regard, the host device 270 can have written a codeword associated with the data to the address, e.g., a codeword including the data and a first set of ECC check bits computed using the data. The peripheral circuitry 215 can export the data to the data path 265 after the ECC circuit 225 checks the codeword read from the address for errors, e.g., computes a second set of ECC check bits using the data read from the memory array 210, compares the first set of ECC check bits to the second set of ECC check bits. Since both the first set of ECC check bits and the second set of ECC check bits are computed based on the data, the ECC circuit 225 can not detect any errors in the codeword read from the memory array 210.

[0050] The peripheral circuitry 215 can invert one or more bits of the data corresponding to one or more bit positions that have been indicated by the host device 270 to the memory device 205. In this way, the peripheral circuitry 215 can “poison” the data according to the indication provided by the host device 270 prior to transmitting the data to the host device 270. Figure 204 illustrates the poisoning with an arrow 275 on the data path 265. As a result of the poisoning, the data path 265 provides the “poisoned” data to the I / O circuit 235. The peripheral circuitry 215 can transmit the “poisoned” data to the host device 270 over the I / O bus 245. In this way, the host device 270 can receive the “poisoned” data from the memory device 205 such that the host device 270 can confirm (validate, verify) system-level ECC functionality using the “poisoned” data.

[0051] Figure 3 is a block diagram of a system 301 having a memory device 300 configured in accordance with an embodiment of the technology. The memory device 300 can be an example of the memory device described with reference to Figure 1 and 2A to 2D. As shown, the memory device 300 includes a main memory 302 (e.g., DRAM, NAND flash, NOR flash, FeRAM, PCM, etc.), registers 315, and control circuitry 306 operably coupled to a host device 308 (e.g., an upstream central processing unit (CPU), a memory controller). The registers 315 can be an example of, or include aspects of, the registers 118 and / or the registers 220. The control circuitry 306 can include aspects of the control circuitry 106 described with reference to Figure 1 and 2AAspects of the various components described to 2D. For example, control circuitry 306 can include aspects of command / address input circuitry 105, address decoders 110, command decoders 115 and / or 230, ECC circuitry 225, peripheral circuitry 215, etc.

[0052] Main memory 302 includes a plurality of memory units 320, each including a plurality of memory cells. Memory units 320 can be individual memory dies, memory planes in a single memory die, a stack of memory dies connected vertically with through-silicon vias (TSVs), etc. For example, in one embodiment, each of memory units 320 can be formed by a semiconductor die and arranged with other memory unit dies in a single device package. In other embodiments, multiple memory units 320 can be co-located on a single die and / or distributed across multiple device packages. In some embodiments, memory units 320 can also be subdivided into memory regions 328 (e.g., banks, ranks, channels, blocks, pages, etc.).

[0053] Memory units can include, for example, floating gate, charge trap, phase change, capacitive, ferroelectric, magnetoresistive, and / or other suitable storage elements configured to store data persistently or semi-persistently. Main memory 302 and / or individual memory units 320 can also include other circuit components, such as multiplexers, decoders, buffers, read / write drivers, address registers, data output / data input registers, etc., for accessing and / or programming (e.g., writing) memory cells and other functions, such as for processing information and / or communicating with control circuitry 306 or host device 308. Although a certain number of memory cells, rows, columns, regions, and memory units are shown in the illustrated embodiments for purposes of illustration, the number of memory cells, rows, columns, regions, and memory units can vary and can be larger or smaller in scale than shown in the illustrated examples. For example, in some embodiments, memory device 300 can include only one memory unit 320. Alternatively, memory device 300 can include two, three, four, eight, ten, or more (e.g., 16, 32, 64, or more) memory units 320. Although memory units 320 are shown as each including four memory regions 328 in Figure 3 In other embodiments, each memory unit 320 can include one, two, three, eight, or more (e.g., 16, 32, 64, 100, 128, 256, or more) memory regions.

[0054] In one embodiment, the control circuitry 306 can be disposed on the same die as the main memory 302 (e.g., including command / address / clock input circuitry, decoders, voltage and timing generators, input / output circuitry, etc.). In another embodiment, the control circuitry 306 can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), control circuitry on a memory die, etc.), or other suitable processor. In one embodiment, the control circuitry 306 can include a processor configured to execute instructions stored in memory to perform various processes, logic flows, and routines that are used to control operation of the memory device 300, including managing the main memory 302 and handling communications between the memory device 300 and the host device 308. In some embodiments, the control circuitry 306 can include embedded memory having memory registers for storing, for example, memory addresses, row counters, bank counters, memory pointers, fetched data, etc. In another embodiment of the present technology, the memory device 300 can not include control circuitry and can instead rely on external control (e.g., provided by the host device 308 or by a processor or controller separate from the memory device 300).

[0055] The host device 308 can be any of a number of electronic devices capable of using memory for the temporary or persistent storage of information, or components thereof. For example, the host device 308 can be a computing device such as a desktop or portable computer, a server, a handheld device (e.g., a mobile phone, a tablet computer, a digital reader, a digital media player), or some component thereof (e.g., a central processing unit, a co-processor, a dedicated memory controller, etc.). The host device 308 can be a networking device (e.g., a switch, a router, etc.) or a recorder of digital images, audio, and / or video, a vehicle, an appliance, a toy, or any of a number of other products. In one embodiment, the host device 308 can be directly connected to the memory device 300, but in other embodiments, the host device 308 can be indirectly connected to the memory device (e.g., via a network connection or through an intermediary device).

[0056] In operation, the control circuitry 306 can directly write to or otherwise program (e.g., erase) individual memory regions of the main memory 302. The control circuitry 306 communicates with the host device 308 via a host device bus or interface 310. In some embodiments, the host device 308 and the control circuitry 306 can communicate via a dedicated memory bus (e.g., a DRAM bus). In other embodiments, the host device 308 and the control circuitry 306 can communicate via a serial interface, such as a Serial Attached SCSI (SAS), a Serial AT Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe), or other suitable interface (e.g., a parallel interface). The host device 308 can send various requests (in the form of, e.g., packets or packet streams) to the control circuitry 306. The requests can include commands to read, write, erase, return information, and / or perform certain operations (e.g., a refresh operation, a TRIM operation, a precharge operation, an activate operation, a wear leveling operation, a garbage collection operation, etc.).

[0057] In some embodiments, the memory device 300 can receive a command from the host device 308 coupled with the memory device 300 that is directed to a first set of data. The first set of data can refer to external data provided by the host (if the command corresponds to a write command) or external data written into the memory array 150 (if the command corresponds to a read command). The memory device 300 can generate a second set of data from the first set of data, where the second set of data includes one or more inverted (e.g., corrupted, poisoned) bits corresponding to one or more bit locations that the host device has indicated to the memory device 300 (e.g., via a multi-purpose command, an MRW command, or any command that writes to the registers 315 of the memory device 300). The second set of data can refer to a codeword generated based on the external data (if the command corresponds to a write command) or a codeword read from the memory array (if the command corresponds to a read command). Subsequently, the memory device 300, in conjunction with the on-die ECC circuit, can detect one or more errors based on the one or more inverted bits in the second set of data. Subsequently, the memory device 300, in conjunction with the on-die ECC circuit, can correct the one or more errors, thereby generating a first set of data that removes the poison, and transmit the first set of data to the host device. In this way, the host device 308 can test the on-die ECC circuit by controlling which bits are poisoned during a write operation or a read operation and receiving unpoisoned data from the memory device 300 to confirm (validate) its functionality.

[0058] Figure 4 is a flow diagram 400 illustrating a method of operating a memory device, in accordance with an embodiment of the technology. The flow diagram 400 can be as described with reference to Figures 1 to 3Examples of methods that the described memory devices (e.g., peripheral circuitry 215, control circuitry 306) can perform, or aspects that include the methods. The flowchart 400 can include as Figure 2A and 2B aspects of checking on-die ECC functionality are described.

[0059] The method includes receiving, at a memory device, a command from a host device coupled with the memory device, the command directed to a first set of data (block 410). According to one aspect of the present technology, the receiving feature of block 410 can be performed by the peripheral circuitry 215 (or control circuitry 306), as described with reference to Figures 2A to 2B and 3.

[0060] The method further includes generating, from the first set of data, a second set of data that includes one or more bits inverted based on one or more bit locations indicated to the memory device (block 415). According to one aspect of the present technology, the generating feature of block 415 can be performed by the peripheral circuitry 215 (or control circuitry 306), as described with reference to Figures 2A to 2B and 3.

[0061] The method further includes detecting one or more errors in the second set of data based at least in part on the one or more inverted bits (block 420). According to one aspect of the present technology, the detecting feature of block 420 can be performed by the peripheral circuitry 215 (or control circuitry 306) in conjunction with the ECC circuit 225, as described with reference to Figures 2A to 2B and 3.

[0062] The method further includes correcting the one or more errors in the second set of data to generate a third set of data that includes bits matching the first set of data (block 425). According to one aspect of the present technology, the correcting feature of block 425 can be performed by the peripheral circuitry 215 (or control circuitry 306) in conjunction with the ECC circuit 225, as described with reference to Figures 2A to 2B and 3.

[0063] The method further includes transmitting the third set of data generated from the second set of data and including bits matching the first set of data to the host device (block 430). According to one aspect of the present technology, the transmitting feature of block 430 can be performed by the peripheral circuitry 215 (or control circuitry 306), as described with reference to Figures 2A to 2B and 3.

[0064] In some embodiments, the one or more registers of the memory device are programmed by the host device to include the one or more bit locations prior to receiving the command. In some embodiments, the one or more bit locations are indicated to the memory device by one or more commands transmitted from the host device to the memory device to program the registers of the memory device prior to receiving the command. In some embodiments, the command corresponds to a write command that provides the first set of data, and generating the second set of data from the first set of data further comprises calculating error correction code (ECC) check bits using the first set of data, wherein the second set of data includes the first set of data and the ECC check bits, and inverting one or more bits of the second set of data corresponding to the one or more bit locations.

[0065] In some embodiments, the method can further include writing the second set of data to a memory array of the memory device, the write command including an address for writing the second set of data to the memory array. In some embodiments, the method can further include receiving a read command from the host device, the read command including the address, and reading the second set of data from the memory array in response to receiving the read command, wherein detecting the one or more errors in the second set of data corresponds to detecting the one or more errors in the second set of data read from the memory array.

[0066] In some embodiments, the command corresponds to a read command that reads the first set of data from a memory array of the memory device, and generating the second set of data from the first set of data further comprises reading the first set of data and a first set of ECC check bits from an address of the memory array included in the read command, calculating the first set of ECC check bits using the first set of data, and inverting one or more bits of the first set of data read from the memory array and the first set of ECC check bits, the one or more bits corresponding to the one or more bit locations, wherein the second set of data includes the first set of data with the one or more inverted bits and the first set of ECC check bits.

[0067] In some embodiments, the method can further include calculating a second set of ECC check bits using the second set of data, and comparing the first set of ECC check bits to the second set of ECC check bits. In some embodiments, detecting the one or more errors in the second set of data is based at least in part on comparing the first set of ECC check bits to the second set of ECC check bits.

[0068] Figure 5 is a flow diagram 500 illustrating a method of operating a memory device in accordance with an embodiment of the technology. The flow diagram 500 can be an example of or include aspects of a method a memory device (e.g., peripheral circuitry 215, control circuitry 306) can perform as described with reference to Figures 1 to 3 The flow diagram 500 can include aspects of a method a memory device (e.g., peripheral circuitry 215, control circuitry 306) can perform as described with reference to Figure 2C and 2DAspects described provide poisoned data for checking system-level ECC functionality.

[0069] The method includes receiving a command at a memory device from a host device coupled with the memory device, the command directed to a first set of data (block 510). According to one aspect of the present technology, the receiving feature of block 510 can be performed by the peripheral circuitry 215 (or control circuitry 306), as described with reference to Figures 2C to 2D and 3.

[0070] The method further includes inverting one or more bits of the first set of data based on one or more bit locations indicated to the memory device by the host device using one or more registers of the memory device, one or more commands used to program the one or more registers of the memory device, or both (block 515). According to one aspect of the present technology, the inverting feature of block 515 can be performed by the peripheral circuitry 215 (or control circuitry 306), as described with reference to Figures 2C to 2D and 3.

[0071] The method further includes transmitting the first set of data with the one or more inverted bits to the host device (block 520). According to one aspect of the present technology, the transmitting feature of block 520 can be performed by the peripheral circuitry 215 (or control circuitry 306), as described with reference to Figures 2C to 2D and 3.

[0072] In some embodiments, the command corresponds to a write command that provides the first set of data, and the method can further include calculating an error correction code (ECC) check bit set using the first set of data with the one or more inverted bits; and writing the first set of data with the one or more inverted bits and the ECC check bit set to an address of a memory array of the memory device, the write command including the address. In some embodiments, the method can further include, after writing the first set of data with the one or more inverted bits to the address, receiving a read command from the host device, the read command including the address; and in response to receiving the read command, reading the first set of data with the one or more inverted bits from the memory array, wherein transmitting the first set of data with the one or more inverted bits corresponds to transmitting the first set of data with the one or more inverted bits read from the memory array. In some embodiments, the ECC check bit set is a first ECC check bit set, and the method can further include calculating a second ECC check bit set using the first set of data with the one or more inverted bits read from the memory array; and comparing the first ECC check bit set to the second ECC check bit set prior to transmitting the first set of data with the one or more inverted bits to the host device.

[0073] In some embodiments, the command corresponds to a read command to read a first set of data from a memory array of the memory device, and the method can further include: reading the first set of data and a first set of ECC check bits from an address of the memory array included in the read command, calculating the first set of ECC check bits using the first set of data; calculating a second set of ECC check bits using the first set of data read from the memory array; and comparing the first set of ECC check bits to the second set of ECC check bits. In some embodiments, inverting one or more bits of the first set of data corresponds to inverting one or more bits of the first set of data read from the memory array after comparing the first set of ECC check bits to the second set of ECC check bits.

[0074] It should be noted that the methods described above describe possible implementations, and that the operations and the steps can be rearranged or otherwise modified and that other implementations are possible. Furthermore, two or more embodiments from the methods can be combined.

[0075] Information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some drawings can illustrate signals as single signals; however, it will be understood by a person of ordinary skill in the art that the signals can be represented by a bus of signals where the bus can have a variety of bit widths.

[0076] Devices discussed herein that include a memory device can be formed on a semiconductor substrate or die, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate can be a silicon-on-insulator (SOI) substrate, such as a silicon-on-glass (SOG) or a silicon-on-sapphire (SOS), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or sub-regions of the substrate can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. The doping can be performed during initial formation or growth of the substrate, by ion implantation, or by any other doping method.

[0077] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. Other examples and implementations are within the scope of the disclosure and appended claims. Features implementing functions can also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations.

[0078] As used herein, including in the claims, "or" used in a list of items (e.g., a list of items beginning with a phrase such as "at least one of" or "one or more of") indicates an inclusive list, such that a list such as at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted similarly to the phrase "based at least in part on."

[0079] It will be appreciated from the foregoing that specific embodiments of the present invention have been described herein for illustrative purposes, but various modifications may be made without departing from the scope of the present invention. On the contrary, in the foregoing description, many specific details are discussed to provide a thorough and illustrative description of embodiments of the present invention. However, those skilled in the relevant art will recognize that the present disclosure may be practiced without one or more of the specific details. In other cases, well-known structures or operations typically associated with memory systems and devices are not shown or described in detail to avoid obscuring other aspects of the technology. In general, it will be understood that various other devices, systems, and methods other than those specific embodiments disclosed herein may be within the scope of the present invention.

Claims

1. A correction method, comprising: receiving a command at a memory device from a host device coupled with the memory device, the command directed to a first set of data; generating a second set of data from the first set of data, the second set of data including one or more bits inverted based on one or more bit positions indicated to the memory device; detecting one or more errors in the second set of data based at least in part on the one or more inverted bits; correcting the one or more errors in the second set of data to generate a third set of data comprising bits matching the first set of data; and transmitting the third set of data generated from the second set of data and comprising the bits matching the first set of data to the host device, wherein one or more registers of the memory device are programmed by the host device prior to receiving the command to include the one or more bit positions.

2. The correction method of claim 1, wherein the one or more bit positions are indicated to the memory device by one or more commands transmitted from the host device to the memory device for programming the one or more registers of the memory device prior to receiving the command.

3. The correction method of claim 1, wherein the command corresponds to a write command providing the first set of data, and generating the second set of data from the first set of data further comprises: calculating error correction code (ECC) check bits using the first set of data, wherein the second set of data includes the first set of data and the ECC check bits; and inverting the one or more bits of the second set of data corresponding to the one or more bit positions.

4. The correction method of claim 3, further comprising: writing the second set of data to a memory array of the memory device, the write command including an address of the memory array for writing the second set of data.

5. The correction method of claim 4, further comprising: receiving a read command from the host device, the read command including the address; and in response to receiving the read command, reading the second set of data from the memory array, wherein detecting the one or more errors in the second set of data corresponds to detecting the one or more errors in the second set of data read from the memory array.

6. The correction method of claim 1, wherein the command corresponds to a read command reading the first set of data from a memory array of the memory device, and generating the second set of data from the first set of data further comprises: reading the first set of data and a first set of ECC check bits from an address of the memory array included in the read command, the first set of ECC check bits calculated using the first set of data; and inverting the one or more bits of the second set of data corresponding to the one or more bit positions. ​ ​ inverting the one or more bits of the first data set read from the memory array and the first set of ECC check bits, the one or more bits corresponding to the one or more bit positions, wherein the second data set includes the first data set with the one or more inverted bits and the first set of ECC check bits.

7. The correction method of claim 6, further comprising: calculating a second set of ECC check bits using the second data set; and comparing the first set of ECC check bits to the second set of ECC check bits.

8. The correction method of claim 7, wherein detecting the one or more errors in the second data set is based at least in part on comparing the first set of ECC check bits to the second set of ECC check bits.

9. A correction method, comprising: receiving, at a memory device, a command from a host device coupled with the memory device, the command directed to a first data set; inverting one or more bits of the first data set based on one or more bit positions indicated to the memory device by the host device using one or more registers of the memory device, one or more commands used to program the one or more registers of the memory device transmitted to the memory device, or both; and transmitting the first data set with the one or more inverted bits to the host device.

10. The correction method of claim 9, wherein the command corresponds to a write command that provides the first data set, the correction method further comprising: calculating an error correction code (ECC) check bit set using the first data set with the one or more inverted bits; and writing the first data set with the one or more inverted bits and the ECC check bit set to an address of a memory array of the memory device, the write command including the address.

11. The correction method of claim 10, further comprising: after writing the first data set with the one or more inverted bits to the address, receiving a read command from the host device, the read command including the address; and in response to receiving the read command, reading the first data set with the one or more inverted bits from the memory array, wherein transmitting the first data set with the one or more inverted bits corresponds to transmitting the first data set with the one or more inverted bits read from the memory array.

12. The correction method of claim 11, wherein the ECC check bit set is a first ECC check bit set, the correction method further comprising: calculating a second ECC check bit set using the first data set with the one or more inverted bits read from the memory array; and comparing the first ECC check bit set to the second ECC check bit set prior to transmitting the first data set with the one or more inverted bits to the host device.

13. The correction method of claim 9, wherein the command corresponds to a read command to read the first data set from a memory array of the memory device, the correction method further comprising: reading the first data set and a first set of ECC check bits from an address of the memory array included in the read command, the first set of ECC check bits calculated using the first data set; calculating a second set of ECC check bits using the first data set read from the memory array; and comparing the first set of ECC check bits to the second set of ECC check bits.

14. The correction method of claim 13, wherein inverting the one or more bits of the first data set corresponds to inverting the one or more bits of the first data set read from the memory array after comparing the first set of ECC check bits to the second set of ECC check bits.

15. A correction apparatus comprising: a memory array; peripheral circuitry coupled with the memory array, the peripheral circuitry configured to: receive a command from a host device coupled with the correction apparatus, the command directed to a first data set; generate a second data set from the first data set, the second data set including one or more bits inverted based on one or more bit positions indicated to the correction apparatus; detect one or more errors in the second data set based at least in part on the one or more inverted bits; correct the one or more errors in the second data set to generate a third data set comprising bits matching the first data set; and transmit the third data set generated from the second data set and comprising the bits matching the first data set to the host device; and one or more registers configured to include the one or more bit positions based at least in part on an indication from the host device.

16. The correction apparatus of claim 15, further comprising: a command decoder configured to determine the one or more bit positions based at least in part on one or more commands transmitted from the host device to program the one or more registers of the correction apparatus.

17. The correction apparatus of claim 15, wherein the peripheral circuitry is further configured to: calculate error correction code (ECC) check bits using the first data set with a write command from the host device, wherein the second data set includes the first data set and the ECC check bits; and invert the one or more bits of the second data set corresponding to the one or more bit positions.

18. The correction apparatus of claim 15, wherein the peripheral circuitry is further configured to: read the first data set and a first set of ECC check bits from an address of the memory array included in a read command from the host device, the first set of ECC check bits calculated using the first data set; and calculate a second set of ECC check bits using the first data set read from the memory array; and inversing the one or more bits of the first data set read from the memory array and the first set of ECC check bits, the one or more bits corresponding to the one or more bit positions, wherein the second data set includes the first data set with the one or more inverted bits and the first set of ECC check bits.

Images