Method of manufacturing a semiconductor device and semiconductor device

Abstract

According to an aspect of the present invention, in a method of manufacturing a semiconductor device, a fin structure in which a first semiconductor layer and a second semiconductor layer are alternately stacked is formed. A sacrificial gate structure is formed over the fin structure. A first capping layer is formed over the sacrificial gate structure and a second capping layer is formed over the first capping layer. A source / drain epitaxial layer is formed. After forming the source / drain epitaxial layer, the second capping layer is removed, thereby forming a gap between the source / drain epitaxial layer and the first capping layer, and a part of the fin structure is exposed from the gap. A part of the first semiconductor layer in the gap is removed, thereby forming a spacer between the second semiconductor layers. The spacer is filled with a first insulating material. Embodiments of the present invention relate to a method of manufacturing a semiconductor device and a semiconductor device.

Description

[0001] This application is a divisional application of the invention patent application with the application number 201711106303.1 and the title of "Method for Manufacturing Semiconductor Devices and Semiconductor Devices", which was filed on November 10, 2017. Technical Field

[0002] Embodiments of the present invention relate to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method and a semiconductor device for manufacturing a semiconductor device including a fin field effect transistor (FinFET) and / or a gate-all-around FET. Background Art

[0003] As the semiconductor industry enters the nanotechnology process node in the pursuit of higher device density, higher performance, and lower cost, challenges from manufacturing and design issues have led to the development of three-dimensional designs such as multi-gate field effect transistors (FETs) (including fin FETs (Fin FETs) and gate-all-around (GAA) FETs). In a Fin FET, the gate electrode is adjacent to three sides of the channel region, and a gate dielectric layer is inserted between the gate electrode and the channel region. Since the gate structure surrounds (wraps) the fin from three surfaces, the transistor essentially has three gates for controlling the current flowing through the fin or the channel region. Unfortunately, the bottom (fourth side) of the channel region is far from the gate electrode and is thus not under the control of the enclosed gate. In contrast, in a GAA FET, all sides of the channel region are surrounded by the gate electrode, which allows for more complete depletion in the channel region and results in fewer short-channel effects due to a steeper subthreshold swing (SS) and a smaller drain-induced barrier lowering (DIBL). As the transistor size continues to scale down to sub-10-15 nm technology nodes, further improvements to GAA FETs are needed. Summary of the Invention

[0004] According to some embodiments of the present invention, a method for manufacturing a semiconductor device is provided, including: forming a fin structure in which a first semiconductor layer and a second semiconductor layer are alternately stacked; forming a sacrificial gate structure above the fin structure; forming a first capping layer above the sacrificial gate structure and a second capping layer above the first capping layer; forming source / drain epitaxial layers on opposite sides of the sacrificial gate structure; after forming the source / drain epitaxial layers, removing the second capping layer, thereby forming a gap between the source / drain epitaxial layer and the first capping layer, and exposing a portion of the fin structure from the gap; removing a portion of the first semiconductor layer located in the gap, thereby forming a spacer between the second semiconductor layers; and filling the spacer with a first insulating material.

[0005] According to some other embodiments of the present invention, there is also provided a method of manufacturing a semiconductor device, including: forming a fin structure in which a first semiconductor layer and a second semiconductor layer are alternately stacked; forming a sacrificial gate structure over the fin structure; forming a first capping layer over the sacrificial gate structure and forming a second capping layer over the first capping layer; removing the second semiconductor layer from a portion of the fin structure not covered by the sacrificial gate structure, thereby forming a source / drain layer including the first semiconductor layer; forming a source / drain epitaxial layer over the source / drain layer; after forming the source / drain epitaxial layer, removing the second capping layer, thereby forming a gap between the source / drain epitaxial layer and the first capping layer and exposing a portion of the fin structure from the gap; removing a portion of the second semiconductor layer located in the gap, thereby forming a space between the first semiconductor layers; and filling the space with a first insulating material.

[0006] According to some further embodiments of the present invention, there is also provided a semiconductor device, including: a first semiconductor wire disposed over a substrate; a first source / drain region in contact with an end of the first semiconductor wire; a gate dielectric layer disposed over each channel region of the first semiconductor wire and surrounding each channel region of the first semiconductor wire; a gate electrode layer disposed over the gate dielectric layer and surrounding each channel region; and first insulating spacers respectively disposed in spaces defined by adjacent first semiconductor wires, the gate electrode layer, and the first source / drain region, wherein end faces of the first insulating spacers in contact with the first source / drain region are vertically aligned. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, according to standard practice in the industry, the various components are not drawn to scale and are for illustrative purposes only. In fact, for the sake of clear discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figures 1A to 1D Various views of a semiconductor FET device according to an embodiment of the present invention are shown. Figure 1A is a perspective view, Figure 1B is corresponding to Figure 1A a cross-sectional view taken along Y1-Y1, Figure 1C is corresponding to Figure 1A a cross-sectional view taken along Y2-Y2, Figure 1D shows a cross-sectional view taken along X1-X1 corresponding to Figure 1C and Figure 1E shows a cross-sectional view taken along X2-X2 corresponding to Figure 1C X2-X2.

[0009] Figure 2 Shows one of the stages of manufacturing a semiconductor FET device according to an embodiment of the present invention.

[0010] Figure 3 Shows one of the stages of manufacturing a semiconductor FET device according to an embodiment of the present invention.

[0011] Figure 4 Shows one of the stages of manufacturing a semiconductor FET device according to an embodiment of the present invention.

[0012] Figure 5 Shows one of the stages of manufacturing a semiconductor FET device according to an embodiment of the present invention.

[0013] Figure 6 Shows one of the stages of manufacturing a semiconductor FET device according to an embodiment of the present invention.

[0014] Figure 7 Shows one of the stages of manufacturing a semiconductor FET device according to an embodiment of the present invention.

[0015] Figure 8 Shows one of the stages of manufacturing a semiconductor FET device according to an embodiment of the present invention.

[0016] Figure 9 Shows one of the stages of manufacturing a semiconductor FET device according to an embodiment of the present invention.

[0017] Figures 10A to 10D Shows one of the stages of manufacturing a semiconductor FET device according to an embodiment of the present invention. Figure 10A Is a perspective view, Figure 10B Is a cross-sectional view along the X direction, Figure 10C Is a cross-sectional view along the Y direction, and Figure 10D Shows another perspective view.

[0018] Figures 11A to 11D Shows one of the stages of manufacturing a semiconductor FET device according to an embodiment of the present invention. Figure 11A Is a perspective view, Figure 11B Is a cross-sectional view along the X direction, Figure 11C Is a cross-sectional view along the Y direction, and Figure 11D Shows another perspective view.

[0019] Figures 12A to 12C Shows one of the stages of manufacturing a semiconductor FET device according to an embodiment of the present invention. Figure 12A Is a perspective view, Figure 12B Is a cross-sectional view along the X direction, and Figure 12CIt is a cross-sectional view along the Y direction.

[0020] Figure 13 It shows one of the various stages of manufacturing a semiconductor FET device according to an embodiment of the present invention.

[0021] Figure 14 It shows one of the various stages of manufacturing a semiconductor FET device according to an embodiment of the present invention.

[0022] Figure 15 It shows one of the various stages of manufacturing a semiconductor FET device according to an embodiment of the present invention.

[0023] Figure 16 It shows one of the various stages of manufacturing a semiconductor FET device according to an embodiment of the present invention.

[0024] Figures 17A to 17E It shows various views of a semiconductor FET device according to other embodiments of the present invention. Figure 17A It is a perspective view, Figure 17B It corresponds to Figure 17A a cross-sectional view of Y1 - Y1, Figure 17C It corresponds to Figure 17A a cross-sectional view of Y2 - Y2, Figure 17D It shows a cross-sectional view corresponding to Figure 17C X1 - X1, and Figure 17E It shows a cross-sectional view corresponding to Figure 17C X2 - X2.

[0025] Figure 18 It shows one of the various stages of manufacturing a semiconductor FET device according to other embodiments of the present invention.

[0026] Figure 19 It shows one of the various stages of manufacturing a semiconductor FET device according to other embodiments of the present invention.

[0027] Figure 20 It shows one of the various stages of manufacturing a semiconductor FET device according to other embodiments of the present invention.

[0028] Figure 21 It shows one of the various stages of manufacturing a semiconductor FET device according to other embodiments of the present invention.

[0029] Figure 22 It shows one of the various stages of manufacturing a semiconductor FET device according to other embodiments of the present invention.

[0030] Figure 23 It shows one of the various stages of manufacturing a semiconductor FET device according to other embodiments of the present invention.

[0031] Figure 24 Shows one of the stages of manufacturing a semiconductor FET device according to other embodiments of the present invention.

[0032] Figure 25 Shows one of the stages of manufacturing a semiconductor FET device according to other embodiments of the present invention.

[0033] Figures 26A to 26D Shows one of the stages of manufacturing a semiconductor FET device according to an embodiment of the present invention. Figure 26A Is a perspective view, Figure 26B Is a cross-sectional view along the X direction, Figure 26C Is a cross-sectional view along the Y direction, and Figure 26D Shows another perspective view.

[0034] Figures 27A to 27D Shows one of the stages of manufacturing a semiconductor FET device according to an embodiment of the present invention. Figure 27A Is a perspective view, Figure 27B Is a cross-sectional view along the X direction, Figure 27C Is a cross-sectional view along the Y direction, and Figure 27D Shows another perspective view.

[0035] Figures 28A to 28C Shows one of the stages of manufacturing a semiconductor FET device according to an embodiment of the present invention. Figure 28A Is a perspective view, Figure 28B Is a cross-sectional view along the X direction, and Figure 28C Is a cross-sectional view along the Y direction.

[0036] Figure 29 Shows one of the stages of manufacturing a semiconductor FET device according to other embodiments of the present invention.

[0037] Figure 30 Shows one of the stages of manufacturing a semiconductor FET device according to other embodiments of the present invention.

[0038] Figure 31 Shows one of the stages of manufacturing a semiconductor FET device according to other embodiments of the present invention.

[0039] Figure 32 Shows one of the stages of manufacturing a semiconductor FET device according to other embodiments of the present invention.

[0040] Figures 33A to 33D Shows various views of a semiconductor FET device according to other embodiments of the present invention. Figure 33A Is a perspective view, Figure 33B Is corresponding to Figure 33ACross-sectional view of Y1 - Y1 Figure 33C is corresponding to Figure 33A Cross-sectional view of Y2 - Y2 Figure 33D shows the cross-sectional view of X1 - X1 corresponding to Figure 33C and Figure 33E shows the cross-sectional view of X2 - X2 corresponding to Figure 33C Cross-sectional view of X2 - X2

[0041] Figures 34A to 34D Shows various views of a semiconductor FET device according to other embodiments of the present invention. Figure 34A Is a perspective view Figure 34B is corresponding to Figure 34A Cross-sectional view of Y1 - Y1 Figure 34C is corresponding to Figure 34A Cross-sectional view of Y2 - Y2 and Figure 34D shows the cross-sectional view of X1 - X1 corresponding to Figure 34C Cross-sectional view of X1 - X1

[0042] Figure 35 Shows one of the various stages of manufacturing a semiconductor FET device according to other embodiments of the present invention.

[0043] Figure 36 Shows one of the various stages of manufacturing a semiconductor FET device according to other embodiments of the present invention.

[0044] Figures 37A to 37C Shows one of the various stages of manufacturing a semiconductor FET device according to an embodiment of the present invention. Figure 37A Is a perspective view Figure 37B Is a cross-sectional view along the X direction and Figure 37C Is a cross-sectional view along the Y direction.

[0045] Figures 38A to 38C Shows one of the various stages of manufacturing a semiconductor FET device according to an embodiment of the present invention. Figure 38A Is a perspective view Figure 38B Is a cross-sectional view along the X direction and Figure 38C Is a cross-sectional view along the Y direction.

[0046] Figures 39A to 39C Shows one of the various stages of manufacturing a semiconductor FET device according to an embodiment of the present invention. Figure 39A Is a perspective view Figure 39B Is a cross-sectional view along the X direction and Figure 39C Is a cross-sectional view along the Y direction.

[0047] Figures 40A to 40C Shows one of the various stages of manufacturing a semiconductor FET device according to an embodiment of the present invention. Figure 40Ais a three-dimensional view, Figure 40B is a cross-sectional view along the X direction, and Figure 40C is a cross-sectional view along the Y direction. Detailed implementation manners

[0048] The following disclosure provides many different embodiments or examples for implementing many different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to limit the present invention. For example, the dimensions of the components are not limited to the disclosed ranges or values, but may depend on process conditions and / or the performance required by the device. In addition, in the following description, forming a first component above or on a second component may include embodiments where the first component and the second component are in direct contact, and may also include embodiments where additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. For simplicity and clarity purposes, the various components may be arbitrarily drawn in different proportions.

[0049] Moreover, for ease of description, spatially relative terms such as "under", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship between one element or component and another (or other) element or component as shown in the figures. In addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. In addition, the term "made of..." may mean "including" or "consisting of...".

[0050] In the present invention, a method for manufacturing an internal spacer between a metal gate electrode and a source / drain epitaxial layer of a GAA FET and a stacked-channel FET is provided. In the present invention, the source / drain refers to the source and / or the drain. The internal spacer can be formed by the following process. After forming a pseudo-gate structure above a stacked fin structure, in which two different semiconductor wires are alternately stacked, the source / drain regions of the stacked fin structure are recessed. Then, an insulating (dielectric) layer is formed in the grooves and then the formed insulating layer is etched to form an internal spacer on the ends of the semiconductor wires. Subsequently, a source / drain epitaxial layer is formed above the internal spacer. It should be noted that in the present invention, the source and the drain can be used interchangeably and their structures are basically the same.

[0051] However, in the above process, it is difficult to precisely control the etching of the insulating layer, and thus it is difficult to precisely control the thickness and position of the internal spacer. In view of this, the present invention provides a method for manufacturing an internal spacer between a metal gate electrode and a source / drain epitaxial layer, which can more precisely control the thickness, shape, and / or position of the internal spacer.

[0052] Figures 1A to 1E Various views of a semiconductor FET device according to an embodiment of the present invention are shown. Figure 1A is a perspective view, Figure 1B is corresponding to Figure 1A a cross-sectional view taken along Y1-Y1, Figure 1C is corresponding to Figure 1A a cross-sectional view taken along Y2-Y2, Figure 1D shows a cross-sectional view corresponding to Figure 1C X1-X1, and Figure 1E shows a cross-sectional view corresponding to Figure 1C X2-X2.

[0053] As Figures 1A to 1E shown, two semiconductor fin structures 11 are provided above a semiconductor substrate 10. In some embodiments, the substrate 10 includes a single-crystal semiconductor layer located at least on its surface portion. The substrate 10 may include a single-crystal semiconductor material such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. In certain embodiments, the substrate 10 is made of crystalline Si.

[0054] The substrate 10 may include one or more buffer layers (not shown) located in its surface region. The buffer layer may be used to gradually change the lattice constant from the lattice constant of the substrate to the lattice constant of the source / drain region. The buffer layer may be formed by epitaxially growing a single-crystal semiconductor material such as, but not limited to, Si, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP, and InP. In a particular embodiment, the substrate 10 includes a silicon germanium (SiGe) buffer layer epitaxially grown on a silicon substrate 10. The germanium concentration of the SiGe buffer layer may increase from 30 atomic % germanium in the bottommost buffer layer to 70 atomic % germanium in the topmost buffer layer.

[0055] The bottom of the fin structure 11 is covered by an insulating layer 35 (fin liner). The fin liner 35 includes one or more layers of insulating material.

[0056] An isolation insulating layer 40, such as a shallow trench isolation (STI), is disposed in a trench above the substrate 10. The isolation insulating layer 40 can be made of a suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric (such as carbon-doped oxide), an ultra-low-k dielectric (such as porous carbon-doped silica), a polymer (such as polyimide), a combination of these, etc. In some embodiments, the isolation insulating layer 40 is formed by processes such as CVD, flowable CVD (FCVD), or spin-on glass process, but any acceptable process can be utilized.

[0057] As Figure 1B shown, a channel layer 25 (as a semiconductor wire) is disposed above the fin structure 11. Each channel layer 25 is surrounded by a gate dielectric layer 102 and a gate electrode layer 104. In some embodiments, the gate dielectric layer 102 includes an interface layer 102A and a high-k dielectric layer 102B. In addition, a gate capping insulating layer 106 is disposed above the gate electrode layer 104.

[0058] As Figure 1A 、 Figure 1C and Figure 1D shown, a source / drain epitaxial layer 80 is disposed above the source / drain regions of the fin structure 11. The source / drain epitaxial layer 80 is covered by an interlayer dielectric (ILD) layer 95. In addition, a first capping layer 51 and / or an insulating layer 85 are formed between the source / drain epitaxial layer 80 and the ILD layer 95 and between the gate electrode 104 and the ILD layer 95. In addition, a source / drain contact 130 is disposed in contact with the source / drain epitaxial layer 80. In some embodiments, the cross-section of the source / drain epitaxial layer 80 has a hexagonal, rhombic, other polygonal, or semi-circular shape.

[0059] Figure 1C is a cross-sectional view of a vertical portion of the insulating layer 85 at a region where the gate electrode 104 and the source / drain epitaxial layer 80 are cut in the Y direction. In this region, the semiconductor wire 25 is at least partially covered by the insulating layer 85. In some embodiments, one or more voids 70 are formed in the insulating layer 85 between the semiconductor wires 25. The cross-sectional shape of the voids 70 includes circular, elliptical (vertically and / or horizontally), teardrop shape, or a rectangle or polygon with rounded corners. In other embodiments, no voids are formed.

[0060] Figure 1D shows a cross-sectional view corresponding to Figure 1C X1 - X1, and Figure 1E shows a cross-sectional view corresponding to Figure 1C X2 - X2. As Figure 1DAs shown, an insulating layer 85 (serving as an internal spacer) is disposed between the end faces of the gate electrode layer 104 and the source / drain epitaxial layer 80. In some embodiments, a gate dielectric layer 102 is disposed between the insulating layer 85 and the gate electrode layer 104. As Figure 1D shown, the end face of the internal spacer 85 in contact with the source / drain epitaxial layer 80 is vertically aligned (disposed in the same vertical plane). Further, the end face of the internal spacer 85 in contact with the source / drain epitaxial layer 80 is also vertically aligned with the interface between the semiconductor wire and the end face of the source / drain epitaxial layer 80. The interface between the gate electrode 104 and the internal spacer 85 has a curved surface protruding toward the gate electrode 104, while the interface between the internal spacer 85 and the source / drain epitaxial layer 80 is substantially flat. As Figure 1E shown, when the void 70 is formed, there is a gap (void) between the end faces of the semiconductor wire 25 and the source / drain epitaxial layer 80. As Figure 1E shown, in this cross-sectional view, the void 70 has one curved side and three substantially straight sides. In some embodiments, the internal spacer 85 is made of a low-k dielectric material such as SiOC and / or SiOCN or any other suitable dielectric material. The low-k dielectric material has a dielectric constant less than that of silicon dioxide.

[0061] In some embodiments, the thickness and width of each semiconductor wire 25 are both in the range from about 5 nm to about 15 nm, and in other embodiments, in the range from about 6 nm to about 12 nm. In some embodiments, the spacing between adjacent semiconductor wires in the Z direction is in the range from about 2 nm to about 6 nm. In some embodiments, the thickness W1 of the internal spacer 85 is in the range from about 2 nm to about 6 nm. The cross-sectional shape of the semiconductor wire 25 in the channel region can be any polygon (square, rectangle, triangle, etc.), a polygon with rounded corners, a circle, or an ellipse (vertically or horizontally).

[0062] In Figures 1A to 1E it, two fin structures 11 and four semiconductor wires 25 are shown. However, the number is not limited thereto. The number of fin structures for each gate can be one, three, four, or more, and the number of semiconductor wires 25 can be one, two, three, and more, up to ten.

[0063] In certain embodiments, Figures 1A to 1E the semiconductor device is an n-type GAA FET. In other embodiments, Figures 1A to 1E the semiconductor device is a p-type GAA FET. In some embodiments, one or more n-type GAA FETs and one or more p-type GAA FETs are provided on the same substrate 10.

[0064] Figures 2 to 16illustrates an exemplary sequential process for manufacturing Figures 1A to 1E the GAAFET shown. It should be understood that additional operations can be provided before, during, and after the Figures 2 to 16 process shown, and for additional embodiments of the method, some of the operations described below can be replaced or eliminated. The order of operations / processes can be interchanged.

[0065] As Figure 2 shown, impurity ions (dopants) 12 are implanted into the silicon substrate 10 to form well regions. Ion implantation is implemented to prevent punch-through effects. The substrate 10 can include various regions that have been appropriately doped with impurities (e.g., p-type or n-type conductivity). The dopant 12 is, for example, boron (BF2) for an n-type Fin FET or phosphorus for a p-type Fin FET.

[0066] After that, as Figure 3 shown, a stacked semiconductor layer is formed over the substrate 10. The stacked semiconductor layer includes a first semiconductor layer 20 and a second semiconductor layer 25. In addition, a mask layer 15 is formed over the stacked layer.

[0067] The first semiconductor layer 20 and the second semiconductor layer 25 are made of materials having different lattice constants and can include one or more layers of Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, or InP.

[0068] In some embodiments, the first semiconductor layer 20 and the second semiconductor layer 25 are made of Si, Si compounds, SiGe, Ge, or Ge compounds. In one embodiment, the first semiconductor layer 20 is Si 1-x Ge x , where x is greater than about 0.3, or Ge (x = 1.0), and the second semiconductor layer 25 is Si or Si 1-y Ge y , where y is less than about 0.4, and x > y. In the present invention, an "M" compound or an "M-based compound" means that most of the compound is M.

[0069] In another embodiment, the second semiconductor layer 25 is Si 1-y Ge y , where y is greater than about 0.3, or Ge, and the first semiconductor layer 20 is Si or Si 1-x Ge x , where x is less than about 0.4, and x < y. In still other embodiments, the first semiconductor layer 20 is made of Si 1-x Ge xfabricated, wherein x ranges from about 0.3 to about 0.8, and the second semiconductor layer 25 is made of Si 1-y Ge y fabricated, wherein y ranges from about 0.1 to about 0.4.

[0070] In Figure 3 four first semiconductor layers 20 and four second semiconductor layers 25 are provided. However, the number of layers is not limited to four and can be as small as 1 (per layer), and in some embodiments, each first semiconductor layer and second semiconductor layer is formed into 2 - 10 layers. By adjusting the number of stacked layers, the drive current of the GAA FET device can be adjusted.

[0071] The first semiconductor layer 20 and the second semiconductor layer 25 are epitaxially formed over the substrate 10. The thickness of the first semiconductor layer 20 can be equal to or greater than the thickness of the second semiconductor layer 25, and in some embodiments, it ranges from about 2 nm to about 20 nm, and in other embodiments, it ranges from about 5 nm to about 15 nm. In some embodiments, the thickness of the second semiconductor layer 25 ranges from about 2 nm to about 20 nm, and in other embodiments, it ranges from about 5 nm to about 15 nm. The thickness of each first semiconductor layer 20 can be the same or can vary.

[0072] In some embodiments, the bottom first semiconductor layer (the layer closest to the substrate 10) is thicker than the remaining first semiconductor layers. In some embodiments, the thickness of the bottom first semiconductor layer ranges from about 10 nm to about 50 nm, or in other embodiments, it ranges from 20 nm to 40 nm.

[0073] In some embodiments, the mask layer 15 includes a first mask layer 15A and a second mask layer 15B. The first mask layer 15A is a pad oxide layer made of silicon oxide (which can be formed by thermal oxidation). The second mask layer 15B is made of silicon nitride (SiN) formed by chemical vapor deposition (CVD) (including low - pressure CVD (LPCVD) and plasma - enhanced CVD (PECVD)), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes. The mask layer 15 is patterned into a mask pattern by using patterning operations including lithography and etching.

[0074] Next, as Figure 4 shown, the stacked layers of the first semiconductor layer 20 and the second semiconductor layer 25 are patterned by using the patterned mask layer, thereby forming the stacked layers into fin structures 30 extending in the X - direction. In Figure 4In [the figure], two fin structures 30 are arranged in the Y direction. However, the number of fin structures is not limited to two, and can be as small as one and three or more. In some embodiments, one or more dummy fin structures are formed on both sides of the fin structure 30 to improve pattern fidelity in the patterning operation. As Figure 4 shown, the fin structure 30 has an upper portion and a well portion 11 composed of stacked semiconductor layers 20, 25.

[0075] In some embodiments, the width W1 of the upper portion of the fin structure in the Y direction ranges from about 10 nm to about 40 nm, and in other embodiments, ranges from about 20 nm to about 30 nm. The height H1 of the fin structure in the Z direction ranges from about 100 nm to about 200 nm.

[0076] The stacked fin structure 30 can be patterned by a suitable method. For example, one or more lithography processes including a double patterning process or a multiple patterning process can be used to pattern the structure. Generally, the double patterning or multiple patterning process combines lithography and self-alignment processes, allowing the creation of patterns having, for example, a smaller pitch than that obtainable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and the sacrificial layer is patterned using a lithography process. A spacer is formed adjacent to the patterned sacrificial layer using a self-alignment process. After that, the sacrificial layer is removed, and then, the remaining spacer can be used to pattern the stacked fin structure 30.

[0077] After forming the fin structure 30, an insulating material layer including one or more layers of insulating material is formed over the substrate such that the fin structure is completely embedded within the insulating layer. The insulating material for the insulating layer can include silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), or a low-k dielectric material formed by LPCVD (low-pressure chemical vapor deposition), plasma CVD, or flowable CVD. An annealing operation can be performed after forming the insulating layer. After that, a planarization operation such as a chemical mechanical polishing (CMP) method and / or an etch-back method is performed so that the upper surface of the topmost second semiconductor layer 25 is exposed to the insulating material layer. In some embodiments, a fin liner layer 35 is formed over the fin structure before forming the insulating material layer. The fin liner layer 35 is made of SiN or a silicon nitride-based material (e.g., SiON, SiCN, or SiOCN).

[0078] In some embodiments, the fin liner layer 35 includes a first fin liner layer formed above the sidewalls at the bottom of the substrate 10 and the fin structure 11, and a second fin liner layer formed above the first fin liner layer. In some embodiments, each liner layer has a thickness between about 1 nm and about 20 nm. In some embodiments, the first fin liner layer includes silicon oxide and has a thickness between about 0.5 nm and about 5 nm, and the second fin liner layer includes silicon nitride and has a thickness between about 0.5 nm and about 5 nm. The liner layers can be deposited by one or more processes such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD), but any acceptable process can be utilized.

[0079] After that, as Figure 5 shown, the insulating material layer is recessed to form the isolation insulating layer 40, such that the upper portions of the fin structures 30 are exposed. Due to this operation, the fin structures 30 are electrically isolated from each other by the isolation insulating layer 40 (also referred to as shallow trench isolation (STI)).

[0080] In Figure 5 the illustrated embodiment, the insulating material layer 40 is recessed until the upper portions of the fin structures (well layers) 11 are exposed. In other embodiments, the upper portions of the fin structures 11 are not exposed. The first semiconductor layer 20 is a sacrificial layer that will subsequently be partially removed, and the second semiconductor layer 25 is a semiconductor wire that will subsequently be formed to serve as the channel layer of the GAA FET.

[0081] As Figure 6 shown, after forming the isolation insulating layer 40, a sacrificial (dummy) gate structure 50 is formed. Figure 6 The structure after forming the sacrificial gate structure 50 above the exposed fin structures 30 is shown. The sacrificial gate structure 50 is formed above the portions of the fin structures that will become the channel regions. The sacrificial gate structure defines the channel regions of the GAA FET. The sacrificial gate structure 50 includes a sacrificial gate dielectric layer 52 and a sacrificial gate electrode layer 54. The sacrificial gate dielectric layer 52 includes one or more layers of insulating material, such as a silicon oxide-based material. In one embodiment, silicon oxide formed by CVD is used. In some embodiments, the thickness of the sacrificial gate dielectric layer 52 is in the range from about 1 nm to about 5 nm.

[0082] A sacrificial gate structure 50 is formed by first blanket depositing a sacrificial gate dielectric layer 52 over the fin structure. Thereafter, a sacrificial gate electrode layer is blanket deposited over the sacrificial gate dielectric layer and over the fin structure such that the fin structure is completely embedded within the sacrificial gate electrode layer. The sacrificial gate electrode layer includes silicon such as polysilicon or amorphous silicon. In some embodiments, the thickness of the sacrificial gate electrode layer ranges from about 100 nm to about 200 nm. In some embodiments, the sacrificial gate electrode layer is subjected to a planarization operation. CVD, PVD, ALD, or other suitable processes including LPCVD and PECVD are used to deposit the sacrificial gate dielectric layer and the sacrificial gate electrode layer. Subsequently, a mask layer is formed over the sacrificial gate electrode layer. The mask layer includes a pad SiN layer 56 and a silicon oxide mask layer 58.

[0083] Next, as Figure 6 shown, a patterning operation is performed on the mask layer and the sacrificial gate electrode layer and the patterned mask layer and sacrificial gate electrode layer are the sacrificial gate structure 50. The sacrificial gate structure includes a sacrificial gate dielectric layer 52, a sacrificial gate electrode layer 54 (e.g., polysilicon), a pad SiN layer 56, and a silicon oxide mask layer 58. As Figure 6 shown, by patterning the sacrificial gate structure, a stack of first and second semiconductor layers is partially exposed on opposite sides of the sacrificial gate structure, thereby defining source / drain (S / D) regions. In the present invention, the source and the drain can be used interchangeably and their structures are substantially the same. In Figure 6 one, a single sacrificial gate structure is formed, but the number of sacrificial gate structures is not limited to one. In some embodiments, two or more sacrificial gate structures are arranged in the X direction. In certain embodiments, one or more pseudo-sacrificial gate structures are formed on both sides of the sacrificial gate structure to improve pattern fidelity.

[0084] After forming the sacrificial gate structure, a first capping layer 51 made of an insulating material is conformally formed over the exposed fin structure and the sacrificial gate structure 50. Further, as Figure 7 shown, a second capping layer 53 is formed over the first capping layer 51. The first and second capping layers are deposited in a conformal manner such that they are formed to have substantially equal thicknesses on vertical surfaces such as sidewalls, horizontal surfaces, and the top of the sacrificial gate structure, respectively. In some embodiments, the first capping layer 51 has a thickness in the range from about 2 nm to about 10 nm, and the second capping layer 53 has a thickness greater than that of the first capping layer and has a thickness in the range from about 5 nm to about 20 nm.

[0085] In one embodiment, the first capping layer 51 includes a low-k dielectric material such as SiOC and / or SiOCN or any other suitable dielectric material. The second capping layer 53 includes one or more of SiN, SiON, and SiCN or any other suitable dielectric material. The first capping layer and the second capping layer are made of different materials so that one of them can be selectively etched. The first capping layer 51 and the second capping layer 53 can be formed by ALD or CVD or any other suitable method.

[0086] After that, as Figure 8 shown, the fin structure of the source / drain region is recessed downward to approximately the upper surface of the isolation insulating layer 40.

[0087] Subsequently, as Figure 9 shown, a source / drain epitaxial layer 80 is formed. The source / drain epitaxial layer 80 includes one or more layers of Si, SiP, SiC, and SiCP for an n-channel FET or one or more layers of Si, SiGe, Ge for a p-channel FET. For a p-channel FET, boron (B) can also be included in the source / drain. The source / drain epitaxial layer 80 can be formed by an epitaxial growth method using CVD, ALD, or molecular beam epitaxy (MBE). As Figure 9 shown, in some embodiments, the source / drain epitaxial layer is grown from two recessed fin structures, and the grown epitaxial layers merge above the isolation insulating layer and form a void 89. The source / drain epitaxial layer 80 is formed to contact the second capping layer 53 disposed above the side of the sacrificial gate structure 50.

[0088] Subsequently, as Figures 10A to 10D shown, the second capping layer 53 is removed by wet and / or dry etching. Figure 10A is a perspective view, Figure 10B is a cross-sectional view along the X direction cutting one fin structure, Figure 10C is along the cutting Figure 10D of the gap 83 in the Y direction, and Figure 10D shows another perspective view.

[0089] When the second capping layer 53 is made of SiN, H3PO4 can be used to selectively remove the second capping layer 53. As Figure 10D shown, by removing the second capping layer 53, a gap 83 is formed between the source / drain epitaxial layer 80 and the first capping layer 51 disposed above the side of the sacrificial gate structure. As Figure 10D shown, a part of this structure is exposed to the gap. The spacing of the gap 83 is substantially the same as the thickness of the second capping layer 53.

[0090] After that, as Figures 11A to 11DAs shown, a portion of the first semiconductor layer 20 in the gap 83 is removed from the fin structure, and a spacer 21 is formed between the second semiconductor layers 25. The first semiconductor layer 20 can be removed or etched using an etchant that can selectively etch the first semiconductor layer 20 relative to the second semiconductor layer 25.

[0091] When the first semiconductor layer 20 is Ge or SiGe and the second semiconductor layer 25 is Si, a wet etchant such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EPD), or potassium hydroxide (KOH) solution can be used to selectively remove the first semiconductor layer 20. Similarly, when the first semiconductor layer 20 is Si and the second semiconductor layer 25 is Ge or SiGe, a wet etchant such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EPD), or potassium hydroxide (KOH) solution can be used to selectively remove the second semiconductor layer 25. As Figure 11C shown, in some embodiments, the remaining second semiconductor layers 25 have a rounded shape. As Figure 11B shown, in some embodiments, due to the wet etching nature, the end face of the first semiconductor layer 20 has a concave shape. By adjusting the etching time, the position of the end face of the first semiconductor layer 20 can be controlled.

[0092] Next, as Figures 12A to 12C shown, an insulating layer 85 is formed over the structure as Figures 11A to 11D shown. The insulating layer 85 can be formed by ALD or CVD or any other suitable method. As Figure 12B shown, by depositing the insulating layer 85, the spacer 21 is filled with the insulating material of the insulating layer 85, thereby forming an internal spacer 85. In some embodiments, the insulating layer 85 includes a low-k dielectric material such as SiOC and / or SiOCN or any other suitable dielectric material.

[0093] In some embodiments, as Figure 12C shown, one or more voids 70 are formed in the internal spacer 85. In certain embodiments, a portion of the second semiconductor layer 25 is exposed to the voids. In other embodiments, a portion of the second semiconductor layer 25 is not exposed to the voids. In some embodiments, no voids are formed.

[0094] Subsequently, as Figure 13 shown, an interlayer dielectric (ILD) layer 95 is formed. Materials for the ILD layer 95 include compounds containing Si, O, C, and / or H, such as silicon oxide, SiCOH, and SiOC. Organic materials such as polymers can be used for the ILD layer 95. After forming the ILD layer 95, a planarization operation such as CMP is performed so that the top of the sacrificial gate electrode layer is exposed. After that, asFigure 14 As shown, the sacrificial gate electrode layer 54 and the sacrificial gate dielectric layer 52 are removed, thereby forming a gate spacer 75 that exposes the channel region of the fin structure.

[0095] During the removal of the sacrificial gate structure, the ILD layer 95 protects the S / D structure 80. The sacrificial gate structure can be removed using plasma dry etching and / or wet etching. When the sacrificial gate electrode layer 54 is polysilicon and the ILD layer 95 is silicon oxide, a wet etchant such as TMAH can be used to selectively remove the sacrificial gate electrode layer 54. Thereafter, the sacrificial gate dielectric layer 52 is removed using plasma dry etching and / or wet etching.

[0096] As Figure 15 shown, after removing the sacrificial gate structure, the first semiconductor layer 20 in the fin structure is removed, thereby forming a line of the second semiconductor layer 25. As described above, an etchant that can selectively etch the first semiconductor layer 20 relative to the second semiconductor layer 25 can be used to remove or etch the first semiconductor layer 20.

[0097] As Figure 16 shown, after forming the semiconductor lines of the second semiconductor layer 25, a gate dielectric layer 102 is formed around each channel layer (line of the second semiconductor layer 25), and a gate electrode layer 104 is formed on the gate dielectric layer 102.

[0098] In certain embodiments, the gate dielectric layer 102 includes one or more layers of dielectric material, such as silicon oxide, silicon nitride, or high-k dielectric material, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconia, alumina, titanium oxide, hafnium oxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high-k dielectric materials, and / or combinations thereof. In some embodiments, the gate dielectric layer 102 includes an interface layer 102A formed between the channel layer and the dielectric material.

[0099] The gate dielectric layer 102 can be formed by CVD, ALD, or any suitable method. In one embodiment, a high-conformal deposition process such as ALD is used to form the gate dielectric layer 102 to ensure that the gate dielectric layer formed around each channel layer has a uniform thickness. In one embodiment, the thickness of the gate dielectric layer 102 ranges from about 1 nm to about 6 nm.

[0100] A gate electrode layer 104 is formed on the gate dielectric layer 102 to surround each channel layer. The gate electrode layer 104 includes one or more layers of conductive materials such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof.

[0101] The gate electrode layer 104 can be formed by CVD, ALD, electroplating, or other suitable methods. The gate electrode layer is also deposited above the upper surface of the ILD layer 95. Thereafter, the gate dielectric layer and the gate electrode layer formed above the ILD layer 95 are planarized by using, for example, CMP until the top surface of the ILD layer 95 is exposed. As Figure 1A shown, after the planarization operation, the gate electrode layer 104 is recessed and a capping insulating layer 106 is formed above the recessed gate electrode 104. The capping insulating layer includes one or more layers of silicon nitride-based materials such as SiN. The capping insulating layer 106 can be formed by depositing an insulating material and subsequent planarization operations.

[0102] In certain embodiments of the present invention, one or more work function adjustment layers (not shown) are inserted between the gate dielectric layer 102 and the gate electrode layer 104. The work function adjustment layer is made of a conductive material such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or a multi-layer of two or more of these materials. For n-channel FETs, one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi, and TaSi are used as the work function adjustment layer, and for p-channel FETs, one or more of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC, and Co are used as the work function adjustment layer. The work function adjustment layer can be formed by ALD, PVD, CVD, electron beam evaporation, or other suitable processes. In addition, different metal layers can be used to form the work function adjustment layers for n-channel FETs and p-channel FETs, respectively.

[0103] Subsequently, contact holes are formed in the ILD layer 95 by using dry etching. In some embodiments, the upper part of the S / D epitaxial layer 80 is etched. In some embodiments, a silicide layer is formed above the S / D epitaxial layer 80. The silicide layer includes one or more of WSi, CoSi, NiSi, TiSi, MoSi, and TaSi. Thereafter, in as Figure 1AA conductive material 130 is formed in the contact hole shown. The conductive material 130 includes one or more of Co, Ni, W, Ti, Ta, Cu, Al, TiN, and TaN. It should be understood that the GAA FET undergoes further CMOS processes to form various components such as contacts / vias, interconnect metal layers, dielectric layers, passivation layers, etc.

[0104] Figures 17A to 17E Various views of a semiconductor FET device according to other embodiments of the present invention are shown. Figure 17A is a perspective view, Figure 17B corresponds to Figure 17A a cross-sectional view taken along Y1 - Y1, Figure 17C corresponds to Figure 17A a cross-sectional view taken along Y2 - Y2, Figure 17D shows a cross-sectional view taken along X1 - X1 corresponding to Figure 17C and Figure 17E shows a cross-sectional view taken along X2 - X2 corresponding to Figure 17C In the following embodiments, materials, configurations, dimensions, and / or processes similar or the same as those described in the above embodiments regarding Figures 1A to 16 may be employed, and their detailed descriptions may be omitted.

[0105] In Figures 17A to 17E the GAA FET, the semiconductor FET is a p-type GAA FET, and semiconductor wires for the channel region are configured through a first semiconductor layer 20. In some embodiments, the first semiconductor layer 20 is Si 1-x Ge x , where x is greater than about 0.3, or Ge (x = 1.0), and the second semiconductor layer 25 is Si or Si 1-y Ge y , where y is less than about 0.4, and x > y. In addition, the structure of the source / drain region is different from that shown in Figures 1A to 1E . In Figures 17A to 17E , the semiconductor wires of the first semiconductor layer 20 extend into the source / drain region and are wrapped by a source / drain epitaxial layer 81.

[0106] As Figures 17A to 17EAs shown, two semiconductor fin structures 11 are provided above a semiconductor substrate 10. In some embodiments, the substrate 10 is made of crystalline Si. The bottom of the fin structure 11 is covered by an insulating layer 35 (fin liner layer). The fin liner layer 35 includes one or more layers of insulating material. An isolation insulating layer 40 such as shallow trench isolation (STI) is disposed in a trench above the substrate 10. The isolation insulating layer 40 can be made of a suitable dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics (such as carbon-doped oxides), very low-k dielectrics (such as porous carbon-doped silica), polymers (such as polyimide), combinations thereof, etc.

[0107] As Figure 17B shown, a channel layer 20 (as a semiconductor wire) is disposed above the fin structure 11. Each channel layer 20 is surrounded by a gate dielectric layer 102 and a gate electrode layer 104. In some embodiments, the gate dielectric layer 102 includes an interface layer 102A and a high-k dielectric layer 102B. In addition, a gate capping insulating layer 106 is disposed above the gate electrode layer 104.

[0108] As Figure 17A 、 Figure 17C and Figure 17D shown, a source / drain epitaxial layer 81 is disposed above the source / drain region of the fin structure 11. The source / drain epitaxial layer 81 is covered by an interlayer dielectric (ILD) layer 95. In addition, a first capping layer 51 and / or an insulating layer 85 are formed between the source / drain epitaxial layer 81 and the ILD layer 95 and between the gate electrode 104 and the ILD layer 95. In addition, a source / drain contact 130 is provided in contact with the source / drain epitaxial layer 81.

[0109] Figure 17C is a cross-sectional view in the Y direction of a vertical portion of the insulating layer 85 at a region where the gate electrode 104 and the source / drain epitaxial layer 81 are cut. In this region, the semiconductor wire 20 is at least partially covered by the insulating layer 85. In some embodiments, one or more voids 70 are formed in the insulating layer 85 between the semiconductor wires 20. In other embodiments, no voids are formed.

[0110] Figure 17D shows a cross-sectional view corresponding to Figure 17C X1-X1, and Figure 17E shows a cross-sectional view corresponding to Figure 17C X2-X2. As Figure 17D shown, an insulating layer 85 (as an inner spacer) is disposed between end faces of the gate electrode layer 104 and the source / drain epitaxial layer 81. In some embodiments, the gate dielectric layer 102 is disposed between the insulating layer 85 and the gate electrode layer 104. As Figure 17DAs shown, the end faces of the internal spacers 85 in contact with the source / drain epitaxial layer 81 are vertically aligned (set in the same vertical plane).

[0111] The interface between the gate electrode 104 and the internal spacer 85 has a curved surface protruding toward the gate electrode 104, while the interface between the internal spacer 85 and the source / drain epitaxial layer 81 is substantially flat. As Figure 17E shown, when the void 70 is formed, there is a gap (void) between the end face of the semiconductor wire 20 and the end face of the source / drain epitaxial layer 81. In some embodiments, the internal spacer 85 is made of a low-k dielectric material such as SiOC and / or SiOCN or any other suitable dielectric material.

[0112] In some embodiments, the thickness and width of each semiconductor wire 20 are both in the range from about 5 nm to about 15 nm, and in other embodiments, in the range from about 6 nm to about 12 nm. In some embodiments, the spacing between adjacent semiconductor wires in the Z direction is in the range from about 2 nm to about 6 nm. In some embodiments, the thickness W1 of the internal spacer 85 is in the range from about 2 nm to about 6 nm. The cross-sectional shape of the semiconductor wire 20 in the channel region can be any polygon (square, rectangle, triangle, etc.), a polygon with rounded corners, a circle, or an ellipse (vertically or horizontally).

[0113] In Figures 17A to 17E it, two fin structures 11 and four semiconductor wires 20 are shown. However, the number is not limited thereto. The number of fin structures for each gate electrode can be one, three, four, or more, and the number of semiconductor wires 20 can be one, two, three, and more, up to ten.

[0114] In certain embodiments, one or more semiconductor devices (n-type and / or p-type GAA FETs) and Figures 1A to 1E one or more p-type GAA FETs are provided on the same substrate 10. Figures 17A to 17E

[0115] Figures 18 to 32 An exemplary sequential process for manufacturing the Figures 17A to 17E shown GAAFET according to an embodiment of the present invention is shown. It should be understood that additional operations can be provided before, during, and after the Figures 18 to 32 shown process, and for additional embodiments of the method, some of the operations described below can be replaced or eliminated. The order of the operations / processes can be interchanged. In the following embodiments, materials, configurations, dimensions, and / or processes the same as or similar to those described in the above embodiments with respect to Figures 1A to 16 can be employed, and their detailed descriptions can be omitted. Figures 1A to 1E The GAAFET can be associated withFigures 17A to 17E The GAA FETs shown are fabricated together.

[0116] As Figure 18 shown, impurity ions (dopants) 12 are implanted into the silicon substrate 10 to form a well region. Ion implantation is implemented to prevent punch-through effects. The substrate 10 may include respective regions that have been appropriately doped with impurities (e.g., p-type or n-type conductivity). The dopant 12 is, for example, phosphorus for a p-type Fin FET.

[0117] After that, as Figure 19 shown, a stacked semiconductor layer is formed over the substrate 10. The stacked semiconductor layer includes a first semiconductor layer 20 and a second semiconductor layer 25. In addition, a mask layer 15 is formed over the stacked layers.

[0118] The first semiconductor layer 20 and the second semiconductor layer 25 are made of materials having different lattice constants and may include one or more layers of Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, or InP. In some embodiments, the first semiconductor layer 20 and the second semiconductor layer 25 are made of Si, Si compounds, SiGe, Ge, or Ge compounds. In one embodiment, the first semiconductor layer 20 is Si 1-x Ge x , where x is greater than about 0.3, or Ge (x = 1.0), and the second semiconductor layer 25 is Si or Si 1-y Ge y , where y is less than about 0.4, and x > y.

[0119] In Figure 20 it, four layers of the first semiconductor layer 20 and four layers of the second semiconductor layer 25 are provided. However, the number of layers is not limited to four and can be as small as 1 (per layer), and in some embodiments, each first semiconductor layer and second semiconductor layer is formed into 2 - 10 layers. By adjusting the number of stacked layers, the drive current of the GAA FET device can be adjusted.

[0120] The first semiconductor layer 20 and the second semiconductor layer 25 are epitaxially formed over the substrate 10. The thickness of the first semiconductor layer 20 can be equal to or greater than the thickness of the second semiconductor layer 25, and in some embodiments, the thickness of the first semiconductor layer 20 is in the range from about 2 nm to about 20 nm, and in other embodiments, in the range from about 5 nm to about 15 nm. In some embodiments, the thickness of the second semiconductor layer 25 is in the range from about 2 nm to about 20 nm, and in other embodiments, in the range from about 5 nm to about 15 nm. The thickness of each first semiconductor layer 20 can be the same or can vary.

[0121] In some embodiments, the bottom first semiconductor layer 20 (the layer closest to the substrate 10) is thicker than the remaining first semiconductor layers. In some embodiments, the thickness of the bottom first semiconductor layer ranges from about 10 nm to about 50 nm, or in other embodiments, ranges from 20 nm to 40 nm.

[0122] In some embodiments, the mask layer 15 includes a first mask layer 15A and a second mask layer 15B. The first mask layer 15A is a pad oxide layer made of silicon oxide (which can be formed by thermal oxidation). The second mask layer 15B is made of silicon nitride (SiN). The mask layer 15 is patterned into a mask pattern by using patterning operations including photolithography and etching.

[0123] Next, as Figure 20 shown, the stacked layer of the first semiconductor layer 20 and the second semiconductor layer 25 is patterned by using the patterned mask layer, thereby forming the stacked layer into a fin structure 30 extending in the X direction. In Figure 20 this case, two fin structures 30 are arranged in the Y direction. However, the number of fin structures is not limited to two, and can be as small as one and more than three. In some embodiments, one or more pseudo fin structures are formed on both sides of the fin structure 30 to improve pattern fidelity in the patterning operation. As Figure 20 shown, the fin structure 30 has an upper portion and a well portion 11 formed by the stacked semiconductor layers 20, 25.

[0124] In some embodiments, the width W1 of the upper portion of the fin structure in the Y direction ranges from about 10 nm to about 40 nm, and in other embodiments, ranges from about 20 nm to about 30 nm. The height H1 of the fin structure in the Z direction ranges from about 100 nm to about 200 nm.

[0125] The stacked fin structure 30 can be patterned by a suitable method. For example, one or more lithography processes including a double patterning process or a multiple patterning process can be used to pattern the structure. Generally, the double patterning or multiple patterning process combines photolithography and a self-alignment process, allowing the creation of patterns having, for example, a smaller pitch than that obtainable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and the sacrificial layer is patterned using a lithography process. A spacer is formed beside the patterned sacrificial layer using a self-alignment process. After that, the sacrificial layer is removed, and then, the remaining spacer can be used to pattern the stacked fin structure 30.

[0126] After forming the fin structure 30, an insulating material layer including one or more layers of insulating material is formed over the substrate such that the fin structure is completely embedded within the insulating layer. Thereafter, a planarization operation such as a chemical mechanical polishing (CMP) process and / or an etch-back process is implemented such that the upper surface of the uppermost second semiconductor layer 25 is exposed to the insulating material layer. In some embodiments, a fin liner layer 35 is formed over the fin structure prior to forming the insulating material layer. The fin liner layer 35 is made of SiN or a silicon nitride-based material (e.g., SiON, SiCN, or SiOCN).

[0127] Thereafter, as Figure 21 shown, the insulating material layer is recessed to form the isolation insulating layer 40 such that the upper portions of the fin structures 30 are exposed. Due to this operation, the fin structures 30 are electrically isolated from each other by the isolation insulating layer 40 (STI).

[0128] In Figure 21 the embodiment shown, the insulating material layer 40 is recessed until the upper portions of the fin structures (well layers) 11 are exposed. In other embodiments, the upper portions of the fin structures 11 are not exposed. The second semiconductor layer 25 is a sacrificial layer that will subsequently be partially removed, and the first semiconductor layer 20 is a semiconductor wire that will subsequently be formed to serve as the channel layer of a GAA FET.

[0129] As Figure 22 shown, after forming the isolation insulating layer 40, a sacrificial (dummy) gate structure 50 is formed. Figure 22 The structure after forming the sacrificial gate structure 50 over the exposed fin structures 30 is shown. The sacrificial gate structure 50 is formed over the portions of the fin structures that will become the channel regions. The sacrificial gate structure defines the channel regions of the GAA FET. The sacrificial gate structure 50 includes a sacrificial gate dielectric layer 52 and a sacrificial gate electrode layer 54. The sacrificial gate dielectric layer 52 includes one or more layers of insulating material such as a silicon oxide-based material. In one embodiment, silicon oxide formed by CVD is used. In some embodiments, the thickness of the sacrificial gate dielectric layer 52 is in the range from about 1 nm to about 5 nm.

[0130] A sacrificial gate structure 50 is formed by first blanket depositing a sacrificial gate dielectric layer 52 over the fin structure. Thereafter, a sacrificial gate electrode layer is blanket deposited over the sacrificial gate dielectric layer and over the fin structure such that the fin structure is completely embedded within the sacrificial gate electrode layer. The sacrificial gate electrode layer includes silicon such as polysilicon or amorphous silicon. In some embodiments, the thickness of the sacrificial gate electrode layer ranges from about 100 nm to about 200 nm. In some embodiments, the sacrificial gate electrode layer is subjected to a planarization operation. CVD, PVD, ALD, or other suitable processes including LPCVD and PECVD are used to deposit the sacrificial gate dielectric layer and the sacrificial gate electrode layer. Subsequently, a mask layer is formed over the sacrificial gate electrode layer 54. The mask layer includes a pad SiN layer 56 and a silicon oxide mask layer 58.

[0131] Next, as Figure 22 shown, a patterning operation is performed on the mask layer and the sacrificial gate electrode layer and the mask layer and the sacrificial gate electrode layer are patterned into the sacrificial gate structure 50. The sacrificial gate structure includes a sacrificial gate dielectric layer 52, a sacrificial gate electrode layer 54 (e.g., polysilicon), a pad SiN layer 56, and a silicon oxide mask layer 58. As Figure 22 shown, by patterning the sacrificial gate structure, a stacked layer of first and second semiconductor layers is partially exposed on opposite sides of the sacrificial gate structure, thereby defining source / drain (S / D) regions. In the present invention, the source and the drain can be used interchangeably and their structures are substantially the same. In Figure 22 one, a single sacrificial gate structure is formed, but the number of sacrificial gate structures is not limited to one. In some embodiments, two or more sacrificial gate structures are arranged in the X direction. In certain embodiments, one or more pseudo-sacrificial gate structures are formed on both sides of the sacrificial gate structure to improve pattern fidelity.

[0132] After forming the sacrificial gate structure, a first capping layer 51 made of an insulating material is conformally formed over the exposed fin structure 30 and the sacrificial gate structure 50. Further, as Figure 23 shown, a second capping layer 53 is formed over the first capping layer 51. The first and second capping layers are deposited in a conformal manner such that they are formed to have substantially equal thicknesses on vertical surfaces such as sidewalls, horizontal surfaces, and the top of the sacrificial gate structure. In some embodiments, the first capping layer 51 has a thickness in the range from about 2 nm to about 10 nm, and the second capping layer 53 has a thickness greater than that of the first capping layer and has a thickness in the range from about 5 nm to about 20 nm.

[0133] In one embodiment, the first capping layer 51 includes a low-k dielectric material such as SiOC and / or SiOCN or any other suitable dielectric material. The second capping layer 53 includes one or more of SiN, SiON, and SiCN or any other suitable dielectric material. The first capping layer and the second capping layer are made of different materials so that one of them can be selectively etched. The first capping layer 51 and the second capping layer 53 can be formed by ALD or CVD or any other suitable method.

[0134] After that, as Figure 24 shown, the second semiconductor layer 25 of the fin structure in the source / drain region is removed, leaving the first semiconductor layer 20 that serves as a semiconductor wire. When the second semiconductor layer 25 is Ge or SiGe and the first semiconductor layer 20 is Si, a wet etchant such as but not limited to ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EPD), or potassium hydroxide (KOH) solution can be used to selectively remove the second semiconductor layer 25.

[0135] Subsequently, as Figure 25 shown, a source / drain epitaxial layer 81 is formed. The source / drain epitaxial layer 81 includes one or more layers of Si, SiGe, Ge, or any other suitable crystalline semiconductor material. The source / drain epitaxial layer 81 can contain boron. The source / drain epitaxial layer 81 can be formed by an epitaxial growth method using CVD, ALD, or molecular beam epitaxy (MBE). As Figure 25 shown, the source / drain epitaxial layer is grown from two recessed fin structures. The source / drain epitaxial layer 81 wraps around each first semiconductor layer (wire) 20. In some embodiments, adjacent source / drain epitaxial layers 81 merge above the isolation insulating layer 40, and in other embodiments, the source / drain epitaxial layer 81 is independently formed above the corresponding fin structure. The source / drain epitaxial layer 81 is formed to contact the second capping layer 53 disposed above the side of the sacrificial gate structure 50.

[0136] Subsequently, as Figures 26A to 26D shown, the second capping layer 53 is removed by wet and / or dry etching. Figure 26A is a perspective view, Figure 26B is a cross-sectional view along the X direction cutting one fin structure, Figure 26C is along the cut Figure 26D of the gap 83 in the Y direction, and Figure 26D shows another perspective view.

[0137] When the second capping layer 53 is made of SiN, the second capping layer 53 can be selectively removed by using H3PO4. As Figure 26DAs shown, by removing the second capping layer 53, a gap 83 is formed between the source / drain epitaxial layer 81 and the first capping layer 51 disposed above the side of the sacrificial gate structure. As Figure 26D shown, a portion of the structure is exposed to the gap 83. The spacing of the gap 83 is substantially the same as the thickness of the second capping layer 53.

[0138] After that, as Figures 27A to 27D shown, a portion of the second semiconductor layer 25 in the gap 83 is removed from the fin structure, and a spacer 21 is formed between the first semiconductor layers 20. An etchant that can selectively etch the second semiconductor layer 25 relative to the first semiconductor layer 20 can be used to remove or etch the second semiconductor layer 25.

[0139] As Figure 27C shown, in some embodiments, the remaining first semiconductor layers 20 have a rounded shape. As Figure 27B shown, in some embodiments, due to the nature of wet etching, the end face of the second semiconductor layer 25 has a concave shape. By adjusting the etching time, the position of the end face of the second semiconductor layer 25 can be controlled.

[0140] Next, as Figures 28A to 28C shown, an insulating layer 85 is formed over the structure as Figures 27A to 27D shown. The insulating layer 85 can be formed by ALD or CVD or any other suitable method. As Figure 28B shown, by depositing the insulating layer 85, the spacer 21 is filled with the insulating material of the insulating layer 85, thereby forming an inner spacer 85. In some embodiments, the insulating layer 85 includes a low-k dielectric material such as SiOC and / or SiOCN or any other suitable dielectric material.

[0141] In some embodiments, as Figure 28C shown, one or more voids 70 are formed in the inner spacer 85. In certain embodiments, a portion of the first semiconductor layer 20 is exposed to the voids. In other embodiments, the portion of the first semiconductor layer 20 is not exposed to the voids. In some embodiments, no voids are formed.

[0142] Subsequently, as Figure 29 shown, an interlayer dielectric (ILD) layer 95 is formed. The material for the ILD layer 95 includes compounds containing Si, O, C, and / or H, such as silicon oxide, SiCOH, and SiOC. Organic materials such as polymers can be used for the ILD layer 95. After forming the ILD layer 95, a planarization operation such as CMP is performed so that the top of the sacrificial gate electrode layer is exposed. After that, as Figure 30 shown, the sacrificial gate electrode layer 54 and the sacrificial gate dielectric layer 52 are removed, thereby forming a gate spacer 76 that exposes the channel region of the fin structure.

[0143] During the removal of the sacrificial gate structure, the ILD layer 95 protects the S / D structure 81. The sacrificial gate structure can be removed using plasma dry etching and / or wet etching. When the sacrificial gate electrode layer 54 is polysilicon and the ILD layer 95 is silicon oxide, a wet etchant such as a TMAH solution can be used to selectively remove the sacrificial gate electrode layer 54. Thereafter, the sacrificial gate dielectric layer 52 is removed using plasma dry etching and / or wet etching.

[0144] As Figure 31 shown, after removing the sacrificial gate structure, the second semiconductor layer 25 in the fin structure is removed, thereby forming a line of the first semiconductor layer 20. As described above, an etchant that can selectively etch the second semiconductor layer 25 relative to the first semiconductor layer 20 can be used to remove or etch the second semiconductor layer 25.

[0145] As Figure 32 shown, after forming the semiconductor line of the first semiconductor layer 20, a gate dielectric layer 102 is formed around each channel layer (the line of the first semiconductor layer 20), and a gate electrode layer 104 is formed on the gate dielectric layer 102.

[0146] Subsequently, contact holes are formed in the ILD layer 95 using dry etching. In some embodiments, the upper portion of the S / D epitaxial layer 81 is etched. In some embodiments, a silicide layer is formed above the S / D epitaxial layer 81. Thereafter, a conductive material 130 is formed in the contact holes as Figure 17A shown. The conductive material 130 includes one or more of Co, Ni, W, Ti, Ta, Cu, Al, TiN, and TaN. It should be understood that the GAA FET undergoes further CMOS processes to form various components such as contacts / vias, interconnect metal layers, dielectric layers, passivation layers, etc.

[0147] Figures 33A to 33E Various views of a semiconductor FET device according to other embodiments of the present invention are shown, and Figures 34A to 34D various views of a semiconductor FET device according to other embodiments of the present invention are shown. Figure 33A is a perspective view, Figure 33B is a cross-sectional view corresponding to Figure 33A Y1 - Y1, Figure 33C is a cross-sectional view corresponding to Figure 33A Y2 - Y2, Figure 33D shows a cross-sectional view corresponding to Figure 33C X1 - X1, and Figure 33E shows a cross-sectional view corresponding to Figure 33C X2 - X2. Figure 34A is a perspective view, Figure 34B is a cross-sectional view corresponding to Figure 34A Y1 - Y1,Figure 34C is a cross-sectional view of Y2 - Y2 corresponding to Figure 34A , and Figure 34D shows a cross-sectional view of X1 - X1 corresponding to Figure 34C . In the following embodiments, materials, configurations, dimensions, and / or processes that are the same as or similar to those described in the above embodiments regarding Figures 1A to 32 may be employed, and their detailed descriptions may be omitted. In some embodiments, the GAA FET shown in Figures 33A to 33E and the FinFET shown in Figures 34A to 34D may be provided on the same substrate.

[0148] Figures 33A to 33E The GAA FET shown in Figures 1A to 1E is substantially the same as the GAA FET shown in Figures 1A to 1E , except that an etch stop layer (ESL) 87 is further formed between the insulating layer 85 and the ILD layer 95. The ESL 87 includes one or more layers of insulating materials such as SiN and SiON or any other suitable materials formed by ALD, CVD, or any other suitable method. Figures 33A to 33E The GAA FET shown in Figures 33A to 33E may be an n - type FET or a p - type FET.

[0149] In the Figures 33A to 33E GAA FET shown, the semiconductor wires in the channel region are made of the second semiconductor layer 25. In some embodiments, the cross - sectional view of the second semiconductor layer 25 is a rectangular shape with rounded corners. In some embodiments, the width W11 of the second semiconductor layer 25 is in the range from about 5 nm to about 15 nm and the thickness T11 of the second semiconductor layer 25 is in the range from about 1.5 nm to about 10 nm. In other embodiments, the width W11 of the second semiconductor layer 25 is in the range from about 6 nm to about 10 nm and the thickness T11 of the second semiconductor layer 25 is in the range from about 2 nm to about 6 nm. In some embodiments, the pitch P11 is in the range from about 5 nm to about 15 nm, and in other embodiments, in the range from about 8 nm to about 12 nm.

[0150] In the Figures 34A to 34D FinFET, the semiconductor FET is a p - type FinFET and the channel region includes the first semiconductor layer 20 and the second semiconductor layer 25. In some embodiments, the first semiconductor layer 20 is Si 1-x Ge x , where x is greater than about 0.3, or Ge (x = 1.0), and the second semiconductor layer 25 is Si or Si 1-y Ge y , where y is less than about 0.4, and x > y. In addition, the structure of the source / drain regions is the same as that in Figures 1A to 1E , Figures 17A to 17E orFigures 33A to 33E The structures shown are different. In Figures 34A to 34D the FinFET of Figures 34A to 34D , the source / drain regions include first semiconductor layers 20 and second semiconductor layers 25 that are alternately stacked, and a source / drain epitaxial layer 81 wraps around the stacked source / drain structure.

[0151] As Figure 34B and Figure 34D shown, the channel region includes a first semiconductor layer 20 and a second semiconductor layer 25. The width of the second semiconductor layer 25 is less than the width of the first semiconductor layer 20. In some embodiments, the width of the first semiconductor layer 20 in the Y direction ranges from about 3 nm to about 10 nm, and the width of the second semiconductor layer 25 in the Y direction ranges from about 1 nm to about 5 nm. In other embodiments, the width of the first semiconductor layer 20 in the Y direction ranges from about 4 nm to about 6 nm, and the width of the second semiconductor layer 25 in the Y direction ranges from about 2 nm to about 4 nm. In some embodiments, the difference in width between the first semiconductor layer 20 and the second semiconductor layer 25 ranges from about 1 nm to about 3 nm.

[0152] Figures 35 to 40C illustrates an exemplary sequential process for manufacturing the Figures 34A to 34D FinFET shown in Figures 34A to 34D . It should be understood that additional operations can be provided before, during, and after the process shown in Figures 35 to 40C Figures 35 to 40C , and for additional embodiments of the method, some of the operations described below can be replaced or eliminated. The order of the operations / processes can be interchanged. In the following embodiments, materials, configurations, dimensions, and / or processes that are the same as or similar to those described in the above embodiments with respect to Figures 1A to 34D can be employed, and their detailed descriptions can be omitted. Figures 1A to 1E the GAA FET of Figures 1A to 1E , Figures 17A to 17E the GAA FET of Figures 17A to 17E , and / or Figures 33A to 33E the GAA FET of Figures 33A to 33E can be fabricated together with the Figures 34A to 34D FinFET shown in Figures 34A to 34D .

[0153] As Figure 35 shown, after forming the Figure 23 structure shown in Figure 23 , a second capping layer 53 and a first capping layer 51 disposed above the source / drain regions of the fin structure are removed.

[0154] Subsequently, as Figure 36As shown, a source / drain epitaxial layer 81 is formed. The source / drain epitaxial layer 81 includes one or more layers of Si, SiGe, Ge, or any other suitable crystalline semiconductor material. The source / drain epitaxial layer 81 may contain boron (B). The source / drain epitaxial layer 81 can be formed by an epitaxial growth method such as CVD, ALD, or molecular beam epitaxy (MBE). As Figure 36 shown, the source / drain epitaxial layer is grown from two recessed fin structures. The source / drain epitaxial layer 81 wraps around the upper portion of each fin structure. In some embodiments, adjacent source / drain epitaxial layers 81 merge above the isolation insulating layer 40, and in other embodiments, the source / drain epitaxial layer 81 is formed independently above the corresponding fin structure. The source / drain epitaxial layer 81 is formed to contact a second capping layer disposed above the side of the sacrificial gate structure.

[0155] After that, as Figures 37A to 37C shown, the second capping layer 53 is removed by wet and / or dry etching. Figure 37A is a perspective view, Figure 37B is a cross-sectional view along the X direction cutting through one fin structure, and Figure 37C is along the cutting Figure 26D of the gap 83 in the Y direction.

[0156] When the second capping layer 53 is made of SiN, the second capping layer 53 can be selectively removed by using H3PO4. As Figure 37B shown, by removing the second capping layer 53, a gap 83 is formed between the source / drain epitaxial layer 81 and the first capping layer 51 disposed above the side of the sacrificial gate structure. As Figure 37B shown, a portion of the fin structure is exposed to the gap 83.

[0157] After that, as Figures 38A to 38C shown, an insulating layer 85 is formed above the Figures 37A to 37C shown structure. The insulating layer 85 can be formed by ALD, CVD, or any other suitable method. In some embodiments, the insulating layer 85 includes a low-k dielectric material such as SiOC and / or SiOCN or any other suitable dielectric material.

[0158] Subsequently, as Figures 39A to 39C shown, an interlayer dielectric (ILD) layer 95 is formed. In some embodiments, an etch stop layer (ESL) 87 is formed above the insulating layer 85 before forming the ILD layer 95. The ESL 87 includes one or more layers of insulating material such as SiN and SiON or any other suitable material formed by ALD, CVD, or any other suitable method.

[0159] The materials for the ILD layer 95 include compounds containing Si, O, C, and / or H, such as silicon oxide, SiCOH, and SiOC. Organic materials such as polymers can be used for the ILD layer 95. After forming the ILD layer 95, a planarization operation such as CMP is performed to expose the top of the sacrificial gate electrode layer 54. After that, as Figures 39A to 39C shown, the sacrificial gate electrode layer 54 and the sacrificial gate dielectric layer 52 are removed, thereby forming the gate spacer 76 that exposes the channel region of the fin structure.

[0160] As Figure 39C shown, after removing the sacrificial gate structure, the second semiconductor layer 25 in the fin structure is partially removed. As described above, an etchant that can selectively etch the second semiconductor layer 25 relative to the first semiconductor layer 20 can be used to etch the second semiconductor layer 25.

[0161] As Figures 40A to 40C shown, after forming the semiconductor wires of the first semiconductor layer 20, a gate dielectric layer 102 is formed over the channel layer including the first semiconductor layer 20 and the second semiconductor layer 25, and a gate electrode layer 104 is formed on the gate dielectric layer 102.

[0162] Subsequently, contact holes are formed in the ILD layer 95 by using dry etching. In some embodiments, the upper portion of the S / D epitaxial layer 81 is etched. In some embodiments, a silicide layer is formed over the S / D epitaxial layer 81. After that, as Figures 34A to 34D shown, a conductive material 130 is formed in the contact holes. The conductive material 130 includes one or more of Co, Ni, W, Ti, Ta, Cu, Al, TiN, and TaN. It should be understood that the FET undergoes further CMOS processes to form various components such as contacts / vias, interconnect metal layers, dielectric layers, passivation layers, etc.

[0163] Each of the embodiments or examples described herein provides several advantages over the prior art. For example, in the present invention, since the internal spacer 85 is formed after forming the source / drain epitaxial layer, the internal spacer can be formed in a self-aligned manner. With the above embodiments, the thickness, shape, and / or position of the internal spacer can be more precisely controlled, and thus the capacitance around the source / drain and the gate can be controlled.

[0164] It should be understood that not all advantages are necessarily discussed herein, no particular advantage is required for all embodiments or examples, and other embodiments or examples may provide different advantages.

[0165] According to an aspect of the present invention, in a method of manufacturing a semiconductor device, a fin structure in which a first semiconductor layer and a second semiconductor layer are alternately stacked is formed. A sacrificial gate structure is formed over the fin structure. A first capping layer is formed over the sacrificial gate structure and a second capping layer is formed over the first capping layer. Source / drain epitaxial layers are formed on opposite sides of the sacrificial gate structure. After forming the source / drain epitaxial layers, the second capping layer is removed, thereby forming a gap between the source / drain epitaxial layer and the first capping layer and exposing a part of the fin structure from the gap. A part of the first semiconductor layer in the gap is removed, thereby forming a spacer between the second semiconductor layers. The spacer is filled with a first insulating material. In one or more of the above or below embodiments, one or more voids are formed in the first insulating material between the second semiconductor layers. In one or more of the above or below embodiments, the first insulating material is a low-k dielectric material. In one or more of the above or below embodiments, the first insulating material is further formed on the source / drain epitaxial layer and the first capping layer. In one or more of the above or below embodiments, the first capping layer is made of a first dielectric material and the second capping layer is made of a second dielectric material different from the first dielectric material. In one or more of the above or below embodiments, the first dielectric material is a low-k dielectric material. In one or more of the above or below embodiments, forming the source / drain epitaxial layer includes: recessing a part of the fin structure not covered by the sacrificial gate structure, and forming a third semiconductor layer as the source / drain epitaxial layer over the recessed fin structure. The third semiconductor layer is made of a semiconductor material different from the second semiconductor layer. In one or more of the above or below embodiments, after forming the first insulating material, the sacrificial gate structure is removed, thereby exposing a part of the fin structure. The first semiconductor layer is removed from the exposed fin structure, thereby forming a channel layer including the second semiconductor layer. A gate dielectric layer and a gate electrode layer are formed around the channel layer. In one or more of the above or below embodiments, the gate electrode layer contacts the first insulating material and is isolated from the source / drain epitaxial layer by the first insulating material. In one or more of the above or below embodiments, the first semiconductor layer is made of SiGe and the second semiconductor layer is made of Si.

[0166] According to another aspect of the present invention, in a method of manufacturing a semiconductor device, a fin structure in which a first semiconductor layer and a second semiconductor layer are alternately stacked is formed. A sacrificial gate structure is formed over the fin structure. A first capping layer is formed over the sacrificial gate structure and a second capping layer is formed over the first capping layer. A second semiconductor layer is removed from a portion of the fin structure not covered by the sacrificial gate structure, thereby forming a source / drain layer made of the first semiconductor layer. A source / drain epitaxial layer is formed over the source / drain layer. After forming the source / drain epitaxial layer, the second capping layer is removed, thereby forming a gap between the source / drain epitaxial layer and the first capping layer, and a portion of the fin structure is exposed from the gap. A portion of the second semiconductor layer in the gap is removed, thereby forming a spacer between the first semiconductor layers. The spacer is filled with a first insulating material. In one or more of the above or below embodiments, one or more voids are formed in the first insulating material between the first semiconductor layers. In one or more of the above or below embodiments, the first insulating material is further formed over the source / drain epitaxial layer and the first capping layer. In one or more of the above or below embodiments, the first capping layer is made of a first dielectric material and the second capping layer is made of a second dielectric material different from the first dielectric material. In one or more of the above or below embodiments, after forming the first insulating material, the sacrificial gate structure is removed, thereby exposing a portion of the fin structure. The second semiconductor layer is removed from the exposed fin structure, thereby forming a channel layer made of the first semiconductor layer. A gate dielectric layer and a gate electrode layer are formed around the channel layer. In one or more of the above or below embodiments, the gate electrode layer contacts the first insulating material and is isolated from the source / drain epitaxial layer by the first insulating material. In one or more of the above or below embodiments, the first semiconductor layer is made of SiGe and the second semiconductor layer is made of Si.

[0167] According to another aspect of the present invention, in a method of manufacturing a semiconductor device, a fin structure in which a first semiconductor layer and a second semiconductor layer are alternately stacked is formed. A sacrificial gate structure is formed over the fin structure. A first capping layer is formed over the sacrificial gate structure and a second capping layer is formed over the first capping layer. The first and second capping layers are removed from source / drain regions of the fin structure not covered by the sacrificial gate structure, thereby exposing the source / drain regions of the fin structure. A source / drain epitaxial layer is formed over the source / drain regions. A first insulating layer is formed over the source / drain epitaxial layer and the first capping layer. An etch stop layer is formed over the first insulating layer. An interlayer dielectric layer is formed over the etch stop layer. In one or more embodiments above or below, after forming the interlayer dielectric layer, the sacrificial gate structure is removed, thereby exposing a portion of the fin structure. The second semiconductor layer is partially removed from the exposed fin structure, thereby forming a channel layer including the first semiconductor layer and the second semiconductor layer (having a width thinner than that of the first semiconductor layer). A gate dielectric layer and a gate electrode layer are formed around the channel layer. In one or more embodiments above or below, the first insulating layer is made of a low-k dielectric material.

[0168] According to one aspect of the present invention, a semiconductor device includes a first semiconductor line disposed over a substrate, a first source / drain region in contact with an end of the first semiconductor line, a gate dielectric layer disposed over each channel region of the first semiconductor line and wrapping each channel region of the first semiconductor line, a gate electrode layer disposed over the gate dielectric layer and wrapping each channel region, and first insulating spacers respectively disposed in the spaces. The spaces are defined by adjacent first semiconductor lines, gate electrode layers, and first source / drain regions. End faces of the first insulating spacers in contact with the first source / drain regions are vertically aligned. In one or more embodiments above or below, an end face of the first insulating spacer in contact with the first source / drain region is vertically aligned with an interface between an end of the first semiconductor line and the first source / drain region. In one or more embodiments above or below, one or more voids are formed in the first insulating spacers between the first semiconductor lines. In one or more embodiments above or below, the first insulating spacers are made of a low-k dielectric material. In one or more embodiments above or below, the low-k dielectric material includes at least one selected from the group consisting of SiOC and SiOCN. In one or more embodiments above or below, a first insulating layer is formed over the source / drain regions and over side surfaces of the gate electrode layer, and the first insulating layer is made of the same material as the first insulating spacers and is formed simultaneously with the first insulating spacers. In one or more embodiments above or below, the semiconductor device further includes a capping layer disposed between side surfaces of the gate electrode layer and the first insulating layer. In one or more embodiments above or below, the source / drain regions and the first capping layer are separated by the first insulating layer.

[0169] According to another aspect of the present invention, a semiconductor device includes a first semiconductor wire disposed above a substrate, a first source / drain epitaxial layer that wraps around the source / drain regions of the first semiconductor wire, a gate dielectric layer disposed on each channel region of the first semiconductor wire and wrapping around each channel region of the first semiconductor wire, a gate electrode layer disposed on the gate dielectric layer and wrapping around each channel region, and first insulating spacers disposed in the spaces respectively. The spaces are defined by adjacent first semiconductor wires, gate electrode layers, and first source / drain regions. The end faces of the first insulating spacers in contact with the first source / drain regions are vertically aligned. In one or more of the above or below embodiments, the first semiconductor wire is made of SiGe or Ge. In one or more of the above or below embodiments, one or more voids are formed in the first insulating spacers between the first semiconductor wires. In one or more of the above or below embodiments, the first insulating spacer includes at least one selected from the group consisting of SiOC and SiOCN. In one or more of the above or below embodiments, a first insulating layer is formed above the source / drain epitaxial layer and above the sides of the gate electrodes, and the first insulating layer is made of the same material as the first insulating spacer and is formed simultaneously with the first insulating spacer. In one or more of the above or below embodiments, the semiconductor device further includes a capping layer disposed between the sides of the gate electrode layer and the first insulating layer. In one or more of the above or below embodiments, the source / drain regions and the first capping layer are separated by the first insulating layer.

[0170] According to another aspect of the present invention, a semiconductor device includes a first field-effect transistor (FET) and a second FET. The first FET includes a first semiconductor wire disposed above a substrate, a first source / drain epitaxial layer in contact with an end of the first semiconductor wire, a first gate dielectric layer disposed on each channel region of the first semiconductor wire and wrapping each channel region of the first semiconductor wire, a first gate electrode layer disposed on the first gate dielectric layer and wrapping each channel region, and first insulating spacers disposed in the intervals respectively. The interval is defined by adjacent first semiconductor wires, first gate electrode layers, and first source / drain epitaxial layers. The second FET includes a fin structure in which a first semiconductor layer and a second semiconductor layer are alternately stacked, a second source / drain epitaxial layer disposed above a source / drain region of the fin structure, a second gate dielectric layer disposed above a channel region of the fin structure, and second gate electrode layers disposed on the second gate dielectric layer respectively. In one or more of the above or below embodiments, the first FET is an n-type FET and the second FET is a p-type FET. In one or more of the above or below embodiments, end faces of the first insulating spacers in contact with the first source / drain epitaxial layer are vertically aligned. In one or more of the above or below embodiments, one or more voids are formed in the first insulating spacers between the first semiconductor layers. In one or more of the above or below embodiments, a width of the first semiconductor layer in the channel region is smaller than a width of the second semiconductor layer in the channel region.

[0171] According to some embodiments of the present invention, a method of manufacturing a semiconductor device is provided, including: forming a fin structure in which a first semiconductor layer and a second semiconductor layer are alternately stacked; forming a sacrificial gate structure above the fin structure; forming a first capping layer above the sacrificial gate structure and a second capping layer above the first capping layer; forming source / drain epitaxial layers on opposite sides of the sacrificial gate structure; after forming the source / drain epitaxial layers, removing the second capping layer, thereby forming a gap between the source / drain epitaxial layer and the first capping layer, and exposing a part of the fin structure from the gap; removing a part of the first semiconductor layer located in the gap, thereby forming an interval between the second semiconductor layers; and filling the interval with a first insulating material.

[0172] In the above method, one or more voids are formed in the first insulating material between the second semiconductor layers.

[0173] In the above method, the first insulating material is a low-k dielectric material.

[0174] In the above method, the first insulating material is further formed on the source / drain epitaxial layer and the first capping layer.

[0175] In the above method, the first capping layer is made of a first dielectric material and the second capping layer is made of a second dielectric material different from the first dielectric material.

[0176] In the above method, the first dielectric material is a low-k dielectric material.

[0177] In the above method, forming the source / drain epitaxial layer includes: recessing a portion of the fin structure not covered by the sacrificial gate structure; and forming a third semiconductor layer over the recessed fin structure as the source / drain epitaxial layer; wherein the third semiconductor layer is made of a semiconductor material different from the second semiconductor layer.

[0178] In the above method, further included, after forming the first insulating material: removing the sacrificial gate structure to expose a portion of the fin structure; removing the first semiconductor layer from the exposed fin structure to form a channel layer including the second semiconductor layer; and forming a gate dielectric layer and a gate electrode layer around the channel layer.

[0179] In the above method, the gate electrode layer contacts the first insulating material and is isolated from the source / drain epitaxial layer by the first insulating material.

[0180] In the above method, the first semiconductor layer is made of SiGe, and the second semiconductor layer is made of Si.

[0181] According to other embodiments of the present invention, there is also provided a method of manufacturing a semiconductor device, including: forming a fin structure in which a first semiconductor layer and a second semiconductor layer are alternately stacked; forming a sacrificial gate structure over the fin structure; forming a first capping layer over the sacrificial gate structure and a second capping layer over the first capping layer; removing the second semiconductor layer from a portion of the fin structure not covered by the sacrificial gate structure to form a source / drain layer including the first semiconductor layer; forming a source / drain epitaxial layer over the source / drain layer; after forming the source / drain epitaxial layer, removing the second capping layer to form a gap between the source / drain epitaxial layer and the first capping layer, exposing a portion of the fin structure from the gap; removing a portion of the second semiconductor layer located in the gap to form a spacer between the first semiconductor layers; and filling the spacer with a first insulating material.

[0182] In the above method, one or more voids are formed in the first insulating material between the first semiconductor layers.

[0183] In the above method, the first insulating material is further formed on the source / drain epitaxial layer and the first capping layer.

[0184] In the above method, the first capping layer is made of a first dielectric material, and the second capping layer is made of a second dielectric material different from the first dielectric material.

[0185] In the above method, after forming the first insulating material, it further includes: removing the sacrificial gate structure to expose a part of the fin structure; removing the second semiconductor layer from the exposed fin structure to form a channel layer made of the first semiconductor layer; and forming a gate dielectric layer and a gate electrode layer around the channel layer.

[0186] In the above method, the gate electrode layer is in contact with the first insulating material and is isolated from the source / drain epitaxial layer by the first insulating material.

[0187] In the above method, the first semiconductor layer is made of SiGe, and the second semiconductor layer is made of Si.

[0188] According to still some other embodiments of the present invention, there is also provided a semiconductor device, including: a first semiconductor wire disposed above a substrate; a first source / drain region in contact with an end of the first semiconductor wire; a gate dielectric layer disposed on each channel region of the first semiconductor wire and surrounding each channel region of the first semiconductor wire; a gate electrode layer disposed on the gate dielectric layer and surrounding each channel region; and a first insulating spacer respectively disposed in a space defined by an adjacent first semiconductor wire, the gate electrode layer, and the first source / drain region, wherein end faces of the first insulating spacer in contact with the first source / drain region are vertically aligned.

[0189] In the above semiconductor device, end faces of the first insulating spacer in contact with the first source / drain region are vertically aligned with an interface between the first semiconductor wire and an end of the first source / drain region.

[0190] In the above semiconductor device, one or more voids are formed in the first insulating spacer between the first semiconductor wires.

[0191] The features of several embodiments are outlined above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments introduced by the present inventor. Those skilled in the art should also be aware that such equivalent structures do not depart from the spirit and scope of the present invention, and they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, comprising: A first semiconductor line, disposed above a substrate; A first source / drain region, in contact with an end of the first semiconductor line; A gate dielectric layer, disposed on each channel region of the first semiconductor line and surrounding each channel region of the first semiconductor line; A gate electrode layer, disposed on the gate dielectric layer and surrounding each of the channel regions; And A first insulating spacer, respectively disposed in a space defined by an adjacent first semiconductor line, the gate electrode layer, and the first source / drain region, Wherein, an end face of the first insulating spacer in contact with the first source / drain region is vertically aligned, and a surface of the first insulating spacer opposite to the end face is a surface protruding toward the gate electrode layer, A capping layer, disposed on sidewalls of the gate electrode layer above the first semiconductor line, and a vertical sidewall of the capping layer is in direct contact with a low-k dielectric layer, wherein the low-k dielectric layer is disposed between an interlayer dielectric layer above the first source / drain region and the gate electrode layer, A sidewall at a bottom of the low-k dielectric layer between the first source / drain region and the gate electrode layer is vertically aligned with the end face.

2. The semiconductor device according to claim 1, wherein, The end face of the first insulating spacer in contact with the first source / drain region is vertically aligned with an interface between the first semiconductor line and an end of the first source / drain region.

3. The semiconductor device according to claim 1, wherein, One or more voids are formed in the first insulating spacer between the first semiconductor lines.

4. A semiconductor device, comprising: A first structure, disposed above a semiconductor substrate; A second structure, disposed above the semiconductor substrate; An isolation insulating layer, disposed between the first structure and the second structure, Wherein the first structure includes: A plurality of stacked semiconductor lines; A first source / drain epitaxial layer, in contact with an end of the semiconductor line; A first gate dielectric layer, disposed on a channel region of each of the semiconductor lines and surrounding the channel region; A first gate electrode layer, disposed on the first gate dielectric layer and surrounding the channel region of each of the semiconductor lines; A capping layer, disposed above sidewalls of a portion of the first gate electrode layer above the channel region; and An insulating spacer, disposed between adjacent semiconductor lines, the first gate electrode layer, and the first source / drain epitaxial layer, and The second structure includes: A fin structure, in which a first semiconductor layer and a second semiconductor layer are alternately stacked; A second source / drain epitaxial layer, disposed above a source / drain region of the fin structure; A second gate dielectric layer, disposed above a channel region of the fin structure; and A second gate electrode layer, disposed on the second gate dielectric layer, An interlayer dielectric layer, disposed above the first source / drain epitaxial layer and the second source / drain epitaxial layer; and A low-k dielectric layer, disposed between the interlayer dielectric layer and the first gate electrode layer and the second gate electrode layer.

5. The semiconductor device according to claim 4, wherein the first structure is an n-type field effect transistor and the second structure is a p-type field effect transistor.

6. The semiconductor device according to claim 4, wherein, The end face of the insulating spacer in contact with the first source / drain epitaxial layer is vertically aligned.

7. The semiconductor device according to claim 4, wherein, One or more voids are formed in the insulating spacer between the semiconductor lines.

8. The semiconductor device according to claim 4, wherein the width of the first semiconductor layer in the channel region is smaller than the width of the second semiconductor layer in the channel region.

9. The semiconductor device according to claim 4, wherein the periphery of each of the insulating spacers forms a right angle at the intersection of the first source / drain epitaxial layer and the semiconductor line.

10. The semiconductor device according to claim 4, wherein the low-k dielectric layer is made of SiOC or SiOCN.

11. The semiconductor device according to claim 4, wherein the semiconductor line is made of Si, SiGe or Ge.

12. The semiconductor device according to claim 4, wherein the first and second semiconductor layers are made of different materials selected from Si, SiGe or Ge.

13. A semiconductor device, comprising: a first field effect transistor and a second field effect transistor, wherein the first field effect transistor comprises: a plurality of silicon semiconductor lines stacked above a substrate; a first source / drain epitaxial layer in contact with the ends of the silicon semiconductor lines: a first gate dielectric layer disposed on the channel region of each of the silicon semiconductor lines and surrounding the channel region; a first gate electrode layer disposed on the first gate dielectric layer and surrounding the channel region of each of the silicon semiconductor lines; a capping layer disposed above the sidewalls of the portion of the first gate electrode layer above the channel region; an insulating spacer comprising spacer material in direct contact with the first source / drain epitaxial layer and the silicon semiconductor lines, wherein the periphery of the insulating spacer forms a right angle at the intersection of the first source / drain epitaxial layer and the silicon semiconductor lines, and the second field effect transistor comprises: a fin structure, a second gate electrode layer disposed above the channel region of the fin structure; and a second source / drain epitaxial layer disposed above the source / drain region of the fin structure, an interlayer dielectric layer disposed above the first source / drain epitaxial layer and the second source / drain epitaxial layer; and a low-k dielectric layer disposed between the interlayer dielectric layer and the first gate electrode layer and the second gate electrode layer.

14. The semiconductor device according to claim 13, wherein the first field effect transistor is an n-type field effect transistor and the second field effect transistor is a p-type field effect transistor.

15. The semiconductor device according to claim 13, wherein, The fin structure comprises an alternating stack of a first semiconductor layer made of Si and a second semiconductor layer made of SiGe.

16. The semiconductor device according to claim 15, further comprising an insulating layer formed of spacer material, the insulating layer being in direct contact with the first semiconductor layer and the second semiconductor layer.

17. The semiconductor device according to claim 13, wherein, One or more voids are formed in the insulating spacer between the silicon semiconductor lines.

18. The semiconductor device according to claim 15, wherein a width of the first semiconductor layer in the channel region is smaller than a width of the second semiconductor layer in the channel region.

19. The semiconductor device according to claim 13, wherein the low-k dielectric layer is made of SiOC or SiOCN.

Images