Embedded SONOS Memory and Its Manufacturing Method

Abstract

The present invention provides an embedded SONOS memory and a method for manufacturing the same. The method includes: forming a connection layer on one side of the polysilicon gate of the select transistor; forming a second silicon oxide layer and an ONO charge storage layer on the other side of the polysilicon gate of the select transistor away from the connection layer; then forming a polysilicon gate of the storage transistor on the side of the second silicon oxide layer away from the connection layer, so as to obtain the polysilicon gate of the select transistor and the polysilicon gate of the storage transistor with a back-to-back structure. By forming the polysilicon gate of the select transistor and the polysilicon gate of the storage transistor with a back-to-back structure, the present application saves the chip design area compared with the traditional SONOS device with two separated transistors. Further, by using the connection layer, the gate of the polysilicon gate of the select transistor can be commonly connected to the corresponding source end in the substrate, and can be commonly connected to the same select transistor word line subsequently, so that the design of the external circuit can be more concise.

Description

Technical Field

[0001] This application relates to the technical field of SONOS memory manufacturing, and particularly relates to an embedded SONOS memory and a preparation method thereof. Background Art

[0002] As an essential storage device in a computer, non-volatile memory plays an important storage function for the processed information. SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) memory has the characteristics of small cell size, good storage retention, low operating voltage, and compatibility with CMOS process.

[0003] Existing SONOS memory devices are generally SONOS devices with a two-transistor (select transistor and storage transistor) separated structure, which requires excessive chip design area; in addition, in existing SONOS memory devices, the source terminal of the select transistor and the gate of the select transistor need to be connected to the peripheral circuit respectively, and the external circuit design is relatively complicated. Summary of the Invention

[0004] This application provides an embedded SONOS memory and a preparation method thereof, which can solve at least one of the problems that existing SONOS memory devices occupy excessive chip design area and the external circuit design is relatively complicated.

[0005] On the one hand, an embodiment of this application provides a preparation method of an embedded SONOS memory, including:

[0006] Providing a substrate, a first silicon oxide layer and a first silicon nitride layer are formed on the substrate, a first trench is formed in the first silicon nitride layer, and two opposite select transistor polysilicon gates covering the side surfaces of the first silicon nitride layer are formed in the first trench;

[0007] Etching the first silicon oxide layer on the bottom wall of the first trench to the surface of the substrate;

[0008] Etching a part of the thickness of the substrate on the bottom wall of the first trench to obtain a second trench, and forming two connection layers in the second trench, the connection layers contact the substrate on the bottom wall of the second trench and respectively cover one of the select transistor polysilicon gates;

[0009] Forming an isolation oxide layer, the isolation oxide layer fills the second trench;

[0010] Removing the first silicon nitride layer and the first silicon oxide layer on the side of the select transistor polysilicon gate;

[0011] Forming a second silicon oxide layer, the second silicon oxide layer covers the side surfaces of the select transistor polysilicon gates;

[0012] Form an ONO material layer that covers the isolation oxide layer, the second silicon oxide layer, and a partial surface of the substrate;

[0013] Form a first polysilicon material layer that covers the ONO material layer;

[0014] Etch the first polysilicon material layer and the ONO material layer above the isolation oxide layer, and the first polysilicon material layer and the ONO material layer on a part of the substrate to obtain an ONO charge storage layer and a storage tube polysilicon gate on the side of the second silicon oxide layer; and,

[0015] Form a stacked logic oxide layer and a logic polysilicon gate on the substrate surface far from the storage tube polysilicon gate.

[0016] Optionally, in the method for manufacturing the embedded SONOS memory, the material of the connection layer is polysilicon.

[0017] Optionally, in the method for manufacturing the embedded SONOS memory, the step of etching a part of the thickness of the bottom wall of the first trench in the substrate to obtain a second trench and forming a connection layer that covers the select tube polysilicon gate in the second trench includes:

[0018] Form a second polysilicon material layer that covers the first silicon nitride layer, the select tube polysilicon gate, and the substrate of the bottom wall of the first trench;

[0019] Etch and remove the second polysilicon material layer on the first silicon nitride layer and the second polysilicon material layer on the bottom wall of the first trench to obtain the connection layer; and,

[0020] Etch a part of the thickness of the bottom wall of the first trench in the substrate to obtain the second trench.

[0021] Optionally, in the method for manufacturing the embedded SONOS memory, during the process of forming the stacked logic oxide layer and the logic polysilicon gate, the method for manufacturing the embedded SONOS memory further includes: forming a silicon oxide sidewall that covers the side surfaces of the storage tube polysilicon gate and the ONO charge storage layer.

[0022] Optionally, in the method for manufacturing the embedded SONOS memory, during the process of etching a part of the thickness of the bottom wall of the first trench in the substrate to obtain the second trench, the etched part of the thickness of the substrate is greater than

[0023] Optionally, in the method for manufacturing the embedded SONOS memory, in the second trench, the isolation oxide layer has a size in width of

[0024] Optionally, in the method for manufacturing the embedded SONOS memory, an active region is formed on the substrate surface at the bottom of each of the connection layers. Among them, through the connection layer, each of the select transistor polysilicon gates is electrically connected to the source region at the bottom of each of the connection layers.

[0025] Optionally, in the method for manufacturing the embedded SONOS memory, the thickness of the second silicon oxide layer is The thickness of the ONO charge storage layer is

[0026] Optionally, in the method for manufacturing the embedded SONOS memory, the ONO charge storage layer includes: a stacked silicon oxide film layer, a silicon nitride film layer, and a silicon oxide film layer.

[0027] On the other hand, an embodiment of the present application further provides an embedded SONOS memory, including:

[0028] A substrate, on which a patterned first silicon oxide layer is formed;

[0029] Two oppositely arranged select transistor polysilicon gates, which cover the patterned first silicon oxide layer;

[0030] Two connection layers, which respectively cover one of the select transistor polysilicon gates and are in contact with the substrate. A second trench is formed between the connection layer and a part of the thickness of the substrate;

[0031] An isolation oxide layer, which fills the second trench;

[0032] A second silicon oxide layer, which covers the side surfaces of the select transistor polysilicon gates;

[0033] Two ONO charge storage layers, which are respectively located on the sides of the second silicon oxide layer and cover the side surfaces of the second silicon oxide layer and a part of the surface of the substrate;

[0034] Two storage transistor polysilicon gates, which cover the ONO charge storage layers; and,

[0035] A stacked logic oxide layer and a logic polysilicon gate, which are located on the substrate surface far from the storage transistor polysilicon gate.

[0036] The technical solution of the present application has at least the following advantages:

[0037] By forming the polysilicon gates of the selection transistor and the storage transistor in a back-to-back structure, the present application saves chip design area compared to traditional two-transistor separated SONOS devices.

[0038] Furthermore, by using the connection layer, the present application can commonly connect the gate of the polysilicon gate of the selection transistor to its corresponding source terminal in the substrate, and then can be commonly connected to the same selection transistor word line, thereby making the design of the external circuit more concise.

[0039] In addition, the present application uses the first silicon nitride layer as a hard mask to define the widths of the polysilicon gates of the selection transistor and the storage transistor in adjacent SONOS memory devices on the entire wafer, and uses the method of polysilicon gate self-aligned etching to define the widths of the single polysilicon gate of the selection transistor and the single polysilicon gate of the storage transistor in each SONOS memory device. Under the condition of limited lithography capabilities, it can be used for the manufacture of smaller-sized SONOS memories. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0041] Figures 1-16 It is a schematic diagram of the semiconductor structure in each process step of preparing an embedded SONOS memory according to an embodiment of the present invention;

[0042] Among them, the reference numerals are explained as follows:

[0043] 100 - Substrate, 110 - First silicon oxide layer, 111 - Patterned first silicon oxide layer, 120 - First silicon nitride layer, 121 - First trench, 122 - Second trench, 130 - Polysilicon material layer, 131 - Polysilicon gate of the selection transistor, 140 - Second polysilicon material layer, 141 - Connection layer, 150 - Isolation oxide layer, 160 - Silicon oxide material layer, 161 - Second silicon oxide layer, 170 - ONO material layer, 171 - ONO charge storage layer, 180 - First polysilicon material layer, 181 - Polysilicon gate of the storage transistor, 190 - Silicon oxide material layer, 191 - Silicon oxide sidewall, 192 - Logic oxide layer, 200 - Polysilicon material layer, 201 - Logic polysilicon gate. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0044] The technical solutions in the present application will be clearly and completely described below in conjunction with the accompanying drawings. Apparently, the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the scope of protection of the present application.

[0045] In the description of the present application, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present application. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and should not be construed as indicating or implying relative importance.

[0046] In the description of the present application, it should be noted that unless otherwise clearly specified and limited, the terms "mounted", "connected", and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can also be the communication inside two elements. It can be a wireless connection or a wired connection. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific situations.

[0047] In addition, the technical features involved in different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0048] The embodiment of the present application provides a method for manufacturing an embedded SONOS memory. Specifically, please refer to Figures 1-16 , Figures 1-16 which is a schematic diagram of a semiconductor structure in each process step for manufacturing an embedded SONOS memory according to an embodiment of the present invention. Next, the manufacturing process of the embedded SONOS memory will be elaborated in detail.

[0049] First, as Figure 1 shown, a substrate 100 is provided, and a first silicon oxide layer 110 and a first silicon nitride layer 120 are formed on the substrate 100; as Figure 2 shown, a first trench 121 is formed in the first silicon nitride layer 120; as Figure 4 shown, two opposite select transistor polysilicon gates 131 covering the side surfaces of the first silicon nitride layer 120 are formed in the first trench 121. Specifically, the step of forming the select transistor polysilicon gates 131 may include: asFigure 3 As shown, after forming the first trench 121, a polysilicon material layer 130 is first deposited, and the polysilicon material layer 130 covers the first silicon nitride layer 120 and the sidewalls and bottom wall of the first trench 121; as Figure 4 shown, then the polysilicon material layer 130 on the first silicon nitride layer 120 and the polysilicon material layer 130 on the bottom wall of the first trench 121 are removed, and finally the polysilicon material layer 130 covering the side surface of the first silicon nitride layer 120 in the first trench 121 is retained to obtain two opposite select transistor polysilicon gates 131.

[0050] Then, as Figure 5 shown, the first silicon oxide layer 110 on the bottom wall of the first trench 121 is etched to expose the surface of the substrate 100.

[0051] Next, a part of the thickness of the substrate 100 on the bottom wall of the first trench 121 is etched to obtain a second trench 122, and two connection layers 141 are formed in the second trench 122. The connection layers 141 contact the substrate 100 on the bottom wall of the second trench 122 and respectively cover one of the select transistor polysilicon gates 131. Wherein, the material of the connection layer 141 is polysilicon. Specifically, the steps of obtaining the second trench 122 and forming the two connection layers 141 may include: the first step: as Figure 6 shown, a second polysilicon material layer 140 is formed, and the second polysilicon material layer 140 covers the first silicon nitride layer 120, the select transistor polysilicon gate 131, and the substrate 100 on the bottom wall of the first trench 121; the second step: as Figure 7 shown, the second polysilicon material layer 140 on the first silicon nitride layer 120 and the second polysilicon material layer 140 on the bottom wall of the first trench 121 are etched away to obtain the connection layer 141; the third step: as Figure 7 shown, a part of the thickness of the substrate 100 on the bottom wall of the first trench 121 is etched to obtain the second trench 122.

[0052] Furthermore, as Figure 8 shown, an isolation oxide layer 150 is formed, and the isolation oxide layer 150 fills the second trench 122. Specifically, in the second trench 122, the size of the isolation oxide layer 150 in width can be

[0053] In this embodiment, an active region (not shown) is formed on the surface of the substrate 100 at the bottom of each of the connection layers 141. Among them, through the connection layer 141, each of the select transistor polysilicon gates 131 is electrically connected to the source region at the bottom of each of the connection layers 141. By using the connection layer 141 in the present application, the gate of the select transistor polysilicon gate 131 can be commonly connected to the corresponding source terminal in the substrate 100, and subsequently can be commonly connected to the same select transistor word line, thereby making the design of the external circuit of the memory device more concise.

[0054] Further, in the process of etching a part of the thickness of the substrate 100 at the bottom wall of the first trench 121 to obtain the second trench 122, it is necessary to etch the substrate 100 with a thickness greater than so that the isolation oxide layer 150 filled in the second trench 122 can well isolate the source regions on both sides.

[0055] Next, as Figure 9 shown, the first silicon nitride layer 120 and the first silicon oxide layer 110 on the side of the select transistor polysilicon gate 131 are removed to obtain the patterned first silicon oxide layer 111 (the remaining first silicon oxide layer 110) at the bottom of the select transistor polysilicon gate 131.

[0056] Further, a second silicon oxide layer 161 is formed, and the second silicon oxide layer 161 covers the side surface of the select transistor polysilicon gate 131. Specifically, the step of forming the second silicon oxide layer 161 may include: First, as Figure 10 shown, a silicon oxide material layer 160 is formed, and the silicon oxide material layer 160 covers the isolation oxide layer 150, the side surface of the select transistor polysilicon gate 131, and the surface of the substrate 100; then, as Figure 11 shown, in this embodiment, since the etching process of the isolation oxide layer 160 is a dry etching process without a photomask, the silicon oxide material layer 160 on the surfaces of the substrate 100 and the isolation oxide layer 150 will be etched off, that is, the silicon oxide material layer 160 on the surfaces of the substrate 100 and the isolation oxide layer 150 is etched off to obtain the final second silicon oxide layer 161 covering the side surface of the select transistor polysilicon gate 131.

[0057] Next, as Figure 12 shown, an ONO material layer 170 is formed, and the ONO material layer 170 covers the second silicon oxide layer 161, the isolation oxide layer 150, and a part of the surface of the substrate 100.

[0058] Further, as Figure 13As shown, a first polysilicon material layer 180 is formed, and the first polysilicon material layer 180 covers the ONO material layer 170.

[0059] Next, as Figure 14 shown, the first polysilicon material layer 180 above the isolation oxide layer 150, the ONO material layer 170, and the first polysilicon material layer 180 and the ONO material layer 170 on a part of the substrate 100 are etched to obtain two ONO charge storage layers 171 and two storage tube polysilicon gates 181 on two sides of the two second silicon oxide layers 161 respectively. Specifically, the thickness of the second silicon oxide layer 161 can be The thickness of the ONO charge storage layer 171 can be Furthermore, the ONO charge storage layer 171 may include: a stacked silicon oxide film layer, a silicon nitride film layer, and a silicon oxide film layer. As Figure 14 can be seen, the cross section of the ONO charge storage layer 171 is L-shaped. In this embodiment, the select tube polysilicon gate 131, the storage tube polysilicon gate 181, and other related film layers on the left side of the isolation oxide layer 150 form a storage unit. Similarly, the select tube polysilicon gate 131, the storage tube polysilicon gate 181, and other related film layers on the right side of the isolation oxide layer 150 also form a storage unit. It can be seen that the embedded SONOS memory provided in this embodiment is equivalent to a 2-row * 1-column array storage device, and several embedded SONOS memories provided in this embodiment can be formed on the entire wafer to form an m-row * n-column array storage device.

[0060] In this embodiment, the present application uses the first silicon nitride layer 120 as a hard mask to define the widths of the select tube polysilicon gates and the storage tube polysilicon gates in adjacent SONOS storage devices on the entire wafer, and adopts a polysilicon gate self-aligned etching method to define the widths of a single select tube polysilicon gate 131 and a single storage tube polysilicon gate 181 in each SONOS storage device. Under the condition of limited lithography capabilities, it can be used for the manufacture of smaller-sized SONOS memories.

[0061] Furthermore, in this embodiment, the present application forms the select tube polysilicon gate 131 and the storage tube polysilicon gate 181 in a back-to-back structure. The select tube polysilicon gate 131 and the storage tube polysilicon gate 181 are isolated by the second silicon oxide layer 161 and the ONO charge storage layer 171, saving chip design area compared with traditional two-tube separated SONOS devices. It can be seen that the embedded SONOS memory provided in this embodiment can save chip design area while the performance is not affected.

[0062] Finally, a stacked logic oxide layer 192 and a logic polysilicon gate 201 are formed on the surface of the substrate 100 away from the storage region (the storage tube polysilicon gate 181). Specifically, the steps of forming the logic oxide layer 192 and the logic polysilicon gate 201 may include: First, as Figure 15 shown, a silicon oxide material layer 190 is first formed, and the silicon oxide material layer 190 covers the second silicon oxide layer 161, the isolation oxide layer 150, the storage tube polysilicon gate 181, and a part of the substrate 100; then a polysilicon material layer 200 is formed, and the polysilicon material layer 200 covers the silicon oxide material layer 190; then, the polysilicon material layer 200 and the silicon oxide material layer 190 above the isolation oxide layer 150 are etched away, and the polysilicon material layer 200 and the silicon oxide material layer 190 on the surface of a part of the substrate 100 are removed, so as to form a silicon oxide sidewall 191 covering the side surface of the storage tube polysilicon gate 181 and the side surface of the ONO charge storage layer 171, and a stacked logic oxide layer 192 and a logic polysilicon gate 201, and the logic oxide layer 192 and the logic polysilicon gate 201 are structures of the logic region.

[0063] Based on the same inventive concept, an embodiment of the present application further provides an embedded SONOS memory, as Figure 16 shown, the embedded SONOS memory includes:

[0064] A substrate 100, the substrate 100 includes: a storage region and a logic region, wherein a patterned first silicon oxide layer 111 is formed on the substrate 100 in the storage region;

[0065] Two oppositely arranged selection tube polysilicon gates 131, the selection tube polysilicon gates 131 cover the patterned first silicon oxide layer 111;

[0066] Two connection layers 141, the connection layers 141 respectively cover one of the selection tube polysilicon gates 131 and are in contact with the substrate 100, and a second trench 122 is formed between the connection layer 141 and a part of the thickness of the substrate 100;

[0067] An isolation oxide layer 150, the isolation oxide layer 150 fills the second trench 122;

[0068] A second silicon oxide layer 161, the second silicon oxide layer 161 covers the side surface of the selection tube polysilicon gate 131;

[0069] Two ONO charge storage layers 171, the ONO charge storage layers 171 are respectively located on the side of the second silicon oxide layer 161 and cover the side surface of the second silicon oxide layer 161 and a part of the surface of the substrate 100;

[0070] Two storage-tube polysilicon gates 181, the storage-tube polysilicon gates 181 covering the ONO charge storage layer 171; and,

[0071] Stacked logic oxide layer 192 and logic polysilicon gate 201, the logic oxide layer 192 and the logic polysilicon gate 201 being located on the surface of the substrate 100 away from the storage area.

[0072] In this embodiment, the patterned first silicon oxide layer 111, the select-tube polysilicon gate 131, the connection layer 141, the isolation oxide layer 150, the second silicon oxide layer 161, the ONO charge storage layer 171, and the storage-tube polysilicon gates 181 are all located in the storage area; the logic oxide layer 192 and the logic polysilicon gate 201 are located in the logic area.

[0073] Obviously, the above embodiments are merely examples given for clear illustration and are not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all implementation manners here. And the obvious changes or modifications derived therefrom are still within the protection scope of the present invention.

Claims

1. A method for fabricating an embedded SONOS memory, characterized in that, comprising: providing a substrate, on which a first silicon oxide layer and a first silicon nitride layer are formed, a first trench is formed in the first silicon nitride layer, and two opposite select transistor polysilicon gates covering the side surfaces of the first silicon nitride layer are formed in the first trench; etching the first silicon oxide layer on the bottom wall of the first trench to the surface of the substrate; etching a part of the thickness of the substrate on the bottom wall of the first trench to obtain a second trench, and forming two connection layers in the second trench, the connection layers contacting the substrate on the bottom wall of the second trench and respectively covering one of the select transistor polysilicon gates; forming an isolation oxide layer, the isolation oxide layer filling the second trench, wherein source regions corresponding to each other are formed on the substrate surfaces at the bottoms of the connection layers, and through the connection layers, each select transistor polysilicon gate is electrically connected to the source region at the bottom of each connection layer; removing the first silicon nitride layer and the first silicon oxide layer on the side of the select transistor polysilicon gate; forming a second silicon oxide layer, the second silicon oxide layer covering the side surfaces of the select transistor polysilicon gates; forming an ONO material layer, the ONO material layer covering the isolation oxide layer, the second silicon oxide layer and a part of the surface of the substrate; forming a first polysilicon material layer, the first polysilicon material layer covering the ONO material layer; etching the first polysilicon material layer and the ONO material layer above the isolation oxide layer and the first polysilicon material layer and the ONO material layer on a part of the substrate to obtain an ONO charge storage layer and a storage transistor polysilicon gate on the side of the second silicon oxide layer; and, forming a stacked logic oxide layer and a logic polysilicon gate on the substrate surface far from the storage transistor polysilicon gate.

2. The method for fabricating an embedded SONOS memory according to claim 1, characterized in that, the material of the connection layer is polysilicon.

3. The method for fabricating an embedded SONOS memory according to claim 2, characterized in that, the step of etching a part of the thickness of the substrate on the bottom wall of the first trench to obtain a second trench and forming a connection layer in the second trench, the connection layer covering the select transistor polysilicon gate, comprises: forming a second polysilicon material layer, the second polysilicon material layer covering the first silicon nitride layer, the select transistor polysilicon gate and the substrate on the bottom wall of the first trench; etching and removing the second polysilicon material layer on the first silicon nitride layer and the second polysilicon material layer on the bottom wall of the first trench to obtain the connection layer; and, etching a part of the thickness of the substrate on the bottom wall of the first trench to obtain the second trench.

4. The method for fabricating an embedded SONOS memory according to claim 1, characterized in that, In the process of forming the stacked logic oxide layer and the logic polysilicon gate, the preparation method of the embedded SONOS memory further includes: forming a silicon oxide sidewall that covers the side surfaces of the storage transistor polysilicon gate and the ONO charge storage layer.

5. The preparation method of the embedded SONOS memory according to claim 1, wherein, In the process of etching a partial thickness of the bottom wall of the first trench in the substrate to obtain the second trench, the partial thickness of the etched substrate is greater than 6. The preparation method of the embedded SONOS memory according to claim 1, wherein, In the second groove, the isolation oxide layer has a dimension in width of 7. The preparation method of the embedded SONOS memory according to claim 1, wherein, The thickness of the second silicon oxide layer is The thickness of the ONO charge storage layer is 8. The preparation method of the embedded SONOS memory according to claim 1, wherein, The ONO charge storage layer includes: a stacked silicon oxide film layer, a silicon nitride film layer, and a silicon oxide film layer.

9. An embedded SONOS memory, wherein, comprising: a substrate, on which a patterned first silicon oxide layer is formed; two oppositely disposed select transistor polysilicon gates that cover the patterned first silicon oxide layer; two connection layers that respectively cover one of the select transistor polysilicon gates and are in contact with the substrate, and a second trench is formed between the connection layer and a part of the thickness of the substrate; an isolation oxide layer that fills the second trench, wherein a corresponding source region is formed on the substrate surface at the bottom of each connection layer, and through the connection layer, each select transistor polysilicon gate is electrically connected to the source region at the bottom of each connection layer; a second silicon oxide layer that covers the side surfaces of the select transistor polysilicon gates; two ONO charge storage layers that are respectively located on the sides of the second silicon oxide layer and cover the side surfaces of the second silicon oxide layer and a part of the surface of the substrate; two storage transistor polysilicon gates that cover the ONO charge storage layers; and, a stacked logic oxide layer and a logic polysilicon gate that are located on the substrate surface far from the storage transistor polysilicon gate.

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