Method for forming a semiconductor memory structure

Abstract

The present invention provides a method for forming a semiconductor memory structure, including sequentially forming an active layer, a hard mask layer, and a core layer on a substrate, and etching the core layer to form a core pattern. The core pattern includes a first strip, a second strip, and a plurality of support members abutting the first strip and the second strip. This method further includes forming a spacer layer beside the core pattern, removing the core pattern, forming a photoresist pattern above the spacer layer, using the photoresist pattern and the spacer layer to etch the hard mask layer to form a hard mask pattern, and transferring the hard mask pattern to the active layer to form a gate stack.

Description

Technical Field

[0001] Embodiments of the present invention relate to a method for forming a semiconductor memory structure, and more particularly to a method for forming a flash memory. Background Art

[0002] To increase the element density and improve the overall performance of flash memory devices, current manufacturing technologies for flash memory devices continue to strive for miniaturization of element sizes. However, as the size of the smallest elements (such as contacts) continues to shrink, many challenges arise. Therefore, the industry still needs to improve the manufacturing methods of flash memory devices to overcome the problems caused by the shrinking of element sizes. Summary of the Invention

[0003] Embodiments of the present invention provide a method for forming a semiconductor memory structure. The method includes sequentially forming an active layer, a hard mask layer, and a core layer on a substrate, and etching the core layer to form a core pattern. The core pattern includes a first strip, a second strip, and a plurality of support components abutting the first strip and the second strip. The method further includes forming a spacer layer beside the core pattern, removing the core pattern, forming a photoresist pattern above the spacer layer, using the photoresist pattern and the spacer layer to etch the hard mask layer to form a hard mask pattern, and transferring the hard mask pattern to the active layer to form a gate stack.

[0004] Embodiments of the present invention provide a method for forming a semiconductor memory structure. The method includes sequentially forming an active layer, a hard mask layer, and a core layer on a substrate, and forming a first photoresist pattern and a second photoresist pattern on the core layer. The second photoresist pattern includes a first strip, a second strip, and a plurality of connecting components extending from the first strip to the second strip. The method further includes transferring the first photoresist pattern and the second photoresist pattern to the core layer to respectively form a first core pattern and a second core pattern, forming a pair of first spacers on both sides of the first core pattern, and a pair of second spacers on both sides of the second core pattern, removing the first core pattern and the second core pattern, forming a third photoresist pattern on the second spacers, and using the third photoresist pattern, the first spacers, and the second spacers to etch the hard mask layer and the active layer. Description of the Drawings

[0005] To make the features and advantages of the present invention more obvious and understandable, different embodiments are specifically described below in conjunction with the accompanying drawings as follows:

[0006] Figure 1A 、 Figure 1B 、 Figure 1C 、 Figure 1D 、 Figure 1E 、 Figure 1F 、 Figure 1G 、 Figure 1H 、Figure 1I FIG. 1 is a cross-sectional view showing a semiconductor memory structure in different stages according to some embodiments of the present invention.

[0007] Figure 1A-1 、 Figure 1B-1 、 Figure 1C-1 、 Figure 1D-1 、 Figure 1E-1 、 Figure 1F-1 、 Figure 1G-1 、 Figure 1H-1 、 Figure 1I-1 FIGS. 2-10 are plan views showing semiconductor memory structures of Figure 1A 、 Figure 1B 、 Figure 1C 、 Figure 1D 、 Figure 1E 、 Figure 1F 、 Figure 1G 、 Figure 1H 、 Figure 1I according to some embodiments of the present invention, respectively.

[0008] Figure 2A 、 Figure 2B 、 Figure 2C FIGS. 11-13 are cross-sectional views showing a semiconductor memory structure in different stages according to some embodiments of the present invention.

[0009] Figure 2A-1 FIG. 14 is a plan view showing a semiconductor memory structure of Figure 2A according to some embodiments of the present invention.

[0010] Figure 3A and Figure 3B FIGS. 15-17 are cross-sectional views showing a semiconductor memory structure in different stages according to some embodiments of the present invention.

[0011] Figure 3B-1 FIG. 18 is a plan view showing a semiconductor memory structure of Figure 3B according to some embodiments of the present invention.

[0012] Figure 4A-1 、 Figure 4B-1 、 Figure 4C-1 FIGS. 19-21 are plan views showing a semiconductor memory structure in different stages according to some embodiments of the present invention.

[0013] Reference numerals:

[0014] 50: Predetermined area of memory cells

[0015] 60: Predetermined area of selection transistors

[0016] 100: Semiconductor memory structure

[0017] 102: Semiconductor substrate

[0018] 103: Tunnel oxide

[0019] 104: First polysilicon layer

[0020] 105 Second polysilicon layer

[0021] 106: Gate dielectric layer

[0022] 107: Third polysilicon layer

[0023] 108: Fourth polysilicon layer

[0024] 110: Active layer

[0025] 115: Gate stack

[0026] 116: Gate stack

[0027] 120: Dielectric hard mask layer

[0028] 120’: Patterened dielectric hard mask layer

[0029] 125: Hard mask pattern

[0030] 126: Hard mask pattern

[0031] 130: Semiconductor hard mask layer

[0032] 130’: Patterened semiconductor hard mask layer

[0033] 135: Hard mask pattern

[0034] 136: Hard mask pattern

[0035] 140: Core layer

[0036] 140’: Patterened core layer

[0037] 145: Second core pattern

[0038] 146: Second core pattern

[0039] 147 1 : Strip

[0040] 147 2 : Strip

[0041] 148: Support member

[0042] 148 1 : Support part

[0043] 148 2 : Support part

[0044] 149; Opening

[0045] 150: Anti-reflection layer

[0046] 150’: Patterened anti-reflection layer

[0047] 160: Patterened photoresist layer

[0048] 165: First photoresist pattern

[0049] 166: Second photoresist pattern

[0050] 167 1 : Strip

[0051] 167 2 : Strip

[0052] 168: Connecting component

[0053] 169: Opening

[0054] 170: Conformal layer

[0055] 170’: Spacer layer

[0056] 175: First spacer

[0057] 176 1 : Second spacer

[0058] 176 2 : Second spacer

[0059] 177: Third spacer

[0060] 180: Filling layer

[0061] 180’: Filling layer

[0062] 182: Anti-reflection layer

[0063] 190: Patterened photoresist layer

[0064] 192: Photoresist pattern

[0065] 192A: Sidewall

[0066] 192B: Sidewall

[0067] 200: Semiconductor memory structure

[0068] 202: Notch

[0069] 300: Semiconductor memory structure

[0070] 302: Opening

[0071] A1: First direction

[0072] A2: The second direction

[0073] D1: Width

[0074] D2: Width

[0075] D3: Length

[0076] D4: Width

[0077] D5: Width

[0078] D6: Width

[0079] D7: Width

[0080] D8: Width

[0081] D9: Distance

[0082] D10: Distance

[0083] E1: Extension line

[0084] E2: Extension line Detailed implementation manners

[0085] The following will more comprehensively elaborate on this disclosure with reference to the diagrams of the embodiments of the present invention. However, this disclosure can also be implemented in various different embodiments and should not be limited to the embodiments described herein. The thickness of the layers and regions in the diagrams may be enlarged for clarity, and the same or similar reference numerals in each diagram represent the same or similar elements.

[0086] Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F , Figure 1G , Figure 1H , Figure 1I and Figure 1A-1 , Figure 1B-1 , Figure 1C-1 , Figure 1D-1 , Figure 1E-1 , Figure 1F-1 , Figure 1G-1 , Figure 1H-1 , Figure 1I-1 are schematic diagrams showing different stages of forming a semiconductor memory structure according to some embodiments of the present invention, where Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F , Figure 1G , Figure 1H , Figure 1I respectively alongFigure 1A-1 , Figure 1B-1 , Figure 1C-1 , Figure 1D-1 , Figure 1E-1 , Figure 1F-1 , Figure 1G-1 , Figure 1H-1 , Figure 1I-1 A cross-sectional schematic diagram taken along line I-I in the plan schematic diagram of

[0087] Figure 1A A cross-sectional schematic diagram showing the semiconductor memory structure 100, which includes a predetermined memory cell region 50 and a predetermined selection transistor region 60 adjacent to the predetermined memory cell region 50. Memory cells and their word lines will be formed in the predetermined memory cell region 50, and selection transistors (e.g., bit line selection transistors or source line selection transistors) will be formed in the predetermined selection transistor region 60. Although Figure 1A shows a predetermined memory cell region 50 and a predetermined selection transistor region 60 adjacent thereto, a predetermined memory cell region 50 can be disposed between two predetermined selection transistor regions 60. In some embodiments, the portion of the predetermined selection transistor region 60 close to the predetermined memory cell region 50 is a pattern-dense region, while the portion of the predetermined selection transistor region 60 far from the predetermined memory cell region 50 is a pattern-sparse region.

[0088] The formation of the semiconductor memory structure 100 includes providing a semiconductor substrate 102. In some embodiments, the semiconductor substrate 102 can be an elemental semiconductor substrate, such as a silicon substrate or a germanium substrate; or a compound semiconductor substrate, such as a silicon carbide substrate or a gallium arsenide substrate. In some embodiments, the semiconductor substrate 102 can be a semiconductor-on-insulator (SOI) substrate.

[0089] Form an active layer 110 over a semiconductor substrate 102. According to some embodiments, the active layer 110 is a multi-layer stack that includes a tunneling oxide layer 103, a first polysilicon layer 104, a second polysilicon layer 105, a gate dielectric layer 106, a third polysilicon layer 107, and a fourth polysilicon layer 108 formed in sequence over the semiconductor substrate 102. The tunneling oxide layer 103 can be formed of silicon oxide. The first polysilicon layer 104 and the second polysilicon layer 105 can be doped and are used to form the floating gate of a memory cell. The gate dielectric layer 106 can be a three-layer structure including oxide-nitride-oxide (ONO). The third polysilicon layer 107 and the fourth polysilicon layer 108 can be doped and are used to form the control gate of a memory cell and can also serve as a word line.

[0090] Form a dielectric hard mask layer 120 over the active layer 110. In some embodiments, the dielectric hard mask layer 120 is formed of a dielectric material, such as, silicon oxide (SiO), silicon oxynitride (SiON), silicon nitride (SiN), and / or other suitable dielectric materials. In one embodiment, the dielectric hard mask layer 120 is formed of tetraethyl orthosilicate (TEOS) oxide.

[0091] Form a semiconductor hard mask layer 130 over the dielectric hard mask layer 120. In some embodiments, the semiconductor hard mask layer 130 is formed of a semiconductor material, such as, polysilicon.

[0092] Form a core layer 140 over the semiconductor hard mask layer 130. In some embodiments, the core layer 140 is formed of a carbon-rich material, such as, a carbon layer or spin-on coating (SOC).

[0093] Form an anti-reflection layer 150 over the core layer 140. In some embodiments, the anti-reflection layer 150 is formed of a silicon-rich material, such as, silicon oxynitride (SiON).

[0094] Use a lithography process to form a patterned photoresist layer 160 over the anti-reflection layer 150, as Figure 1A and Figure 1A-1 shown. The patterned photoresist layer 160 includes a plurality of first photoresist patterns 165 disposed in a predetermined region 50 of the memory cell, and a second photoresist pattern 166 disposed in a predetermined region 60 of the select transistor.

[0095] These first photoresist patterns 165 are long strips arranged in parallel in a first direction A1 and extending along a second direction A2, as Figure 1A-1 shown. The first direction A1 and the second direction A2 are horizontal directions, and the first direction A1 is substantially perpendicular to the second direction A2. The number of the first photoresist patterns 165 in a predetermined memory cell area 50 can be about 6 to about 10, for example, 8.

[0096] The second photoresist pattern 166 has a rail-shaped profile. Specifically, the second photoresist pattern 166 includes strips 167 1 , strips 167 2 , and a plurality of connecting members 168 between the strips 167 1 and the strips 167 2 , as Figure 1A-1 shown. The strip 167 1 is closer to the predetermined memory cell area 50 than the strip 167 2 . The strip 167 1 and the strip 167 2 are arranged in parallel in the first direction A1 and extend along the second direction A2. These connecting members 168 are arranged in parallel in the second direction A2 and extend along the first direction A1. The connecting members 168 continuously extend from the strip 167 1 to the strip 167 2 to connect the strip 167 1 and the strip 167 2 . The strip 167 1 , the strip 167 2 , and the connecting members 168 define a plurality of openings 169 that expose the antireflection layer 150. The number of the connecting members 168 in a predetermined select transistor area 60 can depend on the lengths of the strip 167 1 and the strip 167 2 , for example, about 5 to about 1000.

[0097] In some embodiments, the strip 167 1 and the strip 167 2 of the second photoresist pattern 166 have a width D1 along the first direction A1, and the first photoresist pattern 165 has a width D2 along the first direction A1. The ratio of the width D1 to the width D2 is about 0.8 to about 1.0. If the ratio of the width D1 to the width D2 is too small, the risk of collapse of the core pattern formed subsequently in the predetermined select transistor area 60 increases. If the ratio of the width D1 to the width D2 is too large, the overlay tolerance of the lithography process for forming the select gate pattern subsequently cannot be increased.

[0098] In some embodiments, the opening 169 has a length D3 along the second direction A2 (i.e., the distance between adjacent connecting members 168), and a width D4 along the first direction A1 (i.e., the distance between the strip 167 1 and the strip 167 2 ). The ratio of the length D3 to the width D4 is from about 1.0 to about 4.0.

[0099] Using the patterned photoresist layer 160, an etching process is performed on the semiconductor memory structure 100 to sequentially etch and remove the portions of the anti-reflection layer 150 and the core layer 140 that are not covered by the patterned photoresist layer 160 until the upper surface of the semiconductor hard mask layer 130 is exposed, as shown in Figure 1B and Figure 1B-1 . In some embodiments, the etching process is dry etching. The patterned photoresist layer 160 may be completely consumed during the etching process or removed by an additional ashing process.

[0100] After the etching process, the anti-reflection layer 150 and the core layer 140 are respectively labeled as the patterned reflection layer 150' and the patterned core layer 140'. The photoresist patterns 165 and 166 of the patterned photoresist layer 160 are transferred to the core layer 140, such that the core layer 140 forms a plurality of first core patterns 145 corresponding to the first photoresist pattern 165 and a second core pattern 146 corresponding to the second photoresist pattern 166. According to some embodiments, after the etching process, a trimming process may be performed on the patterned core layer 140' to reduce the defects formed on the surface of the semiconductor memory structure 100. The trimming process may be, for example, an etching process using O 2 .

[0101] These first core patterns 145 are strips that are arranged in parallel in the first direction A1 and extend along the second direction A2. The second core pattern 146 includes the strip 147 1 , the strip 147 2 , and a plurality of support members 148 between the strip 147 1 and the strip 147 2 . The strip 147 1 is closer to the predetermined memory cell region 50 than the strip 147 2 . The strip 147 1 and the strip 147 2 are arranged in parallel in the first direction A1 and extend along the second direction A2. These support members 148 are arranged in parallel in the second direction A2 and extend along the first direction A1. The support members 148 abut against the strip 147 1 and the strip 147 2 , and continuously extend from the strip 147 1 to the strip 147 2。The elongated strip 147 1 、the elongated strip 147 2 、and the support member 148 define a plurality of openings 149, and the openings 149 expose the semiconductor hard mask layer 130.

[0102] Abuts against the elongated strip 147 1 and 147 2 A plurality of support members 148 configured to support the elongated strip 147 1 With the elongated strip 147 2 So as to prevent the elongated strip 147 1 From the elongated strip 147 2 From collapsing. Since the etching process generates a large etching amount in the pattern sparse area, in the case where the support member 148 is not formed, the width of the core pattern formed in the predetermined area of the select transistor needs to be larger than the width of the core pattern formed in the predetermined area of the memory cell, so as to avoid the core pattern in the predetermined area of the select transistor from collapsing during or after, for example, the trimming process. Thus, the elongated strip 147 of the second core pattern 146 formed in the predetermined area 60 of the select transistor 1 And the elongated strip 147 2 Can be formed to have the same width as the first core pattern 145 formed in the predetermined area 50 of the memory cell, or a width narrower than the first core pattern 145, which can increase the overlay tolerance of the photolithography process for subsequently forming the select gate pattern.

[0103] In some embodiments, the elongated strip 147 of the second core pattern 146 1 And the elongated strip 147 2 Has a width D5 along the first direction A1, the first core pattern 145 has a width D6 along the first direction A1, and the ratio of the width D5 to the width D6 is about 0.8 to about 1.0. If the ratio of the width D5 to the width D6 is too small, the risk of collapse of the core pattern 146 increases. If the ratio of the width D5 to the width D6 is too large, the overlay tolerance of the photolithography process for subsequently forming the select gate pattern cannot be increased. In addition, in some embodiments, due to the etching loading effect, the width D5 of the elongated strip 147 near the pattern sparse area 2 May be smaller than the width D5 of the elongated strip 147 located in the pattern dense area 1 .

[0104] The conforming layer 170 is formed along the upper surface of the semiconductor hard mask layer 130, the sidewalls of the patterned core layer 140', the sidewalls and the upper surface of the patterned anti-reflection layer 150', as Figure 1C And Figure 1C-1As shown. The compliant layer 170 overfills the opening 149. In some embodiments, the compliant layer 170 is formed of a dielectric material, such as, silicon oxide, silicon oxynitride, silicon nitride, and / or other suitable dielectric materials.

[0105] A etching process is performed on the semiconductor memory structure 100. The etching process removes portions of the compliant layer 170 along the upper surface of the semiconductor hard mask layer 130 and the upper surface of the patterned anti-reflection layer 150', thereby forming a spacer layer 170' beside the patterned core layer 140', as Figure 1D and Figure 1D-1 shown. In some embodiments, the etching process is a dry etching. The patterned anti-reflection layer 150' may be completely consumed in the etching process or removed by an additional etching process.

[0106] The spacer layer 170' includes multiple pairs of first spacers 175 disposed on both sides of the first core pattern 145, a pair of second spacers 176 disposed on both sides of the second core pattern 146, and multiple third spacers 177 filling the opening 149. Along the strip 147 1 The second spacer layer formed is denoted by the symbol 176 1 and along the strip 147 2 The second spacer layer formed is denoted by the symbol 176 2 shown. According to some embodiments, due to the characteristics of the etching process, the first spacers 175 and the second spacers 176 have a gradually decreasing width upwards.

[0107] The first spacers 175 are arranged in parallel in the first direction A1 and extend along the second direction A2. The second spacers 176 1 and 176 2 are arranged in parallel in the first direction A1 and extend along the second direction A2. The third spacer layer 177 are separated from each other by the support members 148 and are arranged in the second direction A2.

[0108] In some embodiments, the first spacers 175 and the second spacers 176 1 and 176 2 have a width D7, and the third spacer layer 177 has a width D8. In some embodiments, the ratio of the width D7 to the width D8 ranges from about 0.1 to about 1.0.

[0109] The patterned core layer 140' is removed until the semiconductor hard mask layer 130 is exposed, as Figure 1E and Figure 1E-1 shown. In some embodiments, the etching process is a dry etching. Since the strip 147 1 / 147 2 is formed with a relatively narrow width, the second spacer 176 1 / 176 2 The distance D9 between the second spacer 176 and the third spacer 177 (i.e., the width D5 of the second core pattern 147 1 / 147) is equal to or less than the distance D10 between the first spacers 175 (i.e., the width D6 of the first core pattern 145), which can increase the overlay tolerance of the lithography process for subsequently forming the select gate pattern. In some embodiments, the ratio of the distance D9 to the distance D10 ranges from about 0.8 to about 1.0. If the ratio of the distance D9 to the distance D10 is too large, the overlay tolerance of the lithography process for subsequently forming the select gate pattern cannot be increased.

[0110] Form a filling layer 180, an anti-reflection layer 182, and a patterned photoresist layer 190 on the semiconductor memory structure 100 in sequence, as Figure 1F and Figure 1F-1 shown. The filling layer 180 covers the spacer layer 170' and fills the gap formed by removing the patterned core layer 140'. In some embodiments, the filling layer 180 is formed of a carbon-rich material, such as spin-on carbon (SOC) or a carbon layer. In some embodiments, the anti-reflection layer 182 is formed of a silicon-rich material, such as silicon oxynitride (SiON).

[0111] The patterned photoresist layer 190 includes a photoresist pattern 192 disposed in the predetermined region 60 of the select transistor. The photoresist pattern 192 is disposed directly above and covers the second spacer 176 1 and 176 2 and the third spacer 177. In some embodiments, the extension line E1-E1 of the sidewall (edge) 192A of the photoresist pattern 192 in the pattern-dense region is aligned with (e.g., passes through) the second spacer 176 1 . That is, in the plan view of Figure 1F-1 , the sidewall 192A of the photoresist pattern 192 is located within the region of the second spacer 176 1 . In some embodiments, the extension line E2-E2 of the other sidewall (edge) 192B of the photoresist pattern 192 in the pattern-sparse region is aligned with (e.g., passes through) the second spacer 176 2 . That is, in the plan view of Figure 1F-1 , the sidewall 192B of the photoresist pattern 192 is located within the region of the second spacer 176 2 .

[0112] By forming the support member 148 ( Figure 1B-1 ) of the second core pattern 146, the strip 147 1 of the second core pattern 146 and the strip 147 2 can form a narrower width D5, thereby reducing the second spacer 176 1 / 1762 the distance D9 between it and the third spacer 177 Figure 1E-1 ). Thus, the coverage rate (i.e., area ratio) of the second core pattern 146 (including the second spacer 176 1 / 176 2 and the third spacer 177) in the selected transistor predetermined area 60 is increased, which reduces the possibility of misalignment between the photoresist pattern 192 and the second spacer 176 1 / 176 2 . For example, the extension line E1 - E1 (or E2 - E2) of the sidewall 192A (or 192B) of the photoresist pattern 192 does not pass through the second spacer 176 1 (or 176 2 ). If the photoresist pattern 192 is misaligned with the second spacer 176 1 / 176 2 , it may cause a pattern fail problem for the subsequently formed select gate.

[0113] Therefore, the embodiment of the present invention utilizes the support member 148 for forming the second core pattern 146 to increase the overlay tolerance of the lithography process for forming the patterned photoresist layer 190. The specification / control limit of the lithography process overlay is relaxed, thereby reducing the production cost and increasing the product yield.

[0114] Using the patterned photoresist layer 190 and the spacer layer 170', an etching process is performed on the semiconductor memory structure 100 to sequentially etch and remove the portions of the anti - reflection layer 182, the fill layer 180, and the semiconductor hard mask layer 130 that are not covered by the patterned photoresist layer 190 and the spacer layer 170' until the upper surface of the dielectric hard mask layer 120 is exposed, as Figure 1G and Figure 1G-1 shown. In some embodiments, the etching process is dry etching. The semiconductor hard mask layer 130 after the etching process is labeled as the patterned semiconductor hard mask layer 130'. The pattern of the first spacer 175 is transferred to the semiconductor hard mask layer 130 to form the hard mask pattern 135, and the photoresist pattern 192 of the patterned photoresist layer 190 and the second spacer 176 1 / 176 2 patterns are jointly transferred to the semiconductor hard mask layer 130 to form the hard mask pattern 136. The patterned photoresist layer 190 and the anti - reflection layer 182 may also be completely consumed in the etching process or removed by an additional process. The remaining portion of the fill layer 180 is labeled as the fill layer 180'. In addition, the first spacer 175 that is not covered by the photoresist pattern 192 may be partially consumed in the etching process.

[0115] Using a patterned semiconductor hard mask layer 130', an etching process is performed on the semiconductor memory structure 100 to etch the portion of the dielectric hard mask layer 120 that is not covered by the patterned semiconductor hard mask layer 130' until the upper surface of the active layer 110 is exposed, as Figure 1H and Figure 1H-1 shown. In some embodiments, the etching process is a dry etching. The dielectric hard mask layer 120 after the etching process is labeled as the patterned dielectric hard mask layer 120'. The hard mask patterns 135 and 136 of the patterned semiconductor hard mask layer 130' are transferred to the dielectric hard mask layer 120, such that the dielectric hard mask layer 120 forms hard mask patterns 125 and 126 respectively. The fill layer 180' and the spacer layer 170' may also be removed during the etching process, or may be removed by an additional etching process.

[0116] Using the patterned dielectric hard mask layer 120', an etching process is performed on the semiconductor memory structure 100 to etch the portion of the active layer 110 that is not covered by the patterned dielectric hard mask layer 120' until the tunneling oxide layer 103 is exposed, as Figure 1I shown. The etching process includes multiple etching steps for various material layers. The dielectric hard mask layer 120 after the etching process is labeled as the dielectric hard mask layer 120'. The hard mask patterns 125 and 126 of the patterned dielectric hard mask layer 120' are transferred to the active layer 110, such that the active layer 110 forms a gate stack 115 in the memory cell predetermined region 50 and a gate stack 116 in the select transistor predetermined region 60 respectively. In some embodiments, additional components (e.g., source / drain regions) may be formed on the semiconductor memory structure 100 to fabricate a semiconductor memory device, such as a negative-and flash memory (NAND flash memory).

[0117] The gate stack 115 is used to form the memory cells of the flash memory device, wherein the first polysilicon layer 104 and the second polysilicon layer 105 are configured as the floating gates of the memory cells; the third polysilicon layer 107 and the fourth polysilicon layer 108 are configured as the control gates of the memory cells and also serve as the word lines of the memory cells. The gate stack 116 is used to form the select transistor.

[0118] An embodiment of the present invention utilizes a support member 148 for forming a second core pattern 146 to increase the overlay tolerance of the lithography process for forming the patterned photoresist layer 190. Therefore, the specification / control limitations of the lithography process overlay can be alleviated, thereby reducing the production cost and improving the product yield.

[0119] Figure 2A 、 Figure 2B 、 Figure 2C and Figure 2A-1FIG. 0 is a schematic diagram showing different stages of forming a semiconductor memory structure 200 according to some embodiments of the present invention, wherein Figure 2A is a cross-sectional schematic diagram taken along line I-I in the plan view of Figure 2A-1 . Components identical to those in the foregoing Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F , Figure 1G , Figure 1H , Figure 1I embodiments are denoted by the same reference numerals and their descriptions are omitted. Figure 2A , Figure 2B , Figure 2C The semiconductor memory structure 200 of Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F , Figure 1G , Figure 1H , Figure 1I is substantially similar to the semiconductor memory structure 100 of 1 / 176 2 , except for the misalignment of the photoresist pattern 192 and the second spacer 176

[0120] Subsequently Figure 1E , a fill layer 180, an anti-reflection layer 182, and a patterned photoresist layer 190 are sequentially formed over the semiconductor memory structure 200, as shown in Figure 2A and Figure 2A-1 . The patterned photoresist layer 190 includes a photoresist pattern 192 disposed in a predetermined region 60 of the select transistor. The photoresist pattern 192 covers the second spacer 176 1 , but does not cover the second spacer 176 2 . In some embodiments, the extension line E1-E1 of the sidewall 192A of the photoresist pattern 192 does not pass through the second spacer 176 1 . That is, in the plan view of Figure 2A-1 , the sidewall 192A of the photoresist pattern 192 is located outside the region of the second spacer 176 1 . In some embodiments, the extension line E2-E2 of the other sidewall 192B of the photoresist pattern 192 does not pass through the second spacer 176 2 . That is, in the plan view of Figure 2A-1 , the sidewall 192B of the photoresist pattern 192 is located outside the region of the second spacer 176 2 .

[0121] Performing the foregoing Figure 1GThe steps described above are performed to form a patterned semiconductor hard mask layer 130', as shown in Figure 2B . Since the photoresist pattern 192 does not cover the second spacer 176 2 , a notch 202 is formed on the upper surface of the hard mask pattern 136 between the filling layer 180' and the second spacer 176 2 . According to an embodiment of the present invention, by forming a support member 148 of the second core pattern 146( Figure 1B-1 ), the strip 147 of the second core pattern 146 1 and the strip 147 2 can form a narrower width D5, thereby reducing the distance D9 between the second spacer 176 1 and the third spacer 177 (Fig. 1E-1). As a result, the notch 202 formed on the upper surface of the hard mask pattern 136 can also have a smaller size.

[0122] The foregoing Figure 1H etching process is performed on the semiconductor memory structure 200 to form a patterned dielectric hard mask layer 120', as shown in Figure 2C . Due to the smaller-sized notch 202, the possibility of the etching process extending the notch 202 to the mask pattern 126 is reduced. If the notch extends to the mask pattern of the dielectric hard mask layer, it may cause a pattern fail problem for the subsequently formed select gate. Therefore, the specifications / control limits of the photolithography process stack are relaxed, thereby reducing production costs and improving product yield.

[0123] Figure 3A and Figure 3B and Figure 3B-1 are schematic diagrams showing different stages of forming a semiconductor memory structure 300 according to some embodiments of the present invention, where Figure 3B is a cross-sectional schematic diagram taken along line I-I in the plan schematic diagram of Figure 3B-1 . Components identical to those in the foregoing Figure 1A 、 Figure 1B 、 Figure 1C 、 Figure 1D 、 Figure 1E 、 Figure 1F 、 Figure 1G 、 Figure 1H 、 Figure 1I 、 Figure 3A embodiments use the same reference numerals and their descriptions are omitted. and Figure 3B The semiconductor memory structure 300 of Figure 1A 、 Figure 1B 、 Figure 1C 、 Figure 1D 、 Figure 1E 、 Figure 1F 、 Figure 1G, Figure 1H , Figure 1I The semiconductor memory structure 100 is substantially similar, except for the third spacer 177.

[0124] Subsequently Figure 1B , a conforming layer 170 is formed over the semiconductor memory structure 300, as Figure 3A shown. The conforming layer 170 is formed on the sidewalls and bottom surface of the opening 149 to partially fill the opening 149.

[0125] The foregoing Figure 1D and Figure 1E described steps are performed on the semiconductor memory structure 300 to form a spacer layer 170' and remove the patterned core layer 140', as Figure 3B and Figure 3B-1 shown. According to some embodiments, the spacer layer 170' includes second spacers 176 1 and 176 2 , and a plurality of third spacers 177 that partially fill the opening 149. Since the portion of the conforming layer 170 formed on the bottom surface of the opening 149 is removed, the third spacer 177 has an opening 302 that exposes the semiconductor hard mask layer 130. Thus, in Figure 3B-1 the plan view, the third spacer 177 has a closed annular profile.

[0126] Figure 4A-1 , Figure 4B-1 , Figure 4C-1 are plan views showing the formation of a semiconductor memory structure 400 at different stages according to some embodiments of the present invention. The components of the same embodiments as those in the foregoing Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F , Figure 1G , Figure 1H , Figure 1I are denoted by the same reference numerals and their descriptions are omitted. Figure 4A-1 , Figure 4B-1 , Figure 4C-1 The semiconductor memory structure 400 is substantially similar to the semiconductor memory structure 100 of Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F , Figure 1G , Figure 1H , Figure 1I , except for the third spacer 177.

[0127] According to some embodiments, Figure 4A-1The first photoresist pattern 165 and the second photoresist pattern 166 of the patterned photoresist layer 160 are shown. The width of the connecting member 168 of the second photoresist pattern 166 in the second direction D2 tapers from the strip 167 1 and 167 2 towards the center of the connecting member 168, such that the opening 169 can have a hexagonal-like profile.

[0128] The steps as described are performed on the semiconductor memory structure 400 Figure 1B to form the patterned core layer 140', as Figure 4B-1 shown. After the trimming process, the support members 148 of the patterned core layer 140' are disconnected at the center and become separated support portions 148 1 and support portions 148 2 . The support portions 148 1 abut against the strip 147 1 , while the support portions 148 2 abut against the strip 147 2 . The openings 149 are connected to each other.

[0129] The steps as described above are performed on the semiconductor memory structure 400 Figure 3B to form the spacer layer 170' and remove the patterned core layer 140', as Figure 4C-1 shown. The spacer layer 170' includes a plurality of third spacers 177 disposed on the second spacers 176 1 and 176 2 , and partially filling the openings 149. These third spacers 177 are connected to each other and each has an opening 302 exposing the semiconductor hard mask layer 130.

[0130] According to the foregoing, embodiments of the present invention utilize the support members for forming the second core pattern to increase the overlay tolerance of the lithography process for forming the select gate pattern. Therefore, the specifications / control limits of the lithography process overlay are relaxed, thereby reducing production costs and improving product yield.

[0131] The components of several embodiments are outlined above so that those skilled in the art can better understand the viewpoints of the embodiments of the present invention. Those skilled in the art should understand that they can easily design or modify other processes and structures based on the embodiments of the present invention to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of the present invention, and they can make various changes, substitutions, and replacements without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be defined by the appended claims.

Claims

1. A method for forming a semiconductor memory structure, characterized in that, comprising: sequentially forming an active layer, a hard mask layer, and a core layer on a substrate; etching the core layer to form a core pattern, wherein the core pattern includes a first strip, a second strip, and a plurality of support components abutting the first strip and the second strip; forming a spacer layer beside the core pattern; removing the core pattern; forming a photoresist pattern above the spacer layer; using the photoresist pattern and the spacer layer to etch the hard mask layer to form a hard mask pattern; and transferring the hard mask pattern to the active layer to form a gate stack, wherein the step of forming the spacer layer includes: forming a conformal layer along the core pattern and filling a plurality of openings defined by the first strip, the second strip, and the support components; and etching the conformal layer, wherein the spacer layer includes: a first spacer formed on a first side of the first strip; a second spacer formed on a second side of the second strip; and a plurality of third spacers filling the plurality of openings.

2. The method for forming a semiconductor memory structure according to claim 1, characterized in that, the plurality of support components extend along a first direction, the first strip and the second strip extend along a second direction, the second direction is substantially perpendicular to the first direction, and the plurality of support components are arranged in the second direction.

3. The method for forming a semiconductor memory structure according to claim 1, characterized in that, further comprising: before forming the spacer layer, performing a trimming process on the core pattern such that the plurality of support components form a plurality of first support portions abutting the first strip and a plurality of second support portions abutting the second strip, wherein.

4. The method for forming a semiconductor memory structure according to claim 1, characterized in that, the plurality of third spacers are spaced apart from each other, and at least one of the plurality of third spacers has a closed annular profile.

5. The method for forming a semiconductor memory structure according to claim 1, characterized in that, further comprising: before forming the spacer layer, performing a trimming process on the core pattern such that the plurality of openings are connected to each other, wherein the plurality of third spacers are connected to each other.

6. The method for forming a semiconductor memory structure according to claim 1, characterized in that, an extension line of a first sidewall of the photoresist pattern passes through the first spacer, and an extension line of a second sidewall of the photoresist pattern passes through the second spacer.

7. A method for forming a semiconductor memory structure, characterized in that, comprising: sequentially forming an active layer, a hard mask layer, and a core layer on a substrate; forming a first photoresist pattern and a second photoresist pattern on the core layer, wherein the second photoresist pattern includes a first strip, a second strip, and a plurality of connecting components extending from the first strip to the second strip; transferring the first photoresist pattern and the second photoresist pattern to the core layer to respectively form a first core pattern and a second core pattern; Form a pair of first spacers on both sides of the first core pattern, and a pair of second spacers on both sides of the second core pattern; Remove the first core pattern and the second core pattern; Form a third photoresist pattern on the pair of second spacers, wherein the third photoresist pattern covers one of the pair of second spacers but does not cover the other of the pair of second spacers; and Use the third photoresist pattern, the first spacers, and the second spacers to etch the hard mask layer and the active layer.

8. The method of forming a semiconductor memory structure as claimed in claim 7, wherein, the hard mask layer includes a dielectric layer and a semiconductor layer on the dielectric layer, and the step of etching the hard mask layer includes: etching the semiconductor layer such that portions of the semiconductor layer covered by the pair of first spacers form a plurality of first hard mask patterns, and portions of the semiconductor layer covered by the third photoresist pattern and the pair of second spacers form a second hard mask pattern; and etching the dielectric layer such that portions of the dielectric layer covered by the plurality of first hard mask patterns form a plurality of third hard mask patterns, and portions of the dielectric layer covered by the second hard mask pattern form a fourth hard mask pattern.

9. The method of forming a semiconductor memory structure as claimed in claim 8, wherein, etching the active layer such that portions of the active layer covered by the plurality of third hard mask patterns form a plurality of first gate stacks, and portions of the active layer covered by the fourth hard mask pattern form a second gate stack.

10. The method of forming a semiconductor memory structure as claimed in claim 7, wherein, further comprising: while forming the pair of first spacers and the pair of second spacers, form a third spacer to fill a first opening in the second core pattern, wherein the third spacer has a second opening exposing the hard mask layer.

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