Power semiconductor element
By designing multilayer epitaxial layers and optimizing doped regions, the challenge of balancing high breakdown voltage and low on-resistance in power semiconductor devices has been solved, resulting in improved electric field and reliability, while reducing the terminal area.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-02-09
- Publication Date
- 2026-03-20
AI Technical Summary
Existing power semiconductor devices struggle to meet the requirements of both high breakdown voltage and low on-resistance, and common termination area designs increase area or lead to decreased reliability.
A multi-layer epitaxial layer design is adopted. By setting a second doped region in the terminal region and a first doped region in the active region, the doping concentration and width/depth are adjusted to reduce the electric field and optimize the resistance, thereby reducing the area of the terminal region.
It achieves reduced electric field and on-resistance, improved reliability, and maintained or increased breakdown voltage without increasing the terminal area.
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Figure CN114464668B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to a power semiconductor device. BACKGROUND
[0002] The characteristics of a power semiconductor device depend on breakdown voltage and on-resistance (RDSon) characteristics. The doping concentration and thickness of epitaxial layers and the design of the termination region affect the breakdown voltage. However, most methods for increasing the breakdown voltage reduce the on-resistance, so it is difficult to meet the requirements of both high breakdown voltage and low on-resistance.
[0003] One of the common termination region designs is a floating field ring (FFR), but this design requires a large enough termination region area, which is not conducive to the miniaturization of power semiconductor devices. Another common termination region design is to fill the trench with polysilicon or oxide to reduce the electric field concentration phenomenon, but this design easily causes the edge electric stress of the termination region to concentrate and cause reliability to decrease.
[0004] Therefore, how to provide a power semiconductor device that can solve the above problems is still one of the directions that the industry urgently needs to research. SUMMARY
[0005] One technical aspect of the present application is a power semiconductor device.
[0006] In one embodiment, the power semiconductor device includes a first electrode, a substrate, a first epitaxial layer, a second epitaxial layer, a gate electrode, and a second electrode. The substrate is on the first electrode, and the substrate has an active region and a termination region surrounding the active region. The first epitaxial layer is on the substrate, wherein the first epitaxial layer has a first conductivity type, and the first epitaxial layer includes a first doped region and a second doped region. The first doped region has the first conductivity type and is in the termination region and the active region. The second doped region has a second conductivity type and is in the termination region. The second epitaxial layer is on the first epitaxial layer. The gate electrode is on the second epitaxial layer and is in the active region. The second electrode is on the second epitaxial layer and is in the active region.
[0007] In one embodiment, the doping concentration of the first doped region is in the range of 5x10 17 cm -3 to 1x10 19 cm -3 .
[0008] In one embodiment, the doping concentration of the second doped region is in the range of 5x10 16 cm -3 to 2x10 18 cm -3 .
[0009] In one embodiment, the first doped region comprises a first zone and a second zone, wherein the first zone is between the second zone and the second doped region, and the doping concentration of the first zone is greater than the doping concentration of the second zone.
[0010] In one embodiment, the number of the first epitaxial layers is plural, and the width of the first doped region of the first epitaxial layer increases as the distance to the second epitaxial layer increases.
[0011] In one embodiment, the number of the first epitaxial layers is plural, and the width of the first doped region of the first epitaxial layer decreases as the distance to the second epitaxial layer increases.
[0012] In one embodiment, the number of the first epitaxial layers is plural, and the first epitaxial layers have different thicknesses.
[0013] In one embodiment, the width of one of the second doped regions is different from the width of another of the second doped regions.
[0014] In one embodiment, the depth of one of the second doped regions is different from the depth of another of the second doped regions.
[0015] In one embodiment, there is a spacing between two adjacent ones of the second doped regions, and one of the spacings between the second doped regions is different from another of the spacings.
[0016] In the above embodiments, by disposing the second doped regions in the termination region, the electric field of the edge of the first epitaxial layer, the second epitaxial layer and the termination region can be reduced, and the reliability can be improved. By disposing the first doped regions in the active region and the termination region, the resistance of the region where the first doped regions are located can be reduced, and the on-resistance of the power semiconductor element as a whole can be reduced. By such design, the area of the termination region and the overall volume of the power semiconductor element can be reduced. BRIEF DESCRIPTION OF DRAWINGS
[0017] Figure 1A is a top view of a power semiconductor element according to an embodiment of the present application.
[0018] Figure 1B is a cross-sectional view along the center line segment 1B-1B. Figure 1A
[0019] Figure 2 is a cross-sectional view of a power semiconductor element according to another embodiment of the present application.
[0020] Figure 3 is a cross-sectional view of a power semiconductor element according to still another embodiment of the present application.
[0021] Figure 4 This is a cross-sectional view of a power semiconductor device according to another embodiment of the present invention.
[0022] Figure 5 This is a cross-sectional view of a power semiconductor device according to another embodiment of the present invention. Detailed Implementation
[0023] The following describes several embodiments of the present invention with reference to the accompanying drawings. For clarity, many practical details will be described in the following description. However, it should be understood that these practical details are not intended to limit the invention. That is, in some embodiments of the invention, these practical details are not essential. Furthermore, for the sake of simplicity, some conventional structures and elements will be shown in the drawings in a simple schematic manner. And for clarity, the thickness of layers and regions in the drawings may be exaggerated, and the same element symbols denote the same elements in the description of the drawings.
[0024] Figure 1A This is a top view of a power semiconductor element 100 according to an embodiment of the present invention. Figure 1B For along Figure 1A A cross-sectional view along line segment 1B-1B. The power semiconductor device 100 includes a first electrode 110, a substrate 120, a first epitaxial layer 130, a second epitaxial layer 140, a second electrode 154, and a gate electrode 156. The first electrode 110 is the drain electrode, and the second electrode 154 is the source electrode. The substrate 120 has an active region AC and a termination region TM surrounding the active region AC. In this embodiment, the power semiconductor device 100 is an N-type (first conductivity type) device. The substrate 120 is made of silicon carbide (SiC) and is an N-type heavily doped substrate. Silicon carbide is a wide bandgap semiconductor material suitable for high-voltage power devices; this embodiment uses 4H-SiC as an example.
[0025] The first epitaxial layer 130 is stacked on the substrate 120. The first epitaxial layer 130 may be multilayered; for example, this embodiment uses three layers, but the invention is not limited thereto. The second epitaxial layer 140 is located on the side of the first epitaxial layer 130 that faces away from the substrate 120, that is, the second epitaxial layer 140 is the upper epitaxial layer. Both the first epitaxial layer 130 and the second epitaxial layer 140 have the same conductivity type (N-type) as the substrate 120, and the doping concentration of the first epitaxial layer 130 and the second epitaxial layer 140 is lower than the doping concentration of the substrate 120.
[0026] Each of the first epitaxial layers 130 includes a first doped region 132 and a plurality of second doped regions 134. The first doped region 132 is an N-type doped region, and the second doped regions 134 are P-type doped regions (second conductivity type). The first doped region 132 is located in the termination region TM and the active region AC. Specifically, the first doped region 132 is partially located in the active region AC near one side of the termination region TM. The second doped regions 134 are all located in the termination region TM. In the embodiment, each of the first epitaxial layers 130 has the first doped region 132 and the second doped regions 134 with the same doping range, but the present application is not limited thereto.
[0027] The power semiconductor device 100 further includes a well 150, a source region 152, a well 153, and a gate oxide layer 158 located in the active region AC. The well 150 is a P-type doped region (P-well), and the source region 152 is an N-type doped region located in the well 150. A second electrode 154 is electrically connected to the source region 152. The well 153 is a P-type heavily doped region (P+-well) electrically connected to the well 150 and the second electrode 154. A gate electrode 156 is disposed above the source region 152. The gate oxide layer 158 is located on the second epitaxial layer 140. The gate electrode 156 is located on the gate oxide layer 158. A channel region is formed between the P-type well 150 and the N-type source region 152.
[0028] The power semiconductor device 100 further includes a third doped region 160 located between the second epitaxial layer 140 and the gate oxide layer 158 and in the termination region TM. The third doped region 160 is a P-type doped region. When a reverse bias is applied to the power semiconductor device 100, the second electrode 154 (source electrode) is grounded, and the first electrode 110 (drain electrode) is a positive voltage. The third doped region 160 can move the maximum electric field to the second epitaxial layer 140. The present application can reduce the electrical stress of the edge of the first epitaxial layer 130, the second epitaxial layer 140, and the termination region TM by disposing the P-type second doped regions 134 in the first epitaxial layer 130 (N-type) in the termination region TM.
[0029] For example, Figure 1B The equipotential lines in the first epitaxial layers 130 and the second epitaxial layer 140 are schematically shown, and arrows E schematically show the electric lines of force pointing from the second doped regions 134 to the second epitaxial layer 140 according to the equipotential line distribution. The adjacent first epitaxial layers 130 also have similar potential and electric field distributions. Therefore, the electrical stress of the edge of the first epitaxial layer 130, the second epitaxial layer 140, and the termination region TM can be reduced because the second doped regions 134 are distributed in the multiple first epitaxial layers 130 and the second doped regions 134 are distributed throughout the termination region TM.
[0030] In a conventional termination region design, the termination region edge has a high electric stress, which can easily lead to a decrease in reliability. The termination region TM design described above can avoid the problem of a decrease in reliability due to a large electric stress at the termination region edge, and can further reduce the electric field. In this way, the present application can achieve the effect of reducing the electric field without having a large-area termination region design. By such a design, the area and overall volume of the termination region TM of the power semiconductor element 100 can be reduced.
[0031] In addition, the present application sets the first doped region 132 in the active region AC and the termination region TM, so that the resistance of the region where the first doped region 132 is located decreases. As shown in FIG. 1, the current I1 flowing through the first doped region 132 takes a longer path. The current I1 and the current I2 decrease the on-state drain to source resistance (RDSon) of the power semiconductor element 100 as a whole. In the present embodiment, the first doped region 132 is separated from the channel region by a distance, that is, the first doped region 132 does not extend below the well 150 and the source region 152, so as to avoid a decrease in breakdown voltage and early voltage breakdown. In other words, by setting the first doped region 132 in the active region AC and the termination region TM, and simultaneously setting the second doped region 134 in the termination region TM, the technical effects of reducing the electric field and the on-state resistance of the termination region TM, and maintaining or improving the breakdown voltage can be achieved. Figure 1B
[0032] The doping concentration of the first doped region 132 is in the range of about 5x10 17 cm -3 to 1x10 19 cm -3 . The doping concentration of the second doped region 134 is in the range of about 5x10 16 cm -3 to 2x10 18 cm -3 . In some embodiments, the doping concentrations of the first doped regions 132 located in different first epitaxial layers 130 can be the same as or different from each other. In some embodiments, the doping concentrations of the second doped regions 134 located in the same first epitaxial layer 130 can be the same or different. The doping concentrations of the second doped regions 134 located in different first epitaxial layers 130 can be the same as or different from each other. For example, the depths D of the first doped regions 132 and the second doped regions can be adjusted according to actual needs. When the depths D of the first doped regions 132 and the second doped regions 134 are shallower, the corresponding doping concentrations can be higher. When the depths D of the first doped regions 132 and the second doped regions are deeper, the corresponding doping concentrations can be lower.
[0033] The distance Ll between two adjacent second doped regions 134 in the same first epitaxial layer 130 can be arbitrarily adjusted. The distance L2 between the first doped regions 132 and the second doped regions 134 can also be arbitrarily adjusted.
[0034] The width Wl of the second doped regions 134 can be the same or different from each other. In other words, the size and doping concentration of the first doped regions 132 and the second doped regions 134 can be matched with each other, as long as the electric field at the edge of the first epitaxial layer 130, the second epitaxial layer 140 and the termination region TM can be reduced.
[0035] Figure 2 A cross-sectional view of a power semiconductor device 100a according to another embodiment of the present application. The power semiconductor device 100a is substantially the same as the power semiconductor device 100 shown in FIG. 1, except that the first doped regions 132a of the power semiconductor device 100a can include a first region 1322a and a second region 1324a, wherein the doping concentration of the first region 1322a is greater than the doping concentration of the second region 1324a. In other words, the second region 1324a closer to the channel region has a lower doping concentration. In other embodiments, the second region 1324a can also extend under the well 150 and the source region 152 (channel region), as long as the overall on-resistance can be reduced and the breakdown voltage can be maintained. The power semiconductor device 100a has the same technical effects as the power semiconductor device 100, and thus the repeated explanation is omitted herein.
[0036] Figure 3 A cross-sectional view of a power semiconductor device 100b according to yet another embodiment of the present application. The power semiconductor device 100b is substantially the same as the power semiconductor device 100 shown in FIG. 1, except that the first doped regions 132b of the power semiconductor device 100b have different widths, respectively. The first doped regions 132b closer to the substrate 120 have wider widths, i.e., the width of each first doped region 132b increases as the distance from the second epitaxial layer 140 increases. As shown in FIG. 4, the first doped region 132 at the bottom has a width W2, the first doped region 132 at the middle has a width W3, and the first doped region 132 at the top has a width W4. The width W2 is greater than the width W3, and the width W3 is greater than the width W4. In other embodiments, the first doped regions 132b can also have the design of the first region 1322a and the second region 1324a as shown in FIG. 3, i.e., the first doped regions 132b can also have different doping concentrations. The power semiconductor device 100b has the same technical effects as the power semiconductor device 100, and thus the repeated explanation is omitted herein. Figure 3 Figure 2
[0037] Figure 4 This is a cross-sectional view of a power semiconductor device 100c according to another embodiment of the present invention. The power semiconductor device 100c and... Figure 3 The power semiconductor device 100b shown is largely the same, except that the width of the first doped region 132c increases with distance from the substrate 120; that is, the width of each first doped region 132c decreases as the distance from the second epitaxial layer 140 increases. Figure 4 As shown, the width W4 of the lower first doped region 132c is smaller than the width W3 of the middle first doped region 132c, and the width W3 is smaller than the width W2 of the upper first doped region 132c. In other embodiments, the first doped region 132c may also have the aforementioned... Figure 2 The design of the first region 1322a and the second region 1324a shown, that is, the first doped region 132c, can also have different doping concentrations. The power semiconductor device 100b has the same technical effects as the power semiconductor device 100, and will not be described in detail here.
[0038] In other embodiments, the width of the first doped region 132b of the first epitaxial layer 130 located in the middle may be greater than or smaller than the other first doped regions 132b, as long as the overall on-resistance of the power semiconductor device 100c can be reduced.
[0039] Figure 5 This is a cross-sectional view of a power semiconductor device 100d according to another embodiment of the present invention. In this embodiment, the first epitaxial layer 130 may have different thicknesses. For example, the thickness T2 of the middle first epitaxial layer 130a is thicker than the thickness T1 of the other first epitaxial layer 130. In other embodiments, the thickness of each first epitaxial layer 130 may also be different from each other, as long as the technical effect of reducing the electric field in the terminal region TM is achieved.
[0040] In summary, by incorporating a second doped region into the termination region, this invention reduces the electric field at the edges of the first epitaxial layer, the second epitaxial layer, and the termination region, thereby improving reliability. Furthermore, by incorporating a first doped region into the active region and the termination region, this invention reduces the resistance of the region containing the first doped region, and consequently, the overall on-resistance of the power semiconductor device. This design also reduces the area of the termination region and the overall volume of the power semiconductor device.
[0041] [Symbol Explanation]
[0042] 100, 100a, 100b, 100c, 100d: Power semiconductor devices
[0043] 110: First electrode
[0044] 120: Base
[0045] 130, 130a: first epitaxial layer
[0046] 132, 132a, 132b, 132c: first doped region
[0047] 1322a: first region
[0048] 1324a: second region
[0049] 134: second doped region
[0050] 140: second epitaxial layer
[0051] 150, 153: well
[0052] 152: source region
[0053] 154: second electrode
[0054] 156: gate electrode
[0055] 158: gate oxide layer
[0056] 160: third doped region
[0057] AC: active region
[0058] TM: termination region
[0059] I1, I2: current
[0060] D: depth
[0061] L1, L2: spacing
[0062] T1, T2: thickness
[0063] W1, W2, W3, W4: width
[0064] E: arrow
[0065] 1B-1B: line segment
Claims
1. A power semiconductor device, characterized in that, Include: First electrode; A substrate is located on the first electrode, the substrate having an active region and a terminal region surrounding the active region; At least one first epitaxial layer is located on the substrate, wherein the first epitaxial layer has a first conductivity type, and the first epitaxial layer comprises: A first doped region, having the first conductivity type, is located in both the terminal region and the active region; and A plurality of second doped regions, having a second conductivity type and located in the terminal region; The second epitaxial layer is located on the first epitaxial layer; The gate electrode is located on the second epitaxial layer and in the active region; The second electrode is located on the second epitaxial layer and in the active region; as well as The source region, wherein the second electrode is electrically connected to the source region, and the first doped region does not extend below the source region.
2. The power semiconductor device according to claim 1, characterized in that, The doping concentration of the first doped region is 5 x 10⁻⁶. 17 cm -3 Up to 1x10 19 cm -3 Within the range.
3. The power semiconductor device according to claim 1, characterized in that, The doping concentration of these second doped regions is 5 x 10⁻⁶. 16 cm -3 Up to 2x10 18 cm -3 Within the range.
4. The power semiconductor device according to claim 1, characterized in that, The first doped region includes a first region and a second region, wherein the first region is located between the second region and the second doped regions, and the doping concentration of the first region is greater than the doping concentration of the second region.
5. The power semiconductor device according to claim 1, characterized in that, The number of the first epitaxial layers is complex, and the width of the first doped regions of the first epitaxial layers increases with the distance from the second epitaxial layer.
6. The power semiconductor device according to claim 1, characterized in that, The number of the first epitaxial layers is complex, and the width of the first doped regions of the first epitaxial layers decreases as the distance from the second epitaxial layer increases.
7. The power semiconductor device according to claim 1, characterized in that, The number of the first epitaxial layers is complex, and these first epitaxial layers have different thicknesses.
8. The power semiconductor device according to claim 1, characterized in that, The width of one of the second doped regions is different from the width of the other of the second doped regions.
9. The power semiconductor device according to claim 1, characterized in that, The depth of one of these second doped regions differs from the depth of the other of these second doped regions.
10. The power semiconductor device according to claim 1, characterized in that, The second doped regions are spaced apart from each other, and one of the spaces between the second doped regions is different from the other.
Citation Information
Patent Citations
Multi-epitaxial super-junction terminal structure and manufacturing method thereof
CN109509784A