Silicon carbide mosfet device and method of making same

Abstract

The application discloses a silicon carbide MOSFET device and a manufacturing method thereof. The silicon carbide MOSFET device comprises an epitaxial wafer, which comprises a semiconductor substrate, an epitaxial layer arranged on the surface of the substrate, a well region, a source region and a trench gate arranged in the epitaxial layer. The trench gate comprises a trench arranged in the surface of the epitaxial layer away from the substrate, a gate arranged in the trench, and the source region surrounds the trench and is in contact with the sidewall of the trench. The well region comprises a first layer well region, a second layer well region and a third layer well region arranged in the direction of the substrate pointing to the source region in sequence. The third layer well region surrounds the trench and is in contact with the sidewall of the trench. The epitaxial layer below the trench has a doped region, the first layer well region surrounds the doped region and is in contact with the doped region. There is a partial epitaxial layer between the first layer well region and the third layer well region, and the second layer well region is arranged on both sides of the partial epitaxial layer. The partial epitaxial layer has a mask layer for protecting the bottom of the trench gate, and the mask layer is arranged below the trench.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, and more particularly, to a silicon carbide (SiC) MOSFET device and a manufacturing method thereof. BACKGROUND

[0002] With the continuous development of science and technology, more and more electronic devices are widely used in people's daily life and work, which brings great convenience to people's daily life and work, and becomes an important tool indispensable to people today.

[0003] The main structure of electronic devices to realize various functions is integrated circuits, and MOSFET devices are important component electronic elements of integrated circuits. Silicon carbide MOSFET devices have become a major development direction in the field of semiconductors due to their excellent characteristics in high-power application fields.

[0004] The existing silicon carbide MOSFET devices still have deficiencies, and their structure and manufacturing method need to be further optimized to improve their performance. SUMMARY

[0005] Therefore, the technical scheme of the present application provides a silicon carbide MOSFET device and a manufacturing method thereof, as follows:

[0006] A silicon carbide MOSFET device, comprising:

[0007] An epitaxial wafer, comprising: a semiconductor substrate; an epitaxial layer arranged on a surface of the substrate;

[0008] A well region, a source region, and a trench gate arranged in the epitaxial layer;

[0009] The trench gate comprises a trench on a surface of the epitaxial layer away from the substrate; a gate arranged in the trench, and a gate dielectric layer between the gate and the trench;

[0010] The source region surrounds the trench and is in contact with the sidewall of the trench;

[0011] The well region comprises: a first layer well region, a second layer well region and a third layer well region arranged in sequence in the direction of the substrate pointing to the source region; the bottom of the trench is located between the first layer well region and the third layer well region; the third layer well region surrounds the trench and is in contact with the sidewall of the trench; the epitaxial layer below the trench has a doped region, the first layer well region surrounds and is in contact with the doped region; there is a partial epitaxial layer between the first layer well region and the third layer well region, and the second layer well region is located on both sides of the partial epitaxial layer; the partial epitaxial layer has a mask layer for protecting the bottom of the trench gate; the mask layer is located below the trench and has the same doping type as each layer of well region.

[0012] Preferably, in the above-mentioned silicon carbide MOSFET device, the vertical projection of the doped region on the substrate is located within the vertical projection of the trench on the substrate.

[0013] The vertical projection of the trench on the substrate is located within the vertical projection of the partial epitaxial layer on the substrate, and the two vertical projections have a non-zero spacing.

[0014] Preferably, in the above-mentioned silicon carbide MOSFET device, the partial epitaxial layer further has a connecting region connecting the mask layer and the first layer well region, and the connecting region has the same doping type as each layer of well region.

[0015] Preferably, in the above-mentioned silicon carbide MOSFET device, the first layer well region comprises: a first part of the first layer well region and a second part of the first layer well region located on both sides of the trench, respectively.

[0016] The first part of the first layer well region is connected to the mask layer through a plurality of connecting regions arranged in sequence in a first direction, and / or the second part of the first layer well region is connected to the mask layer through a plurality of connecting regions arranged in sequence in a first direction.

[0017] Wherein, the first direction is parallel to the substrate and parallel to the extension direction of the trench.

[0018] Preferably, in the above-mentioned silicon carbide MOSFET device, there is at least one doped region below the trench.

[0019] When there are a plurality of doped regions, the plurality of doped regions are arranged in sequence in a first direction, wherein the first direction is parallel to the substrate and parallel to the extension direction of the trench.

[0020] Preferably, in the above-mentioned silicon carbide MOSFET device, in the direction perpendicular to the substrate, the distance from the mask layer to the bottom of the trench is less than the distance to the first layer well region.

[0021] Preferably, in the silicon carbide MOSFET device, the mask layer is in contact with the bottom of the trench.

[0022] Preferably, in the silicon carbide MOSFET device, the second layer of the well region comprises a first part of the second layer of the well region and a second part of the second layer of the well region respectively located on two sides of the trench.

[0023] The first part of the second layer of the well region and the second part of the second layer of the well region are respectively integrated structures.

[0024] Preferably, in the silicon carbide MOSFET device, the second layer of the well region comprises a first part of the second layer of the well region and a second part of the second layer of the well region respectively located on two sides of the trench.

[0025] The first part of the second layer of the well region and the second part of the second layer of the well region each comprise a plurality of sub-regions arranged in a first direction; in the first direction, between two adjacent sub-regions, there is a current spreading region with a doping type opposite to that of the sub-regions; wherein the first direction is parallel to the substrate and parallel to the extension direction of the trench.

[0026] Preferably, in the silicon carbide MOSFET device, the doping types of each layer of the well region, the mask layer and the connection region are the same, and the doping concentration of the connection region is greater than the doping concentration of each layer of the well region.

[0027] Preferably, in the silicon carbide MOSFET device, for the same connection region, the connection region extends from the bottom of the trench to at least the first layer of the well region, or a part of the connection region extends from the bottom of the trench to at least the first layer of the well region, and another part extends from the surface of the epitaxial layer to at least the first layer of the well region along the sidewall of the trench.

[0028] The application also provides a manufacturing method of the silicon carbide MOSFET device.

[0029] Providing an epitaxial wafer, the epitaxial wafer comprising: a semiconductor substrate; an epitaxial layer arranged on the surface of the substrate;

[0030] Forming a well region, a source region and a trench gate in the epitaxial layer;

[0031] The trench gate comprises a trench on the surface of the epitaxial layer away from the substrate; a gate in the trench, and a gate dielectric layer between the gate and the trench.

[0032] The source region surrounds the trench and is in contact with the sidewall of the trench.

[0033] The trap region comprises: a first layer trap region, a second layer trap region and a third layer trap region arranged in sequence in the direction of the source region from the substrate; the bottom of the trench is located between the first layer trap region and the third layer trap region; the third layer trap region surrounds the trench and is in contact with the sidewall of the trench; the epitaxial layer below the trench has a doped region, the first layer trap region surrounds and is in contact with the doped region; the first layer trap region and the third layer trap region have a partial epitaxial layer, and the second layer trap region is located on both sides of the partial epitaxial layer; the partial epitaxial layer has a masking layer for protecting the bottom of the trench gate; the masking layer is located below the trench and has the same doping type as each layer of trap region.

[0034] Preferably, in the above manufacturing method, the epitaxial layer comprises: a first epitaxial layer arranged on the surface of the substrate; a second epitaxial layer arranged on the surface of the first epitaxial layer away from the substrate; a third epitaxial layer arranged on the surface of the second epitaxial layer away from the first epitaxial layer; the second epitaxial layer has a to-be-injected region and a first layer trap region surrounding the to-be-injected region;

[0035] Forming a trap region, a source region and a trench gate in the epitaxial layer, comprising:

[0036] Forming the source region, the second layer trap region and the third layer trap region in the surface of the third epitaxial layer away from the substrate;

[0037] Forming the trench in the surface of the third epitaxial layer away from the substrate;

[0038] Forming the masking layer and the doped region based on the trench;

[0039] Based on the trench, forming a connecting region connecting the masking layer and the first layer trap region;

[0040] Forming a gate dielectric layer and a gate in the trench.

[0041] The silicon carbide MOSFET device and the manufacturing method thereof provided by the technical scheme have the following advantages: the silicon carbide MOSFET device comprises an epitaxial wafer, the epitaxial wafer comprises a semiconductor substrate, an epitaxial layer arranged on a surface of the substrate, a well region, a source region and a trench gate arranged in the epitaxial layer, the trench gate comprises a trench arranged in a surface of the epitaxial layer away from the substrate, a gate arranged in the trench, and a gate dielectric layer between the gate and the trench, the source region surrounds the trench and is in contact with a side wall of the trench, the well region comprises a first layer well region, a second layer well region and a third layer well region arranged in the substrate in sequence in a direction from the substrate to the source region, a bottom of the trench is located between the first layer well region and the third layer well region, the third layer well region surrounds the trench and is in contact with the side wall of the trench, the epitaxial layer below the trench has a doped region, the first layer well region surrounds and is in contact with the doped region, there is a partial epitaxial layer between the first layer well region and the third layer well region, the second layer well region is located on both sides of the partial epitaxial layer, the partial epitaxial layer has a mask layer for protecting the bottom of the trench gate, and the mask layer is located below the trench and has the same doping type as each layer of the well region. BRIEF DESCRIPTION OF DRAWINGS

[0042] In order to more clearly illustrate the technical scheme in the embodiments of the present application or the related art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are only embodiments of the present application, and those skilled in the art can obtain other drawings according to the provided drawings without any creative effort.

[0043] The structures, proportions, sizes and the like shown in the drawings of the present specification are only used to cooperate with the content disclosed in the specification, to enable those skilled in the art to understand and read, and are not used to limit the conditions that can be implemented by the present application, so they do not have technical significance. Any modification of structure, change of proportion relationship or adjustment of size, which does not affect the effects and purposes that can be achieved by the present application, should still fall within the scope of the technical content disclosed by the present application.

[0044] Figure 1 It is a structural schematic diagram of a DMOSFET;

[0045] Figure 2 It is a structural schematic diagram of a UMOSFET;

[0046] Figure 3 It is a waveform diagram of voltage overshoot and oscillation phenomenon of MOSFET switch instant;

[0047] Figure 4aThis is a schematic diagram of the structure of a silicon carbide MOSFET device provided in an embodiment of this application;

[0048] Figure 4b for Figure 4a The diagram shows the main current path of the silicon carbide MOSFET device at the moment of turn-on.

[0049] Figure 4c for Figure 4b The diagram shows the equivalent parasitic parameters of the silicon carbide MOSFET device.

[0050] Figure 5 This is a schematic diagram of another silicon carbide MOSFET device provided in an embodiment of this application;

[0051] Figure 6 A three-dimensional view of a silicon carbide MOSFET device provided in an embodiment of this application;

[0052] Figure 7 for Figure 6 The diagram shows a top view of the spacer well region, trench, doped region, and connection region in a silicon carbide MOSFET device.

[0053] Figure 8 for Figure 6 The image shows a first cross-sectional view of the silicon carbide MOSFET device perpendicular to the trench extension direction;

[0054] Figure 9 for Figure 6 The image shows a second cross-sectional view of the silicon carbide MOSFET device perpendicular to the trench extension direction;

[0055] Figure 10 A three-dimensional view of another silicon carbide MOSFET device provided for an embodiment of this application;

[0056] Figure 11 for Figure 10 The diagram shows a top view of the spacer well region, trench, doped region, and connection region in a silicon carbide MOSFET device.

[0057] Figure 12 A schematic diagram of the structure of another silicon carbide MOSFET device provided in the embodiments of this application;

[0058] Figures 13-19 A process flow diagram of a method for fabricating a silicon carbide MOSFET device provided in this application embodiment;

[0059] Figure 20 This is a layout of a silicon carbide MOSFET device in terms of trench design and ion implantation area in the doped region, provided for an embodiment of this application. Detailed Implementation

[0060] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0061] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0062] Due to its excellent properties, SiC material is highly attractive for high-power applications, making it one of the ideal materials for high-performance power MOSFETs. SiC vertical power MOSFET devices mainly include lateral double-diffused DMOSFETs and UMOSFETs with vertical gate trench structures.

[0063] like Figure 1 As shown, Figure 1 This is a schematic diagram of a DMOSFET structure, including: an n+ (heavily n-type doped) substrate 2; an n- (lightly n-type doped) drift region 3 disposed on the surface of the substrate 2; a p-type well region 4 located within the drift region 3; and a source region 5 located within the p-type well region, the source region 5 including an n+ doped region 51 and a p+ (heavily p-type doped) doped region 52. A gate dielectric layer 7 is disposed on the surface of the drift region 3, and a gate 8 is disposed on the surface of the gate dielectric layer 7. A drain 1 is disposed on the side of the substrate 2 opposite to the drift region 3.

[0064] The DMOSFET structure employs planar diffusion technology, using a refractory material, such as a polysilicon gate, as a mask. The edges of the polysilicon gate define the p-base region and the n+ source region. The name DMOS originates from this double-diffusion process. The surface channel region is formed by utilizing the lateral diffusion difference between the p-type base region and the n+ source region.

[0065] like Figure 2 As shown, Figure 2 This is a schematic diagram of a UMOSFET structure, and Figure 1 The difference in the structure shown is that the UMOSFET has a U-shaped trench, the surface of which is covered by a gate dielectric layer 7, and the gate 8 is filled within the U-shaped trench. The vertical gate trench structure of the UMOSFET derives its name from the U-shaped trench structure. This U-shaped trench structure is formed in the gate region using reactive ion etching. The U-shaped trench structure has a high channel density (channel density is defined as the active region channel width), which significantly reduces the on-state characteristic resistance of the device.

[0066] After years of research in the industry, some manufacturers have already launched commercial products of planar SiC MOSFETs. For the conventional lateral DMOSFET structure, modern technological advancements have reached a point where shrinking the MOSFET cell size no longer reduces the on-resistance. This is mainly due to the limitation of the JFET neck resistance; even with smaller photolithography dimensions, it is difficult to reduce the on-resistance per unit area to 2 mΩ·cm. 2 A trench structure can effectively solve this problem. A U-shaped trench structure, such as... Figure 2 As shown, it employs trench etching technology in the manufacturing process of memory storage capacitors, changing the conductive channel from horizontal to vertical. Compared with the ordinary structure, it eliminates the neck resistance of JFET, greatly increases the cell density, and improves the current handling capability of power semiconductors.

[0067] However, several problems still exist in the actual fabrication and application of SiC UMOSFETs:

[0068] 1) The high electric field in the SiC drift region leads to a very high electric field on the gate dielectric layer. This problem is exacerbated at the trench corner, resulting in rapid breakdown of the gate dielectric layer under high drain voltage. It also has poor electrostatic effects in harsh environments and poor tolerance to high voltage spikes in the circuit.

[0069] 2) Since SiC power MOSFETs are mainly used in high-voltage, high-frequency, and high-current applications, parasitic parameters in the circuit can cause spikes and glitches during high-frequency switching, such as... Figure 3 As shown, Figure 3 The waveforms show the voltage overshoot and oscillation phenomena during MOSFET switching, based on... Figure 3 It is known that instantaneous overvoltage in the current path of a device increases the losses during the switching process; or large surge voltages are generated due to changes in power load, etc. Therefore, the surge voltage resistance and overvoltage protection of MOSFETs are also very important.

[0070] Because conventional MOSFET devices do not inherently possess surge voltage suppression or overvoltage protection capabilities, complex buffer circuits, surge voltage suppression circuits, and overvoltage protection circuits are often required in practical applications. However, these externally matched suppression and overvoltage protection circuits often have a time delay; the high-frequency spike voltage surges during actual switching processes are still absorbed by the device itself. This can sometimes lead to breakdown failure in the device's channel region, as well as gradual failure of the gate structure and electrode ohmic contact areas, causing device reliability issues.

[0071] 3) Ion implantation depth is limited, resulting in many targeted trench gate protection structure and surge protection design from the process is difficult to achieve. Generally used to form the trench depth of the gate is 1 μm-2 μm above, because to protect the trench gate structure, the actual manufacturing process of the buried type protection structure can not be directly completed by ion implantation, because in silicon carbide process, ion implantation depth is difficult to exceed 1 μm. Due to the characteristics of silicon carbide material, if you want to achieve a larger depth of implantation, high-energy ion implantation will cause its lattice damage, so in the process of epitaxial wafer, first form the required doping region in the previously formed epitaxial layer by etching and ion implantation, and then form the subsequent epitaxial layer. Therefore, the conventional process is to first form the required doping region in the previously formed epitaxial layer by etching and ion implantation, and then form two layers of P-type epitaxial layer with specific structure, resulting in complex manufacturing process and high manufacturing cost.

[0072] As shown in Figure 4a , Figure 4a A structure diagram of a silicon carbide MOSFET device provided by the embodiment of the application, comprising:

[0073] An epitaxial wafer, the epitaxial wafer comprising: a semiconductor substrate 10; an epitaxial layer arranged on the surface of the substrate 10;

[0074] A well region, a source region 15 and a trench gate arranged in the epitaxial layer;

[0075] Wherein, the trench gate comprises a trench 20 located on the surface of the epitaxial layer away from the substrate; a gate 18 located in the trench 20, the gate 18 and the trench 20 have a gate dielectric layer 181 therebetween;

[0076] The source region 15 surrounds the trench 20 and is in contact with the sidewall of the trench 20;

[0077] The well region comprises: a first layer well region 141, a second layer well region 142 and a third layer well region 143 arranged in sequence in the direction of the substrate 10 pointing to the source region 15; the bottom of the trench 20 is located between the first layer well region 141 and the third layer well region 143; the third layer well region 143 surrounds the trench 20 and is in contact with the sidewall of the trench 20; the epitaxial layer below the trench 20 has a doped region 17, the first layer well region 141 surrounds the doped region 17 and is in contact with the doped region 17; the first layer well region 141 and the third layer well region 143 have a partial epitaxial layer 100 therebetween, and the second layer well region 142 is located on both sides of the partial epitaxial layer 100.

[0078] The side of the substrate 10 facing away from the epitaxial layer has a metal drain 19. The source region 15 includes a first region 151 and a second region 152 of opposite doping types, which can be configured as an n+ type doped region and a p+ type doped region, respectively. A metal source 21 contacts both the first region 151 and the second region 152. The surface of the source region 15 has an insulating layer 16, which exposes the metal source 21 and a gate 18. The gate 18 includes a filled medium in the trench 20 and a metal gate on the surface of the filled medium.

[0079] Figure 4a In the illustrated silicon carbide MOSFET device, the well region structure includes three layers, namely a first layer well region 141, a second layer well region 142, and a third layer well region 143. The uppermost third layer well region 143 is located on both sides of the trench 20 and contacts the sidewall of the trench 20. The middle layer second layer well region 142 includes two parts on both sides of the trench 20 and does not contact the sidewall of the trench 20. The lowermost first layer well region 141 is located below the trench 20 and does not contact the trench 20.

[0080] The distance between the left and right parts of the second layer well region 142 and the vertical central axis of the cell structure is greater than the distance between the left and right parts of the first layer well region 141 and the vertical central axis of the cell structure. Specifically, the vertical central axis of the cell structure is the central axis of the trench 20, as shown by the dashed line, the first layer well region 141 is closer to the central axis than the second layer well region 142. The first layer well region 141 is closer to the sidewall of the trench than the second layer well region 142, which can protect the corner of the bottom of the trench 20, form a parasitic JFET, and suppress high-frequency oscillation and surges. The second layer well region 142 connects the first layer well region 141 to the source, which can suppress surges. Figure 4a The distance between the left and right parts of the second layer well region 142 and the vertical central axis of the cell structure is greater than the distance between the left and right parts of the first layer well region 141 and the vertical central axis of the cell structure. Specifically, the vertical central axis of the cell structure is the central axis of the trench 20, as shown by the dashed line, the first layer well region 141 is closer to the central axis than the second layer well region 142. The first layer well region 141 is closer to the sidewall of the trench than the second layer well region 142, which can protect the corner of the bottom of the trench 20, form a parasitic JFET, and suppress high-frequency oscillation and surges. The second layer well region 142 connects the first layer well region 141 to the source, which can suppress surges.

[0081] The doping region 17 can form a specific JFET structure on the current path between the source and the drain, and the conduction characteristics of the JFET structure can be optimized and adjusted by the pattern design, ion implantation concentration, and pattern profile of the doping region 17 to improve the performance of the MOSFET device.

[0082] The technical solution of the present application solves the problems of shielding of the SiC trench MOSFET gate oxide structure and deep implantation process in silicon carbide material by ingeniously designing the second epitaxial layer 12 and the doping region 17 penetrating through the second epitaxial layer 12 in the epitaxial wafer. At the same time, the doping region 17 can also introduce a JFET structure that can be modulated by ion implantation on the current path of the device, which can automatically adjust the on-resistance of the device and the self-locking protection effect while maintaining a small device cell size.

[0083] Figure 4aThe silicon carbide MOSFET device shown has at least the following beneficial effects:

[0084] The silicon carbide MOSFET device can introduce a JFET structure into the current path of the cell structure, which can automatically adjust the on-resistance and self-locking protection effect of the device while maintaining a small device cell size. Furthermore, the conduction characteristics of the JFET structure are optimized and adjusted by the pattern design of the doping region 17 and the ion implantation concentration and pattern profile. The design and process are flexible and have good manufacturability.

[0085] By utilizing an epitaxial wafer with a buried layer (second epitaxial layer 12) and a JFET structure modulated by implantation from the doped region 17, the depletion regions on both sides can automatically expand under large surge voltages, thereby increasing the on-resistance of the JFET structure. This is equivalent to a buffer circuit structure that suppresses surge spikes on its own. At the same time, when the surge voltage is too large, the depletion regions on both sides continue to expand and overlap each other, playing a blocking effect and protecting the gate dielectric layer on the surface of the internal trench, thus providing a certain level of overvoltage protection against spike voltages.

[0086] Although introducing the JFET structure increases the on-resistance to a certain extent, it provides switching buffering and surge voltage self-suppression.

[0087] The silicon carbide MOSFET device can increase the device's self-suppression resistance to surge voltage and overvoltage, and avoid device damage and reliability reduction caused by the time delay in actual operation of overvoltage protection circuit and overcurrent protection circuit.

[0088] It also buffers the spike jitter during circuit switching, reducing switching losses; it can reduce the number of buffer circuits and damper circuit structures in circuit design, reduce discrete components, thereby reducing costs, reducing the actual module size, and enhancing reliability.

[0089] like Figure 4b As shown, Figure 4b for Figure 4a The diagram shows the main current path of a silicon carbide MOSFET device at turn-on, with a current path between the source and drain. Figure 4b The dashed curve in the middle represents the circuit path, through which current flows through the JFET structure formed based on doped region 17. Due to the rapid change in current, high-frequency voltage spikes are generated in the circuit, while simultaneously, due to the rapid voltage change along the current path, the depletion region of the JFET structure ( Figure 4b The region between the two dashed curves (left and right) corresponds to different voltage changes and will expand or contract rapidly. In this case, the JFET structure is equivalent to a parallel structure of a variable resistor R and a junction capacitance C, as shown below. Figure 4c As shown, Figure 4c for Figure 4bEquivalent parasitic parameter diagram of the shown silicon carbide MOSFET device.

[0090] By specific circuit application and device electrical model simulation, selecting appropriate thickness d and doping concentration of the second epitaxial layer 12, and the pattern design, concentration and pattern profile design of the ion implantation structure of the doping region 17 to optimize and adjust, the appropriate parasitic parameter values (the required variable resistance R and a junction capacitance C) can be obtained, which plays an effective voltage spike suppression role when applied in different switching frequency circuit modules, while reducing the turn-on loss.

[0091] Figure 4a In the shown silicon carbide MOSFET device, the voltage resistance performance of the trench gate bottom needs to be further improved, based on which, as shown in Figure 5 Figure 5 Another structure diagram of a silicon carbide MOSFET device provided by the embodiment of the present application, comprising:

[0092] An epitaxial wafer, comprising: a semiconductor substrate 10; an epitaxial layer arranged on the surface of the substrate;

[0093] A well region, a source region 15 and a trench gate arranged in the epitaxial layer;

[0094] The trench gate comprises a trench 20 located in the surface of the epitaxial layer away from the substrate 10; a gate 18 located in the trench 20, and the gate 18 and the trench 20 have a gate dielectric layer 181 therebetween;

[0095] The source region 15 surrounds the trench 20 and is in contact with the sidewall of the trench 20;

[0096] The well region comprises: a first layer well region 141, a second layer well region 142 and a third layer well region 143 arranged in sequence in the direction of the substrate 10 pointing to the source region 15; the bottom of the trench 20 is located between the first layer well region 141 and the third layer well region 143; the third layer well region 143 surrounds the trench 20 and is in contact with the sidewall of the trench 20; the epitaxial layer below the trench 20 has a doping region 17, the first layer well region 141 surrounds the doping region 17 and is in contact with the doping region 17; the first layer well region 141 and the third layer well region 143 have a partial epitaxial layer 100 therebetween, and the second layer well region 142 is located on both sides of the partial epitaxial layer 100; the partial epitaxial layer 100 has a masking layer 31 for protecting the bottom of the trench gate; the masking layer 31 is located below the trench 20 and has the same doping type as each layer of well region. The doping type of each layer of well region is the same.

[0097] ​Optionally, the doping type and concentration of each layer of well region are the same, i.e. the doping type and concentration of the first layer of well region 141, the second layer of well region 142 and the third layer of well region 143 are the same, such as p-doping. The masking layer 31 can have the same doping concentration as each layer of well region, can be p-doped, or can be greater than the doping concentration of each layer of well region, such as the masking layer 31 can be p+ doped. Obviously, in other ways, the doping concentration of the first layer of well region 141, the second layer of well region 142 and the third layer of well region 143 can be different.

[0098] In Figure 5 In the illustrated manner, by providing the masking layer 31 below the trench 20, the bottom of the trench gate can be protected, and the withstand voltage performance of the bottom of the trench gate can be improved.

[0099] In the direction perpendicular to the substrate 10, the distance from the masking layer 31 to the bottom of the trench 20 is less than the distance to the first layer of well region 141, so that the bottom of the trench gate can be effectively protected. Optionally, the masking layer 31 is in contact with the bottom of the trench 20, i.e. the distance between the masking layer 31 and the bottom of the trench 20 is 0.

[0100] In Figure 5 In the illustrated manner, the vertical projection of the doping region 17 on the substrate 10 is located within the vertical projection of the trench 20 on the substrate 10. The vertical projection of the trench 20 on the substrate 10 is located within the vertical projection of the partial epitaxial layer 100 on the substrate 10, and the two vertical projections have a non-zero spacing, i.e. Figure 5 The side wall of the two parts of the second layer of well region 142 and the trench 20 has a non-zero spacing.

[0101] As Figure 5 As shown, the partial epitaxial layer 100 also has a connecting region 32 connecting the masking layer 31 and the first layer of well region 141, and the doping type of the connecting region 32 is the same as that of each layer of well region. The connecting region 32 connects the masking layer 31 and the first layer of well region 141, and the bottom of the trench gate is cleverly wrapped into a "capsule" shape, thereby achieving better protection of the trench bottom.

[0102] By setting the connecting region 32, the shielding layer 31 can be connected with the third layer well region 143 through the connecting region 32, and further connected with the source region 15, so that the source electrode 21 can be grounded. On the one hand, the shielding layer 31 can avoid losing the protection of the bottom of the trench gate due to the dynamic carrier trapping and accumulation effect in the long-term dynamic switching process, and on the other hand, the shielding layer 31 can avoid the problem of increasing the gate parasitic capacitance due to the potential suspension of the shielding layer 31, and avoid the problem of increasing the switching loss due to the parasitic capacitance.

[0103] The doping type of each layer well region, the shielding layer 31 and the connecting region 32 is the same, and the doping concentration of the connecting region 32 is greater than the doping concentration of each layer well region, so as to reduce the connection impedance between the shielding layer 31 and the first layer well region 141. For example, each layer well region can be p-doped, and the connecting region 32 can be p+-doped.

[0104] As shown in Figures 6-9 , a three-dimensional view of a silicon carbide MOSFET device provided by an embodiment of the present application is shown, Figure 6 , a top view of a barrier well region, a trench, a doped region and a connecting region in the silicon carbide MOSFET device shown, Figure 7 , a first cross-sectional view of the silicon carbide MOSFET device shown in the direction perpendicular to the extension direction of the trench, Figure 6 , a second cross-sectional view of the silicon carbide MOSFET device shown in the direction perpendicular to the extension direction of the trench. Wherein, Figure 8 the cross section ofpasses through two opposite connecting regions 32 on both sides of the doped region 17, Figure 6 the cross section of passes through the interval region between the two adjacent connecting regions 32 in the first direction X. Figure 9 Figure 6 As shown in Figure 8 , the first layer well region 141 includes a first part of the first layer well region 141a and a second part of the first layer well region 141b located on both sides of the trench 20, respectively. The first part of the first layer well region 141a is connected with the shielding layer 31 through at least one connecting region 32, and / or the second part of the first layer well region 141b is connected with the shielding layer 31 through at least one connecting region 32. Figure 9 In order to improve the connection reliability and stability, and reduce the connection impedance, in combination with

[0105] and Figure 6 , the first layer well region 141 includes a first part of the first layer well region 141a and a second part of the first layer well region 141b located on both sides of the trench 20, respectively. The first part of the first layer well region 141a is connected with the shielding layer 31 through at least one connecting region 32, and / or the second part of the first layer well region 141b is connected with the shielding layer 31 through at least one connecting region 32.

[0106] In order to improve the connection reliability and stability, and reduce the connection impedance, in combination with Figure 6 and Figure 7As shown, the first part of the first layer well region 141a is connected to the mask layer 31 through a plurality of connection regions 32 arranged in the first direction X, and / or the second part of the first layer well region 141b is connected to the mask layer 31 through a plurality of connection regions 32 arranged in the first direction X; wherein the first direction X is parallel to the substrate 10 and parallel to the extension direction of the trench 20.

[0107] For one trench 20, at least one doped region 17 can be arranged below the trench 20. When there are a plurality of doped regions 17 below the trench 20, the plurality of doped regions 17 are arranged in the first direction X, and the number of doped regions 17 includes but is not limited to Figure 7 As shown, two can be set to any number as needed. In order to ensure the protection effect of the bottom of the trench gate, the mask layer 31 is arranged in an integral structure below the trench 20, and extends from one end of the trench 20 to the other end.

[0108] In combination with Figure 6 And Figure 7 As shown, the second layer well region 142 includes a first part of the second layer well region and a second part of the second layer well region located on both sides of the trench 20; the first part of the second layer well region and the second part of the second layer well region are respectively an integral structure.

[0109] As shown in Figure 10 And Figure 11 As shown, Figure 10 Another three-dimensional view of a silicon carbide MOSFET device provided by the embodiments of the present application, Figure 11 As Figure 10 As shown in the plan view of the barrier well region, the trench, the doped region and the connection region in the silicon carbide MOSFET device, the second layer well region 142 includes a first part of the second layer well region 142a and a second part of the second layer well region 142b located on both sides of the trench 20; the first part of the second layer well region 142a and the second part of the second layer well region 142b each include a plurality of sub-regions 33 arranged in the first direction X; in the first direction X, between two adjacent sub-regions 33, there is a current spreading region 34 with a doping type opposite to that of the sub-region 33. The part of the epitaxial layer 100 includes the current spreading region 34.

[0110] Taking the first layer well region 141 as P-type as an example, when the first layer well region 141 is inversely type N-channel, the current spreads to the boundary of the second layer well region 142, and the current spreading region 34 between two adjacent sub-regions 33 of the second layer well region 142 can spread the current, thereby reducing the resistance and reducing the loss.

[0111] In the above embodiment, for the same connection region 32, the connection region 32 is extended by the bottom of the trench 20 at least to the first layer well region 141. At this time, the trench 20 completely blocks the connection region 32 in the direction perpendicular to the substrate 10.

[0112] As shown in Figure 12 , the connection region 32 is extended by the bottom of the trench 20 at least to the first layer well region 141, and the other part is extended by the surface of the epitaxial layer along the sidewall of the trench 20 at least to the first layer well region 141. At this time, the trench 20 partially blocks the connection region 32. This way can make the mask layer 31 better connected with the source region 15, and reduce the connection impedance. Figure 12 Figure 12 In the embodiment of the present application, based on the trench 20, the connection region 32 is formed by ion implantation, the ion implantation region is located in the trench 20, and there is no overlap with the sidewall of the trench 20, then the connection region 32 will be completely located below the trench 20, if the ion implantation region is close to one side of the trench 20 and has a preset incident angle with the sidewall of the side, then the structure as shown in can be formed.

[0113] Figure 12 In the embodiment of the present application, the lower end of the connection region 32 is extended at least to the first layer well region 141, and can also pass through the first layer well region 141 downward.

[0114] It should be noted that in the drawings of the embodiment of the present application, only one cell structure of the MOSFET device is shown. In actual products, the MOSFET device can have multiple cell structures. The number and layout of the cells can be set according to the needs, and the embodiment of the present application does not make specific limitations.

[0115] In the silicon carbide MOSFET device, the thickness of the third epitaxial layer 13 is not more than 1 μm, so that the ion implantation depth of the second layer well region 142 and the third layer well region 143 is not more than 1 μm, the second layer well region 142 and the third layer well region 143 can be formed in the third epitaxial layer 13 of the silicon carbide material by ion implantation, and no lattice damage is caused.

[0116] In the silicon carbide MOSFET device, the thickness of the third epitaxial layer 13 is not more than 1 μm, so that the ion implantation depth of the second layer well region 142 and the third layer well region 143 is not more than 1 μm, the second layer well region 142 and the third layer well region 143 can be formed in the third epitaxial layer 13 of the silicon carbide material by ion implantation, and no lattice damage is caused.

[0117] ​In the embodiment, the distance between the bottom of the trench 20 and the first epitaxial layer 11 is less than 1 μm, so that the ion implantation depth of the doped region 17 is less than 1 μm when the doped region 17 is formed by ion implantation based on the trench, and the doped region 17 can be formed in the second epitaxial layer 12 of silicon carbide material by ion implantation without causing lattice damage. The doped region 17 and the bottom of the trench have a non-zero spacing.

[0118] In the embodiment, the width of the trench 20 in the direction in which the bottom of the trench 20 points to the opening satisfies a uniform condition, that is, the width of the trench is the same or approximately the same in the direction, that is, the trench 20 is a rectangular trench. Generally, the second epitaxial layer 12 is an epitaxial layer with uniform thickness, and the width of the trench is set to satisfy the uniform condition, so as to facilitate formation of a doped region 17 with uniform width in the direction.

[0119] In other manners, the width of the trench 20 in the direction in which the bottom of the trench points to the opening can also be gradually increased, that is, the trench is a V-shaped trench or an inverted trapezoidal trench. If the trench is a V-shaped trench, the doped region 17 has a V-shaped structure, and if the trench is an inverted trapezoidal trench, the doped region has an inverted trapezoidal structure when the ion implantation window is greater than the bottom of the trench, and the doped region has a rectangular structure if the ion implantation window is not greater than the bottom of the trench. Figure 11

[0120] In the embodiment, the width of the doped region 17 is not greater than the width of the trench, so as to facilitate formation of the doped region 17 by ion implantation based on the trench, and to reduce the depth of ion implantation.

[0121] The doping concentration of the doped region 17 is greater than the doping concentration of the first epitaxial layer 11 and the third epitaxial layer 13. For example, the doped region 17 is n+ doped, and the first epitaxial layer 11 and the third epitaxial layer 13 are n- doped.

[0122] The substrate 10 is an n+ substrate, the second epitaxial layer 12 is p- doped, and the doped region 17 is n- doped. In the embodiment, the doping concentration relationship is n+ > n > n- and p+ > p > p-. n-, n, and n+ are the same type of doping, which are the first type of doping. p-, p, and p+ are the same type of doping, which are the second type of doping. The first type of doping and the second type of doping are opposite types of doping.

[0123] The silicon carbide MOSFET device can be an NMOS or a PMOS, and the doping type of each region can be set based on requirements to form an NMOS or a PMOS.

[0124] ​Based on the above embodiments, another embodiment of the present application further provides a manufacturing method for manufacturing the silicon carbide MOSFET device described in the above embodiments, as shown in Figures 13-19 Figures 13-19 A process flow chart of a silicon carbide MOSFET device manufacturing method provided by an embodiment of the present application is shown in

[0125] Step S11: as shown in Figure 13 An epitaxial wafer is provided, which includes a semiconductor substrate 10 and an epitaxial layer arranged on the surface of the substrate.

[0126] The epitaxial wafer is a silicon carbide epitaxial wafer, and the substrate 10 and each epitaxial layer on the surface thereof are silicon carbide materials.

[0127] Step S12: as shown in any of Figures 5-12 A well region, a source region 15 and a trench gate are formed in the epitaxial layer.

[0128] The trench gate includes a trench 20 arranged on the surface of the epitaxial layer away from the substrate 10, and a gate arranged in the trench 20, with a gate dielectric layer 181 between the gate and the trench 20.

[0129] The source region 15 surrounds the trench 20 and is in contact with the sidewall of the trench 20.

[0130] The well region includes a first layer well region 141, a second layer well region 142 and a third layer well region 143 arranged in sequence in the direction of the substrate 10 pointing to the source region 15, the bottom of the trench 20 is between the first layer well region 141 and the third layer well region 143, the third layer well region 143 surrounds the trench 20 and is in contact with the sidewall of the trench 20, the epitaxial layer below the trench 20 has a doped region 17, the first layer well region 141 surrounds and is in contact with the doped region 17, there is a partial epitaxial layer 100 between the first layer well region 141 and the third layer well region 143, the second layer well region 142 is located on both sides of the partial epitaxial layer 100, the partial epitaxial layer 100 has a mask layer 31 for protecting the bottom of the trench gate, the mask layer 31 is located below the trench 20 and has the same doping type as each layer of well region.

[0131] As shown in Figure 13 ​As shown, the epitaxial layer includes; a first epitaxial layer 11 disposed on the surface of the substrate 10; a second epitaxial layer 12 disposed on the surface of the first epitaxial layer 11 away from the substrate 10; a third epitaxial layer 13 disposed on the surface of the second epitaxial layer 12 away from the first epitaxial layer 11; the second epitaxial layer 12 has a to-be-implanted region 140 and a first layer well region 141 surrounding the to-be-implanted region 140.

[0132] In the MOSFET device, the well region structure includes: a first layer well region 141, a second layer well region 142 and a third layer well region 143. The second epitaxial layer 12 has a to-be-implanted region and a first layer well region 141 surrounding the to-be-implanted region; the to-be-implanted region 140 is used to form the doped region 17.

[0133] In the manufacturing method, the manufacturing method of the epitaxial wafer includes: sequentially epitaxially forming the first epitaxial layer 11, the second epitaxial layer 12 and the third epitaxial layer 13 on the surface of the substrate 10; wherein the first epitaxial layer 11 and the third epitaxial layer 13 are of the same doping type, and are of opposite doping type with the second epitaxial layer 12.

[0134] The substrate 10 can be an n+ type doped silicon carbide substrate, the first epitaxial layer 11 and the third epitaxial layer 13 are both n- type doped silicon carbide epitaxial layers, and the second epitaxial layer 12 is a p type doped silicon carbide epitaxial layer. In this way, the p type doped second epitaxial layer 12 is a buried layer, and the epitaxial wafer with the buried layer is ingeniously used to perform ion implantation by using the trench 20 required by the gate 18 to form the doped region 17, thereby solving the shielding of the trench gate structure and the difficulty of the silicon carbide material implantation process. Moreover, the doped region 17 can form a modulatable JFET structure in the current path of the device, which can automatically adjust the device resistance and self-locking protection effect while having a smaller device cell size.

[0135] In the step S12, the well region, the source region 15 and the trench gate are formed in the epitaxial layer, including:

[0136] In the step S121, as shown, the source region, the second layer well region and the third layer well region are formed in the surface of the third epitaxial layer away from the substrate. Figures 14-16

[0137] In this step, the second layer well region 142, the third layer well region 143 and the source region 15 are sequentially formed in the third epitaxial layer 13 by ion implantation; the second layer well region 142 is located between the first layer well region 141 and the third layer well region 143, and the source region 15 is located on the side of the third layer well region 143 away from the second layer well region 142. ​

[0138] Specifically, such as Figure 14 As shown, ion implantation is performed based on the mask layer 01 to form a second well region 142 within the third epitaxial layer 13. The second well region 142 surrounds a non-implanted region, which includes the aforementioned portion of the epitaxial layer 100. The desired non-implanted region is formed based on the patterned mask layer 01. The vertical projections of the trench 20 and the doped region 17 are both within this non-implanted region and in a direction parallel to the epitaxial wafer (i.e., Figure 14 In the horizontal direction, it has a distance from the non-injection area. Furthermore, as... Figure 15 As shown, a third well region 143 is formed on the second well region 142 by ion implantation again. The third well region 143 covers the second well region 142 and the surrounding non-implanted region. Further, as... Figure 16 As shown, the source region 15 is formed on the third trap region 143 by ion implantation again.

[0139] Step S122: As Figure 17 As shown, the trench 20 is formed in the surface of the third epitaxial layer 13 on the side opposite to the substrate 10; the bottom of the trench 20 is located between the second epitaxial layer 12 and the third layer well region 143.

[0140] In this configuration, both the source region 15 and the third well region 143 are in contact with the sidewall of the trench 20. When the source region 15 is formed by ion implantation, the ion implantation region covers the area used to form the trench 20. Therefore, after the trench is formed subsequently, the remaining source region 15 can directly contact the sidewall of the trench 20. Similarly, when the third well region 143 is formed by ion implantation, the ion implantation region covers the area used to form the trench 20. Therefore, after the trench is formed subsequently, the remaining third well region 143 can directly contact the sidewall of the trench 20.

[0141] The second layer well region 142 is spaced from the sidewall of the trench 20. The size of the non-injection area surrounded by the second layer well region 142 is larger than the size of the trench 20. The vertical projection of the trench 20 is located within the non-injection area and is spaced from it. This ensures that the second layer well region 142 does not contact the sidewall of the trench 20, thus maintaining a distance between them.

[0142] Step S123: As Figure 18 As shown, the masking layer 31 and the doped region 17 are formed based on the trench.

[0143] The doping type of the doped region 17, the first epitaxial layer 11 and the third epitaxial layer 13 is the same.

[0144] Based on the trench 20, the masking layer 31 and the doped region 17 are formed by ion implantation, and the masking layer 31 and the doped region 17 meeting the quality requirement can be formed in a large depth of the epitaxial layer. The first layer well region 141 is an epitaxial layer, and the required first layer well region 141 can be formed in a large depth of the epitaxial layer without ion implantation. The doped region 17 penetrates the second epitaxial layer 12.

[0145] Step S124: as shown in the figure, based on the trench 20, a connecting region 32 connecting the masking layer 31 and the first layer well region 141 is formed. Figure 19

[0146] The connecting region 32 can be formed by ion implantation. Based on the trench, the connecting region 32 is formed by ion implantation, and the connecting region 32 meeting the quality requirement can be formed in a large depth of the epitaxial layer.

[0147] Step S125: a gate dielectric layer 181 and a gate 18 are formed in the trench 20 to form the silicon carbide MOSFET device as described in the above embodiment.

[0148] The gate 18 includes a filling dielectric filling the trench 20 and a metal gate on the surface of the filling dielectric. The trench 20 has the gate dielectric layer 181 on the surface, and the gate 18 is formed in the trench 20 after the gate dielectric layer 181 is formed. The filling dielectric 181 can be polysilicon or the like. The doped region 17 is formed before the gate dielectric layer 181 is formed in the trench 20.

[0149] In the embodiment, the manufacturing method further includes: forming a metal source 21 connected with the source region 15; and forming a metal drain 19 on the surface of the substrate 10 away from the first epitaxial layer 11. The source region 15 includes a first region 151 and a second region 152 having opposite doping types, and the metal source 21 is in contact with the first region 151 and the second region 152. The first region 151 can be n+ doped, and the second region 152 can be p+ doped.

[0150] As shown in the figure, Figure 20 Figure 20 A silicon carbide MOSFET device provided by the embodiment has a layout of a trench design and a doping region ion implantation area. The implantation window of the doping region 17 is located in the trench 20, and the channel characteristics of the JFET structure can be adjusted by the pattern design, ion implantation concentration and pattern profile design of the doping region 17. The implantation window area of the doping region 17 can be less than or equal to the area of the trench 20.

[0151] ​​The single cell structure is only used to describe the silicon carbide MOSFET device in the embodiments of the present application. Obviously, when the MOSFET device is manufactured, multiple cell structures can be simultaneously manufactured based on wafer-level processes, and then the wafer is divided to form the silicon carbide MOSFET device having multiple cell structures.

[0152] The various embodiments in the specification are described in a progressive or parallel or progressive and parallel combination manner, and each embodiment focuses on the difference from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0153] It should be noted that in the description of the present application, it should be understood that the terms "upper", "lower", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. When a component is considered to be "connected" to another component, it can be directly connected to the other component or there can be a component disposed therebetween.

[0154] It should also be noted that in this document, relational terms such as first and second and the like are used solely to distinguish one entity or action from another entity or action, without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprising", "including" or any other variant thereof are intended to cover non-exclusive inclusion, such that a process, method, article or apparatus that comprises a list of elements does not include only those elements recited, but can also include other elements not expressly listed or inherent to such process, method, article or apparatus. Without more limitations, an element defined by the phrase "comprising a..." does not exclude the existence of additional identical elements in the process, method, article or apparatus including the above-mentioned element. The above description of the disclosed embodiments enables a person skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A silicon carbide MOSFET device, characterized in that, include: An epitaxial wafer, comprising: a semiconductor substrate; and an epitaxial layer disposed on the surface of the substrate; The well region, source region, and trench gate are disposed within the epitaxial layer; The trench gate includes a trench located in the surface of the epitaxial layer opposite to the substrate; a gate located in the trench, and a gate dielectric layer between the gate and the trench; The source region surrounds the trench and contacts the sidewall of the trench; The well region includes: a first well region, a second well region, and a third well region sequentially disposed on the substrate in the direction pointing towards the source region; the bottom of the trench is located between the first well region and the third well region; the third well region surrounds the trench and contacts the sidewall of the trench; the epitaxial layer below the trench has a doped region, the first well region surrounds the doped region and contacts the doped region; a partial epitaxial layer is located between the first well region and the third well region, and the second well region is located on both sides of the partial epitaxial layer; the partial epitaxial layer has a masking layer for protecting the bottom of the trench gate; the masking layer is located below the trench and has the same doping type as each well region; The vertical projection of the doped region onto the substrate lies within the vertical projection of the trench onto the substrate; The vertical projection of the trench onto the substrate lies within the vertical projection of the portion of the epitaxial layer onto the substrate, and the two vertical projections have a non-zero spacing. The epitaxial layer also has a connection region connecting the masking layer and the first layer well region, and the connection region has the same doping type as each layer well region.

2. The silicon carbide MOSFET device according to claim 1, characterized in that, The first layer well region includes: a first portion of the first layer well region and a second portion of the first layer well region located on both sides of the trench, respectively; The first portion of the first layer trap region is connected to the masking layer through a plurality of connection regions arranged sequentially in a first direction, and / or the second portion of the first layer trap region is connected to the masking layer through a plurality of connection regions arranged sequentially in a first direction; Wherein, the first direction is parallel to the substrate and parallel to the extension direction of the trench.

3. The silicon carbide MOSFET device according to claim 1, characterized in that, The trench has at least one of the doped regions below it; When there are multiple doped regions, the multiple doped regions are arranged sequentially in a first direction, wherein the first direction is parallel to the substrate and parallel to the extension direction of the trench.

4. The silicon carbide MOSFET device according to claim 1, characterized in that, In a direction perpendicular to the substrate, the distance from the masking layer to the bottom of the trench is less than the distance to the first layer well region.

5. The silicon carbide MOSFET device according to claim 4, characterized in that, The masking layer is in contact with the bottom of the trench.

6. The silicon carbide MOSFET device according to claim 1, characterized in that, The second layer well region includes: a first part of the second layer well region and a second part of the second layer well region located on both sides of the trench, respectively; The first part of the second layer well region and the second part of the second layer well region are each an integral structure.

7. The silicon carbide MOSFET device according to claim 1, characterized in that, The second layer well region includes: a first part of the second layer well region and a second part of the second layer well region located on both sides of the trench, respectively; Both the first portion of the second layer well region and the second portion of the second layer well region include a plurality of sub-regions arranged sequentially in a first direction; in the first direction, there is a current extension region between two adjacent sub-regions that is opposite to the doping type of the sub-region; wherein, the first direction is parallel to the substrate and parallel to the extension direction of the trench.

8. The silicon carbide MOSFET device according to claim 1, characterized in that, The doping types of each well region, the masking layer, and the connection region are the same, and the doping concentration of the connection region is greater than that of each well region.

9. The silicon carbide MOSFET device according to claim 1, characterized in that, For the same connection region, the connection region extends at least from the bottom of the trench into the first layer well region, or a portion of the connection region extends at least from the bottom of the trench into the first layer well region, and another portion extends at least from the surface of the epitaxial layer along the sidewall of the trench into the first layer well region.

10. A method for fabricating a silicon carbide MOSFET device as described in any one of claims 1-9, characterized in that, include: An epitaxial wafer is provided, the epitaxial wafer comprising: a semiconductor substrate; and an epitaxial layer disposed on the surface of the substrate; A well region, a source region, and a trench gate are formed within the epitaxial layer; The trench gate includes a trench located in the surface of the epitaxial layer opposite to the substrate; a gate located in the trench, and a gate dielectric layer between the gate and the trench; The source region surrounds the trench and contacts the sidewall of the trench; The well region includes: a first well region, a second well region, and a third well region sequentially disposed on the substrate in the direction pointing towards the source region; the bottom of the trench is located between the first well region and the third well region; the third well region surrounds the trench and contacts the sidewall of the trench; the epitaxial layer below the trench has a doped region, the first well region surrounds the doped region and contacts the doped region; a partial epitaxial layer is located between the first well region and the third well region, and the second well region is located on both sides of the partial epitaxial layer; the partial epitaxial layer has a masking layer for protecting the bottom of the trench gate; the masking layer is located below the trench and has the same doping type as each well region.

11. The manufacturing method according to claim 10, characterized in that, The epitaxial layer includes: a first epitaxial layer disposed on the surface of the substrate; a second epitaxial layer disposed on a surface of the first epitaxial layer opposite to the substrate; and a third epitaxial layer disposed on a surface of the second epitaxial layer opposite to the first epitaxial layer; the second epitaxial layer has a region to be injected and a first well region surrounding the region to be injected. A well region, a source region, and a trench gate are formed within the epitaxial layer, including: The source region, the second layer well region, and the third layer well region are formed in the surface of the third epitaxial layer on the side opposite to the substrate; The trench is formed in the surface of the third epitaxial layer on the side opposite to the substrate; The masking layer and the doped region are formed based on the trench; Based on the trench, a connection region is formed connecting the shielding layer and the first layer trap region; A gate dielectric layer and a gate are formed within the trench.

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