A current compensation circuit of differential structure and rail-to-rail operational amplifier

Abstract

The application discloses a differential structure current compensation circuit and a rail-to-rail operational amplifier. The differential structure comprises a bias circuit, a differential circuit and a current circuit connected in sequence, a compensation bias circuit, a compensation differential circuit and a compensation current circuit connected in sequence. The compensation bias circuit and the bias circuit are in a common source and gate structure, the compensation differential circuit and the differential circuit are in a common gate structure, the input of the compensation current circuit is connected with the output of the compensation differential circuit and the output of the differential circuit, and the input of the compensation current circuit is connected with the current circuit, so as to flow out the current of the differential circuit and make the output current of the differential circuit not flow through the current circuit. The rail-to-rail operational amplifier comprises the differential structure current compensation circuit, the current of the differential input circuit is directly flowed into the current compensation circuit, and is not injected into the intermediate stage of the operational amplifier, so that the current of the differential input stage does not affect the current source of the intermediate stage of the operational amplifier, the influence of the amplifier input on the output is avoided, and the performance of the amplifier is improved.

Description

Technical Field

[0001] This invention relates to the field of operational amplifier circuit technology, and in particular to a differential current compensation circuit and a rail-to-rail operational amplifier. Background Technology

[0002] Currently, rail-to-rail input and rail-to-rail output operational amplifier designs typically employ a folded cascode input stage and intermediate stages, with a push-pull structure for the output stage. In the folded cascode intermediate stage, a fixed current source provides bias current, while a floating current source provides bias voltage to the push-pull output stage. The total current in the intermediate stage equals the sum of the current generated by the fixed current source and the current injected by the differential input stage. In this structure, the current injected by the differential input stage varies with the input common-mode voltage, causing the total current in the intermediate stage to also change accordingly. The voltage across the floating current source and the magnitude of the rail-to-rail output stage current also change with the input common-mode voltage. This variation in the total current in the intermediate stage causes the rail-to-rail intermediate stage to switch between the amplification and switching regions, thus affecting the overall performance of the operational amplifier.

[0003] Therefore, how to overcome the influence of the output of the differential input stage on the intermediate stage is an urgent problem to be solved. Summary of the Invention

[0004] The purpose of this invention is to provide a current compensation circuit for a differential structure and a rail-to-rail operational amplifier. By adding a current compensation circuit outside the differential structure, the current in the differential circuit flows through the current compensation circuit instead of flowing through the current circuit, ensuring that the current in the intermediate stage circuit of the operational amplifier remains stable and is not affected by the differential circuit being turned on, thereby improving the accuracy of the amplifier.

[0005] Firstly, the above-mentioned objective of this invention is achieved through the following technical solution:

[0006] A differential current compensation circuit includes a bias circuit, a differential circuit, and a current circuit connected in sequence. It also includes a compensation bias circuit, a compensation differential circuit, and a compensation current circuit connected in sequence. The compensation bias circuit and the bias circuit have a common source and common gate structure, and the compensation differential circuit and the differential circuit have a common gate structure. The input of the compensation current circuit is connected to the output of the compensation differential circuit, the output of the differential circuit, and the input of the current circuit. The compensation current circuit is used to control the current flowing through the differential circuit, preventing the current in the differential circuit from flowing through the current circuit. The inputs of the bias circuit and the compensation bias circuit are connected to the positive power supply, and the outputs of the current circuit and the compensation current circuit are connected to the power supply ground.

[0007] The present invention is further configured such that: the bias circuit, differential circuit, current circuit, compensation bias circuit, compensation differential circuit, and compensation current circuit each include a MOSFET; the MOSFETs in the bias circuit, differential circuit, compensation bias circuit, and compensation differential circuit are P-type transistors; and the MOSFETs in the current circuit and compensation current circuit are N-type transistors.

[0008] Secondly, the above-mentioned objective of this invention is achieved through the following technical solution:

[0009] A differential current compensation circuit includes a current circuit, a differential circuit, and a bias circuit connected in sequence. The circuit also includes a compensation current circuit, a compensation differential circuit, and a compensation bias circuit connected in sequence. The compensation bias circuit and the bias circuit have a common source and common gate structure, and the compensation differential circuit and the differential circuit have a common gate structure. The output of the compensation current circuit is connected to the input of the compensation differential circuit, the input of the differential circuit, and the output of the current circuit. The compensation current circuit is used to control the current flowing through the differential circuit, preventing the current in the differential circuit from flowing through the current circuit. The input of the current circuit and the input of the compensation current circuit are connected to the positive power supply. The output of the current circuit and the output of the compensation current circuit are connected to the input of the differential circuit. The output of the differential circuit is connected to the input of the bias circuit. The output of the compensation differential circuit is connected to the input of the compensation bias circuit. The output of the bias circuit and the output of the compensation bias circuit are connected to the power supply ground.

[0010] The present invention is further configured such that: the bias circuit, differential circuit, current circuit, compensation bias circuit, compensation differential circuit, and compensation current circuit each include a MOSFET; the MOSFETs in the bias circuit, differential circuit, compensation bias circuit, and compensation differential circuit are all N-type transistors; and the MOSFETs in the current circuit and compensation current circuit are all P-type transistors.

[0011] The present invention is further configured such that: the compensation bias circuit, the compensation differential circuit, the bias circuit, and the differential circuit each include a MOSFET; the width-to-length ratio of the compensation bias MOSFET in the compensation bias circuit is N times that of the bias MOSFET in the bias circuit; the width-to-length ratio of the compensation differential MOSFET in the compensation differential circuit is N times that of the differential MOSFET in the differential circuit, where N is any positive number; the width-to-length ratio of the current MOSFET in the current circuit is equal to that of the compensation current MOSFET in the compensation current circuit.

[0012] The present invention is further configured as follows: a compensation differential circuit, each differential circuit including a pair of MOS transistors, the first compensation differential MOS transistor in the compensation differential circuit being connected to the first differential MOS transistor in the differential circuit via a common gate, the second compensation differential MOS transistor in the compensation differential circuit being connected to the second differential MOS transistor in the differential circuit via a common gate, one end of the compensation differential circuit being connected to the first end of the compensation current circuit, the first end of the differential circuit being connected to the second end of the compensation current circuit and the first end of the current circuit, the second end of the differential circuit being connected to the third end of the compensation current circuit and the second end of the current circuit, the third end and the fourth end of the differential circuit being connected together and connected to a bias circuit, the first end of the first compensation differential MOS transistor and the first end of the second compensation differential MOS transistor being connected together and connected to a compensation bias circuit, the second end of the first compensation differential MOS transistor and the second end of the second compensation differential MOS transistor being connected together and connected to a compensation current circuit.

[0013] The present invention is further configured such that: the compensation current circuit includes a current mirror circuit, the current mirror circuit includes a current source terminal and two mirror current terminals, the current source terminal is the first terminal, and the two mirror current terminals are the second terminal and the third terminal, respectively.

[0014] Thirdly, the above-mentioned objective of this invention is achieved through the following technical solution:

[0015] A rail-to-rail operational amplifier with folded common-source cascode bias current compensation includes the current compensation circuit, complementary differential circuit, intermediate stage current bias circuit, and push-pull output circuit described in this application. The complementary differential circuit, intermediate stage current bias circuit, and push-pull output circuit are connected in sequence. The complementary differential circuit is complementary to the differential circuit in the current compensation circuit. The output of the intermediate stage current bias circuit is connected to the input of the current circuit in the current compensation circuit.

[0016] The present invention is further configured such that: when the MOS transistor included in the differential circuit is P-type, the MOS transistor included in the complementary differential circuit is N-type, the input of the compensation bias circuit is connected to the positive power supply, the output of the differential circuit is connected to the output of the intermediate stage current bias circuit, the input of the current circuit, and the input of the compensation current circuit, and the output of the current circuit is connected to the power supply ground.

[0017] When the MOSFETs included in the differential circuit are N-type, the MOSFETs included in the complementary differential circuit are P-type. The output of the compensation bias circuit is connected to the power supply ground. The output of the compensation current circuit is also connected to the input of the intermediate current bias circuit, the output of the current circuit, and the input of the differential circuit. The input of the current circuit is connected to the positive power supply.

[0018] Fourthly, the above-mentioned objective of this invention is achieved through the following technical solutions:

[0019] A current compensation method for a differential structure, the differential structure including a bias circuit, a differential circuit and a current circuit, wherein a compensation bias circuit, a compensation differential circuit and a compensation current circuit are provided. The compensation bias circuit is used to track the current magnitude of the bias circuit, and the voltages at the three terminals of the compensation bias circuit are the same as the voltages at the three terminals of the bias circuit. The compensation differential circuit is used to track the current magnitude of the differential circuit, and the current of the differential circuit flows through the compensation current circuit but not through the current circuit.

[0020] Compared with the prior art, the beneficial technical effects of this application are as follows:

[0021] 1. This application sets a current compensation circuit in the amplifier circuit so that the current of the differential input circuit flows directly into the circuit and is not injected into the intermediate stage of the operational amplifier. This ensures that the current of the differential input stage does not affect the current source of the intermediate stage of the operational amplifier, avoids the influence of the amplifier input on the output, and improves the amplifier performance.

[0022] 2. Furthermore, the current compensation circuit of this application is modeled on the differential input stage and scaled down, which reduces the layout size while ensuring current tracking. The differential input stage current is directly injected into the current compensation circuit without entering the intermediate stage current source, ensuring that the input does not affect the subsequent stage. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the current compensation circuit structure of a specific embodiment of this application;

[0024] Figure 2 This is a schematic diagram of the current compensation circuit structure of another specific embodiment of this application;

[0025] Figure 3 This is a schematic diagram of an operational amplifier structure according to a specific embodiment of this application;

[0026] Figure 4 This is a schematic diagram of the operational amplifier circuit structure according to a specific embodiment of this application;

[0027] Figure 5 This is a schematic diagram of the operational amplifier circuit structure of another specific embodiment of this application. Detailed Implementation

[0028] The present invention will be further described in detail below with reference to the accompanying drawings. Specific Implementation Example 1

[0030] This application discloses a differential current compensation circuit, comprising a bias circuit, a differential circuit, and a current circuit connected in sequence, and a compensation bias circuit, a compensation differential circuit, and a compensation current circuit connected in sequence. The compensation bias circuit and the bias circuit are in a common-source, common-gate structure, and the compensation differential circuit and the differential circuit are in a common-gate structure. The input of the compensation current circuit is connected to the output of the compensation differential circuit and the output of the differential circuit, and its input is connected to the current circuit to allow current from the differential circuit to flow out, so that the output current of the differential circuit does not flow through the current circuit.

[0031] This application provides a differential current compensation circuit, such as... Figure 1 As shown, the current compensation circuit is located on the differential side of the common-gate common-source circuit. The bias circuit and differential circuit are each composed of P-type MOSFETs, and the current circuit is composed of N-type MOSFETs. The bias circuit is connected to the positive power supply. The bias circuit, differential circuit, and current circuit are connected in sequence, and the output of the current circuit is connected to the power supply ground. The compensation bias circuit, compensation differential circuit, and compensation current circuit are connected in sequence. The compensation bias circuit is connected to the positive power supply. The first input of the compensation current circuit is connected to the output of the compensation differential circuit. Its second input is connected to the first output of the differential circuit and the first input of the current circuit. Its third input is connected to the second output of the differential circuit and the second input of the current circuit. The output of the compensation current circuit is connected to the power supply ground.

[0032] The bias circuit and the compensation bias circuit are both connected to the positive terminal of the first bias power supply, and the differential circuit and the compensation differential circuit are both connected to the two ends of the signal input. The output of the compensation differential circuit is connected to the compensation current circuit.

[0033] The differential circuit and the compensation differential circuit include a pair of transistors. The first compensation differential MOSFET in the compensation differential circuit is connected to the first differential MOSFET in the differential circuit via a common gate. The second compensation differential MOSFET in the compensation differential circuit is connected to the second differential MOSFET in the differential circuit via a common gate. The source of the first compensation differential MOSFET and the source of the second compensation differential MOSFET are connected to the output of the compensation bias circuit. The drain of the first compensation differential MOSFET and the drain of the second compensation differential MOSFET are connected to the first input of the compensation current circuit. The drain of the first differential MOSFET is connected to the second input of the compensation current circuit. The drain of the second differential MOSFET is connected to the third input of the compensation current circuit.

[0034] The source terminals of the first differential MOSFET are connected together and connected to the output of the bias circuit.

[0035] The bias circuit, the compensation bias circuit, the differential circuit, and the compensation differential circuit are all composed of P-type MOS transistors. The compensation current circuit includes a mirror circuit, which is composed of N-type MOS transistors.

[0036] The width-to-length ratio of the compensation bias MOSFET in the compensation bias circuit is N times that of the bias MOSFET in the bias circuit, and the width-to-length ratio of the compensation differential MOSFET in the compensation differential circuit is N times that of the differential MOSFET in the differential circuit, where N is any positive number.

[0037] The width-to-length ratio of the current MOSFET in the current circuit is equal to the width-to-length ratio of the compensation current MOSFET in the compensation current circuit.

[0038] The current compensation circuit includes a current mirror circuit, comprising a current side and two mirror current sides. The input of the current side serves as the first input terminal of the current compensation circuit, and the inputs of the two mirror current sides serve as the second and third input terminals of the current compensation circuit, respectively. The output terminals of the current side and the two mirror current sides are connected to the power supply ground.

[0039] The first input of the current mirror circuit is connected to the output of the compensation differential circuit, the second input is connected to the first output of the differential circuit and the first input of the current circuit, and the third input is connected to the second output of the differential circuit and the second input of the current circuit; all outputs of the current mirror circuit are connected to the power supply ground.

[0040] The width-to-length ratio of the current mirror MOSFET is equal to that of the current circuit MOSFET. Specific Implementation Example 2

[0042] This application provides a differential current compensation circuit, such as... Figure 2 As shown, the current compensation circuit is located on the complementary differential side of the common-gate common-source circuit. The bias circuit and differential circuit are each composed of N-type MOSFETs, and the current circuit is composed of P-type MOSFETs. The current circuit, differential circuit, and bias circuit are connected in sequence. The input of the current circuit is connected to the positive power supply, and the bias circuit is connected to the ground power supply. The compensation current circuit, compensation differential circuit, and compensation bias circuit are connected in sequence. The compensation bias circuit is connected to the ground power supply, the input of the compensation current circuit is connected to the positive power supply, and the output of the compensation bias circuit is connected to the ground power supply.

[0043] The bias circuit and the compensation bias circuit are both connected to the positive side of the fourth bias power supply, and the differential circuit and the compensation differential circuit are both connected to the two ends of the signal input. The input of the compensation differential circuit is connected to the output of the compensation current circuit.

[0044] The bias circuit and the compensation bias circuit each include an N-type MOSFET. The bias MOSFET in the bias circuit and the compensation bias MOSFET in the compensation bias circuit are connected via a common gate. The outputs of the bias MOSFET and the compensation bias MOSFET are connected to the power supply ground. The input of the bias MOSFET is connected to the output of the differential circuit, and the input of the compensation bias MOSFET is connected to the output of the compensation differential circuit.

[0045] The width-to-length ratio of the compensation bias MOSFET is N times that of the bias MOSFET, and the width-to-length ratio of the compensation differential MOSFET in the compensation differential circuit is N times that of the differential MOSFET in the differential circuit, where N is any positive number.

[0046] The width-to-length ratio of the current MOSFET in the current circuit is equal to the width-to-length ratio of the compensation current MOSFET in the compensation current circuit.

[0047] The bias circuit, the compensation bias circuit, the differential circuit, and the compensation differential circuit are all composed of N-type MOS transistors. The compensation current circuit includes a mirror circuit, which is composed of P-type MOS transistors.

[0048] The differential circuit and the compensation differential circuit include pairs of transistors. The first compensation differential MOSFET in the compensation differential circuit is connected to the first differential MOSFET in the differential circuit via a common gate. The second compensation differential MOSFET in the compensation differential circuit is also connected to the second differential MOSFET in the differential circuit via a common gate. The sources of the first and second compensation differential MOSFETs are connected to the input of the compensation bias circuit. The drains of the first and second compensation differential MOSFETs are connected to the first output terminal of the compensation current circuit. The drain of the first differential MOSFET is connected to the second output terminal of the compensation current circuit, and the drain of the second differential MOSFET is connected to the third output terminal of the compensation current circuit. The sources of the first and second differential MOSFETs are connected together and connected to the input of the bias circuit.

[0049] The current compensation circuit includes a current mirror circuit, comprising a current side and two mirror current sides. The output of the current side serves as the first output terminal of the current compensation circuit, and the outputs of the two mirror current sides serve as the second and third output terminals of the current compensation circuit, respectively.

[0050] All inputs of the current mirror circuit are connected to the positive power supply. Its first output is connected to the input of the compensation differential circuit, its second output is connected to the first input of the differential circuit and the first output of the current circuit, and its third output is connected to the second input of the differential circuit and the second output of the current circuit. Specific Implementation Example 3

[0052] This application discloses a rail-to-rail operational amplifier with folded common-source cascode bias current compensation, comprising a differential structure current compensation circuit, a complementary differential circuit, a complementary bias circuit, an intermediate stage, and an output stage as described in Specific Embodiment 1. Figure 3 As shown, the complementary differential circuit is connected to the intermediate stage and the complementary bias circuit, and is connected to the differential circuit via a common gate.

[0053] The first differential MOSFET in the differential circuit, the first compensating differential MOSFET in the current compensation circuit, and the first complementary differential MOSFET in the complementary differential circuit are connected in a common gate configuration; the second differential MOSFET in the differential circuit, the second compensating differential MOSFET in the current compensation circuit, and the second complementary differential MOSFET in the complementary differential circuit are connected in a common gate configuration.

[0054] In differential circuits, the MOSFETs used for compensation and current compensation are both P-type, while the MOSFETs used for complementary differential circuits are N-type.

[0055] The intermediate stage output is connected to the current circuit. The output stage is connected to the intermediate stage.

[0056] In one specific embodiment of this application, a rail-to-rail operational amplifier structure with folded cascode bias current compensation is described, such as... Figure 4 As shown.

[0057] The differential current compensation circuit includes:

[0058] The bias circuit includes a P-type MOSFET M4. The differential circuit includes P-type MOSFETs M2A and M2B, and the current circuit includes N-type MOSFETs M5A and M5B. The bias circuit, differential circuit, and current circuit are connected in sequence.

[0059] The bias compensation circuit includes a P-type MOSFET M21. The differential compensation circuit includes P-type MOSFETs M22A and M22B, and the current compensation circuit includes N-type MOSFETs M23, M24A, and M24B. The bias compensation circuit, differential compensation circuit, and current compensation circuit are connected in sequence. The differential circuit and the differential compensation circuit are connected to the current compensation circuit and the current circuit.

[0060] P-type MOSFETs M21 and M4 form the first common-source common-gate circuit. The gates of MOSFETs M21 and M4 are connected to the first bias voltage source Vbias1. The sources of MOSFETs M4 and M21 are connected to the power supply VCC. The drain of MOSFET M4 is connected to the input of the differential circuit, and the drain of MOSFET M21 is connected to the input of the compensation differential circuit.

[0061] The input terminals of P-type MOSFETs M2A and M2B are connected together to form the input of the differential circuit. The gate of MOSFET M2A is connected to the signal input terminal Vinn, and the gate of MOSFET M2B is connected to the signal input terminal Vinp. The drain of P-type MOSFET M2A serves as the first output terminal of the differential circuit, and the drain of MOSFET M2B serves as the second output terminal of the differential circuit.

[0062] P-type MOSFETs M2A and M22A form the first common-gate circuit, and P-type MOSFETs M2B and M22B form the second common-gate circuit. The source terminals of MOSFETs M22A and M22B are connected together to form the input of the compensation differential circuit, and the drain terminals of MOSFETs M22A and M22B are connected together to serve as the output of the compensation differential circuit. The gate terminal of MOSFET M22A is connected to the signal input terminal Vinn, and the gate terminal of MOSFET M22B is connected to the signal input terminal Vinp. N-type MOSFETs M23, M24A, and M24B form a current mirror circuit. The gate terminals of MOSFETs M23, M24A, and M24B are connected together to serve as the first input terminal of the current mirror circuit, which is connected to the output terminal of the compensation differential circuit.

[0063] The drain of MOSFET M24A serves as the second input terminal of the current mirror circuit, connecting to the first output terminal of the differential circuit and the first input terminal of the current circuit; the drain of MOSFET M24B serves as the third input terminal of the current mirror circuit, connecting to the second output terminal of the differential circuit and the second input terminal of the current circuit.

[0064] N-type MOSFETs M5A and M5B form the third common-gate circuit. The gates of M5A and M5B are connected to the fourth bias voltage source Vbias4. The drain of M5A serves as the first input terminal of the current circuit and is connected to the first output terminal of the differential circuit. The drain of M5B serves as the second input terminal of the current circuit and is connected to the second output terminal of the differential circuit.

[0065] The sources of N-type MOSFETs M23, M24A, M24B, M5A, and M5B are connected to the power supply ground gnd.

[0066] The complementary bias circuit includes N-type MOSFET M3. The complementary differential circuit includes N-type MOSFETs M1A and M1B.

[0067] The source of MOSFET M3 is connected to the power supply ground, and the drain is connected to the output of the complementary differential circuit.

[0068] The gates of MOSFET M1A in the complementary differential circuit, the gates of MOSFETs M2A and M22A in the differential circuit are connected together to form the first common-gate circuit. The gates of MOSFET M1B, the gates of MOSFETs M2B and M22B in the differential circuit are connected together to form the second common-gate circuit. The sources of MOSFETs M1A and M1B are connected together as the output terminal of the complementary differential circuit; the drain of MOSFET M1A serves as the first input terminal of the complementary differential circuit, connected to the first output terminal of the intermediate stage circuit; the drain of MOSFET M1B serves as the second input terminal of the complementary differential circuit, connected to the second output terminal of the intermediate stage circuit.

[0069] The intermediate stage includes a common-source cascode current mirror circuit, comprising a first common-source cascode current mirror circuit and a second common-source cascode current mirror circuit. The first common-source cascode current mirror circuit includes N-type MOSFETs M6A and M6B, used to provide intermediate stage bias current. The gates of MOSFETs M6A and M6B are connected to a third bias power supply Vbias3. The source of M6A is connected to the first output of the differential circuit, and the source of M6B is connected to the second output of the differential circuit.

[0070] The second common-source common-gate current mirror circuit includes P-type MOSFETs M7A, M7B, M8A, and M8B. The sources of MOSFETs M7A and M7B are connected to the power supply VCC. The gates of MOSFETs M7A and M7B, the drains of MOSFETs M8A and M6A are connected together. The drains of MOSFETs M7A and M8A are connected together, serving as the first output of the intermediate stage and connected to the first input of the complementary differential circuit. The drains of MOSFETs M7B and M8B are connected together, serving as the second output of the intermediate stage and connected to the second input of the complementary differential circuit. The gates of MOSFETs M8A and M8B are connected to the second bias power supply Vbias2.

[0071] The drain of M8B, the source of P-type MOSFET M10, and the drain of N-type MOSFET M9 are connected together as the third output terminal of the intermediate stage, which is connected to the first input terminal of the output stage. The drain of P-type MOSFET M10, the source of N-type MOSFET M9, and the drain of M6B are connected together as the fourth output terminal of the intermediate stage, which is connected to the second input terminal of the output stage.

[0072] The gate of MOSFET M10 is connected to the output terminal of the first voltage Vpcas, and the gate of MOSFET M9 is connected to the output terminal of the second voltage Vncas.

[0073] The first voltage Vpcas is determined by the P-type MOSFETs M16 and M15 and the N-type MOSFETs M14 and M13 in the first series connection circuit. The source of MOSFET M16 is connected to the power supply VCC. The gate and drain of M16 and the source of M15 are connected together. The gate and drain of M15 and the drain of M14 are connected together to output the first voltage Vpcas. The source of M14 and the drain of M13 are connected together. The source of MOSFET M13 is connected to the power supply ground.

[0074] The gate of MOSFET M14 is connected to the third bias power supply Vbias3, and the gate of MOSFET M13 is connected to the fourth bias power supply Vbias4.

[0075] The P-type MOSFETs M20 and M19 and the N-type MOSFETs M18 and M17 in the second series connection circuit are used to provide the second voltage Vncas. The source of MOSFET M20 is connected to the power supply VCC, the gate of M20 is connected to the first bias power supply Vbias1, and its drain is connected to the source of M19. The gate of M19 is connected to the second bias power supply Vbias2, and its drain is connected to the drain and gate of M18 to output the second voltage Vncas. The source of M18, the drain of M17, and the gate of M17 are connected together, and the source of M17 is connected to the power supply ground.

[0076] The current I5 flowing through the first series-connected circuit is equal to the current I5 flowing through the second series-connected circuit.

[0077] The output stage includes a third series-connected P-type MOSFET M12 and an N-type MOSFET M11. The gate of MOSFET M12 is connected to the third output terminal of the intermediate stage, its source is connected to the power supply VCC, and its drain is connected to the drain of MOSFET M11, serving as the output terminal of the amplifier circuit. The gate of MOSFET M11 is connected to the fourth output terminal of the intermediate stage, and its source is connected to the power supply ground gnd.

[0078] The current compensation circuit is used to track the on-state of the differential circuit. To reduce quiescent current and chip area, the aspect ratio of PMOS transistor M21 is N times that of M4, the aspect ratio of M22A is N times that of M2A, the aspect ratio of M22B is N times that of M2B, and the aspect ratio of M22A is equal to that of M22B. Here, N is any positive number, and changing the value of N will affect the dimensions of transistors M21, M22A / M22B, and M23, as well as the current in that branch. The aspect ratios of M24A, M24B, M5A, and M5B are equal.

[0079] When the current flowing through M4 is I2, the current flowing through M21 is N*I2. Since the width-to-length ratio of M22A / M22B is N times that of M2A / M2B, and the sum of the currents in M22A / M22B is also N times the sum of the currents in M2A / M2B, therefore the V of M22A / M22B... GS Voltage and V of M2A / M2B GS With equal voltages, the leakage voltage V of transistor M4 is obtained. D and the leakage voltage V of transistor M21 DSince they are equal, the branch containing M22A / M22B can track the current in the branch containing M2A / M2B very well. The magnitude of the current in the M22A / M22B branch is compensated to the branch containing M2A / M2B through the current mirror formed by M23 and M24A / M24B. Ultimately, all the current in M2A / M2B flows out through M24A / M24B. The current flowing through M6A / M6B and M8A / M8B is not affected by the on state of M2A / M2B. That is, the magnitude of the input common-mode voltage does not affect the magnitude of the current I3 flowing through M5A / M5B. In other words, the bias current flowing through the folded common-source and common-gate M5A, M5B, M6A, M6B, M8A, M8B, and M9+M10 is constant at I3, and the bias current of the output stage M11 and M12 is constant at I4. This does not change with the input common-mode voltage, ensuring the stability of the intermediate stage output, thereby ensuring that the output of the operational amplifier circuit is not affected by the input common-mode voltage. Specific Implementation Example 4

[0081] This application discloses a rail-to-rail operational amplifier with folded common-source cascode bias current compensation, such as... Figure 5 As shown, the difference from Specific Embodiment 3 is that the differential structure current compensation circuit described in Specific Embodiment 2 is used.

[0082] The first differential MOSFET in the differential circuit, the first compensating differential MOSFET in the current compensation circuit, and the first complementary differential MOSFET in the complementary differential circuit are connected in a common gate configuration; the second differential MOSFET in the differential circuit, the second compensating differential MOSFET in the current compensation circuit, and the second complementary differential MOSFET in the complementary differential circuit are connected in a common gate configuration.

[0083] In differential circuits, the MOSFETs used for compensation and current compensation are both N-type, while the MOSFETs used for complementary differential circuits are P-type.

[0084] Specifically, in the differential current compensation circuit described in Embodiment 2, the complementary bias circuit includes an N-type MOSFET M3, and the complementary differential circuit includes N-type MOSFETs M1A and M1B. The current circuit includes P-type MOSFETs M7A and M7B.

[0085] The bias compensation circuit includes N-type MOSFET M21. The differential compensation circuit includes N-type MOSFETs M22A and M22B, and the current compensation circuit includes P-type MOSFETs M23, M24A, and M24B.

[0086] MOSFETs M23, M24A, and M24B form a current mirror circuit. The sources of MOSFETs M23, M24A, and M24B are connected to the power supply VCC. The gates of MOSFETs M23, M24A, and M24B, and the drain of MOSFET M23 are connected together as the first output terminal of the compensation current circuit, used to connect to the input of the compensation differential circuit. The drain of M24A serves as the second output terminal of the compensation current circuit, used to connect to the drain of M1A in the differential circuit and the drain of M7A in the current circuit. The drain of M24B serves as the third output terminal of the compensation current circuit, used to connect to the drain of M1B in the differential circuit and the drain of M7B in the current circuit.

[0087] The gate of MOSFET M22A is connected to the gate of MOSFET M1A in the differential circuit, forming a common gate circuit. The gate of MOSFET M22B is connected to the gate of MOSFET M1B in the differential circuit, forming a common gate circuit. The drains of MOSFETs M22A and M22B are connected to the first output terminal of the compensation current circuit. The drain of MOSFET M1A is connected to the second output terminal of the compensation current circuit. The drain of MOSFET M1B is connected to the third output terminal of the compensation current circuit.

[0088] The sources of MOSFETs M1A and M1B are connected together and connected to the drain of complementary bias MOSFET M3. The source of MOSFET M3 is connected to the power supply ground, and its gate is connected to the fourth bias power supply Vbias4.

[0089] The sources of MOSFETs M22A and M22B are connected together and connected to the drain of the compensation bias MOSFET M21. The source of MOSFET M21 is connected to the power supply ground, and its gate is connected to the fourth bias power supply Vbias4.

[0090] Correspondingly, the aspect ratio of NMOS transistor M21 is N times that of M3, the aspect ratio of M22A is N times that of M1A, the aspect ratio of M22B is N times that of M1B, and the aspect ratio of M22A is equal to that of M22B. Here, N is any positive number, and changing the value of N will affect the dimensions of transistors M21, M22A / M22B, and M23, as well as the current in that branch. The aspect ratio of M24A is equal to that of M7A, and the aspect ratio of M24B is equal to that of M7B.

[0091] When the current flowing through M3 is I1, the current flowing through M21 is N*I1. Since the width-to-length ratio of M22A / M22B is N times that of M1A / M2B, and the sum of the currents in M22A / M22B is also N times the sum of the currents in M1A / M1B, therefore the V of M22A / M22B... GS Voltage and V of M1A / M1B GS With equal voltages, the leakage voltage V of transistor M3 is obtained. Dand the leakage voltage V of transistor M21 D Since they are equal, the branch containing M22A / M22B can track the current in the branch containing M1A / M1B very well. The magnitude of the current in the M22A / M22B branch is compensated to the branch containing M1A / M1B through the current mirror formed by M23 and M24A / M24B. Ultimately, all the current in M1A / M1B flows into M24A / M24B. The current flowing through M6A / M6B and M8A / M8B is not affected by the on state of M1A / M1B. That is, the magnitude of the input common-mode voltage does not affect the magnitude of the current I3 flowing through M7A / M7B. In other words, the bias current flowing through the folded common-source and common-gate M5A, M5B, M6A, M6B, M8A, M8B, and M9+M10 is constant at I3, and the bias current of the output stage M11 and M12 is constant at I4. This does not change with the input common-mode voltage, ensuring the stability of the intermediate stage output, thereby ensuring that the output of the operational amplifier circuit is not affected by the input common-mode voltage.

[0092] The embodiments described herein are preferred embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Therefore, all equivalent changes made in accordance with the structure, shape, and principle of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A current compensation circuit of a differential structure including a bias circuit, a differential circuit, a current circuit connected in this order, characterized by, The current compensation circuit comprises a compensation bias circuit, a compensation differential circuit and a compensation current circuit connected in sequence, the compensation bias circuit and the bias circuit are in a common source and common gate structure, and the compensation differential circuit and the differential circuit are in a common gate structure; The input of the compensation current circuit is connected to the output of the compensation differential circuit, the output of the differential circuit and the input of the current circuit, the input of the bias circuit is connected to the input of the compensation bias circuit, and the output of the current circuit is connected to the output of the compensation current circuit; or, the output of the compensation current circuit is connected to the input of the compensation differential circuit, the input of the differential circuit and the output of the current circuit, the input of the current circuit is connected to the input of the compensation current circuit, the output of the current circuit is connected to the input of the differential circuit, the output of the differential circuit is connected to the input of the bias circuit, the output of the compensation differential circuit is connected to the input of the compensation bias circuit, and the output of the bias circuit is connected to the output of the compensation bias circuit. The compensation current circuit is used for flowing through the differential circuit, so that the current of the differential circuit does not flow through the current circuit. The compensation bias circuit, the compensation differential circuit, the bias circuit and the differential circuit comprise MOS tubes, the width-length ratio of a compensation bias MOS tube in the compensation bias circuit is N times of the width-length ratio of a bias MOS tube in the bias circuit, the width-length ratio of a compensation differential MOS tube in the compensation differential circuit is N times of the width-length ratio of a differential MOS tube in the differential circuit, N is an arbitrary positive number, the width-length ratio of a current MOS tube in the current circuit is equal to the width-length ratio of a compensation current MOS tube in the compensation current circuit. The compensation current circuit comprises a current mirror circuit, the current mirror circuit comprises a current source end and two mirror current ends, the current source end is a first end, the two mirror current ends are a second end of the compensation current circuit connected to a first end of the differential circuit and a third end of the compensation current circuit connected to a second end of the differential circuit.

2. The current compensation circuit of differential structure according to claim 1, characterized in that, The current circuit and the compensation current circuit comprise MOS tubes, when the input of the compensation current circuit is connected to the output of the compensation differential circuit, the MOS tubes in the bias circuit, the differential circuit, the compensation bias circuit and the compensation differential circuit are P-type tubes, and the MOS tubes in the current circuit and the compensation current circuit are N-type tubes.

3. The current compensation circuit of claim 1, wherein, The current circuit and the compensation current circuit comprise MOS tubes, when the output of the compensation current circuit is connected to the input of the compensation differential circuit, the MOS tubes in the bias circuit, the differential circuit, the compensation bias circuit and the compensation differential circuit are N-type tubes, and the MOS tubes in the current circuit and the compensation current circuit are P-type tubes.

4. The current compensation circuit of claim 1, wherein, The compensation differential circuit and the differential circuit each comprise MOS pairs, the first compensation differential MOS pair in the compensation differential circuit is connected in common gate with the first differential MOS pair in the differential circuit, the second compensation differential MOS pair in the compensation differential circuit is connected in common gate with the second differential MOS pair in the differential circuit, one end of the compensation differential circuit is connected to the first end of the compensation current circuit, the first end of the differential circuit is also connected to the first end of the current circuit, the second end of the differential circuit is also connected to the second end of the current circuit, the third end and the fourth end of the differential circuit are connected together and connected to the biasing circuit, the first end of the first compensation differential MOS pair and the first end of the second compensation differential MOS pair are connected together and connected to the compensation biasing circuit, the second end of the first compensation differential MOS pair and the second end of the second compensation differential MOS pair are connected together and connected to the compensation current circuit.

5. A rail-to-rail operational amplifier with folded cascode bias current compensation, comprising: The current compensation circuit comprising the differential structure of claim 1 and sequentially connected complementary differential circuit, intermediate stage current biasing circuit and push-pull output circuit, the complementary differential circuit is complementary to the differential circuit in the current compensation circuit, the output of the intermediate stage current biasing circuit is connected to the input of the current circuit in the current compensation circuit.

6. The folded cascode bias current compensated rail-to-rail operational amplifier of claim 5, wherein, When the MOS pairs included in the differential circuit are P-type, the MOS pairs included in the complementary differential circuit are N-type, the input of the compensation biasing circuit is connected to the positive power supply, the output of the differential circuit is connected to the output of the intermediate stage current biasing circuit, the input of the current circuit and the input of the compensation current circuit, and the output of the current circuit is connected to the ground of the power supply; When the MOS pairs included in the differential circuit are N-type, the MOS pairs included in the complementary differential circuit are P-type, the output of the compensation biasing circuit is connected to the ground of the power supply, and the output of the compensation current circuit is also connected to the input of the intermediate stage current biasing circuit, the output of the current circuit and the input of the differential circuit, and the input of the current circuit is connected to the positive power supply.

7. A current compensation method of a differential structure including a bias circuit, a differential circuit, and a current circuit, characterized by, The current compensation method comprises: setting a compensation biasing circuit, a compensation differential circuit and a compensation current circuit to manufacture the current compensation circuit of the differential structure of claim 1; tracking the current size of the biasing circuit with the compensation biasing circuit, and the voltages at the three ends of the compensation biasing circuit are the same as the voltages at the three ends of the biasing circuit; tracking the current size of the differential circuit with the compensation differential circuit, and the current of the differential circuit flows through the compensation current circuit without flowing through the current circuit.

Images