An operational amplifier circuit with improved slew rate

Abstract

This invention discloses an operational amplifier circuit for improving slew rate in the field of integrated circuit technology. It includes a basic op-amp unit, a positive-phase slew rate enhancement circuit, and a negative-phase slew rate enhancement circuit. The basic op-amp unit includes an input stage, a common-source common-gate stage, and a Class AB output stage. The output terminal of the input stage is connected to the first input terminal of the common-source common-gate stage, and the output terminal of the common-source common-gate stage is connected to the input terminal of the Class AB output stage. By introducing positive-phase and negative-phase slew rate enhancement circuits and their respective bias circuits, this invention can dynamically adjust the charging and discharging current of the frequency compensation capacitor according to the input voltage. This does not affect the normal operation of the circuit when the op-amp is operating stably. When a large signal step occurs at the input, the slew rate enhancement circuit is rapidly activated, increasing the current of the common-source common-gate stage, accelerating the charging and discharging process of the compensation capacitor, and improving the slew rate of the circuit.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, specifically to an operational amplifier circuit for improving slew rate. Background Technology

[0002] With the continuous development of integrated circuit technology, operational amplifiers face higher requirements in terms of efficiency, speed, and bandwidth. Slew rate, as a key indicator measuring the output's ability to follow rapid changes in input, has become a significant performance bottleneck in modern high-speed electronic systems.

[0003] Traditional slew rate enhancement techniques increase the quiescent current of the common-source gate capacitor to directly enhance the charging and discharging current of the frequency compensation capacitor, thereby improving the slew rate. This method sacrifices power consumption, gain, area, and voltage margin for improved large-signal transient response speed. Current mainstream techniques improve slew rate by dynamically enhancing the current, but these still suffer from limitations in bandwidth, power consumption, and stability.

[0004] Existing dynamic slew rate enhancement circuits increase the slew rate by adjusting the gate potential of the common-source cascode input transistor through feedback voltage to increase the current. However, the feedback resistor in these circuits limits the common-mode range, bandwidth, and offset voltage parameters of the op-amp, making them unsuitable for wide input range and high bandwidth applications. Summary of the Invention

[0005] The purpose of this invention is to provide an operational amplifier circuit that improves slew rate. By introducing positive and negative slew rate enhancement circuits and their respective bias circuits, the charging and discharging current of the frequency compensation capacitor can be dynamically adjusted according to the input voltage. When the op-amp is operating stably, the slew rate enhancement circuit is turned off to avoid affecting the normal operation of the circuit. When a large signal step occurs at the input, the slew rate enhancement circuit is quickly activated, increasing the common-source common-gate current, thereby accelerating the charging and discharging process of the compensation capacitor and effectively improving the slew rate. Compared with other structures, it has the advantages of simple structure and easy implementation. In the static state, it does not introduce additional poles and power consumption, and has minimal impact on the key parameters of the op-amp. It achieves a balance between dynamic enhancement of slew rate and overall system performance, which is beneficial for expanding the common-mode range, bandwidth, and offset voltage parameters of the op-amp. It is suitable for wide input range and high bandwidth scenarios.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] An operational amplifier circuit for improving slew rate includes a basic op-amp unit, a positive-inverting slew rate enhancement circuit, and a negative-inverting slew rate enhancement circuit.

[0008] The basic operational amplifier unit includes an input stage, a common-source common-gate stage, and a Class AB output stage. The input terminal of the input stage is used to receive the input signal of the pre-amplification circuit. The output terminal of the input stage is connected to the first input terminal of the common-source common-gate stage. The output terminal of the common-source common-gate stage is connected to the input terminal of the Class AB output stage. The output terminal of the Class AB output stage is used to output a signal.

[0009] The input terminal of the positive slew rate enhancement circuit is connected to the input terminal of the input stage, and the output terminal of the positive slew rate enhancement circuit is connected to the second input terminal of the common source and common gate circuit.

[0010] The input terminal of the negative slew rate enhancement circuit is connected to the input terminal of the input stage, and the output terminal of the negative slew rate enhancement circuit is connected to the third input terminal of the common source and common gate circuit.

[0011] When a signal step occurs at the input, the positive-phase slew rate enhancement circuit and the negative-phase slew rate enhancement circuit output excitation current to the common-source common-gate transistor, dynamically enhancing the charging and discharging current of the frequency compensation capacitor.

[0012] As a further aspect of the present invention: the output terminal of the common source common gate is a high impedance output node, and the common source common gate directly drives the Class AB input through the high impedance output node.

[0013] As a further aspect of the present invention: the high-impedance output node directly drives the input of the Class AB stage through the input terminal of the Class AB stage, fully preserving the gain of the preceding stage. When a fast response to a large signal is required, the common-source common-gate can provide enhanced transient current to quickly charge and discharge the gate capacitance of the Class AB stage, thereby improving the high slew rate of the operational amplifier.

[0014] As a further embodiment of the present invention: the input stage includes a first NMOS transistor M1 and a second NMOS transistor M2, the source of the first NMOS transistor M1 is connected to the output terminal of the first current source I0 and the source of the second NMOS transistor M2, the drain of the first NMOS transistor M1 is connected to the source of the first PMOS transistor M7 and the drain of the third PMOS transistor M9, and the drain of the second NMOS transistor M2 is connected to the source of the second PMOS transistor M8 and the drain of the fourth PMOS transistor;

[0015] The common-source common-gate transistor includes the third NMOS transistor M3, the fourth NMOS transistor M4, the fifth NMOS transistor M5, the sixth NMOS transistor M6, the first PMOS transistor M7, the second PMOS transistor M8, the third PMOS transistor M9, and the fourth PMOS transistor M10;

[0016] The Class AB output stage includes a first resistor R1, a first capacitor C1, a second resistor R2, a second capacitor C2, a seventh NMOS transistor M11, and a fifth PMOS transistor M12;

[0017] The input terminal of the first current source I0 is connected to the source of the third NMOS transistor M3, the source of the fourth NMOS transistor M4, and the source of the eleventh NMOS transistor M11. The gate of the third NMOS transistor M3 is connected to the gate of the fourth NMOS transistor M4. The drain of the third NMOS transistor M3 is connected to the source of the fifth NMOS transistor M5. The drain of the fourth NMOS transistor M4 is connected to the source of the sixth NMOS transistor.

[0018] The drain of the fifth NMOS transistor M5 is connected to the drain of the first PMOS transistor M7, the gate of the third PMOS transistor M9, and the gate of the fourth PMOS transistor M10. The gate of the fifth NMOS transistor M5 is connected to the gate of the sixth NMOS transistor. The drain of the sixth NMOS transistor M6 is connected to the source of the eighth NMOS transistor M13, the drain of the sixth PMOS transistor M14, the gate of the seventh NMOS transistor M11, and the first terminal of the first resistor R1. The second terminal of the first resistor R1 is connected to the first terminal of the first capacitor C1. The second terminal of the first capacitor C1 is connected to the drain of the seventh NMOS transistor M11.

[0019] The gate of the first PMOS transistor M7 is connected to the gate of the second PMOS transistor M8. The drain of the second PMOS transistor M8 is connected to the drain of the eighth NMOS transistor M13, the source of the sixth PMOS transistor M14, the gate of the fifth PMOS transistor M12, and the first terminal of the second resistor R2. The second terminal of the second resistor R2 is connected to the first terminal of the second capacitor C2. The second terminal of the second capacitor C2 is connected to the second terminal of the first capacitor C1 and the drain of the fifth PMOS transistor M12.

[0020] The sources of the third PMOS transistor M9, the fourth PMOS transistor M10, and the fifth PMOS transistor M12 are all grounded.

[0021] As a further aspect of the present invention: both the first capacitor C1 and the second capacitor C2 are frequency compensation capacitors.

[0022] As a further aspect of the present invention: when the input voltage of the operational amplifier undergoes a step change, the output voltage needs to go through a transition process of rising or falling before it can stabilize to the target value. The time required for this process is directly constrained by the slew rate.

[0023] As a further aspect of the present invention: the slew rate of the operational amplifier circuit is:

[0024] SR = I / (C1+C2), where SR is the slew rate of the op-amp, I is the charging and discharging current flowing through the sixth NMOS transistor M6 and the second PMOS transistor M8 in the basic op-amp unit, C1 is the first capacitor, and C2 is the second capacitor.

[0025] As a further aspect of the present invention: the slew rate of the operational amplifier is related to the magnitude of the drive current and the size of the frequency compensation capacitor in the operational amplifier circuit. Since the static current and frequency compensation capacitor of the common source cascode are limited by various factors in the design of the operational amplifier and cannot be adjusted arbitrarily, the prior art adds an additional slew rate enhancement circuit to dynamically increase I, thereby improving the slew rate.

[0026] As a further aspect of the present invention: the positive slew rate enhancement circuit includes a first high-frequency signal path and a second high-frequency signal path, wherein the first end of the first high-frequency signal path is connected to the second end of the second high-frequency signal path.

[0027] The first high-frequency signal path includes a fourth capacitor C4 and a sixth resistor R6. The first end of the fourth capacitor C4 is connected to the first end of the second high-frequency signal path and the output end of the pre-amplifier circuit. The second end of the fourth capacitor C4 is connected to the first end of the sixth resistor R6. The second end of the sixth resistor R6 is grounded.

[0028] The second high-frequency signal path includes a third capacitor C3 and a fifth resistor R5. The first end of the third capacitor C3 is connected to the first end of the fourth capacitor C4, the second end of the third capacitor C3 is connected to the first end of the fifth resistor R5, and the second end of the fifth resistor R5 is connected to the input negative phase signal VIN-.

[0029] As a further embodiment of the present invention: the positive slew rate enhancement circuit further includes a ninth PMOS transistor M17, a tenth PMOS transistor M18, an eleventh PMOS transistor M19, and a ninth NMOS transistor M20. The first end of the fifth resistor R5 is connected to the gate of the tenth PMOS transistor M18, the second end of the fifth resistor R5 is connected to the gate of the eleventh PMOS transistor M19, the drain of the tenth PMOS transistor M18 is connected to the drain of the fourth PMOS transistor M10, the source of the tenth PMOS transistor M18 is connected to the drain of the ninth PMOS transistor M17, the source of the eleventh PMOS transistor M19, and the input terminal of the second current source I1, the drain of the eleventh PMOS transistor M19 is connected to the drain and gate of the ninth NMOS transistor M20, the source of the ninth NMOS transistor M20 is connected to a high level, and the source of the ninth PMOS transistor M17 and the output terminal of the second current source I1 are grounded.

[0030] As a further aspect of the present invention: the size of the ninth PMOS transistor M17 is larger than the size of the tenth PMOS transistor M18 or the eleventh PMOS transistor M19, the ninth PMOS transistor M17 is used to provide slew rate enhancement current, and the current output by the second current source I1 is a small current bias.

[0031] The width-to-length ratio of the tenth PMOS transistor M18 and the eleventh PMOS transistor M19 is the same.

[0032] As a further embodiment of the present invention: the negative phase slew rate enhancement circuit includes a third high-frequency signal path and a fourth high-frequency signal path, wherein the second end of the third high-frequency signal path is connected to the first end of the fourth high-frequency signal path;

[0033] The third high-frequency signal path includes the fifth capacitor C5 and the seventh resistor R7. The first end of the fifth capacitor C5 is connected to the second end of the seventh resistor R7. The second end of the fifth capacitor C5 is connected to the output of the pre-amplifier circuit. The first end of the seventh resistor R7 is connected to a high level.

[0034] The fourth high-frequency signal path includes a sixth capacitor C6 and an eighth resistor R8. The first end of the sixth capacitor C6 is connected to the output of the pre-amplifier circuit, and the second end of the sixth capacitor C6 is connected to the first end of the eighth resistor R8. The second end of the eighth resistor R8 is connected to the input negative phase signal VIN-.

[0035] As a further embodiment of the present invention: the negative phase slew rate enhancement circuit further includes a tenth NMOS transistor M21, an eleventh NMOS transistor M22, a twelfth NMOS transistor M23, a twelfth PMOS transistor M24, and a third current source I2. The gate of the tenth NMOS transistor M21 is connected to the first terminal of the seventh resistor R7. The source of the tenth NMOS transistor M21 is connected to the second terminal of the seventh resistor R7 and the input terminal of the third current source I2. The drain of the tenth NMOS transistor M21 is connected to the source of the eleventh NMOS transistor M22, the source of the twelfth NMOS transistor M23, and the output terminal of the third current source I2. The gate of the eleventh NMOS transistor M22 is connected to the second terminal of the sixth capacitor C6. The drain of the eleventh NMOS transistor M22 is connected to the drain of the fourth NMOS transistor M4. The drain of the twelfth NMOS transistor M23 is connected to the drain and gate of the twelfth PMOS transistor M24. The gate of the twelfth NMOS transistor M23 is connected to the second terminal of the eighth resistor R8.

[0036] As a further aspect of the present invention: the size of the tenth NMOS transistor M21 is larger than the size of the eleventh NMOS transistor M22 or the twelfth NMOS transistor M23, wherein the tenth NMOS transistor M21 is the tenth NMOS transistor M21.

[0037] As a further aspect of the present invention: the output current of the third current source I2 is equal to the output current of the second current source I1.

[0038] As a further aspect of the present invention, the eleventh NMOS transistor M22 and the twelfth NMOS transistor M23 have the same width-to-length ratio.

[0039] As a further aspect of the present invention: the pre-amplifier circuit is a two-stage amplifier circuit used to amplify the input inverting signal VIN+. The pre-amplifier circuit includes a seventh PMOS transistor M15, an eighth PMOS transistor M16, a third resistor R3, and a fourth resistor R4. The gate of the seventh PMOS transistor M15 is connected to the input inverting signal. The drain of the seventh PMOS transistor M15 is connected to the second terminal of the third resistor R3 and the gate of the eighth PMOS transistor M16. The first terminal of the third resistor R3 is connected to a high level. The drain of the eighth PMOS transistor M16 is connected to the second terminal of the fourth resistor R4 and the first terminal of the third capacitor C3. The first terminal of the fourth resistor R4 is connected to a high level. The sources of the seventh PMOS transistor M15 and the eighth PMOS transistor M16 are grounded respectively.

[0040] Compared with the prior art, the beneficial effects of the present invention are:

[0041] 1. This invention introduces positive and negative slew rate enhancement circuits and their respective bias circuits, which can dynamically adjust the charging and discharging current of the frequency compensation capacitor according to the input voltage. When the operational amplifier is working stably, it does not affect the normal operation of the circuit. When a large signal step occurs at the input, the slew rate enhancement circuit is quickly activated, increasing the current of the common source and common gate circuit, thereby accelerating the charging and discharging process of the compensation capacitor and improving the slew rate of the circuit.

[0042] 2. This invention improves the slew rate by detecting changes in the op-amp input signal in real time and activating the corresponding slew rate enhancement circuit to dynamically adjust the common-source common-gate drive current. On the other hand, by detecting changes in the op-amp input signal in real time, it can provide a dynamic bias current for the slew rate enhancement circuit.

[0043] 3. This invention can adapt to different application scenarios by flexibly adjusting the voltage threshold of the signal required to activate the slew rate enhancement circuit. Attached Figure Description

[0044] Figure 1 This is a schematic diagram of an existing slewing rate enhancement structure;

[0045] Figure 2 This is an overall circuit block diagram of the present invention;

[0046] Figure 3 This is a circuit diagram of the basic operational amplifier unit of the present invention;

[0047] Figure 4 This is a schematic diagram of the positive and negative phase slew rate enhancement circuit of the present invention. Detailed Implementation

[0048] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0049] It should be noted that, as Figure 1 The diagram shows a schematic of an existing slew rate enhancement structure. Existing dynamic slew rate enhancement circuits increase the current by adjusting the gate potential of the common-source cascode input transistor through feedback voltage, thereby improving the slew rate. Therefore, the feedback resistor of the existing dynamic slew rate enhancement circuit limits the common-mode range, bandwidth, and offset voltage parameters of the op-amp, making it difficult to apply to wide input range and high bandwidth scenarios.

[0050] Example:

[0051] like Figure 2 As shown, this embodiment provides an operational amplifier circuit for improving slew rate, including an operational amplifier basic unit, a positive slew rate enhancement circuit, and a negative slew rate enhancement circuit.

[0052] The basic operational amplifier unit includes an input stage, a common-source common-gate stage, and a Class AB output stage. The input terminal of the input stage is used to receive the input signal of the pre-amplification circuit. The output terminal of the input stage is connected to the first input terminal of the common-source common-gate stage. The output terminal of the common-source common-gate stage is connected to the input terminal of the Class AB output stage. The output terminal of the Class AB output stage is used to output the signal.

[0053] like Figure 2 and Figure 3 As shown, the input stage includes a first NMOS transistor M1 and a second NMOS transistor M2. The source of the first NMOS transistor M1 is connected to the output terminal of the first current source I0 and the source of the second NMOS transistor M2. The drain of the first NMOS transistor M1 is connected to the source of the first PMOS transistor M7 and the drain of the third PMOS transistor M9. The drain of the second NMOS transistor M2 is connected to the source of the second PMOS transistor M8 and the drain of the fourth PMOS transistor. The common-source common-gate stage includes a third NMOS transistor M3, a fourth NMOS transistor M4, a fifth NMOS transistor M5, a sixth NMOS transistor M6, a first PMOS transistor M7, a second PMOS transistor M8, a third PMOS transistor M9, and a fourth PMOS transistor M10.

[0054] The Class AB output stage includes a first resistor R1, a first capacitor C1, a second resistor R2, a second capacitor C2, a seventh NMOS transistor M11, and a fifth PMOS transistor M12. The input terminal of the first current source I0 is connected to the source of the third NMOS transistor M3, the source of the fourth NMOS transistor M4, and the source of the eleventh NMOS transistor M11. The gate of the third NMOS transistor M3 is connected to the gate of the fourth NMOS transistor M4. The drain of the third NMOS transistor M3 is connected to the source of the fifth NMOS transistor M5. The drain of the fourth NMOS transistor M4 is connected to the source of the sixth NMOS transistor. The drain of the fifth NMOS transistor M5 is connected to the drain of the first PMOS transistor M7, the gate of the third PMOS transistor M9, and the gate of the fourth PMOS transistor M10. The gate of the fifth NMOS transistor M5 is connected to the gate of the sixth NMOS transistor. The drain of the sixth NMOS transistor M6 is connected to the source of the eighth NMOS transistor M13, the drain of the sixth PMOS transistor M14, and the seventh NMOS transistor M11. The gate and the first terminal of the first resistor R1 are connected. The second terminal of the first resistor R1 is connected to the first terminal of the first capacitor C1. The second terminal of the first capacitor C1 is connected to the drain of the seventh NMOS transistor M11. The gate of the first PMOS transistor M7 is connected to the gate of the second PMOS transistor M8. The drain of the second PMOS transistor M8 is connected to the drain of the eighth NMOS transistor M13, the source of the sixth PMOS transistor M14, the gate of the fifth PMOS transistor M12, and the first terminal of the second resistor R2. The second terminal of the second resistor R2 is connected to the first terminal of the second capacitor C2. The second terminal of the second capacitor C2 is connected to the second terminal of the first capacitor C1 and the drain of the fifth PMOS transistor M12. The sources of the third PMOS transistor M9, the fourth PMOS transistor M10, and the fifth PMOS transistor M12 are all grounded. When the input voltage of the operational amplifier undergoes a step change, the output voltage needs to go through a rising or falling transition process before stabilizing to the target value. The time required for this process is directly constrained by the slew rate.

[0055] like Figure 4As shown, the input terminal of the non-inverting slew rate enhancement circuit is connected to the input terminal of the input stage, and the output terminal of the non-inverting slew rate enhancement circuit is connected to the second input terminal of the common-source common-gate circuit. The non-inverting slew rate enhancement circuit includes a first high-frequency signal path and a second high-frequency signal path. The first terminal of the first high-frequency signal path is connected to the second terminal of the second high-frequency signal path. The first high-frequency signal path includes a fourth capacitor C4 and a sixth resistor R6. The first terminal of the fourth capacitor C4 is connected to the first terminal of the second high-frequency signal path and the output terminal of the pre-amplifier circuit. The second terminal of the fourth capacitor C4 is connected to the first terminal of the sixth resistor R6, and the second terminal of the sixth resistor R6 is grounded. The second high-frequency signal path includes a third capacitor C3 and a fifth resistor R5. The first terminal of the third capacitor C3 is connected to the first terminal of the fourth capacitor C4. The second terminal of the third capacitor C3 is connected to the first terminal of the fifth resistor R5, and the second terminal of the fifth resistor R5 is connected to... The negative input signal VIN- is used. The positive slew rate enhancement circuit also includes the ninth PMOS transistor M17, the tenth PMOS transistor M18, the eleventh PMOS transistor M19, and the ninth NMOS transistor M20. The first end of the fifth resistor R5 is connected to the gate of the tenth PMOS transistor M18, and the second end of the fifth resistor R5 is connected to the gate of the eleventh PMOS transistor M19. The drain of the tenth PMOS transistor M18 is connected to the drain of the fourth PMOS transistor M10. The source of the tenth PMOS transistor M18 is connected to the drain of the ninth PMOS transistor M17, the source of the eleventh PMOS transistor M19, and the input terminal of the second current source I1. The drain of the eleventh PMOS transistor M19 is connected to the drain and gate of the ninth NMOS transistor M20. The source of the ninth NMOS transistor M20 is connected to a high level. The source of the ninth PMOS transistor M17 and the output terminal of the second current source I1 are grounded.

[0056] The input terminal of the negative slew rate enhancement circuit is connected to the input terminal of the input stage, and the output terminal of the negative slew rate enhancement circuit is connected to the third input terminal of the common-source common-gate circuit. The negative slew rate enhancement circuit includes a third high-frequency signal path and a fourth high-frequency signal path. The second terminal of the third high-frequency signal path is connected to the first terminal of the fourth high-frequency signal path. The third high-frequency signal path includes a fifth capacitor C5 and a seventh resistor R7. The first terminal of the fifth capacitor C5 is connected to the second terminal of the seventh resistor R7, and the second terminal of the fifth capacitor C5 is connected to the output terminal of the pre-amplifier circuit. The first terminal of the seventh resistor R7 is connected to a high level. The fourth high-frequency signal path includes a sixth capacitor C6 and an eighth resistor R8. The first terminal of the sixth capacitor C6 is connected to the output terminal of the pre-amplifier circuit, and the second terminal of the sixth capacitor C6 is connected to the first terminal of the eighth resistor R8. The second terminal of the eighth resistor R8 is connected to the negative input signal VIN-. The negative slew rate enhancement circuit also... It includes the tenth NMOS transistor M21, the eleventh NMOS transistor M22, the twelfth NMOS transistor M23, the twelfth PMOS transistor M24, and the third current source I2. The gate of the tenth NMOS transistor M21 is connected to the first terminal of the seventh resistor R7. The source of the tenth NMOS transistor M21 is connected to the second terminal of the seventh resistor R7 and the input terminal of the third current source I2. The drain of the tenth NMOS transistor M21 is connected to the source of the eleventh NMOS transistor M22, the source of the twelfth NMOS transistor M23, and the output terminal of the third current source I2. The gate of the eleventh NMOS transistor M22 is connected to the second terminal of the sixth capacitor C6. The drain of the eleventh NMOS transistor M22 is connected to the drain of the fourth NMOS transistor M4. The drain of the twelfth NMOS transistor M23 is connected to the drain and gate of the twelfth PMOS transistor M24. The gate of the twelfth NMOS transistor M23 is connected to the second terminal of the eighth resistor R8.

[0057] When a signal step occurs at the input, the positive-phase slew rate enhancement circuit and the negative-phase slew rate enhancement circuit output excitation current to the common-source common-gate transistor, dynamically enhancing the charging and discharging current of the frequency compensation capacitor.

[0058] In this embodiment, the output terminal of the common-source common-gate is a high-impedance output node. The common-source common-gate directly drives the input of Class AB through the high-impedance output node, and the high-impedance output node directly drives the input of Class AB through the input terminal of Class AB, thus fully preserving the gain of the preceding stage. When a fast response to a large signal is required, the common-source common-gate can provide enhanced transient current to quickly charge and discharge the gate capacitor of Class AB, thereby improving the high slew rate of the op-amp.

[0059] In this embodiment, both the first capacitor C1 and the second capacitor C2 are frequency compensation capacitors.

[0060] In this embodiment, the slew rate of the operational amplifier circuit is:

[0061] SR = I / (C1+C2), where SR is the slew rate of the op-amp, I is the charging and discharging current flowing through the sixth NMOS transistor M6 and the second PMOS transistor M8 in the basic op-amp unit, C1 is the first capacitor, and C2 is the second capacitor. The slew rate of the op-amp is related to the magnitude of the drive current and the size of the frequency compensation capacitor in the op-amp circuit. Since the static current and frequency compensation capacitor of the common source and common gate op-amp are limited by various factors in the op-amp design process and cannot be adjusted arbitrarily, the existing technology adds an additional slew rate enhancement circuit to dynamically increase I, thereby increasing the slew rate.

[0062] In this embodiment, the size of the ninth PMOS transistor M17 is larger than that of the tenth PMOS transistor M18 or the eleventh PMOS transistor M19. The ninth PMOS transistor M17 is used to provide slew rate enhancement current, and the current output by the second current source I1 is a small current bias. The width-to-length ratio of the tenth PMOS transistor M18 and the eleventh PMOS transistor M19 is equal. The size of the tenth NMOS transistor M21 is larger than that of the eleventh NMOS transistor M22 or the twelfth NMOS transistor M23. The width-to-length ratio of the tenth NMOS transistor M21, the eleventh NMOS transistor M22, and the twelfth NMOS transistor M23 is equal.

[0063] In this embodiment, the output current of the third current source I2 is equal to the output current of the second current source I1.

[0064] like Figure 4 As shown, the pre-amplifier circuit is a two-stage amplifier circuit used to amplify the input non-inverting signal VIN+. The pre-amplifier circuit includes a seventh PMOS transistor M15, an eighth PMOS transistor M16, a third resistor R3, and a fourth resistor R4. The gate of the seventh PMOS transistor M15 is connected to the input non-inverting signal. The drain of the seventh PMOS transistor M15 is connected to the second terminal of the third resistor R3 and the gate of the eighth PMOS transistor M16. The first terminal of the third resistor R3 is connected to a high level. The drain of the eighth PMOS transistor M16 is connected to the second terminal of the fourth resistor R4 and the first terminal of the third capacitor C3. The first terminal of the fourth resistor R4 is connected to a high level. The sources of the seventh PMOS transistor M15 and the eighth PMOS transistor M16 are grounded respectively.

[0065] In this embodiment, when the operational amplifier circuit is in a stable operating state (Vin+ = Vin-), both the positive slew rate enhancement circuit and the negative slew rate enhancement circuit are in the off state. Since Vin+ remains unchanged, the small-signal voltage of node S3 is 0. Current sources I1 and I2 are small current biases that provide a quiescent operating point for the circuit. The gate of M17 is connected to ground through the sixth resistor R6, and M17 is cut off. The gate of M18 is connected to Vin- through the fifth resistor R5 and is connected to M19. The gate of M21 is connected to the power supply through the seventh resistor R7, and M21 is cut off. The gate of M22 is connected to Vin- through the eighth resistor R8 and is connected to M23.

[0066] When a large-signal change occurs in the circuit input, the output of the operational amplifier cannot follow the change of the input in time, and Vin+ starts to be unequal to Vin-. Assume that the small-signal gain of the preamplifier circuit is A and the change voltage of Vin+ is V, then the small-signal voltage of node S3 is A•V.

[0067] If the input signal is at the rising edge (Vin+ > Vin-): In the positive slew rate enhancement circuit, A•V is positive and is coupled to the gates of M18 and M17 through the third capacitor C3 and the fourth capacitor C4 respectively. When A•V > Vth,M17, M17 conducts; since the gate voltage of M18 rises faster than that of M19, M18 conducts more tail current. Therefore, the current flowing through node S0 in the positive slew rate enhancement circuit increases sharply, accelerating the discharge rate of the frequency compensation capacitors C1 and C2, and thus greatly improving the slew rate. In the negative slew rate enhancement circuit, the voltage A•V of node S3 is coupled to the gates of M21 and M22 through the fifth capacitor C5 and the sixth capacitor C6, and M21 still remains cut off; the tail current flowing through M22 decreases, which can also slightly enhance the slew rate.

[0068] Similarly, when the input signal is at the falling edge (Vin+ < Vin-): In the negative slew rate enhancement circuit, A•V is negative and is coupled to the gates of M21 and M22 through the fifth capacitor C5 and the sixth capacitor C6 respectively. When A•V<Vth,M21, M21 conducts; since the gate potential of M22 rises faster than that of M23, M22 conducts more tail current. Therefore, the current flowing into the basic unit of the operational amplifier through node S1 in the negative slew rate enhancement circuit increases sharply, accelerating the charging rate of the frequency compensation capacitors C1 and C2, and thus greatly improving the slew rate. In the positive slew rate enhancement circuit, the voltage A•V of node S3 is coupled to the gates of M18 and M17 through the third capacitor C3 and the fourth capacitor C4, and M17 remains cut off; the tail current flowing through M18 decreases, which can also slightly enhance the slew rate.

[0069] By appropriately setting the dimensions of M15 and M16 and the values ​​of R3 and R4, the voltage threshold of the input signal required to activate the slew rate enhancement circuit can be adjusted; by appropriately setting the dimensions of M17 and M18, the magnitude of the enhancement current can be adjusted. Therefore, after reasonable adjustments, this invention can be applied to a variety of different application scenarios.

[0070] The above are merely preferred embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. An operational amplifier circuit for improving slew rate, characterized in that, include: The operational amplifier basic unit includes an input stage, a common-source common-gate stage, and a Class AB output stage. The input terminal of the input stage is used to receive the input signal of the pre-amplification circuit. The output terminal of the input stage is connected to the first input terminal of the common-source common-gate stage. The output terminal of the common-source common-gate stage is connected to the input terminal of the Class AB output stage. The output terminal of the Class AB output stage is used to output a signal. A positive slew rate enhancement circuit is provided, wherein the input terminal of the positive slew rate enhancement circuit is connected to the input terminal of the input stage, and the output terminal of the positive slew rate enhancement circuit is connected to the second input terminal of the common-source common-gate circuit. The input stage includes a first NMOS transistor M1 and a second NMOS transistor M2. The source of the first NMOS transistor M1 is connected to the output terminal of the first current source I0 and the source of the second NMOS transistor M2. The drain of the first NMOS transistor M1 is connected to the source of the first PMOS transistor M7 and the drain of the third PMOS transistor M9. The drain of the second NMOS transistor M2 is connected to the source of the second PMOS transistor M8 and the drain of the fourth PMOS transistor. The common-source common-gate circuit includes a third NMOS transistor M3, a fourth NMOS transistor M4, a fifth NMOS transistor M5, a sixth NMOS transistor M6, a first PMOS transistor M7, a second PMOS transistor M8, a third PMOS transistor M9, and a fourth PMOS transistor M10. The AB output stage includes a first resistor R1, a first capacitor C1, a second resistor R2, a second capacitor C2, a seventh NMOS transistor M11, and a fifth PMOS transistor M12; the input terminal of the first current source I0 is connected to the source of the third NMOS transistor M3, the source of the fourth NMOS transistor M4, and the source of the eleventh NMOS transistor M11; the gate of the third NMOS transistor M3 is connected to the gate of the fourth NMOS transistor M4; the drain of the third NMOS transistor M3 is connected to the source of the fifth NMOS transistor M5; and the drain of the fourth NMOS transistor M4 is connected to the source of the sixth NMOS transistor. The drain of the fifth NMOS transistor M5 is connected to the drain of the first PMOS transistor M7, the gate of the third PMOS transistor M9, and the gate of the fourth PMOS transistor M10. The gate of the fifth NMOS transistor M5 is connected to the gate of the sixth NMOS transistor. The drain of the sixth NMOS transistor M6 is connected to the source of the eighth NMOS transistor M13, the drain of the sixth PMOS transistor M14, the gate of the seventh NMOS transistor M11, and the first terminal of the first resistor R1. The second terminal of the first resistor R1 is connected to the first terminal of the first capacitor C1, and the second terminal of the first capacitor C1 is connected to the drain of the seventh NMOS transistor M11. The gate of PMOS transistor M7 is connected to the gate of PMOS transistor M8. The drain of PMOS transistor M8 is connected to the drain of NMOS transistor M13, the source of NMOS transistor M14, the gate of NMOS transistor M12, and the first terminal of resistor R2. The second terminal of resistor R2 is connected to the first terminal of capacitor C2. The second terminal of capacitor C2 is connected to the second terminal of capacitor C1 and the drain of NMOS transistor M12. The sources of PMOS transistor M9, M10, and M12 are all grounded. A negative slew rate enhancement circuit, wherein the input terminal of the negative slew rate enhancement circuit is connected to the input terminal of the input stage, and the output terminal of the negative slew rate enhancement circuit is connected to the third input terminal of the common source common gate circuit; When a signal step occurs at the input, the positive-phase slew rate enhancement circuit and the negative-phase slew rate enhancement circuit output excitation current to the common-source common-gate transistor to dynamically enhance the charging and discharging current of the frequency compensation capacitor. The positive-phase slew rate enhancement circuit also includes a ninth PMOS transistor M17, a tenth PMOS transistor M18, an eleventh PMOS transistor M19, and a ninth NMOS transistor M20. The first end of the fifth resistor R5 is connected to the gate of the tenth PMOS transistor M18, and the second end of the fifth resistor R5 is connected to the gate of the eleventh PMOS transistor M19. The drain of the tenth PMOS transistor M18 is connected to the drain of the fourth PMOS transistor M10. The source of the tenth PMOS transistor M18 is connected to the drain of the ninth PMOS transistor M17, the source of the eleventh PMOS transistor M19, and the input terminal of the second current source I1. The drain of the eleventh PMOS transistor M19 is connected to the drain and gate of the ninth NMOS transistor M20. The source of the ninth NMOS transistor M20 is connected to a high level. The source of the ninth PMOS transistor M17 and the output terminal of the second current source I1 are grounded.

2. The operational amplifier circuit for improving slew rate according to claim 1, characterized in that, The output terminal of the common source common gate is a high impedance output node, and the common source common gate directly drives the Class AB input through the high impedance output node.

3. The operational amplifier circuit for improving slew rate according to claim 2, characterized in that, Both capacitor C1 and capacitor C2 are frequency compensation capacitors.

4. The operational amplifier circuit for improving slew rate according to claim 3, characterized in that, The slew rate of the operational amplifier circuit is: SR = I / (C1+C2), where SR is the slew rate of the op-amp, I is the charging and discharging current flowing through the sixth NMOS transistor M6 and the second PMOS transistor M8 in the basic op-amp unit, C1 is the first capacitor, and C2 is the second capacitor.

5. The operational amplifier circuit for improving slew rate according to claim 4, characterized in that, The positive slew rate enhancement circuit includes a first high-frequency signal path and a second high-frequency signal path, with the first end of the first high-frequency signal path connected to the second end of the second high-frequency signal path. The first high-frequency signal path includes a fourth capacitor C4 and a sixth resistor R6. The first end of the fourth capacitor C4 is connected to the first end of the second high-frequency signal path and the output end of the pre-amplifier circuit. The second end of the fourth capacitor C4 is connected to the first end of the sixth resistor R6. The second end of the sixth resistor R6 is grounded. The second high-frequency signal path includes a third capacitor C3 and a fifth resistor R5. The first end of the third capacitor C3 is connected to the first end of the fourth capacitor C4, the second end of the third capacitor C3 is connected to the first end of the fifth resistor R5, and the second end of the fifth resistor R5 is connected to the input negative phase signal VIN-.

6. The operational amplifier circuit for improving slew rate according to claim 5, characterized in that, The ninth PMOS transistor M17 is larger than the tenth PMOS transistor M18 or the eleventh PMOS transistor M19. The ninth PMOS transistor M17 is used to provide slew rate enhancement current, and the current output by the second current source I1 is a small current bias. The width-to-length ratio of the tenth PMOS transistor M18 and the eleventh PMOS transistor M19 is the same.

7. The operational amplifier circuit for improving slew rate according to claim 6, characterized in that, The negative phase slew rate enhancement circuit includes a third high-frequency signal path and a fourth high-frequency signal path, with the second end of the third high-frequency signal path connected to the first end of the fourth high-frequency signal path. The third high-frequency signal path includes the fifth capacitor C5 and the seventh resistor R7. The first end of the fifth capacitor C5 is connected to the second end of the seventh resistor R7. The second end of the fifth capacitor C5 is connected to the output of the pre-amplifier circuit. The first end of the seventh resistor R7 is connected to a high level. The fourth high-frequency signal path includes a sixth capacitor C6 and an eighth resistor R8. The first end of the sixth capacitor C6 is connected to the output of the pre-amplifier circuit, and the second end of the sixth capacitor C6 is connected to the first end of the eighth resistor R8. The second end of the eighth resistor R8 is connected to the input negative phase signal VIN-.

8. The operational amplifier circuit for improving slew rate according to claim 7, characterized in that, The negative phase slew rate enhancement circuit also includes a tenth NMOS transistor M21, an eleventh NMOS transistor M22, a twelfth NMOS transistor M23, a twelfth PMOS transistor M24, and a third current source I2. The gate of the tenth NMOS transistor M21 is connected to the first terminal of the seventh resistor R7. The source of the tenth NMOS transistor M21 is connected to the second terminal of the seventh resistor R7 and the input terminal of the third current source I2. The drain of the tenth NMOS transistor M21 is connected to the source of the eleventh NMOS transistor M22, the source of the twelfth NMOS transistor M23, and the output terminal of the third current source I2. The gate of the eleventh NMOS transistor M22 is connected to the second terminal of the sixth capacitor C6. The drain of the eleventh NMOS transistor M22 is connected to the drain of the fourth NMOS transistor M4. The drain of the twelfth NMOS transistor M23 is connected to the drain and gate of the twelfth PMOS transistor M24. The gate of the twelfth NMOS transistor M23 is connected to the second terminal of the eighth resistor R8.

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