A slew rate enhanced wideband low power consumption transconductance operational amplifier

Abstract

The application discloses a wideband low-power consumption transconductance operational amplifier with enhanced slew rate, which comprises an improved cyclic folded transconductance operational amplifier and a slew rate enhancement circuit. The slew rate enhancement circuit can significantly improve the positive and negative slew rates during large signal operation of the amplifier. During small signal operation of the amplifier, the transistors thereof work in a subthreshold region and hardly consume current, so that the unit gain bandwidth and the slew rate of the amplifier can be improved while keeping low power consumption, thereby improving the working speed and output current capacity of the operational amplifier. The embodiment of the application improves the working speed of a high-performance switched capacitor circuit, reduces power consumption, is easy to popularize and use, and can be widely applied to the technical field of operational amplifiers.

Description

Technical Field

[0001] This invention relates to the field of operational amplifier technology, and in particular to a broadband low-power transconductance operational amplifier with enhanced slew rate. Background Technology

[0002] Transconductance operational amplifiers (ICAs) are among the most important circuit units in analog circuits, widely used in analog and mixed-signal processing circuits, such as switched capacitors and analog-to-digital / digital-to-analog converters. The transconductance of an ICA typically determines the power consumption, accuracy, and speed achievable by a high-performance switched capacitor circuit. In switched capacitor circuits, the load is usually a pure capacitive load, where a single-stage ICA is superior to a multi-stage ICA; therefore, traditional folded transconductance amplifiers have gained widespread application.

[0003] Traditional folded transconductance amplifiers operate in Class A, exhibiting low current efficiency and drawbacks such as slow speed and high power consumption. Improving slew rate and bandwidth often comes at the cost of increased power consumption, making it difficult to meet current design requirements for high slew rate and wide bandwidth transconductance operational amplifiers. To improve the current efficiency of operational transconductance amplifiers, modifications to traditional folded cascode amplifiers are needed, leading to the development of cyclic folded transconductance operational amplifiers, which utilize current multiplexing technology to enhance current efficiency. However, existing cyclic folded transconductance operational amplifiers offer limited slew rate increases within a given power consumption limit, and the positive and negative slew rates are not equal, thus limiting the maximum achievable output current. Summary of the Invention

[0004] The purpose of this invention is to at least partially solve one of the technical problems existing in the prior art.

[0005] Therefore, one objective of this invention is to provide a broadband low-power transconductance operational amplifier with enhanced slew rate, which can improve the unity-gain bandwidth and slew rate of the amplifier while maintaining low power consumption, thereby improving the operating speed and output current capability of the operational amplifier.

[0006] To achieve the above-mentioned technical objectives, the technical solutions adopted in the embodiments of the present invention include:

[0007] This invention provides a broadband low-power transconductance operational amplifier with enhanced slew rate, comprising an improved cyclic folded transconductance operational amplifier and a slew rate enhancement circuit. The improved cyclic folded transconductance operational amplifier includes a third PMOS transistor, an eighth PMOS transistor, a first NMOS transistor, a fourth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a fifth PMOS transistor, a thirteenth PMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, and a fifteenth NMOS transistor. The slew rate enhancement circuit includes a first PMOS transistor, a second PMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a sixteenth NMOS transistor, a seventeenth NMOS transistor, and an eighteenth NMOS transistor, wherein:

[0008] The sources of the first, second, third, fourth, fifth, sixth, and seventh NMOS transistors are all connected to an analog positive power supply. The gates of the first and second PMOS transistors are both connected to the drain of the seventh NMOS transistor. The drain of the second PMOS transistor is connected to the negative terminal of the differential output, the drain of the seventeenth NMOS transistor, the drain of the eighth PMOS transistor, and the drain of the first NMOS transistor. The gate of the third PMOS transistor is connected to a common-mode feedback voltage, and the drain of the third PMOS transistor is connected to the source of the eighth PMOS transistor. The gate of the eighth PMOS transistor... The fourth PMOS transistor's drain is connected to the source of the ninth, tenth, eleventh, and twelfth PMOS transistors, and its gate is connected to the second PMOS transistor's gate. The fifth PMOS transistor's gate is connected to the common-mode feedback voltage, and its drain is connected to the source of the thirteenth PMOS transistor. The gates of the sixth and seventh PMOS transistors are both connected to the drain of the eighteenth NMOS transistor. The drain of the sixth PMOS transistor is connected to the differential output positive terminal, the drain of the eighth NMOS transistor, the drain of the thirteenth PMOS transistor, and the drain of the second NMOS transistor. The drain of the first NMOS transistor is connected to the drain of the ninth NMOS transistor, the drain of the tenth NMOS transistor, the drain of the ninth PMOS transistor, the gate of the seventh NMOS transistor, the gate of the eighth NMOS transistor, and the gate of the ninth NMOS transistor. The gate of the first NMOS transistor is connected to a first N-type bias voltage. The gates of the ninth and tenth PMOS transistors are both connected to the positive terminal of the differential input. The drain of the tenth PMOS transistor is connected to the drain of the fifth NMOS transistor, the drain of the sixth NMOS transistor, the gate of the fourteenth NMOS transistor, and the gate of the fifteenth NMOS transistor. The drain of the eleventh PMOS transistor is connected to the drain of the... The drain of the third NMOS transistor, the drain of the fourth NMOS transistor, the gate of the tenth NMOS transistor, and the gate of the eleventh NMOS transistor are connected together. The gates of the eleventh PMOS transistor and the twelfth PMOS transistor are both connected to the negative terminal of the differential input. The gate of the thirteenth PMOS transistor is connected to the first P-type bias voltage. The source of the second NMOS transistor is connected to the drain of the fifteenth NMOS transistor, the drain of the sixteenth NMOS transistor, the drain of the twelfth PMOS transistor, the gate of the sixteenth NMOS transistor, the gate of the seventeenth NMOS transistor, and the gate of the eighteenth NMOS transistor. The gate of the second NMOS transistor is connected to the first N-type bias voltage.The source of the third NMOS transistor is connected to the drain of the eleventh NMOS transistor; the source of the fourth NMOS transistor is connected to the drain of the twelfth NMOS transistor; the source of the fifth NMOS transistor is connected to the drain of the thirteenth NMOS transistor; and the source of the sixth NMOS transistor is connected to the drain of the fourteenth NMOS transistor. The gates of the third, fourth, fifth, and sixth NMOS transistors are all connected to the first N-type bias voltage. The gates of the twelfth and thirteenth NMOS transistors are both connected to the second N-type bias voltage. The sources of the seventh, eighth, ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, fifteenth, sixteenth, seventeenth, and eighteenth NMOS transistors are all connected to analog ground.

[0009] Furthermore, in one embodiment of the present invention, the substrates of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor, the eighth NMOS transistor, the ninth NMOS transistor, the tenth NMOS transistor, the eleventh NMOS transistor, the twelfth NMOS transistor, the thirteenth NMOS transistor, the fourteenth NMOS transistor, the fifteenth NMOS transistor, the sixteenth NMOS transistor, the seventeenth NMOS transistor, and the eighteenth NMOS transistor are all connected to the analog ground, and the substrates of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, the sixth PMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, the ninth PMOS transistor, the tenth PMOS transistor, the eleventh PMOS transistor, the twelfth PMOS transistor, and the thirteenth PMOS transistor are all connected to the analog positive power supply.

[0010] Furthermore, in one embodiment of the present invention, the potential of the simulated ground is 0V, and the potential of the simulated positive power supply is 3.3V.

[0011] Furthermore, in one embodiment of the present invention, the ninth PMOS transistor, the tenth PMOS transistor, the eleventh PMOS transistor, and the twelfth PMOS transistor have the same transistor size, and the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor have the same transistor size.

[0012] Furthermore, in one embodiment of the present invention, the transistor size ratio of the ninth NMOS transistor, the eighth NMOS transistor, and the seventh NMOS transistor is 1:m:n, the transistor size ratio of the sixteenth NMOS transistor, the seventeenth NMOS transistor, and the eighteenth NMOS transistor is 1:m:n, n = m + 2.5, and the transistor size of the ninth NMOS transistor and the sixteenth NMOS transistor is the same.

[0013] Furthermore, in one embodiment of the present invention, the first PMOS transistor, the second PMOS transistor, the sixth PMOS transistor, and the seventh PMOS transistor have the same transistor size.

[0014] Furthermore, in one embodiment of the present invention, the transistor size ratio of the tenth NMOS transistor, the eleventh NMOS transistor, and the twelfth NMOS transistor is 6:1:1, the transistor size ratio of the fifteenth NMOS transistor, the fourteenth NMOS transistor, and the thirteenth NMOS transistor is 6:1:1, and the transistor size of the twelfth NMOS transistor and the fifteenth NMOS transistor are the same.

[0015] Furthermore, in one embodiment of the present invention, the common-mode feedback voltage is generated by a switched-capacitor common-mode feedback circuit.

[0016] The advantages and beneficial effects of the present invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention:

[0017] This invention provides a broadband low-power transconductance operational amplifier with enhanced slew rate, comprising an improved cyclic folded transconductance operational amplifier and a slew rate enhancement circuit. The slew rate enhancement circuit significantly improves the positive and negative slew rates during the amplifier's large-signal operation, while its transistors operate in the subthreshold region during the amplifier's small-signal operation, consuming almost no current. Therefore, it can improve the amplifier's unity-gain bandwidth and slew rate while maintaining low power consumption, thereby improving the operational amplifier's operating speed and output current capability. This invention also improves the operating speed of the high-performance switched-capacitor circuit, reduces power consumption, and is easy to promote and use. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the embodiments of the present invention are described below. It should be understood that the drawings described below are only for the convenience of clearly describing some embodiments of the technical solutions of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of a broadband low-power transconductance operational amplifier with enhanced slew rate provided in an embodiment of the present invention.

[0020] Figure label:

[0021] P1 to P13 represent the first to thirteenth PMOS transistors, respectively; N1 to N18 represent the first to eighteenth NMOS transistors, respectively; AVDD represents the analog positive power supply; AVSS represents the analog ground; Vbp1 represents the P-type first bias voltage; Vbp2 represents the P-type second bias voltage; Vbn1 represents the N-type first bias voltage; Vbn2 represents the N-type second bias voltage; Vo+ represents the differential output positive terminal; Vo- represents the differential output negative terminal; Vin+ represents the differential input positive terminal; Vin- represents the differential input negative terminal; Vcmfb represents the common-mode feedback voltage. Detailed Implementation

[0022] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0023] In the description of this invention, "multiple" means two or more. The use of "first" and "second" is for distinguishing technical features only and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or the order of the indicated technical features. Furthermore, unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art.

[0024] Reference Figure 1 This invention provides a broadband low-power transconductance operational amplifier with enhanced slew rate, including an improved cyclic folded transconductance operational amplifier (such as...). Figure 1 (as shown in the area outside the dashed box) and slew rate enhancement circuit (such as...) Figure 1(As shown in the area within the dashed box), the improved cyclic folded transconductance operational amplifier includes the third PMOS transistor (P3), the eighth PMOS transistor (P8), the first NMOS transistor (N1), the fourth PMOS transistor (P4), the ninth PMOS transistor (P9), the tenth PMOS transistor (P10), the eleventh PMOS transistor (P11), the twelfth PMOS transistor (P12), the fifth PMOS transistor (P5), the thirteenth PMOS transistor (P13), the second NMOS transistor (N2), the third NMOS transistor (N3), the fourth NMOS transistor (N4), the fifth NMOS transistor (N5), the sixth NMOS transistor (N6), and the tenth NMOS transistor (P10). The NMOS transistors are: NMOS transistor (N10), NMOS transistor (N11), NMOS transistor (N12), NMOS transistor (N13), NMOS transistor (N14), and NMOS transistor (N15). The slew rate enhancement circuit includes PMOS transistor (P1), PMOS transistor (P2), NMOS transistor (N7), NMOS transistor (N8), NMOS transistor (N9), PMOS transistor (P6), PMOS transistor (P7), NMOS transistor (N16), NMOS transistor (N17), and NMOS transistor (N18), wherein:

[0025] The sources of the first PMOS transistor (P1), second PMOS transistor (P2), third PMOS transistor (P3), fourth PMOS transistor (P4), fifth PMOS transistor (P5), sixth PMOS transistor (P6), and seventh PMOS transistor (P7) are all connected to the analog positive power supply (AVDD). The gates of the first PMOS transistor (P1) and second PMOS transistor (P2) are both connected to the drain of the seventh NMOS transistor (N7). The drain of the second PMOS transistor (P2) is connected to the differential output negative terminal (Vo-), the drain of the seventeenth NMOS transistor (N17), the drain of the eighth PMOS transistor (P8), and the drain of the first NMOS transistor (N1). The gate of the third PMOS transistor (P3) is connected to the common-mode feedback voltage. (Vcmfb), the drain of the third PMOS transistor (P3) is connected to the source of the eighth PMOS transistor (P8), and the gate of the eighth PMOS transistor (P8) is connected to the first P-type bias voltage (Vbp1). The drain of the fourth PMOS transistor (P4) is connected to the sources of the ninth PMOS transistor (P9), the tenth PMOS transistor (P10), the eleventh PMOS transistor (P11), and the twelfth PMOS transistor (P12), and the gate of the fourth PMOS transistor (P4) is connected to the second P-type bias voltage (Vbp2). The gate of the fifth PMOS transistor (P5) is connected to the common-mode feedback voltage (Vcmfb), and the drain of the fifth PMOS transistor (P5) is connected to the source of the thirteenth PMOS transistor (P13). The sixth PMOS transistor (P... 6) The gates of the seventh PMOS transistor (P7) and the eighth NMOS transistor (N18) are connected to the drain of the eighteenth NMOS transistor (N18). The drain of the sixth PMOS transistor (P6) is connected to the differential output positive terminal (Vo+), the drain of the eighth NMOS transistor (N8), the drain of the thirteenth PMOS transistor (P13), and the drain of the second NMOS transistor (N2). The source of the first NMOS transistor (N1) is connected to the drain of the ninth NMOS transistor (N9), the drain of the tenth NMOS transistor (N10), the drain of the ninth PMOS transistor (P9), and the gates of the seventh to ninth NMOS transistors (N7, N8, N9). The gate of the first NMOS transistor (N1) is connected to the first N-type bias voltage (Vbn1), and the gate of the ninth PMOS transistor (P9) is connected to the drain of the seventh PMOS transistor (N9). The gates of the eleventh and eleventh PMOS transistors (P10) are both connected to the positive differential input terminal (Vin+). The drain of the tenth PMOS transistor (P10) is connected to the drains of the fifth NMOS transistor (N5), the sixth NMOS transistor (N6), the gate of the fourteenth NMOS transistor (N14), and the gate of the fifteenth NMOS transistor (N15). The drain of the eleventh PMOS transistor (P11) is connected to the drains of the third NMOS transistor (N3), the fourth NMOS transistor (N4), the gate of the tenth NMOS transistor (N10), and the gate of the eleventh NMOS transistor (N11). The gates of the eleventh PMOS transistor (P11) and the twelfth PMOS transistor (P12) are both connected to the negative differential input terminal (Vin-).The gate of the thirteenth PMOS transistor (P13) is connected to the first P-type bias voltage (Vbp1). The source of the second NMOS transistor (N2) is connected to the drain of the fifteenth NMOS transistor (N15), the drain of the sixteenth NMOS transistor (N16), the drain of the twelfth PMOS transistor (P12), and the gates of the sixteenth to eighteenth NMOS transistors (N16, N17, N18). The gate of the second NMOS transistor (N2) is connected to the first N-type bias voltage (Vbn1). The source of the third NMOS transistor (N3) is connected to the drain of the eleventh NMOS transistor (N11). The source of the fourth NMOS transistor (N4) is connected to the drain of the twelfth NMOS transistor (N12). The source of the fifth NMOS transistor (N5) is connected to the drain of the thirteenth NMOS transistor (N13). The source of the sixth NMOS transistor (N6) is connected to the drain of the eleventh NMOS transistor (N11). The drains of the fourteenth NMOS transistor (N14) are connected together. The gates of the third to sixth NMOS transistors (N3, N4, N5, N6) are connected to the first N-type bias voltage (Vbn1). The gates of the twelfth NMOS transistor (N12) and the thirteenth NMOS transistor (N13) are both connected to the second N-type bias voltage. The sources of the seventh NMOS transistor (N7), eighth NMOS transistor (N8), ninth NMOS transistor (N9), tenth NMOS transistor (N10), eleventh NMOS transistor (N11), twelfth NMOS transistor (N12), thirteenth NMOS transistor (N13), fourteenth NMOS transistor (N14), fifteenth NMOS transistor (N15), sixteenth NMOS transistor (N16), seventeenth NMOS transistor (N17), and eighteenth NMOS transistor (N18) are all connected to analog ground (AVSS).

[0026] As a further optional implementation, the substrates of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor, the eighth NMOS transistor, the ninth NMOS transistor, the tenth NMOS transistor, the eleventh NMOS transistor, the twelfth NMOS transistor, the thirteenth NMOS transistor, the fourteenth NMOS transistor, the fifteenth NMOS transistor, the sixteenth NMOS transistor, the seventeenth NMOS transistor, and the eighteenth NMOS transistor (N1 to N18) are all connected to analog ground (AVSS), and the substrates of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, the sixth PMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, the ninth PMOS transistor, the tenth PMOS transistor, the eleventh PMOS transistor, the twelfth PMOS transistor, and the thirteenth PMOS transistor (P1 to P13) are all connected to analog positive power supply (AVDD).

[0027] As an optional implementation, the potential of the analog ground (AVSS) is 0V and the potential of the analog positive power supply (AVDD) is 3.3V.

[0028] As a further optional implementation, the ninth, tenth, eleventh, and twelfth PMOS transistors (P9 to P12) have the same transistor size, and the third, fourth, fifth, and sixth NMOS transistors (N3 to N6) have the same transistor size.

[0029] As a further optional implementation, the transistor size ratio of the ninth NMOS transistor (N9), the eighth NMOS transistor (N8), and the seventh NMOS transistor (N7) is 1:m:n, and the transistor size ratio of the sixteenth NMOS transistor (N16), the seventeenth NMOS transistor (N17), and the eighteenth NMOS transistor (N18) is 1:m:n, where n = m + 2.5, and the transistor size of the ninth NMOS transistor (N9) and the sixteenth NMOS transistor (N16) is the same.

[0030] As a further optional implementation, the first PMOS transistor (P1), the second PMOS transistor (P2), the sixth PMOS transistor (P6), and the seventh PMOS transistor (P7) have the same transistor size.

[0031] As a further optional implementation, the transistor size ratio of the tenth NMOS transistor (N10), the eleventh NMOS transistor (N11), and the twelfth NMOS transistor (N12) is 6:1:1, the transistor size ratio of the fifteenth NMOS transistor (N15), the fourteenth NMOS transistor (N14), and the thirteenth NMOS transistor (N13) is 6:1:1, and the transistor size of the twelfth NMOS transistor (N12) and the fifteenth NMOS transistor (N15) is the same.

[0032] As a further optional implementation, the common-mode feedback voltage (Vcmfb) is generated by a switched-capacitor common-mode feedback circuit.

[0033] In this embodiment of the invention, direct current can flow through the tenth NMOS transistor (N10), eleventh NMOS transistor (N11), twelfth NMOS transistor (N12), thirteenth NMOS transistor (N13), fourteenth NMOS transistor (N14), and fifteenth NMOS transistor (N15), while almost no alternating current flows through the fourth NMOS transistor (N4), fifth NMOS transistor (N5), twelfth NMOS transistor (N12), and thirteenth NMOS transistor (N13), because they exhibit high impedance to AC signals. Assuming the transconductance of the ninth PMOS transistor (P9) is gm, then through the above proportional control, the final transconductance of the operational amplifier in this embodiment is Gm1 = 7 * gm. If the input transistor of a conventional folded transconductance amplifier is twice the size of P9 for comparison, then its transconductance is Gm2 = 2 * gm. This indicates that the transconductance of the amplifier in this embodiment is 3.5 times that of a conventional folded transconductance amplifier, which will significantly improve the amplifier's bandwidth.

[0034] Meanwhile, the positive slew rate SR of the operational amplifier + It can be represented as:

[0035] SR + = (1+n)*I b / C L

[0036] Among them, I b C is half the current flowing through the fourth PMOS transistor (P4). L This refers to the size of the load capacitors connected to each of the two output terminals of the amplifier.

[0037] The negative slew rate SR of an operational amplifier can be expressed as:

[0038] SR - = (m + 3.5) * I b / C L

[0039] Therefore, this embodiment shows that the slew rate of the amplifier can be adjusted by changing the value of m. To make the positive and negative slew rates of the operational amplifier as close as possible, this embodiment uses n = m + 2.5. In this case, the total slew rate SR of the operational amplifier can be expressed as:

[0040] SR=(2m+7)*I b / C L

[0041] In this embodiment, m = 5 is selected, and SPICE simulation is performed on the CADENCE platform. The simulation results show that when the load capacitor CL = 40pF is connected to each of the output terminals, under a total bias current of 400μA (including the current of the bias circuit), the unity-gain bandwidth is 15.4MHz, the DC gain is 87.8dB, the positive slew rate is 15.5V·μs^(-1), the negative slew rate is 15.4V·μs^(-1), the total slew rate is 30.9V·μs^(-1), and the phase margin is 44°.

[0042] It can be recognized that by adopting the embodiments of the present invention, through careful design of the size of each branch transistor, the current of each branch is utilized more fully compared with the traditional transconductance amplifier. By designing the slew rate enhancement circuit, the positive and negative slew rates can be significantly improved during the large-signal operation of the amplifier, while the transistors operate in the subthreshold region during the small-signal operation of the amplifier, consuming almost no current. This further improves the unity-gain bandwidth and slew rate of the amplifier, thereby improving the operating speed and output current capability of the operational amplifier. It has high reliability and broad application prospects.

[0043] The slew rate enhancement circuit of this invention can significantly improve the positive and negative slew rates during the large-signal operation of the amplifier, while during the small-signal operation of the amplifier, its transistors operate in the subthreshold region and consume almost no current. Therefore, it can improve the unity-gain bandwidth and slew rate of the amplifier while maintaining low power consumption, thereby improving the operating speed and output current capability of the operational amplifier. This invention also improves the operating speed of the high-performance switched capacitor circuit, reduces power consumption, and is easy to promote and use.

[0044] In the foregoing description of this specification, references to terms such as "one embodiment," "another embodiment," or "some embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of the present invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0045] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

[0046] The above is a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.

Claims

1. A broadband low-power transconductance operational amplifier with enhanced slew rate, characterized in that, The system includes an improved cyclically folded transconductance operational amplifier and a slew rate enhancement circuit. The improved cyclically folded transconductance operational amplifier includes a third PMOS transistor, an eighth PMOS transistor, a first NMOS transistor, a fourth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a fifth PMOS transistor, a thirteenth PMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, and a fifteenth NMOS transistor. The slew rate enhancement circuit includes a first PMOS transistor, a second PMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a sixteenth NMOS transistor, a seventeenth NMOS transistor, and an eighteenth NMOS transistor, wherein: The sources of the first, second, third, fourth, fifth, sixth, and seventh NMOS transistors are all connected to an analog positive power supply. The gates of the first and second PMOS transistors are both connected to the drain of the seventh NMOS transistor. The drain of the second PMOS transistor is connected to the negative terminal of the differential output, the drain of the seventeenth NMOS transistor, the drain of the eighth PMOS transistor, and the drain of the first NMOS transistor. The gate of the third PMOS transistor is connected to a common-mode feedback voltage, and the drain of the third PMOS transistor is connected to the source of the eighth PMOS transistor. The gate of the eighth PMOS transistor... The fourth PMOS transistor's drain is connected to the source of the ninth, tenth, eleventh, and twelfth PMOS transistors, and its gate is connected to the second PMOS transistor's gate. The fifth PMOS transistor's gate is connected to the common-mode feedback voltage, and its drain is connected to the source of the thirteenth PMOS transistor. The gates of the sixth and seventh PMOS transistors are both connected to the drain of the eighteenth NMOS transistor. The drain of the sixth PMOS transistor is connected to the differential output positive terminal, the drain of the eighth NMOS transistor, the drain of the thirteenth PMOS transistor, and the drain of the second NMOS transistor. The drain of the first NMOS transistor is connected to the drain of the ninth NMOS transistor, the drain of the tenth NMOS transistor, the drain of the ninth PMOS transistor, the gate of the seventh NMOS transistor, the gate of the eighth NMOS transistor, and the gate of the ninth NMOS transistor. The gate of the first NMOS transistor is connected to a first N-type bias voltage. The gates of the ninth and tenth PMOS transistors are both connected to the positive terminal of the differential input. The drain of the tenth PMOS transistor is connected to the drain of the fifth NMOS transistor, the drain of the sixth NMOS transistor, the gate of the fourteenth NMOS transistor, and the gate of the fifteenth NMOS transistor. The drain of the eleventh PMOS transistor is connected to the drain of the... The drain of the third NMOS transistor, the drain of the fourth NMOS transistor, the gate of the tenth NMOS transistor, and the gate of the eleventh NMOS transistor are connected together. The gates of the eleventh PMOS transistor and the twelfth PMOS transistor are both connected to the negative terminal of the differential input. The gate of the thirteenth PMOS transistor is connected to the first P-type bias voltage. The source of the second NMOS transistor is connected to the drain of the fifteenth NMOS transistor, the drain of the sixteenth NMOS transistor, the drain of the twelfth PMOS transistor, the gate of the sixteenth NMOS transistor, the gate of the seventeenth NMOS transistor, and the gate of the eighteenth NMOS transistor. The gate of the second NMOS transistor is connected to the first N-type bias voltage.The source of the third NMOS transistor is connected to the drain of the eleventh NMOS transistor; the source of the fourth NMOS transistor is connected to the drain of the twelfth NMOS transistor; the source of the fifth NMOS transistor is connected to the drain of the thirteenth NMOS transistor; and the source of the sixth NMOS transistor is connected to the drain of the fourteenth NMOS transistor. The gates of the third, fourth, fifth, and sixth NMOS transistors are all connected to the first N-type bias voltage. The gates of the twelfth and thirteenth NMOS transistors are both connected to the second N-type bias voltage. The sources of the seventh, eighth, ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, fifteenth, sixteenth, seventeenth, and eighteenth NMOS transistors are all connected to analog ground.

2. The broadband low-power transconductance operational amplifier with enhanced slew rate according to claim 1, characterized in that: The substrates of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor, the eighth NMOS transistor, the ninth NMOS transistor, the tenth NMOS transistor, the eleventh NMOS transistor, the twelfth NMOS transistor, the thirteenth NMOS transistor, the fourteenth NMOS transistor, the fifteenth NMOS transistor, the sixteenth NMOS transistor, the seventeenth NMOS transistor, and the eighteenth NMOS transistor are all connected to the analog ground. The substrates of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, the sixth PMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, the ninth PMOS transistor, the tenth PMOS transistor, the eleventh PMOS transistor, the twelfth PMOS transistor, and the thirteenth PMOS transistor are all connected to the analog positive power supply.

3. The broadband low-power transconductance operational amplifier with enhanced slew rate according to claim 2, characterized in that: The potential of the simulated ground is 0V, and the potential of the simulated positive power supply is 3.3V.

4. The broadband low-power transconductance operational amplifier with enhanced slew rate according to claim 1, characterized in that: The ninth, tenth, eleventh, and twelfth PMOS transistors have the same transistor size, and the third, fourth, fifth, and sixth NMOS transistors have the same transistor size.

5. A broadband low-power transconductance operational amplifier with enhanced slew rate according to claim 1, characterized in that: The transistor size ratio of the ninth NMOS transistor, the eighth NMOS transistor, and the seventh NMOS transistor is 1:m:n, and the transistor size ratio of the sixteenth NMOS transistor, the seventeenth NMOS transistor, and the eighteenth NMOS transistor is 1:m:n, where n = m + 2.

5. The transistor size of the ninth NMOS transistor and the sixteenth NMOS transistor is the same.

6. The broadband low-power transconductance operational amplifier with enhanced slew rate according to claim 1, characterized in that: The first PMOS transistor, the second PMOS transistor, the sixth PMOS transistor, and the seventh PMOS transistor have the same transistor size.

7. A broadband low-power transconductance operational amplifier with enhanced slew rate according to claim 1, characterized in that: The transistor size ratio of the tenth, eleventh, and twelfth NMOS transistors is 6:1:1, and the transistor size ratio of the fifteenth, fourteenth, and thirteenth NMOS transistors is 6:1:

1. The transistor size of the twelfth and fifteenth NMOS transistors is the same.

8. A broadband low-power transconductance operational amplifier with enhanced slew rate according to any one of claims 1 to 7, characterized in that: The common-mode feedback voltage is generated by a switched-capacitor common-mode feedback circuit.

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