Folded cascode amplifier, integrated circuit, chip and electronic device
By splitting the input differential pair transistors of the folded cascode amplifier into symmetrical units and configuring a current mirror, the problems of low slew rate and high power consumption are solved, achieving high efficiency conversion rate and low power consumption of the amplifier.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- CHIPONE TECHNOLOGY (BEIJING) CO LTD
- Filing Date
- 2025-06-03
- Publication Date
- 2026-06-09
Smart Images
Figure CN224343154U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of amplifier technology, specifically to a folded common-source cascode amplifier, integrated circuit, chip, and electronic device. Background Technology
[0002] Advances in CMOS technology have greatly propelled the development of mobile and portable electronic devices. This is thanks to the high integration of analog and digital circuits. In analog circuits, the transconductance amplifier is a crucial component, often occupying the largest area and consuming the most power in many applications. To a certain extent, the performance of the transconductance amplifier determines the performance of the entire analog circuit. Folded cascode amplifiers are widely used in analog circuits due to their low power consumption. A folded cascode amplifier typically consists of a tail current source, an input differential pair of transistors, two sets of cascode amplifier transistors, and a current mirror. The load current transistor of the cascode amplifier carries the largest current, providing a folding node for the small-signal current of the input pair, resulting in relatively low efficiency. The equivalent output transconductance of this amplifier is approximately equal to the transconductance of one transistor in the input differential pair, with both transconductance and slew rate being relatively low. Therefore, current folded cascode amplifiers have low slew rate, high power consumption, and their performance needs improvement. Utility Model Content
[0003] To address the aforementioned technical problems, this application provides a folded common-source cascode amplifier, integrated circuit, and electronic device.
[0004] According to one aspect of the present invention, a folded cascode amplifier is provided, comprising: a bias circuit receiving a bias voltage to output a bias current; a first input differential unit receiving a positive input voltage, comprising a first positive input transistor, a second positive input transistor, and a third positive input transistor connected in parallel, wherein the sources of the first positive input transistor to the third positive input transistor are all connected to the output terminal of the bias circuit; a second input differential unit receiving a negative input voltage, comprising a first negative input transistor, a second negative input transistor, and a third negative input transistor connected in parallel, wherein the sources of the first negative input transistor to the third negative input transistor are all connected to the output terminal of the bias circuit; and a folded cascode unit comprising a first group of cascode transistors and a second group of cascode transistors, as well as a first group of current mirrors and a second group of current mirrors. The amplifier comprises a first group of current mirrors, a third group of current mirrors, and a fourth group of current mirrors. The first group of common-source cascode transistors includes a first output transistor and a first load current transistor connected in series, with the common node of the first output transistor and the first load current transistor connected to the drain of the first positive input transistor. The second group of common-source cascode transistors includes a second output transistor and a second load current transistor connected in series, with the common node of the second output transistor and the second load current transistor connected to the drain of the first negative input transistor. The first group of current mirrors reuses the first load current transistor, and the fourth group of current mirrors reuses the second load current transistor. A fifth group of current mirrors is connected to the first output transistor and the second output transistor, and the common node of the fifth group of current mirrors and the second output transistor is the output terminal of the folded common-source cascode amplifier.
[0005] Optionally, the bias circuit includes a tail current source, the input terminal of which receives the supply voltage, the control terminal receives the bias voltage, and the output terminal outputs the bias current, and the tail current source includes a PMOS transistor.
[0006] Optionally, all three positive input transistors are PMOS transistors, and the gates of the first positive input transistor to the third positive input transistor are connected to serve as the non-inverting input terminal of the folded cascode amplifier, receiving the positive input voltage; all three negative input transistors are PMOS transistors, and the gates of the first negative input transistor to the third negative input transistor are connected to serve as the inverting input terminal of the folded cascode amplifier, receiving the negative input voltage.
[0007] Optionally, the size ratio of the first positive input transistor to the third positive input transistor is the same as the size ratio of the first negative input transistor to the third negative input transistor.
[0008] Optionally, the first set of current mirrors includes a first load current transistor, a first transistor, and a first enhancement transistor. The gate of the first load current transistor is connected to the gate of the first transistor. The source of the first load current transistor and the source of the first transistor are grounded together. The drain of the first transistor is connected to the source of the first enhancement transistor. The drain of the first enhancement transistor is connected to the gate of the first transistor and the drain of the third negative input transistor. The gate of the first enhancement transistor receives a control voltage. The second set of current mirrors includes a second transistor, a second enhancement transistor, a third transistor, and a third enhancement transistor. The gate of the second transistor is connected to the gate of the third transistor. The source of the second transistor and the source of the third transistor are grounded together. The drain of the second transistor is connected to the source of the second enhancement transistor. The drain of the second enhancement transistor is connected to the gate of the second transistor and the drain of the second positive input transistor. The drain of the third transistor is connected to the source of the third enhancement transistor. The drain of the third enhancement transistor is connected to the drain of the third negative input transistor. The gates of the second enhancement transistor and the third enhancement transistor are connected and receive the control voltage. The fourth set of current mirrors includes a second load current transistor, a fourth transistor, and a fourth enhancement transistor. The gate of the second load current transistor is connected to the gate of the fourth transistor. The source of the second load current transistor and the source of the fourth transistor are grounded together. The drain of the fourth transistor is connected to the source of the fourth enhancement transistor. The drain of the fourth enhancement transistor is connected to the gate of the fourth transistor and the drain of the third positive input transistor. The gate of the fourth enhancement transistor receives the control voltage. The third set of current mirrors includes a fifth transistor, a fifth enhancement transistor, a sixth transistor, and a sixth enhancement transistor. The gate of the fifth transistor is connected to the gate of the sixth transistor. The source of the fifth transistor and the source of the sixth transistor are grounded together. The drain of the fifth transistor is connected to the source of the fifth enhancement transistor. The drain of the fifth enhancement transistor is connected to the gate of the fifth transistor and the drain of the second negative input transistor. The drain of the sixth transistor is connected to the source of the sixth enhancement transistor. The drain of the sixth enhancement transistor is connected to the drain of the third positive input transistor. The gate of the fifth enhancement transistor and the gate of the sixth enhancement transistor are connected and receive the control voltage.
[0009] Optionally, the mirror ratio of the first group of current mirrors is the same as that of the third group of current mirrors, and the mirror ratio of the second group of current mirrors is the same as that of the fourth group of current mirrors.
[0010] Optionally, the fifth current mirror includes a seventh transistor and an eighth transistor. The gate of the seventh transistor is connected to the gate of the eighth transistor. The source of the seventh transistor and the source of the eighth transistor share the same supply voltage. The drain of the seventh transistor is connected to the drain of the first output transistor. The drain of the eighth transistor is connected to the drain of the second output transistor. The gate of the seventh transistor is also connected to the drain of the seventh transistor. The gates of the first output transistor and the second output transistor are connected and receive a control voltage. The connection node between the second output transistor and the eighth transistor provides an output voltage.
[0011] Optionally, the transistors included in the first to fourth current mirrors are all NMOS transistors, the seventh and eighth transistors included in the fifth current mirror are both PMOS transistors, and the first and second output transistors are both NMOS transistors.
[0012] According to another aspect of the present invention, an integrated circuit is provided, comprising: the above-described folded common-source common-gate amplifier, which amplifies the input differential signal and outputs an output voltage.
[0013] According to another aspect of the present invention, a chip is provided, comprising: the above-described folded common-source common-gate amplifier, which amplifies the input differential signal and outputs an output voltage.
[0014] According to another aspect of the present invention, an electronic device is provided, comprising: the above-described folded common-source common-gate amplifier, which amplifies the input differential signal and outputs an output voltage.
[0015] The beneficial effects of this application include at least the following:
[0016] This application provides a folded cascode amplifier, integrated circuit, chip, and electronic device. The traditional folded cascode amplifier's input differential pair is split into symmetrical first and second input differential units. Each input differential unit includes three transistors connected in parallel. Two load current sources connected to the input differential pair are respectively configured as current mirrors, and the two input differential units are connected to a total of four sets of current mirrors, forming a negative feedback loop. With this symmetrical circuit structure, the size ratio of the transistors in the two input differential units and the mirror ratio of the four sets of current mirrors can be flexibly configured. Under a reasonable proportional design, the equivalent output transconductance and slew rate of the operational amplifier can be multiplied, thereby improving the op-amp's slew rate and gain-bandwidth product. At the same slew rate, the circuit requires less current and consumes less power.
[0017] Furthermore, by setting the size ratio of the three transistors in each input differential unit to 1:1:2, and the mirror ratios of the two sets of current mirrors below each input differential unit to 1:1 and 1:5 respectively, calculations show that, under these ratios, the equivalent input transconductance of this circuit structure is increased by 4 times and the slew rate by 2.5 times compared to a traditional folded cascode amplifier. Thus, the gain-bandwidth product (GBW) increases fourfold while maintaining the same power consumption, and the conversion speed also increases fourfold. Similarly, while ensuring the same conversion rate, the power consumption will be reduced accordingly. In this invention, other ratios can be set according to actual needs to obtain other transconductance and slew rates; that is, different transconductance and slew rates can be obtained by setting different size ratios and mirror ratios.
[0018] It should be noted that the above general description and the following detailed description are merely exemplary and explanatory, and do not limit this application. Attached Figure Description
[0019] Figure 1 A circuit diagram of a folded common-source cascode amplifier in the prior art is shown;
[0020] Figure 2 A circuit diagram of a folded common-source cascode amplifier according to an embodiment of the present invention is shown. Detailed Implementation
[0021] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in different forms and is not limited to the embodiments described herein.
[0022] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized. "A plurality" means two or more.
[0023] In addition, the same reference numerals in the figures indicate the same or similar structures, so repeated descriptions of them will be omitted. That is, the various parts in this specification are described in a combination of parallel and progressive manner. Each part focuses on the differences from other parts, and the same or similar parts between the various parts can be referred to each other.
[0024] Figure 1 A circuit diagram of a folded cascode amplifier in the prior art is shown.
[0025] like Figure 1 As shown, the folded cascode amplifier 100 mainly includes a bias circuit 110, an input differential pair transistor 120, a folded cascode unit 130, and a current mirror 140. The bias circuit 110 receives the bias voltage Vbp1 and converts it into a bias current Iss. The bias circuit 110 includes, for example, a tail current source, which typically includes a transistor. In this embodiment, the tail current source includes transistor M0, which is a PMOS transistor. The source of transistor M0 receives the supply voltage VDD, the gate receives the bias voltage Vbp1, and the drain serves as the output terminal, outputting the bias current Iss. The input differential pair transistor 120 is connected to the output terminal of the bias circuit 110 and includes transistors M1 and M2. Transistors M1 and M2 are used to shunt the bias current Iss. Furthermore, the gate of transistor M1 is used to receive the positive input voltage Vin+, and the gate of transistor M2 is used to receive the negative input voltage Vin-. Transistor M1 serves as the positive input terminal of the amplifier, and transistor M2 serves as the negative input terminal of the amplifier. Transistors M1 and M2 are, for example, PMOS transistors, and the sources of transistors M1 and M2 are both connected to the output terminal of the bias circuit 110.
[0026] The folded cascode unit 130 includes a first group of cascode transistors and a second group of cascode transistors. The first group of cascode transistors includes a first output transistor M5 and a load current transistor M3 connected in series. The common node of the first output transistor M5 and the load current transistor M3 is connected to the drain of transistor M1. The second group of cascode transistors includes a second output transistor M6 and a load current transistor M4 connected in series. The common node of the second output transistor M6 and the load current transistor M4 is connected to the drain of transistor M2. Specifically, the drain of the load current transistor M3 is connected to the drain of transistor M1 and the source of the first output transistor M5, and the drain of the load current transistor M4 is connected to the drain of transistor M2 and the source of the second output transistor M6. The sources of the load current transistors M3 and M4 are both grounded to GND. The gates of the load current transistors M3 and M4 are connected and receive a control voltage Vbn1. The gates of the first output transistor M5 and the second output transistor M6 are connected and receive a control voltage Vbn2. For example, the load current transistors M3 and M4, the first output transistor M5, and the second output transistor M6 are all NMOS transistors.
[0027] The current mirror 140 includes a seventh transistor M7 and an eighth transistor M8. The gates of the seventh transistor M7 and the eighth transistor M8 are connected, and their sources share the supply voltage VDD. The drain of the seventh transistor M7 is connected to the drain of the first output transistor M5, and the drain of the eighth transistor M8 is connected to the drain of the second output transistor M6. The gate of the seventh transistor M7 is also connected to its drain. Both the seventh transistor M7 and the eighth transistor M8 are, for example, PMOS transistors. The output voltage Vout is provided by node A, which connects the second output transistor M6 and the eighth transistor M8. This node A serves as the output terminal of the amplifier.
[0028] exist Figure 1 In the amplifier circuit architecture shown, its equivalent output transconductance is approximately equal to the transconductance of transistor M1, which is relatively small. The slew rate is generally equal to Iss / CL, where CL is the load capacitance. Increasing the slew rate requires increasing the current, resulting in higher power consumption. Therefore, to further reduce power consumption and improve the slew rate of the output as a function of input, this invention proposes another folded cascode amplifier, detailed in [link to details]. Figure 2 .
[0029] Figure 2 A circuit diagram of a folded common-source cascode amplifier according to an embodiment of the present invention is shown.
[0030] like Figure 2 As shown, the folded cascode amplifier 200 of this embodiment includes a bias circuit 110, a first input differential unit 221, a second input differential unit 222, a folded cascode unit 230, and a current mirror 140 (also referred to as the fifth current mirror 140 to distinguish it from the four current mirrors in the folded cascode unit 230). The bias circuit 110 and the current mirror 140 are connected to... Figure 1 The descriptions in the embodiments are consistent and will not be repeated here. In this embodiment, Figure 1 Transistor M1 is replaced with the first input differential unit 221, and transistor M2 is replaced with the second input differential unit 222. Correspondingly, load current transistor M3 is replaced with the first load current transistor M3b, and load current transistor M4 is replaced with the second load current transistor M4b. The first output transistor M5 and the second output transistor M6 are also... Figure 1 The implementation methods are the same, so they will not be repeated here.
[0031] Furthermore, the first input differential unit 221 serves as the non-inverting input terminal of the amplifier, receiving the positive input voltage Vin+. The first input differential unit 221 includes a first positive input transistor M1a, a second positive input transistor M1b, and a third positive input transistor M1c connected in parallel. The sources of the first positive input transistor M1a to the third positive input transistor M1c are all connected to the output terminal of the bias circuit 110, and their gates are connected together to serve as the non-inverting input terminal, receiving the common positive input voltage Vin+. The first positive input transistor M1a to the third positive input transistor M1c are, for example, PMOS transistors. The second input differential unit 222 serves as the inverting input terminal of the amplifier, receiving the negative input voltage Vin-. The second input differential unit 222 includes a first negative input transistor M2a, a second negative input transistor M2b, and a third negative input transistor M2c connected in parallel. The sources of all three transistors (M2a to M2c) are connected to the output terminal of the bias circuit 110, and their gates, when connected, serve as the inverting input terminal, receiving the negative input voltage Vin-. For example, all three transistors (M2a to M2c) are PMOS transistors.
[0032] In this embodiment, the size ratio of the first positive input transistor M1a to the third positive input transistor M1c is the same as the size ratio of the first negative input transistor M2a to the third negative input transistor M2c. If the size ratio of the first positive input transistor M1a to the third positive input transistor M1c is set to K:M:N, then the size ratio of the first negative input transistor M2a to the third negative input transistor M2c is also K:M:N. K, M, and N are all natural numbers, and different size ratios can be set according to actual circuit requirements.
[0033] The folded cascode unit 230 of this embodiment includes a first group of cascode transistors and a second group of cascode transistors, as well as a first group of current mirrors 231, a second group of current mirrors 232, a third group of current mirrors 233, and a fourth group of current mirrors 234. The first group of cascode transistors includes a first output transistor M5 and a first load current transistor M3b connected in series, with the common node of the first output transistor M5 and the first load current transistor M3b connected to the drain of the first positive input transistor M1a. The second group of cascode transistors includes a second output transistor M6 and a second load current transistor M4b connected in series, with the common node of the second output transistor M6 and the second load current transistor M4b connected to the drain of the first negative input transistor M2a. The first group of current mirrors 231 multiplexes the first load current transistor M3b, and the fourth group of current mirrors 234 multiplexes the second load current transistor M4b.
[0034] Specifically, the first set of current mirrors 231 includes a first load current transistor M3b, a first transistor M3a, and a first enhancement transistor M3e. The gate of the first load current transistor M3b is connected to the gate of the first transistor M3a. The source of the first load current transistor M3b and the source of the first transistor M3a are grounded to GND. The drain of the first transistor M3a is connected to the source of the first enhancement transistor M3e. The drain of the first enhancement transistor M3e is connected to the gate of the first transistor M3a and the drain of the third negative input transistor M2c. The gate of the first enhancement transistor M3e receives the control voltage Vbn. The second set of current mirrors 232 includes a second transistor M3c, a second enhancement transistor M3f, a third transistor M3d, and a third enhancement transistor M3g. The gate of the second transistor M3c is connected to the gate of the third transistor M3d. The source of the second transistor M3c is grounded together with the source of the third transistor M3d. The drain of the second transistor M3c is connected to the source of the second enhancement transistor M3f. The drain of the second enhancement transistor M3f is connected to the gate of the second transistor M3c and the drain of the second positive input transistor M1b. The drain of the third transistor M3d is connected to the source of the third enhancement transistor M3g. The drain of the third enhancement transistor M3g is connected to the drain of the third negative input transistor M2c. The gates of the second enhancement transistor M3f and the third enhancement transistor M3g are connected and receive a control voltage Vbn. The fourth current mirror 234 includes a second load current transistor M4b, a fourth transistor M4a, and a fourth enhancement transistor M4e. The gate of the second load current transistor M4b is connected to the gate of the fourth transistor M4a. The source of the second load current transistor M4b and the source of the fourth transistor M4a are grounded together. The drain of the fourth transistor M4a is connected to the source of the fourth enhancement transistor M4e. The drain of the fourth enhancement transistor M4e is connected to the gate of the fourth transistor M4a and the drain of the third positive input transistor M1c. The gate of the fourth enhancement transistor M4e receives the control voltage Vbn. The third set of current mirrors 233 includes a fifth transistor M4c, a fifth enhancement transistor M4f, a sixth transistor M4d, and a sixth enhancement transistor M4g. The gate of the fifth transistor M4c is connected to the gate of the sixth transistor M4d. The source of the fifth transistor M4c is grounded together with the source of the sixth transistor M4d. The drain of the fifth transistor M4c is connected to the source of the fifth enhancement transistor M4f. The drain of the fifth enhancement transistor M4f is connected to the gate of the fifth transistor M4c and the drain of the second negative input transistor M2b. The drain of the sixth transistor M4d is connected to the source of the sixth enhancement transistor M4g. The drain of the sixth enhancement transistor M4g is connected to the drain of the third positive input transistor M1c. The gates of the fifth enhancement transistor M4f and the sixth enhancement transistor M4g are connected and receive a control voltage Vbn. All transistors included in the first set of current mirrors 231 to the fourth set of current mirrors 234 are, for example, NMOS transistors.
[0035] In this embodiment, the mirror ratio of the first set of current mirrors 231 is the same as that of the third set of current mirrors 233, and the mirror ratio of the second set of current mirrors 232 is the same as that of the fourth set of current mirrors 234. For example, if the mirror ratio of the first set of current mirrors 231 is X:W and the mirror ratio of the second set of current mirrors 232 is Z:Y, then the mirror ratio of the fourth set of current mirrors 234 is also X:W, and the mirror ratio of the third set of current mirrors 233 is also Z:Y.
[0036] The gates of the first output transistor M5 and the second output transistor M6 are connected and receive the control voltage Vbn. The connection node between the second output transistor M6 and the eighth transistor M8 provides the output voltage Vout. The seventh transistor M7 and the eighth transistor M8 included in the current mirror 140 are both PMOS transistors, while the first output transistor M5 and the second output transistor M6 are both NMOS transistors.
[0037] In summary, for Figure 2 The illustrated folded cascode amplifier allows for flexible adjustment of the K:M:N ratio to alter the current flowing through the branches of the transistors in the two input differential units, based on the specific circuit requirements. Furthermore, setting appropriate Z:Y and X:W ratios according to the actual circuit needs can result in different current values in the output stage. The advantage of this circuit architecture is that the aforementioned ratios can be flexibly set according to different circuit requirements, and with a reasonable proportional design, the amplifier's equivalent output transconductance and slew rate can be multiplied, thereby improving the amplifier's slew rate and reducing power consumption.
[0038] The following is a detailed description using a specific embodiment: For example, K:M:N = 1:1:2, and the corresponding ratios of the current mirrors are Z:Y = 1:1 and X:W = 1:5. After calculation, under this ratio, the circuit architecture of this embodiment is compared to... Figure 1 For this amplifier, its equivalent input transconductance increases to four times its original value, and its slew rate increases to 2.5 times its original value. In other words, with the same power consumption, Figure 2 The gain-bandwidth product (GBW) of the circuit architecture shown is Figure 1 Four times faster, therefore the switching speed of the amplifier in this embodiment will also be... Figure 1 Four times that of the amplifier. Similarly, while maintaining the same conversion rate, power consumption will be reduced accordingly. Furthermore, by designing other suitable ratios, other transconductance and slew rates can be obtained while ensuring normal circuit operation.
[0039] In addition, this utility model also provides an integrated circuit, which can be an analog circuit and may include the folded cascode amplifier mentioned in the above embodiments. The folded cascode amplifier amplifies the input differential signal and outputs an output voltage.
[0040] Furthermore, this utility model also provides a chip that may include an analog circuit, which may include the folded cascode amplifier of the above embodiment. The folded cascode amplifier amplifies the input differential signal and outputs an output voltage.
[0041] Furthermore, this utility model also provides an electronic device that may include the aforementioned integrated circuit, wherein the integrated circuit includes the aforementioned folded cascode amplifier.
[0042] This invention relates to a folded cascode amplifier and its application in integrated circuits, chips, and electronic devices. The traditional folded cascode amplifier's input differential pair is split into symmetrical first and second input differential units. Each input differential unit includes three transistors connected in parallel. Two load current sources connected to the input differential pair are respectively configured as current mirrors, resulting in a total of four current mirrors connected to the two input differential units, creating negative feedback in the overall circuit. With this symmetrical circuit structure, the size ratio of the transistors in the two input differential units and the mirror ratio of the four current mirrors can be flexibly configured. With a reasonable proportional design, the equivalent output transconductance and slew rate of the operational amplifier can be multiplied, thereby improving the op-amp's slew rate and gain-bandwidth product. At the same slew rate, the circuit requires less current and consumes less power.
[0043] Finally, it should be noted that the above embodiments are merely examples for clearly illustrating this application and are not intended to limit the implementation. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.
Claims
1. A folded cascode amplifier, comprising: a biasing circuit receiving a bias voltage to output a bias current; a first input differential unit receiving a positive input voltage, comprising a first positive input transistor, a second positive input transistor and a third positive input transistor connected in parallel, the sources of the first positive input transistor to the third positive input transistor are connected to an output of the biasing circuit; a second input differential unit receiving a negative input voltage, comprising a first negative input transistor, a second negative input transistor and a third negative input transistor connected in parallel, the sources of the first negative input transistor to the third negative input transistor are connected to the output of the biasing circuit; a folded cascode unit comprising a first group of cascode transistors and a second group of cascode transistors, and a first group of current mirrors, a second group of current mirrors, a third group of current mirrors and a fourth group of current mirrors, the first group of cascode transistors comprising a first output transistor and a first load current transistor connected in series, a common node of the first output transistor and the first load current transistor is connected to a drain of the first positive input transistor, the second group of cascode transistors comprising a second output transistor and a second load current transistor connected in series, a common node of the second output transistor and the second load current transistor is connected to a drain of the first negative input transistor, and the first group of current mirrors multiplexes the first load current transistor, the fourth group of current mirrors multiplexes the second load current transistor; and a fifth group of current mirrors connected to the first output transistor and the second output transistor, and a common node of the fifth group of current mirrors and the second output transistor is an output of the folded cascode amplifier. The biasing circuit comprises a tail current source, an input of the tail current source receives a supply voltage, a control terminal of the tail current source receives the bias voltage, and an output of the tail current source outputs the bias current, the tail current source comprises a PMOS transistor.
2. The folded cascode amplifier of claim 1, wherein, 3. The folded cascode amplifier of claim 1, wherein: the first positive input transistor to the third positive input transistor are PMOS transistors, and gates of the first positive input transistor to the third positive input transistor are connected to receive the positive input voltage as a non-inverting input of the folded cascode amplifier; the first negative input transistor to the third negative input transistor are PMOS transistors, and gates of the first negative input transistor to the third negative input transistor are connected to receive the negative input voltage as an inverting input of the folded cascode amplifier. a size ratio of the first positive input transistor to the third positive input transistor is the same as a size ratio of the first negative input transistor to the third negative input transistor.
4. The folded cascode amplifier of claim 1, wherein, 5. The folded cascode amplifier of claim 1, wherein: The first group of current mirrors comprises the first load current tube, a first transistor and a first enhancement tube, the gate of the first load current tube is connected with the gate of the first transistor, the source of the first load current tube and the source of the first transistor are commonly grounded, the drain of the first transistor is connected with the source of the first enhancement tube, the drain of the first enhancement tube is connected with the gate of the first transistor and the drain of the third negative input transistor, and the gate of the first enhancement tube receives a control voltage; The second group of current mirrors comprises a second transistor, a second enhancement tube, a third transistor and a third enhancement tube, the gate of the second transistor is connected with the gate of the third transistor, the source of the second transistor and the source of the third transistor are commonly grounded, the drain of the second transistor is connected with the source of the second enhancement tube, the drain of the second enhancement tube is connected with the gate of the second transistor and the drain of the second positive input transistor, the drain of the third transistor is connected with the source of the third enhancement tube, the drain of the third enhancement tube is connected with the drain of the third negative input transistor, and the gate of the second enhancement tube and the gate of the third enhancement tube are connected and receive the control voltage; The fourth group of current mirrors comprises the second load current tube, a fourth transistor and a fourth enhancement tube, the gate of the second load current tube is connected with the gate of the fourth transistor, the source of the second load current tube and the source of the fourth transistor are commonly grounded, the drain of the fourth transistor is connected with the source of the fourth enhancement tube, the drain of the fourth enhancement tube is connected with the gate of the fourth transistor and the drain of the third positive input transistor, and the gate of the fourth enhancement tube receives the control voltage; The third group of current mirrors comprises a fifth transistor, a fifth enhancement tube, a sixth transistor and a sixth enhancement tube, the gate of the fifth transistor is connected with the gate of the sixth transistor, the source of the fifth transistor and the source of the sixth transistor are commonly grounded, the drain of the fifth transistor is connected with the source of the fifth enhancement tube, the drain of the fifth enhancement tube is connected with the gate of the fifth transistor and the drain of the second negative input transistor, the drain of the sixth transistor is connected with the source of the sixth enhancement tube, the drain of the sixth enhancement tube is connected with the drain of the third positive input transistor, and the gate of the fifth enhancement tube and the gate of the sixth enhancement tube are connected and receive the control voltage.
6. The folded cascode amplifier of claim 1, wherein, The mirror ratio of the first group of current mirrors is the same as the mirror ratio of the third group of current mirrors, and the mirror ratio of the second group of current mirrors is the same as the mirror ratio of the fourth group of current mirrors.
7. The folded cascode amplifier of claim 1, wherein, The fifth group of current mirrors comprises a seventh transistor and an eighth transistor, the gate of the seventh transistor is connected with the gate of the eighth transistor, the source of the seventh transistor and the source of the eighth transistor commonly receive a power supply voltage, the drain of the seventh transistor is connected with the drain of the first output transistor, the drain of the eighth transistor is connected with the drain of the second output transistor, the gate of the seventh transistor is also connected with the drain of the seventh transistor, The gate of the first output transistor and the gate of the second output transistor are connected and receive a control voltage, and the connection node of the second output transistor and the eighth transistor provides an output voltage.
8. The folded cascode amplifier of claim 1, wherein, The transistors included in the first to fourth groups of current mirrors are all NMOS transistors, the seventh and eighth transistors included in the fifth group of current mirrors are both PMOS transistors, and the first and second output transistors are both NMOS transistors.
9. An integrated circuit, characterized by Comprising: The folded cascode amplifier according to any one of claims 1-8, amplifies an input differential signal and outputs an output voltage.
10. A chip, characterized by Comprising: The folded cascode amplifier according to any one of claims 1-8, amplifies an input differential signal and outputs an output voltage.
11. An electronic device, comprising: Comprising: The folded cascode amplifier according to any one of claims 1-8, amplifies an input differential signal and outputs an output voltage. Comprising: The folded cascode amplifier according to any one of claims 1-8, amplifies an input differential signal and outputs an output voltage.