A synthesizable dynamic amplifier with stable common mode output voltage

Abstract

The application belongs to the technical field of semiconductor and integrated circuit, and particularly relates to a comprehensive dynamic amplifier with stable common-mode output voltage. The comprehensive dynamic amplifier comprises an input stage, a common-mode detection stage and an output stage circuit. The dynamic amplifier works in three phases, namely, a reset phase, an amplification phase and a latch phase. The amplification phase is divided into a sampling stage and an amplification stage. The sampling stage controls the output common mode to be stable, and the amplification stage amplifies the differential-mode voltage to improve the gain of the amplifier. The dynamic amplifier is composed of digital standard units, is compatible with automatic process design, shortens the circuit design time and is convenient for process migration.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor and integrated circuit technology, and specifically relates to a synthesizable dynamic amplifier circuit. Background Technology

[0002] Traditional complementary metal-oxide-semiconductor (CMOS) analog circuits are mostly implemented using custom-sized MOSFETs. The layout design of analog circuits is completed manually through placement and routing, resulting in long layout and design iteration times. When migrating analog circuits completed under custom-defined CMOS processes to other CMOS processes, the circuit needs to be rebuilt and the layout and routing completed again. Traditional analog circuits are difficult to migrate quickly between CMOS processes.

[0003] Synthesizable analog circuits refer to analog circuits implemented using digital standard cells that can be automatically generated using digital layout tools. Synthesizable analog circuits require the use of digital standard cells to replace the CMOS transistors in traditional analog circuits. During the layout generation stage, digital circuit layout generation tools can be used for automatic placement and routing, greatly improving the layout design speed. Furthermore, the differences between digital standard cells across different processes are minimal, allowing for the rapid replacement of existing circuits with similar cells during process migration, enabling the rapid migration of analog circuits between different processes.

[0004] Dynamic amplifiers are widely used in analog circuits such as pipelined analog-to-digital converters and are a common module in analog circuit design. Traditional dynamic amplifiers typically utilize the high transconductance of large-size input transistor pairs to discharge the output node in a short time, generating a differential amplified signal through the difference in discharge rate. However, dynamic amplifiers lacking common-mode detection struggle to achieve a stable common-mode output voltage. Synthesizable dynamic amplifiers use digital standard cells for their input transistor pairs. Limited by the size of these digital standard cells, the discharge rate of the output node is slow. Furthermore, the complementary MOSFETs in the digital standard cells introduce additional quiescent current, and paralleling multiple digital standard cells to achieve a larger discharge rate can lead to excessive quiescent current accumulation, negatively impacting circuit performance. Therefore, designing a high-gain, high-speed synthesizable dynamic amplifier with a stable common-mode output voltage is particularly important. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a synthesizable dynamic amplifier with a stable common-mode output voltage that is built entirely from digital standard units, and to solve the problems of low amplification gain and slow amplification speed of synthesizable amplifiers.

[0006] The present invention provides a synthesizable dynamic amplifier with a stable common-mode output voltage, comprising an input stage circuit, a common-mode detection stage circuit, and an output stage circuit; its input ports are a pair of positive and negative signal ports, an amplification clock port, and a reset clock port; its output ports are a pair of differential signal output ports; wherein:

[0007] (1) The input stage circuit consists of a pair of input units; the ports of the input units include a signal input terminal, a signal output terminal and an enable terminal; the signal input terminals of the pair of signal input units are respectively connected to the positive and negative inputs, the enable input terminals are both connected to the sampling clock, and the signal output terminals are respectively connected to the intermediate differential signal.

[0008] (2) The common-mode detection stage circuit is composed of a common-mode detection module; the ports of the common-mode detection module include a pair of signal input ports, a control signal input port and a control signal output port; its signal input ports are respectively connected to the intermediate differential signal node, the control signal input port is connected to the amplification clock, and the control signal output port is connected to the sampling clock;

[0009] (3) The output stage circuit consists of a pair of signal transmission switches, a pair of reset switches and a clock-controlled positive feedback module; the intermediate differential signal nodes are respectively connected to the differential signal output ports through the pair of signal transmission switches; the differential signal output ports are respectively connected to the reset voltage through the pair of reset switches; the pair of signal transmission switches are both controlled by the amplified clock; the pair of reset switches are both controlled by the reset clock; the clock-controlled positive feedback module has a pair of input / output ports and a control signal input port, the input / output ports are respectively connected to the intermediate differential signals, and the control signal input port is connected to the amplified clock.

[0010] The present invention provides a synthesizable dynamic amplifier with a stable common-mode output voltage. Its clocked positive feedback module operates in two modes under the control of the amplification clock. In the reset mode, the clocked positive feedback module connects the intermediate differential signal to the reset voltage. In the enable mode, the clocked positive feedback module performs a positive feedback function, causing the intermediate differential signals to compete with each other and eventually converge to logic 0 and logic 1 voltages respectively.

[0011] The present invention provides a synthesizable dynamic amplifier with a stable common-mode output voltage. Its common-mode detection module operates in two modes under the control of the amplification clock. In the reset mode, the output sampling clock is at the off level. When entering the detection mode, the output sampling clock jumps to the on level, and the intermediate differential signal approaches the threshold voltage of the logic gate from the reset voltage. When the common-mode voltage reaches the threshold voltage of the logic gate, the output sampling clock jumps to the off level.

[0012] The present invention provides a synthesizable dynamic amplifier with a stable common-mode output voltage, wherein the first input unit and the second input terminal are both controlled by a sampling clock; when a pair of input units are turned on, the positive and negative inputs are respectively transmitted to the intermediate differential signal; when a pair of input units are turned off, their outputs are both in a high-impedance state.

[0013] The present invention provides a synthesizable dynamic amplifier with a stable common-mode output voltage, the circuit of which operates in three phases;

[0014] (1) Reset phase: The reset clock is at the on level and the amplification clock is at the off level; a pair of reset switches are turned on and the amplification signal output port is connected to the reset voltage; the clock-controlled positive feedback module is in reset mode and connects the intermediate differential signal to the reset voltage.

[0015] (2) Amplification phase: The reset clock is at the off level, and the amplification clock is at the on level; the common-mode detection module is in detection mode, the clock-controlled positive feedback module is enabled, a pair of signal transmission switches are turned on, and the intermediate differential signal is connected to the output port; the amplification phase is divided into two stages. When the sampling clock is at the on level, it is the sampling stage, a pair of input units are turned on, so that the intermediate differential signal approaches the threshold voltage of the logic gate from the reset voltage; when the sampling clock is at the off level, it is the signal amplification stage, a pair of input units are turned off; the clock-controlled positive feedback module amplifies the differential voltage of the intermediate differential signal;

[0016] (3) Latch phase: Both the reset clock and the amplification clock are at the off level; the voltage at the differential signal output port remains unchanged;

[0017] The present invention provides a synthesizable dynamic amplifier with a stable common-mode output voltage. All modules in the circuit used to implement the dynamic amplifier, including the input unit, signal transmission switch, reset switch, common-mode detection module and clocked positive feedback module, are implemented by digital standard units. Attached Figure Description

[0018] Figure 1 This is a circuit diagram of a traditional MOS transistor-based dynamic amplifier.

[0019] Figure 2 This is a circuit diagram of the synthesizable dynamic amplifier with a stable common-mode output voltage according to the present invention.

[0020] Figure 3 This is an example circuit diagram of the synthesizable dynamic amplifier with a stable common-mode output voltage according to the present invention.

[0021] Figure 4 This is an example circuit diagram of the signal input unit of the improved dynamic amplifier of the present invention.

[0022] Figure 5 This is an example circuit diagram of the positive feedback module of the improved dynamic amplifier of the present invention.

[0023] Figure 6 This is an example circuit diagram of the common-mode detection module of the improved dynamic amplifier of the present invention.

[0024] Figure 7This is an example circuit diagram of the signal transmission switch for the improved dynamic amplifier of the present invention.

[0025] Figure 8 This is an example circuit diagram of the reset switch in this invention.

[0026] Figure 9 This is an example circuit diagram of the N-type reset switch in this invention.

[0027] Figure 10 The circuit diagrams are examples of inverters, NAND gates, and AND gates used in this invention. Detailed Implementation

[0028] like Figure 1 As shown, in a traditional dynamic amplifier with a stable common-mode output voltage, INP and INN are amplified input signals that control the gate terminals of input transistors M3 and M4; CLK is the enable input signal that controls the gate terminals of M1, M5, M6, and M7. When CLK is logic 0, M1 is off, M5, M6, and M7 are on, nodes VN, VP, and VX are connected to the power supply voltage, transmission gates TN and TP are on, and outputs OUTN and OUTP are charged to the power supply voltage. When CLK is 1, M1 is turned on, and M5, M6, and M7 are turned off. At this time, VX is still high voltage, and transmission gates TN and TP continue to be turned on. The load capacitor (CLP / CLN) on the output node discharges through the transmission gates TN / TP, M3 / M4, M2, and M1. VX is the common-mode voltage of VN and VP. When the common-mode voltage VX drops to half of the power supply voltage, the outputs of inverters I1 and I2 flip, transmission gates TN and TP turn off, M2 turns off, the discharge path turns off, and the outputs OUTN and OUTP remain unchanged, resulting in a stable common-mode amplified signal.

[0029] Traditional dynamic amplifiers with stable common-mode output voltage achieve higher discharge rates by manually setting large-sized input transistors M3 and M4, thereby achieving higher amplification gain and faster amplification speed. However, synthesizable dynamic amplifiers use digital standard cells for their input transistors. Due to the size limitations of digital standard cells, their discharge rates are slow, and the complementary MOSFETs of the digital standard cells introduce additional quiescent current. Parallel connection of multiple digital standard cells to achieve a higher discharge rate can lead to excessive accumulation of quiescent current, affecting circuit performance.

[0030] Figure 2 This invention provides an improved synthesizable dynamic amplifier with a stable common-mode output voltage. Figure 3 This invention provides an example circuit of a synthesizable dynamic amplifier with a stable common-mode output voltage. It includes an input stage circuit (100), a common-mode detection stage circuit (200), and an output stage circuit (300); its input ports are a pair of positive and negative signal ports (INP and INN), and its amplification clock port (Φ...).A ) and reset clock port (Φ RST Its output ports are a pair of differential signal output ports (OUTN and OUTP).

[0031] (1) The input stage circuit (100) consists of a pair of input units (C11 and C12); the ports of the input units include a signal input terminal (IN), a signal output terminal (OUT), and an enable terminal (EN); the signal input terminal (IN) of this pair of signal input units (C11 and C12) is connected to the positive and negative input terminals (INP and INN) respectively, and the enable input terminal (EN) is connected to the sampling clock (Φ). AD The signal output terminals (OUT) are connected to the intermediate differential signals (MIDN and MIDP).

[0032] (2) The common-mode detection stage circuit consists of a common-mode detection module (210); the ports of the common-mode detection module include a pair of signal input ports (TN and TP), a control signal input port (CKIN), and a control signal output port (CKOUT); its signal input ports (TN and TP) are respectively connected to the intermediate differential signal (MIDN and MIDP) nodes, and the control signal input port (CKIN) is connected to the amplified clock (Φ). A The control signal output port (CKOUT) is connected to the sampling clock (Φ). AD ).

[0033] (3) The output stage circuit consists of a pair of signal transmission switches (S21 and S22), a pair of reset switches (S31 and S32), and a clock-controlled positive feedback module (310); the intermediate differential signal (MIDN and MIDP) nodes are connected to the differential signal output ports (OUTN and OUTP) through a pair of signal transmission switches (S21 and S22); the differential signal output ports (OUTN and OUTP) are connected to the reset voltage (VRST) through a pair of reset switches (S31 and S32), where the reset voltage is the power supply voltage (VDD); both the pair of signal transmission switches (S21 and S22) are connected to the clock amplification module (Φ). A Controlled by a reset clock (Φ); a pair of reset switches (S31 and S32) are both controlled by a reset clock (Φ). RST The clock-controlled positive feedback module (310) has a pair of input / output ports (VN and VP) and a control signal input port (CKIN). Its input / output ports (VN and VP) are connected to the intermediate differential signals (MIDN and MIDP) respectively, and the control signal input port (CKIN) is connected to the amplified clock (Φ). A ).

[0034] Figure 4This is an example circuit of the clock-controlled positive feedback module of the improved dynamic amplifier of the present invention. The example circuit of the clock-controlled positive feedback module consists of a pair of inverters and a pair of 2-to-1 data selectors; the inputs of the pair of inverters are respectively connected to the outputs of the pair of data selectors, and the outputs of the inverters are respectively connected to the signal input / output ports (VN and VP) of the clock-controlled positive feedback module. One input of the data selector is connected to the signal input / output ports (VN and VP), and the other input is connected to a logic 0 level. The control terminal of the data selector is connected to the control input port (CKIN) of the clock-controlled positive feedback module; when the control input port (CKIN) is logic 0, the input / output ports (VN and VP) are logic 1; when the control input port (CKIN) is logic 1, the clock-controlled positive feedback module exhibits positive feedback function.

[0035] Figure 5 This is an example circuit for a common-mode detection module applied to an improved dynamic amplifier. The example circuit consists of two identical capacitors, a reset switch, a cascaded inverter chain, and an AND gate. One end of each capacitor is connected to the common-mode signal (VX), and the other end is connected to the input ports (VN and VP) of the common-mode detection module. The common-mode signal (VX) is connected to one input of the AND gate via the cascaded inverter, and the other input of the AND gate is connected to the amplified clock (Φ). A The output of the AND gate is the output of the common-mode detection module (Φ). AD The common-mode detection module (210) amplifies the clock (Φ). A It operates in two modes under control; in reset mode, the output sampling clock (Φ) is activated. AD When entering detection mode, the output sampling clock (Φ) is set to logic 0; AD The common-mode voltage transitions to logic 1, and the intermediate differential signals (MIDN and MIDP) approach the threshold voltage of the logic gate from the power supply voltage (VDD). When the common-mode voltage reaches the threshold voltage of the logic gate, the output sampling clock (Φ) is activated. AD (Jump to logic 0.)

[0036] Figure 6 This is an example circuit for the input unit of an improved dynamic amplifier. The input unit consists of a NAND gate and a signal transmission switch. One input of the NAND gate is connected to the signal input (IN) of the input unit, and the other input of the NAND gate, together with the control terminal of the signal transmission switch, is connected to the enable input (EN) of the input unit. The output of the NAND gate is connected to the signal output (OUT) of the input unit through the signal transmission switch. When the enable input (EN) is logic 1, the output of the NAND gate is connected to the signal output (OUT) through the signal transmission switch; when the enable input (EN) is logic 0, the signal transmission switch is turned off, and the signal output (OUT) is in a high-impedance state.

[0037] Figure 7 This is an example circuit for the signal transmission switch applied to the improved dynamic amplifier. The example circuit is a synthesizable bootstrap switch circuit implemented with digital standard cells, consisting of four inverters, one bootstrap capacitor, one reset switch, and three N-type reset switches. Since the bootstrap switch is existing technology and not included in the improvements of this invention, it will not be described in detail here.

[0038] The dynamic amplifier operates in three phases:

[0039] (1) Reset phase: Reset clock (Φ RST ) is logic 1, amplifying the clock (Φ) A The logic is 0; a pair of reset switches (S31 and S32) are turned on, and the amplified signal output ports (OUTN and OUTP) are connected to the power supply voltage (VDD); the clocked positive feedback module (310) is in reset mode, and the intermediate differential signals (MIDN and MIDP) are connected to the power supply voltage (VDD).

[0040] (2) Amplified phase: Reset clock (Φ RST ) is logic 0, amplify clock (Φ) A ) is logic 1; the common-mode detection module (210) is in detection mode, the clocked positive feedback module (310) is enabled, a pair of signal transmission switches (S21 and S22) are turned on, and the intermediate differential signals (MIDN and MIDP) are connected to the output ports (OUTN and OUTP); the amplification phase is divided into two stages, when the sampling clock (Φ AD When the input clock is 1, it is the sampling phase. A pair of input cells (C11 and C12) are turned on, causing the intermediate differential signals (MIDN and MIDP) to approach the threshold voltage of the logic gate from the power supply voltage (VDD); when the sampling clock (Φ) is 1, the sampling phase begins. AD When the logic value is 0, it is the signal amplification stage, and a pair of input units (C11 and C12) are turned off; the clocked positive feedback module (310) amplifies the differential voltage of the intermediate differential signals (MIDN and MIDP);

[0041] (3) Latch phase: Reset clock (Φ RST ) and amplified clock (Φ A All values ​​are logic 0; the voltages at the differential signal output ports (OUTN and OUTP) remain unchanged.

[0042] Figure 8 This is an example circuit for the reset switch used. Figure 9 This is an example circuit for using an N-type reset switch. Figure 10 Examples of inverters, NAND gates, and AND gates are shown below. The capacitors used in this scheme are digital standard decoupling capacitor units, and all circuit modules are implemented using digital standard units.

[0043] The above embodiments are only for illustrating the technical concept and features of the present invention. The positive feedback module, common-mode detection module, signal transmission switch, reset switch, and N-type reset switch can all be implemented using other circuit structures to achieve the same function. The purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly, and should not be construed as limiting the scope of protection of the present invention. All modifications made according to the spirit and essence of the main technical solution of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A synthesizable dynamic amplifier with stable common mode output voltage, characterized by, The application relates to a differential amplifier circuit, which comprises an input stage circuit (100), a common mode detection stage circuit (200) and an output stage circuit (300); the input ports of the differential amplifier circuit are a pair of positive and negative signal ports (INP and INN), an amplification clock port (Phi A ) and a reset clock port (Phi RST ); the output ports of the differential amplifier circuit are a pair of differential signal output ports (OUTN and OUTP); wherein: (1) the input stage circuit (100) is composed of a pair of input units (C11 and C12); the port of the input unit includes a signal input end (IN), a signal output end (OUT) and an enable end (EN); the signal input ends (IN) of the pair of signal input units (C11 and C12) are connected with positive and negative inputs (INP and INN) respectively, the enable input ends (EN) are connected with sampling clock (Φ AD ) respectively, and the signal output ends (OUT) are connected to intermediate differential signals (MIDN and MIDP) respectively; (2) the common mode detection stage circuit, composed of a common mode detection module (210); the port of common mode detection module (210) includes a pair of signal input port (TN and TP), a control signal input port (CKIN) and a control signal output port (CKOUT); its signal input port (TN and TP) is connected to the intermediate differential signal (MIDN and MIDP) node respectively, control signal input port (CKIN) connects the amplification clock (Φ A ), control signal output port (CKOUT) connects sampling clock (Φ AD ); (3) the output stage circuit, by a pair of signal transmission switch (S21 and S22), a pair of reset switch (S31 and S32) and clocked positive feedback module (310) is composed of;Intermediate differential signal (MIDN and MIDP) node is connected to the differential signal output port (OUTN and OUTP) through a pair of signal transmission switch (S21 and S22) respectively;Differential signal output port (OUTN and OUTP) is connected to reset voltage (VRST) through a pair of reset switch (S31 and S32) respectively;A pair of signal transmission switch (S21 and S22) is controlled by amplification clock (Φ A );A pair of reset switch (S31 and S32) is controlled by reset clock (Φ RST );Clocked positive feedback module (310) has a pair of input and output port (VN and VP) and a control signal input port (CKIN), its input and output port (VN and VP) is connected intermediate differential signal (MIDN and MIDP) respectively, control signal input port (CKIN) connects amplification clock (Φ A ).

2. The scalable dynamic amplifier with stable common mode output voltage of claim 1, wherein, The clocked positive feedback module (310) works in two modes under the control of an amplification clock (Φ A ); in a reset mode, the clocked positive feedback module (310) connects the intermediate differential signals (MIDN and MIDP) to a reset voltage (VRST); in an enable mode, the clocked positive feedback module (310) behaves as a positive feedback function, causing the intermediate differential signals (MIDN and MIDP) to compete with each other, and finally converge to a logic 0 and a logic 1 voltage, respectively.

3. The scalable dynamic amplifier with stable common mode output voltage of claim 1, wherein, The common mode detection module (210) works in two modes under the control of the amplified clock (Φ A ); in the reset mode, the output sampling clock (Φ AD ) is off; in the detection mode, the output sampling clock (Φ AD ) jumps to the on level, and the intermediate differential signal (MIDN and MIDP) is close to the threshold voltage of the logic gate from the reset voltage (VRST); when the common mode voltage reaches the threshold voltage of the logic gate, the output sampling clock (Φ AD ) jumps to the off level.

4. The scalable dynamic amplifier with stable common mode output voltage of claim 1, wherein, The first input unit (C11) and the second input unit (C12) are both controlled by a sampling clock (Φ AD ); when a pair of input units (C11 and C12) are turned on, the positive and negative inputs (INP and INN) are transmitted to the intermediate differential signals (MIDN and MIDP) respectively; when a pair of input units (C11 and C12) are turned off, the outputs of both are in high resistance state.

5. The scalable dynamic amplifier with stable common mode output voltage of claim 1, wherein, The dynamic amplifier works in three phases; (1) Reset phase: the reset clock (Φ RST ) is at the on level, and the amplification clock (Φ A ) is at the off level; A pair of reset switches (S31 and S32) are turned on, and the output ports of the amplified signal (OUTN and OUTP) are connected to the reset voltage (VRST); the clocked positive feedback module (310) is in the reset mode, and the intermediate differential signal (MIDN and MIDP) is connected to the reset voltage (VRST); (2) amplification phase: the reset clock (Φ RST ) is off level, the amplification clock (Φ A ) is on level; the common mode detection module (210) is in detection mode, the clocked positive feedback module (310) is enabled, a pair of signal transmission switches (S21 and S22) are on, and the intermediate differential signals (MIDN and MIDP) are connected to the output ports (OUTN and OUTP); the amplification phase is divided into two stages, when the sampling clock (Φ AD ) is on level, it is the sampling stage, a pair of input units (C11 and C12) are on, so that the intermediate differential signals (MIDN and MIDP) approach the threshold voltage of the logic gate from the reset voltage (VRST); when the sampling clock (Φ AD ) is off level, it is the signal amplification stage, a pair of input units (C11 and C12) are off; the clocked positive feedback module (310) amplifies the differential mode voltage of the intermediate differential signals (MIDN and MIDP); (3) Latch phase: Reset clock (ΦRST) and amplification clock (Φ A All are at the off level; the voltages of the differential signal output ports (OUTN and OUTP) remain unchanged.

6. The scalable dynamic amplifier with stable common mode output voltage of claim 1, wherein, All modules for implementing the dynamic amplifier, including the input unit (C11 and C12), the signal transmission switch (S21 and S22), the reset switch (S31 and S32), the common mode detection module (210) and the clocked positive feedback module (310) are realized by digital standard cells.

7. The scalable dynamic amplifier with stable common mode output voltage of claim 1, wherein, The clocked positive feedback module is composed of a pair of inverters and a pair of two-input data selectors; the inputs of the pair of inverters are connected to the outputs of the pair of data selectors, respectively, and the outputs of the inverters are connected to the signal input / output ports (VN and VP) of the clocked positive feedback module, respectively; one input of the data selector is connected to the signal input / output ports (VN and VP), respectively, and the other input is connected to the logic 0 level; the control end of the data selector is connected to the control input port (CKIN) of the clocked positive feedback module; when the control input port (CKIN) is logic 0, the input / output ports (VN and VP) are logic 1; when the control input port (CKIN) is logic 1, the clocked positive feedback module exhibits a positive feedback function.

8. The scalable dynamic amplifier with stable common mode output voltage of claim 1, wherein, The common mode detection module is composed of two identical capacitors, a reset switch, a chain of cascaded inverters and an AND gate; one end of the two capacitors is connected to a common mode signal (VX), and the other end is connected to the input port (VN and VP) of the common mode detection module; the common mode signal (VX) is connected to one input end of the AND gate through the chain of cascaded inverters, and the other input end of the AND gate is connected to an amplified clock (Φ A ); the output of the AND gate is the output (Φ AD ) of the common mode detection module; the common mode detection module (210) works in two modes under the control of the amplified clock (Φ A ); in the reset mode, the output sampling clock (Φ AD ) is logic 0; when entering the detection mode, the output sampling clock (Φ AD ) jumps to logic 1, and the intermediate differential signal (MIDN and MIDP) is close to the threshold voltage of the logic gate from the power supply voltage (VDD), when the common mode voltage reaches the threshold voltage of the logic gate, the output sampling clock (Φ AD ) jumps to logic 0.

9. The scalable dynamic amplifier with stable common mode output voltage of claim 1, wherein, The input unit is composed of a NAND gate and a signal transmission switch; one input end of the NAND gate is connected to the signal input end (IN) of the input unit, and the other input end of the NAND gate is connected to the enable input end (EN) of the input unit together with the control end of the signal transmission switch; the output end of the NAND gate is connected to the signal output end (OUT) of the input unit through the signal transmission switch; when the enable input end (EN) is logic 1, the output of the NAND gate is connected to the signal output end (OUT) through the signal transmission switch; when the enable input end (EN) is logic 0, the signal transmission switch is turned off, and the signal output end (OUT) is in a high resistance state.

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