A floating switch drive circuit and method
By combining a reference voltage unit and a bootstrap unit, a suitable gate drive voltage is generated, which solves the problem of complex gate drive circuit design for floating switches and achieves accurate control and stability of floating switches.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- UNIV OF MACAU
- Filing Date
- 2021-10-29
- Publication Date
- 2026-06-02
Smart Images
Figure CN114465612B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of circuit control, and in particular to a floating switch driving circuit and method. Background Technology
[0002] Floating switches come in two different types: N-type metal-oxide-semiconductor (NMOS) transistors and P-type metal-oxide-semiconductor (PMOS) transistors. Floating switches are commonly used in the power transfer stage of some power converters to connect different power components in switching mode.
[0003] A key characteristic of floating switches is the dynamic change in the relative magnitudes of the voltages across the source and drain of the MOSFET; that is, low and high voltages alternate across the floating switch. To achieve accurate on / off control of the floating switch, it is necessary to accurately determine the potential levels across the switch and provide a suitable gate drive voltage based on these levels. However, the dynamic changes in the potential across the floating switch make the design of its gate drive circuit complex and difficult.
[0004] Existing technologies use a dual-branch architecture to detect the high or low voltage across the floating switch in order to generate a suitable driving voltage, but this has the disadvantage of complex structure and the limitation of having to use a dual-branch structure. Summary of the Invention
[0005] To address the aforementioned technical problems, this invention provides a floating switch driving circuit and method, the specific solution of which is as follows:
[0006] In a first aspect, embodiments of this application provide a floating switch driving circuit, the circuit including a reference voltage unit, a timing control unit, a bootstrap unit, and a driving voltage control unit;
[0007] One end of the reference voltage unit is used to connect to either the source or the drain of the floating switch, and the other end of the reference voltage unit is connected to the drive voltage control unit. The reference voltage unit is used to take the voltage of the source or the drain of the floating switch connected to the reference voltage unit as a reference voltage and output it to the drive voltage control unit.
[0008] The bootstrap unit is connected to the timing control unit and the drive voltage control unit respectively. The bootstrap unit outputs a corresponding bootstrap voltage to the drive voltage control unit according to different control signals output by the timing control unit.
[0009] The drive voltage control unit is connected to the gate of the floating switch. The drive voltage control unit includes a turn-on subunit and a turn-off subunit. The turn-on subunit includes four cross-coupled MOS transistors. The turn-on subunit is used to control the turn-on or turn-off of different MOS transistors according to the reference voltage and the bootstrap voltage to generate a corresponding turn-on voltage to turn on the floating switch. The turn-off subunit is connected to the timing control unit. The turn-off subunit is used to turn on according to the control signal to generate a corresponding turn-off voltage to turn off the floating switch.
[0010] According to a specific embodiment disclosed in this application, the floating switch is a PMOS transistor, and the conduction subunit includes a first PMOS transistor and a first NMOS transistor connected via a first node, and a second PMOS transistor and a second NMOS transistor connected via a second node.
[0011] The gates of the first PMOS transistor and the first NMOS transistor are connected to the second node, and the gates of the second PMOS transistor and the second NMOS transistor are connected to the first node.
[0012] The source of the first PMOS transistor and the source of the second PMOS transistor are connected to the output terminal of the reference voltage unit through a third node, and the drain of the first NMOS transistor and the drain of the second NMOS transistor are connected to the turn-off sub-unit through a fourth node.
[0013] The turn-on subunit or the turn-off subunit outputs the corresponding turn-on voltage or turn-off voltage to the floating switch through the fourth node, so that the floating switch is turned on or off.
[0014] According to a specific embodiment disclosed in this application, the circuit further includes a signal generation unit, and the bootstrap unit includes a first branch and a second branch;
[0015] The first branch includes a first capacitor and a third PMOS transistor and a third NMOS transistor connected via a fifth node; the second branch includes a second capacitor and a fourth PMOS transistor and a fourth NMOS transistor connected via a sixth node.
[0016] The source of the third PMOS transistor and the source of the fourth PMOS transistor are used to receive the first voltage output by the signal generating unit, and the source of the third NMOS transistor and the source of the fourth NMOS transistor are used to receive the second voltage of the signal generating unit.
[0017] The gates of the third PMOS transistor, the third NMOS transistor, the fourth PMOS transistor, and the fourth NMOS transistor are connected to the output terminal of the timing control unit;
[0018] The upper plate of the first capacitor is connected to the first node, the lower plate of the first capacitor is connected to the fifth node, the upper plate of the second capacitor is connected to the second node, and the lower plate of the second capacitor is connected to the sixth node.
[0019] According to a specific embodiment disclosed in this application, the shutdown subunit includes a fifth PMOS transistor;
[0020] The gate of the fifth PMOS transistor is connected to the output terminal of the timing control unit, and the source of the fifth PMOS transistor is used to receive the third voltage output by the signal generation unit, wherein the third voltage is greater than or equal to the first voltage.
[0021] According to a specific embodiment disclosed in this application, the floating switch is an NMOS transistor, and the conducting sub-unit includes a sixth PMOS transistor and a sixth NMOS transistor connected via a seventh node, and a seventh PMOS transistor and a seventh NMOS transistor connected via an eighth node;
[0022] The gates of the sixth PMOS transistor and the sixth NMOS transistor are connected to the seventh node, and the gates of the seventh PMOS transistor and the seventh NMOS transistor are connected to the eighth node.
[0023] The source of the sixth NMOS transistor and the source of the seventh NMOS transistor are connected to the output terminal of the reference voltage unit through the ninth node, and the drain of the sixth PMOS transistor and the drain of the sixth PMOS transistor are connected to the turn-off sub-unit through the tenth node.
[0024] The turn-on subunit or the turn-off subunit outputs the corresponding turn-on voltage or turn-off voltage to the floating switch through the tenth node, so that the floating switch is turned on or off.
[0025] According to a specific embodiment disclosed in this application, the circuit further includes a signal generation unit, and the bootstrap unit includes a third branch and a fourth branch;
[0026] The third branch includes a third capacitor and an eighth PMOS transistor and an eighth NMOS transistor connected via an eleventh node; the fourth branch includes a fourth capacitor and a ninth PMOS transistor and a ninth NMOS transistor connected via a twelfth node.
[0027] The source of the eighth PMOS transistor and the source of the ninth PMOS transistor are used to receive the first voltage output by the signal generating unit, and the source of the eighth NMOS transistor and the source of the eighth NMOS transistor are used to receive the second voltage of the signal generating unit.
[0028] The gates of the eighth PMOS transistor, the eighth NMOS transistor, the ninth PMOS transistor, and the ninth NMOS transistor are connected to the output terminal of the timing control unit;
[0029] The upper plate of the third capacitor is connected to the seventh node, the lower plate of the fourth capacitor is connected to the eleventh node, the upper plate of the fourth capacitor is connected to the eighth node, and the lower plate of the fourth capacitor is connected to the twelfth node.
[0030] According to a specific embodiment disclosed in this application, the shutdown subunit includes a tenth NMOS transistor;
[0031] The gate of the tenth NMOS transistor is connected to the output terminal of the timing control unit, and the source of the tenth NMOS transistor is used to receive the second voltage output by the signal generation unit.
[0032] In a second aspect, embodiments of this application provide a floating switch driving method, wherein the floating switch driving method is applied to the floating switch driving circuit described in any embodiment of the first aspect, the method comprising:
[0033] The reference voltage unit takes the voltage of the source or drain connected to the reference voltage unit in the floating switch as the reference voltage and outputs it to the drive voltage control unit.
[0034] The bootstrap unit outputs a corresponding bootstrap voltage to the drive voltage control unit based on the different control signals output by the timing control unit.
[0035] The turn-on subunit controls the turn-on or turn-off of different MOS transistors according to the reference voltage and the bootstrap voltage, and generates a corresponding drive voltage and outputs it to the floating switch to turn on the floating switch. The turn-off subunit turns on according to the control signal, generates a corresponding drive voltage and outputs it to the floating switch to turn off the floating switch.
[0036] According to a specific embodiment disclosed in this application, the floating switch driving method is applied to the floating switch driving circuit described in the first aspect, wherein the switching period of the timing control unit includes a turn-on period and a turn-off period, the turn-on voltage is a first turn-on sub-voltage, the turn-off voltage is a first turn-off sub-voltage, and the method includes:
[0037] During the conduction period, the timing control unit outputs a first conduction control signal or a second conduction control signal to turn on the conduction subunit and generate a first conduction sub-voltage to turn on the floating switch. The magnitude of the first conduction sub-voltage is the difference between the reference voltage and the first voltage.
[0038] During the shutdown period, the timing control unit outputs a first shutdown control signal to control the third PMOS transistor, the third NMOS transistor, the fourth PMOS transistor, and the fourth NMOS transistor to turn off, while the fifth PMOS transistor turns on, so that all MOS transistors in the turn-on sub-unit turn off, and the shutdown sub-unit turns on, generating a first shutdown sub-voltage to turn off the floating switch, wherein the magnitude of the first shutdown sub-voltage is equal to that of the third voltage.
[0039] According to a specific embodiment disclosed in this application, the conduction period includes a first period and a second period, and the conversion order of the switching period is the first period, the shutdown period, and the second period in sequence. The method includes:
[0040] During the first cycle, the timing control unit outputs a first turn-on control signal to control the third NMOS transistor and the fourth PMOS transistor to turn on, and the third PMOS transistor, the fourth NMOS transistor, and the fifth PMOS transistor to turn off, so that the first NMOS transistor and the second PMOS transistor turn on, generating the first turn-on sub-voltage to turn on the floating switch. The second capacitor is charged during the first cycle, and the magnitude of the corresponding first charging voltage is the difference between the reference voltage and the first voltage.
[0041] During the second cycle, the timing control unit outputs a second turn-on control signal to control the third PMOS transistor and the fourth NMOS transistor to turn on, and the third NMOS transistor, the fourth PMOS transistor, and the fifth PMOS transistor to turn off, so that the first PMOS transistor and the second NMOS transistor turn on, generating the first turn-on sub-voltage to turn on the floating switch. The first capacitor is charged during the second cycle, and the magnitude of the corresponding second charging voltage is the difference between the reference voltage and the first voltage.
[0042] According to a specific embodiment disclosed in this application, the floating switch driving method is applied to the floating switch driving circuit described in the first aspect, wherein the switching period of the timing control unit includes a turn-on period and a turn-off period, the turn-on voltage is a second turn-on sub-voltage, the turn-off voltage is a second turn-off sub-voltage, and the method includes:
[0043] During the conduction cycle, the timing control unit outputs a third conduction control signal or a fourth conduction control signal to turn on the conduction subunit, generating the second conduction sub-voltage to turn on the floating switch, wherein the magnitude of the second conduction sub-voltage is the sum of the reference voltage and the first voltage;
[0044] During the shutdown period, the timing control unit outputs a first shutdown control signal to control the eighth PMOS transistor, the eighth NMOS transistor, the ninth PMOS transistor, and the ninth NMOS transistor to turn off, while the tenth NMOS transistor turns on, so that all MOS transistors in the turn-on sub-unit turn off, and the shutdown sub-unit turns on, generating a second shutdown sub-voltage to turn off the floating switch, wherein the second shutdown sub-voltage is equal in magnitude to the second voltage.
[0045] According to a specific embodiment disclosed in this application, the conduction cycle includes a third cycle and a fourth cycle, and the conversion sequence of the switching cycle is the third cycle, the shutdown cycle, and the fourth cycle in sequence. The method includes:
[0046] During the third cycle, the timing control unit outputs a third turn-on control signal to turn on the eighth PMOS transistor and the ninth NMOS transistor, and turn off the eighth NMOS transistor, the ninth PMOS transistor, and the tenth NMOS transistor, so that the sixth PMOS transistor and the seventh NMOS transistor are turned on, generating the second turn-on sub-voltage to turn on the floating switch. The fourth capacitor is charged during the third cycle, and the corresponding third charging voltage is equal to the magnitude of the reference voltage.
[0047] During the fourth cycle, the timing control unit outputs a fourth turn-on control signal to turn on the eighth NMOS transistor and the ninth PMOS transistor, and turns off the eighth PMOS transistor, the ninth NMOS transistor, and the tenth NMOS transistor, so that the sixth NMOS transistor and the seventh PMOS transistor turn on, generating the second turn-on sub-voltage to turn on the floating switch. The third capacitor is charged during the fourth cycle, and the corresponding fourth charging voltage is equal to the magnitude of the reference voltage.
[0048] Compared with the prior art, this application has the following beneficial effects:
[0049] The floating switch driving circuit provided in this application includes a reference voltage unit, a timing control unit, a bootstrap unit, and a drive voltage control unit. One end of the reference voltage unit is connected to the source of the floating switch, and the other end is connected to the drive voltage control unit. The bootstrap unit is connected to both the timing control unit and the drive voltage control unit. The drive voltage control unit is connected to the gate of the floating switch and includes a turn-on subunit and a turn-off subunit. The turn-on subunit includes four cross-coupled MOSFETs. The floating switch driving circuit in this application uses the source voltage of the floating switch as a reference voltage to provide a suitable gate drive voltage for the floating switch, accurately realizing the turn-on and turn-off control of the floating switch. Attached Figure Description
[0050] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope of protection of the present invention. In the various drawings, similar components are numbered similarly.
[0051] Figure 1 This application provides a schematic diagram of the structure of a PMOS floating switch according to an embodiment of the present application.
[0052] Figure 2 A schematic diagram of a floating switch driving circuit provided in an embodiment of this application;
[0053] Figure 3 This is one of the structural schematic diagrams of a floating switch driving circuit provided in an embodiment of this application;
[0054] Figure 4 One of the schematic diagrams of a timing control unit involved in a floating switch driving circuit provided in an embodiment of this application;
[0055] Figure 5(a) is one of the schematic diagrams of the conduction state of the PMOS tube floating switch in a floating switch driving circuit provided in an embodiment of this application;
[0056] Figure 5(b) is one of the schematic diagrams of the PMOS tube floating switch off state in a floating switch driving circuit provided in an embodiment of this application;
[0057] Figure 5(c) is one of the schematic diagrams of the conduction state of the PMOS tube floating switch in a floating switch driving circuit provided in an embodiment of this application;
[0058] Figure 6 A flowchart illustrating a floating switch driving method provided in an embodiment of this application;
[0059] Figure 7 This application provides a schematic diagram of the structure of an NMOS transistor floating switch according to an embodiment of the present application.
[0060] Figure 8 This is a second schematic diagram of a floating switch driving circuit provided in an embodiment of this application;
[0061] Figure 9 A second schematic diagram of the timing control unit involved in a floating switch driving circuit provided in an embodiment of this application;
[0062] Figure 10(a) is one of the schematic diagrams of the NMOS tube floating switch conduction state involved in a floating switch driving circuit provided in an embodiment of this application;
[0063] Figure 10(b) is one of the schematic diagrams of the NMOS transistor floating switch off state in a floating switch driving circuit provided in an embodiment of this application;
[0064] Figure 10(c) is one of the schematic diagrams of the NMOS tube floating switch conduction state involved in a floating switch driving circuit provided in an embodiment of this application. Detailed Implementation
[0065] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.
[0066] The components of the embodiments of the invention described and illustrated herein can typically be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.
[0067] In the following, the terms “comprising,” “having,” and their cognates, which may be used in various embodiments of the invention, are intended only to indicate a particular feature, number, step, operation, element, component, or combination thereof, and should not be construed as excluding, firstly, the presence of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, or adding the possibility of one or more features, numbers, steps, operations, elements, components, or combinations thereof.
[0068] Furthermore, the terms "first," "second," and "third" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.
[0069] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of the invention pertain. Terms (such as those defined in commonly used dictionaries) shall be interpreted as having the same meaning as in their contextual meaning in the relevant technical field and shall not be interpreted as having an idealized or overly formal meaning, unless clearly defined in the various embodiments of the invention.
[0070] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.
[0071] Example 1
[0072] See Figure 1 , Figure 1 This is a schematic diagram of a PMOS floating switch M1 provided in an embodiment of this application. Floating switches are typically MOS transistors and are commonly used in the power transmission stage of power converters to connect different power components in switching mode. A key characteristic is that the relative magnitudes of the source and drain voltages of the floating switch dynamically change. Generally, the turn-on and turn-off of a MOS transistor are controlled by controlling the voltage between its gate and source. For a PMOS transistor, a gate-source voltage Ugs < 0 indicates turn-on, and a gate-source voltage Ugs ≥ 0 indicates turn-off. However, because dynamic high and low potential changes easily occur across the source and drain of a floating switch—that is, alternating low and high voltages across the switch—the voltage between the gate and source is difficult to control. To accurately control the turn-on and turn-off of the floating switch, it is necessary to clearly determine the potential levels across the floating switch and use this as a reference voltage to provide a suitable gate drive voltage for the floating switch.
[0073] To address the aforementioned technical problems, this application provides a driving circuit for a floating switch corresponding to a PMOS transistor. See also... Figure 2 , Figure 2 This is a schematic diagram of a floating switch driving circuit provided in an embodiment of this application. The floating switch driving circuit 20 includes a reference voltage unit 21, a timing control unit 22, a bootstrap unit 23, and a drive voltage control unit 24. One end of the reference voltage unit 21 is connected to either the source or drain of the floating switch, and the other end of the reference voltage unit 21 is connected to the drive voltage control unit 24. The bootstrap unit 23 is connected to both the timing control unit 22 and the drive voltage control unit 24. The drive voltage control unit 24 is connected to the gate of the floating switch. In a specific implementation, the floating switch driving circuit 20 further includes a signal generation unit 25, which is connected to both the bootstrap unit 23 and the drive voltage control unit 24.
[0074] In this application, the reference voltage unit 21 is used to take the source or drain voltage of the floating switch connected to the reference voltage unit as the reference voltage VBASE and output it to the drive voltage control unit 24. In specific implementations, the reference voltage unit 21 is not limited to a specific circuit structure, and may also refer to an interface or node connected to the source or drain of the floating switch, etc., which is not specifically limited here.
[0075] The following criteria are required to determine the source and drain of a MOSFET:
[0076] For a PMOS transistor, the terminal with the higher voltage is the source.
[0077] For an NMOS transistor, the terminal with the lower voltage is the source.
[0078] The source and drain of a floating switch change with the voltage across them. This application uses the voltage of the source or drain connected to the reference voltage unit in the floating switch as the reference voltage. Therefore, regardless of how the voltage across the floating switch changes, the gate voltage of the floating switch can be controlled by generating a drive voltage from the reference voltage.
[0079] The bootstrap unit 23 outputs a corresponding bootstrap voltage to the drive voltage control unit 24 according to different control signals output by the timing control unit 22. The drive voltage control unit 24 includes a turn-on subunit and a turn-off subunit. The turn-on subunit includes four cross-coupled MOSFETs. The turn-on subunit controls the turn-on or turn-off of different MOSFETs according to the reference voltage VBASE and the bootstrap voltage to generate a corresponding turn-on voltage to turn on the floating switch. The turn-off subunit is connected to the timing control unit 22 and is turned on according to the control signal to generate a corresponding turn-off voltage to turn off the floating switch. The signal generation unit 25 outputs different voltages: a first voltage VDD, a second voltage (GND, the ground voltage), and a third voltage VIN, where the first voltage VDD is less than the third voltage VIN.
[0080] See Figure 3 , Figure 3 This is one of the structural schematic diagrams of a floating switch driving circuit provided in an embodiment of this application. The turn-on subunit includes a first PMOS transistor MP1 and a first NMOS transistor MN1 connected via a first node X1, and a second PMOS transistor MP2 and a second NMOS transistor MN2 connected via a second node X2; the gates of the first PMOS transistor MP1 and the first NMOS transistor MN1 are connected to the second node X2, and the gates of the second PMOS transistor MP2 and the second NMOS transistor MN2 are connected to the first node X1; the sources of the first PMOS transistor MP1 and the second PMOS transistor MP2 are connected to the output terminal of the reference voltage unit 21 via a third node X3, and the drains of the first NMOS transistor MN1 and the second NMOS transistor MN2 are connected to the turn-off subunit via a fourth node X4.
[0081] The bootstrap unit 23 includes a first branch and a second branch. The first branch includes a first capacitor CA and a third PMOS transistor MP3 and a third NMOS transistor MN3 connected via a fifth node X5. The second branch includes a second capacitor CB and a fourth PMOS transistor MP4 and a fourth NMOS transistor MN4 connected via a sixth node X6. The sources of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are used to receive a first voltage VDD output by the signal generation unit 25, and the sources of the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are used to receive a second voltage GND from the signal generation unit 25. The gates of the third PMOS transistor MN4, the third NMOS transistor MN3, the fourth PMOS transistor MP4, and the fourth NMOS transistor MN4 are connected to the output terminal of the timing control unit 22. The upper plate of the first capacitor CA is connected to the first node X1, and the lower plate of the first capacitor CA is connected to the fifth node X5. The upper plate of the second capacitor CB is connected to the second node X2, and the lower plate of the second capacitor CB is connected to the sixth node X6.
[0082] The shutdown sub-unit includes a fifth PMOS transistor MP5. The gate of the fifth PMOS transistor MP5 is connected to the output terminal of the timing control unit 22, and the source of the fifth PMOS transistor MP5 is used to receive the third voltage VIN output by the signal generation unit 25.
[0083] In practical implementation, different control signals output by the timing control unit 22 can control the on / off state of different MOSFETs, generating corresponding on-state or off-state voltages, which are then output to the gate of the floating switch to turn the floating switch on or off. (See also...) Figure 4 , Figure 4 This is one of the schematic diagrams of a timing control unit involved in a floating switch driving circuit provided in an embodiment of this application. The timing control unit 22 can output different control signals: a turn-on control signal, a first turn-off control signal, and a disable control signal. The turn-on control signal is divided into a first turn-on control signal and a second turn-on control signal used to control the on / off states of different MOS transistors. Different control signals include different combinations of sub-signals, such as AP being 1 and AN being 0, etc. Specific combinations are shown in Table 1.
[0084] Table 1
[0085]
[0086] Wherein, EN is the enable signal for the floating switch drive circuit, SON is the turn-on / turn-off signal, AP is the turn-on / turn-off signal for the third PMOS transistor MP3, AN is the turn-on / turn-off signal for the third NMOS transistor MN3, BP is the turn-on / turn-off signal for the fourth PMOS transistor MP4, BN is the turn-on / turn-off signal for the fourth NMOS transistor MN4, and SOFFP is the turn-on / turn-off signal for the fifth PMOS transistor MP5.
[0087] Figures 5(a), 5(b), and 5(c) are schematic diagrams of the PMOS transistor floating switch in the on-state, the off-state, and the on-state of the PMOS transistor floating switch in the floating switch driving circuit provided in this application, respectively. The different driving control methods of the floating switch driving circuit are described below based on Table 1, Figures 5(a), 5(b), and 5(c).
[0088] 1. The first type of drive control mode corresponds to the first conduction control signal. Under this type of drive control mode, the sub-signals included in the input first conduction control signal are: EN is 1, SON is 1, SOFFP is 1, AP is 1, AN is 1, BP is 0, and BN is 0.
[0089] For PMOS transistors, conduction occurs when the gate-source voltage Ugs < 0, and turn-off occurs when the gate-source voltage Ugs ≥ 0. Taking the third PMOS transistor MP3 as an example: at this time, AP is 1, meaning the gate voltage is high, and the source receives the first voltage VDD output by the signal generation unit 25. Therefore, the gate-source voltage of the third PMOS transistor MP3 is greater than 0, satisfying the turn-off condition. The judgment of conduction and turn-off for other MOS transistors is similar, and will not be elaborated here. At this time, the first conduction control signal causes the fourth PMOS transistor MP4 and the third NMOS transistor MN3 in the bootstrap unit 23 and the turn-off sub-unit to conduct, while the third PMOS transistor MP3, the fourth NMOS transistor MN4, and the fifth PMOS transistor MP5 are turned off. It should be noted that in this application, the high potential of any sub-signal included in each control signal is greater than the first voltage VDD, but less than the third voltage VIN, and the low potential of any sub-signal is less than the first voltage VDD.
[0090] As shown in Figure 5(a), at this time, the lower plate of the first capacitor CA is grounded, the source voltage of the second PMOS transistor MP2 at the first node X1 is the reference voltage VBASE, and its gate voltage is VBASE-VDD. The gate voltage of the second PMOS transistor MP2 is lower than its source voltage, so the second PMOS transistor MP2 is turned on. After the second PMOS transistor MP2 is turned on, it pulls the gate voltage of the first NMOS transistor MN1 at the second node X2 to the reference voltage VBASE, which is higher than its source voltage at the first node X1, so the first NMOS transistor MN1 is turned on. The gate voltage of the first PMOS transistor MP1 is equal to its source voltage, and the gate voltage of the second NMOS transistor MN2 is less than its source voltage, so both the first PMOS transistor MP1 and the second NMOS transistor MN2 are turned off. In this state, the lower plate of the second capacitor CB is connected to VDD, and the upper plate is connected to the reference voltage VBASE. The second capacitor CB is charged, and the corresponding first charging voltage is VBASE-VDD. Meanwhile, the lower plate of the first capacitor CA is grounded, and the upper plate is connected to the output terminal, so the first capacitor CA is discharged. Since the first NMOS transistor MN1 is turned on, the drive voltage output by the drive voltage control unit 24 is VDRVP = VBASE - VDD. At this time, the drive voltage VDRVP is the turn-on voltage, which can be defined as the first turn-on sub-voltage in this state.
[0091] In specific implementation, the working cycle corresponding to the first type of drive control method can be defined as the first cycle. During the entire first cycle, the drive voltage VDRVP is output to the gate of the floating switch. The gate voltage of the floating switch is VBASE-VDD, and its source voltage is the reference voltage VBASE. The floating switch is turned on, and this on state is driven by the first capacitor CA.
[0092] 2. The second type of drive control mode corresponds to the first turn-off control signal. In this type of drive control mode, the input first turn-off control signal includes the following sub-signals: EN = 1, SON = 0, SOFFP = 0, AP = 1, AN = 0, BP = 1, and BN = 0, which turns on the fifth PMOS transistor MP5 and turns off the other MOS transistors. At this time, the upper and lower plates of the first capacitor CA and the second capacitor CB are in a floating state to minimize charge leakage. The output drive voltage VDRVP of the drive voltage control unit 24 is the turn-off voltage, which can be defined as the first turn-off sub-voltage in this state. The first turn-off sub-voltage is equal in magnitude to the third voltage VIN received by the source of the fifth PMOS transistor MP5.
[0093] In practical implementation, the working cycle corresponding to the second type of drive control method can be defined as the turn-off cycle. Throughout the entire turn-off cycle, the floating switch remains off regardless of how the voltage across the floating switch dynamically changes.
[0094] 3. The third type of drive control corresponds to the second conduction control signal. In this type of drive control, the input second conduction control signal includes the following sub-signals: EN = 1, SON = 1, SOFFP = 1, AP = 0, AN = 0, BP = 1, and BN = 1. This causes the third PMOS transistor MP3 and the fourth NMOS transistor MN4 to conduct, and the fourth PMOS transistor MP4, the third NMOS transistor MN3, and the fifth PMOS transistor MP5 to turn off. At this time, the lower plate of the second capacitor CB is grounded. The gate voltage of the first PMOS transistor MP1 at the second node X2 is VBASE-VDD, and its source voltage is the reference voltage VBASE. The gate voltage of the second PMOS transistor MP2 is lower than its source voltage, therefore the second PMOS transistor MP2 conducts. After the second PMOS transistor MP2 conducts, it pulls the gate voltage of the second NMOS transistor MN2 at the first node X1 to the reference voltage VBASE, which is higher than its source voltage at the second node X2, therefore the second NMOS transistor MN2 conducts. The gate voltage of the first NMOS transistor MN1 is less than its source voltage, while the gate and source voltages of the second PMOS transistor MP2 are equal. Therefore, both the first NMOS transistor MN1 and the second PMOS transistor MP2 are turned off. In this state, the lower plate of the first capacitor CA is connected to VDD, and the upper plate is connected to the reference voltage VBASE. The first capacitor CA is charged, and the corresponding second charging voltage is VBASE-VDD. The lower plate of the second capacitor CB is grounded, and the upper plate is connected to the output terminal. The second capacitor CB is discharged. Since the second NMOS transistor MN2 is turned on, the drive voltage VDRVP output by the drive voltage control unit 24 is VBASE-VDD. At this time, the drive voltage VDRVP is the turn-on voltage, which can also be defined as the first turn-on sub-voltage in this state.
[0095] The operating cycle corresponding to the third type of drive control method can be defined as the second cycle. During the entire second cycle, the drive voltage VDRVP is output to the gate of the floating switch. The gate voltage of the floating switch is VBASE-VDD, and its source voltage is the reference voltage VBASE. The floating switch is turned on, and this on state is driven by the second capacitor CB.
[0096] In practice, the entire floating switch drive circuit transitions between on and off states. The transition cycle includes an on-cycle and an off-cycle. The on-cycle can be divided into a first cycle and a second cycle. The on-cycle corresponds to the on-state driven by the first capacitor CA, while the on-state corresponds to the on-state driven by the second capacitor CB. The specific duration of the first and second cycles can be determined by the discharge time of the corresponding first capacitor CA or second capacitor CB. The first and second cycles are essentially equal and approximately half the transition cycle, while the off-cycle duration is short, approximately zero.
[0097] The switching cycle sequence is first cycle, then off cycle, and finally second cycle. After each on-state ends, the circuit first enters the off-state before entering the next on-state. The on-state is driven alternately by the first capacitor CA and the second capacitor CB. For the on-state driven by the first capacitor CA, the second capacitor CB is charged with a first charging voltage of VBASE-VDD. For the on-state driven by the second capacitor CB, the first capacitor CA is charged with the same first charging voltage. The two bootstrap capacitors alternately discharge and charge, ensuring the stability of the entire floating switch drive circuit's cyclic operation.
[0098] In addition, the above-mentioned floating switch drive circuit adopts a single-branch architecture, which is simple in structure and avoids the limitation of the existing technology that uses a dual-branch architecture to detect the high or low voltage at both ends of the floating switch in order to generate a suitable drive voltage.
[0099] Corresponding to the above embodiments, this application also provides a floating switch driving method, which is applied to the above-described floating switch driving circuit 20. See also... Figure 6 , Figure 6 This is a flowchart illustrating a floating switch driving method provided in an embodiment of this application. The method includes:
[0100] In step S601, the reference voltage unit takes the voltage of the source or drain connected to the reference voltage unit in the floating switch as the reference voltage and outputs it to the drive voltage control unit.
[0101] In step S602, the bootstrap unit outputs a corresponding bootstrap voltage to the drive voltage control unit according to the different control signals output by the timing control unit.
[0102] In step S603, the turn-on subunit controls the turn-on or turn-off of different MOS transistors according to the reference voltage and the bootstrap voltage, and generates a corresponding drive voltage and outputs it to the floating switch to turn on the floating switch. The turn-off subunit turns on according to the control signal, generates a corresponding drive voltage and outputs it to the floating switch to turn off the floating switch.
[0103] In specific implementation, the switching cycle of the timing control unit 22 includes a turn-on cycle and a turn-off cycle, the turn-on voltage is a first turn-on sub-voltage, the turn-off voltage is a first turn-off sub-voltage, and the method includes:
[0104] During the conduction period, the timing control unit 22 outputs a first conduction control signal or a second conduction control signal to turn on the conduction subunit and generate a first conduction sub-voltage to turn on the floating switch. The magnitude of the first conduction sub-voltage is the difference between the reference voltage and the first voltage.
[0105] During the shutdown period, the timing control unit 22 outputs a first shutdown control signal to control the third PMOS transistor MP3, the third NMOS transistor MN3, the fourth PMOS transistor MP4, and the fourth NMOS transistor MN4 to turn off, while the fifth PMOS transistor MP5 turns on, so that all MOS transistors in the turn-on sub-unit turn off, and the shutdown sub-unit turns on, generating the first shutdown sub-voltage to turn off the floating switch, wherein the first shutdown sub-voltage is equal to the magnitude of the third voltage VIN.
[0106] The conduction cycle includes a first cycle and a second cycle, and the conversion sequence of the switching cycle is the first cycle, the shutdown cycle, and the second cycle in sequence. The method includes:
[0107] During the first cycle, the timing control unit 22 outputs a first turn-on control signal to control the third NMOS transistor MN3 and the fourth PMOS transistor MP4 to turn on, while the third PMOS transistor MP3, the fourth NMOS transistor MN4, and the fifth PMOS transistor MP5 are turned off, so that the first NMOS transistor MN1 and the second PMOS transistor MP2 are turned on, generating the first turn-on sub-voltage to turn on the floating switch. The second capacitor CB is charged during the first cycle, and the magnitude of the corresponding first charging voltage is the difference between the reference voltage VBASE and the first voltage VDD.
[0108] During the second cycle, the timing control unit outputs a second turn-on control signal to turn on the third PMOS transistor MP3 and the fourth NMOS transistor MN4, while turning off the third NMOS transistor MN3, the fourth PMOS transistor MP4, and the fifth PMOS transistor MP5, so that the first PMOS transistor MP1 and the second NMOS transistor MN2 are turned on, generating the first turn-on sub-voltage to turn on the floating switch. The first capacitor CA is charged during the second cycle, and the magnitude of the corresponding second charging voltage is the difference between the reference voltage VBASE and the first voltage VDD.
[0109] The floating switch driving method provided in this application operates periodically in three states at a frequency divider of the timing control unit's switching frequency. These three states are two on-states driven by either the first capacitor CA or the second capacitor CB, and one off-state. During the off-state period, the lower plates of both the first capacitor CA and the second capacitor CB are floating, minimizing charge leakage. During the on-state period, the first capacitor CA and the second capacitor CB are driven alternately, using the potential of the fixed end of the floating switch as the reference voltage VBASE, ensuring that the floating switch driving circuit can achieve fast switching operation. For a detailed description of the specific implementation process of the floating switch driving method provided in this application, please refer to the specific implementation process of the floating switch driving circuit provided in the above embodiments, which will not be repeated here.
[0110] Example 2
[0111] To address the aforementioned technical problems, this application also provides a driving circuit for a floating switch corresponding to an NMOS transistor. See [link to relevant documentation]. Figure 7 , Figure 7 This is a schematic diagram of an NMOS transistor floating switch M2 provided in an embodiment of this application. For an NMOS transistor, it is turned on when the gate-source voltage Ugs > 0 and turned off when the gate-source voltage Ugs ≤ 0. See also Figure 2 The floating switch driving circuit applied to an NMOS transistor also includes a reference voltage unit 21, a timing control unit 22, a bootstrap unit 23, and a drive voltage control unit 24. One end of the reference voltage unit 21 is connected to either the source or drain of the floating switch, and the other end of the reference voltage unit 21 is connected to the drive voltage control unit 24. The bootstrap unit 23 is connected to both the timing control unit 22 and the drive voltage control unit 24. The drive voltage control unit 24 is connected to the gate of the floating switch. In a specific implementation, the floating switch driving circuit 20 also includes a signal generation unit 25, which is connected to both the bootstrap unit 23 and the drive voltage control unit 24.
[0112] The current, voltage, and other transmission relationships between the units in the floating switch drive circuit applied to NMOS transistors described above are shown in Example 1, and will not be repeated here.
[0113] See Figure 8 , Figure 8 This is a second schematic diagram of a floating switch driving circuit provided in an embodiment of this application. For the NMOS floating switch driving circuit, the conducting sub-unit includes a sixth PMOS transistor MP6 and a sixth NMOS transistor MN6 connected via a seventh node X7, and a seventh PMOS transistor MP7 and a seventh NMOS transistor MN7 connected via an eighth node X8;
[0114] The gates of the sixth PMOS transistor MP6 and the sixth NMOS transistor MN6 are connected to the seventh node X7, and the gates of the seventh PMOS transistor MP7 and the seventh NMOS transistor MN7 are connected to the eighth node X8.
[0115] The source of the sixth NMOS transistor MN6 and the source of the seventh NMOS transistor MN7 are connected to the output terminal of the reference voltage unit 21 through the ninth node X9, and the drain of the sixth PMOS transistor MP6 and the drain of the seventh PMOS transistor MP7 are connected to the turn-off sub-unit through the tenth node X10.
[0116] The turn-on subunit or the turn-off subunit outputs the corresponding turn-on voltage or turn-off voltage to the floating switch through the tenth node X10, so that the floating switch is turned on or off.
[0117] In specific implementation, the bootstrap unit 23 includes a third branch and a fourth branch;
[0118] The third branch includes a third capacitor CD and an eighth PMOS transistor MP8 and an eighth NMOS transistor MN8 connected via an eleventh node X11. The fourth branch includes a fourth capacitor CE and a ninth PMOS transistor MP9 and a ninth NMOS transistor MN9 connected via a twelfth node X12.
[0119] The source of the eighth PMOS transistor MP8 and the source of the ninth PMOS transistor MP9 are used to receive the first voltage VDD output by the signal generation unit 25, and the source of the eighth NMOS transistor MN8 and the source of the ninth NMOS transistor MN9 are used to receive the second voltage GND of the signal generation unit 25.
[0120] The gates of the eighth PMOS transistor MP8, the eighth NMOS transistor MN8, the ninth PMOS transistor MP9, and the ninth NMOS transistor MN9 are connected to the output terminal of the timing control unit 22;
[0121] The upper plate of the third capacitor CD is connected to the seventh node X7, the lower plate of the fourth capacitor CE is connected to the eleventh node X11, the upper plate of the fourth capacitor CE is connected to the eighth node X8, and the lower plate of the fourth capacitor CE is connected to the twelfth node X12.
[0122] In a specific implementation, the shutdown sub-unit includes a tenth NMOS transistor MN10. The gate of the tenth NMOS transistor MN10 is connected to the output terminal of the timing control unit 22, and the source of the tenth NMOS transistor MN10 is used to receive the second voltage GND output by the signal generation unit 25.
[0123] In practical implementation, different control signals output by the timing control unit 22 can control the on / off state of different MOSFETs, generating corresponding on-state or off-state voltages, which are then output to the gate of the floating switch to turn the floating switch on or off. (See also...) Figure 9 , Figure 9 This is a second schematic diagram of the timing control unit involved in a floating switch driving circuit provided in this application embodiment. The timing control unit 22 can output different control signals: a turn-on control signal, a second turn-off control signal, and a disable control signal. The turn-on control signal is further divided into a third turn-on control signal and a fourth turn-on control signal used to control the on / off states of different MOS transistors. Different control signals include different combinations of sub-signals, such as AP being 1 and AN being 0, etc. Specific combination methods are shown in Table 2.
[0124] Table 2
[0125]
[0126]
[0127] Wherein, EN is the enable signal for the floating switch drive circuit, SON is the turn-on / turn-off signal, JP is the turn-on / turn-off signal for the eighth PMOS transistor MP8, JN is the turn-on / turn-off signal for the eighth NMOS transistor MN8, KP is the turn-on / turn-off signal for the ninth PMOS transistor MP9, KN is the turn-on / turn-off signal for the ninth NMOS transistor MN9, and SOFFN is the turn-on / turn-off signal for the tenth PMOS transistor MP10.
[0128] Figures 10(a), 10(b), and 10(c) are schematic diagrams of the NMOS transistor floating switch in the on-state, the off-state, and the on-state, respectively, of a floating switch driving circuit according to an embodiment of this application. The different driving control methods of the floating switch driving circuit 20 are described below based on Table 2, Figures 10(a), 10(b), and 10(c).
[0129] 1. The fourth type of drive control mode corresponds to the third conduction control signal. Under this type of drive control mode, the sub-signals included in the input third conduction control signal are: EN is 1, SON is 1, SOFFN is 0, JP is 0, JN is 0, KP is 1, and KN is 1, which turns on the eighth PMOS transistor MP8 and the ninth NMOS transistor MN9, and turns off the ninth PMOS transistor MP9, the eighth NMOS transistor MN8, and the tenth NMOS transistor MN10.
[0130] As shown in Figure 10(a), at this time, the lower plate of the third capacitor CD is connected to VDD. The source voltage of the sixth PMOS transistor MP6 at the first node X1 is VBASE + VDD, the source voltage of the seventh NMOS transistor MN7 is the reference voltage VBASE, and the gate voltage of the seventh NMOS transistor MN7 is VBASE + VDD. Since the gate voltage of the seventh NMOS transistor MN7 is greater than its source voltage, MN7 is turned on and pulls the voltage of the second node X2 to the reference voltage VBASE. The gate voltage of the sixth PMOS transistor MP6 is less than its source voltage, so it is turned on. However, the gate voltage of the seventh PMOS transistor MP7 is greater than its source voltage, and the gate voltage of the sixth NMOS transistor MN6 is equal to its source voltage, so both MP7 and MN6 are turned off. In this state, the lower plate of the fourth capacitor CE is grounded, and the upper plate is connected to the reference voltage VBASE. The fourth capacitor CE is charged, and the corresponding second charging voltage is VBASE. Meanwhile, the lower plate of the third capacitor CD is connected to the first voltage VDD, and the upper plate is connected to the output terminal, so the third capacitor CD is discharged. With the sixth PMOS transistor MP6 turned on, the drive voltage output by the drive voltage control unit 24 is VDRVN - = VBASE + VDD. At this time, the drive voltage VDRVN is the turn-on voltage, which can be defined as the second turn-on sub-voltage in this state.
[0131] In practical implementation, the working cycle corresponding to the fourth type of drive control method can be defined as the third cycle. During the entire third cycle, the drive voltage VDRVN is output to the gate of the floating switch. The gate voltage of the floating switch is VBASE+VDD, and its source voltage is the reference voltage VBASE. The floating switch is turned on, and this on state is driven by the third capacitor CD.
[0132] 2. The fifth type of drive control mode corresponds to the second turn-off control signal. In this type of drive control mode, the input second turn-off control signal includes the following sub-signals: EN = 1, SON = 1, SOFFN = 0, JP = 0, JN = 0, KP = 1, and KN = 1, which turns on the tenth NMOS transistor MN10 and turns off the other MOS transistors. At this time, the upper and lower plates of the third capacitor CD and the fourth capacitor CE are in a floating state to minimize charge leakage. The output drive voltage VDRVN of the drive voltage control unit 24 is the turn-off voltage, which can be defined as the second turn-off sub-voltage in this state. The second turn-off sub-voltage is the second voltage GND received by the source of the tenth NMOS transistor MN10.
[0133] In practical implementation, the working cycle corresponding to the second type of drive control method can be defined as the turn-off cycle. Throughout the entire turn-off cycle, the floating switch remains off regardless of how the voltage across the floating switch dynamically changes.
[0134] 3. The sixth type of drive control mode corresponds to the fourth conduction control signal. Under this type of drive control mode, the sub-signals included in the input fourth conduction control signal are: EN is 1, SON is 0, SOFFN is 1, JP is 1, JN is 0, KP is 1, and KN is 0, which turns on the eighth NMOS transistor MN8 and the ninth PMOS transistor MP9, and turns off the ninth NMOS transistor MN9, the eighth PMOS transistor MP8, and the tenth NMOS transistor MN10.
[0135] At this time, the lower plate of the fourth capacitor CE is connected to VDD. The gate voltage of the sixth NMOS transistor MN6 at the second node X2 is VBASE + VDD, and the source voltage of the sixth NMOS transistor MN6 is the reference voltage VBASE. Therefore, the sixth NMOS transistor MN6 is turned on. The gate voltage of the seventh PMOS transistor MP7 at the first node X1 is pulled to the reference voltage VBASE, and the source voltage of the seventh PMOS transistor MP7 is VBASE + VDD. Therefore, the seventh PMOS transistor MP7 is turned on. However, the gate voltage of the sixth PMOS transistor MP6 is greater than its source voltage, and the gate voltage of the seventh NMOS transistor MN7 is equal to its source voltage. Therefore, both the sixth PMOS transistor MP6 and the seventh NMOS transistor MN7 are turned off. In this state, the lower plate of the third capacitor CD is grounded, and the upper plate is connected to the reference voltage VBASE. The first capacitor CD is charged, and the corresponding second charging voltage is the reference voltage VBASE. The lower plate of the fourth capacitor CE is connected to the first voltage VDD, and the upper plate is connected to the output terminal. The fourth capacitor CE is discharged. With the seventh PMOS transistor MP7 turned on, the drive voltage output by the drive voltage control unit 24 is VDRVN = VBASE + VDD. At this time, the drive voltage VDRVN is the turn-on voltage, which can also be defined as the second turn-on sub-voltage in this state.
[0136] In practical implementation, the working cycle corresponding to the sixth type of drive control method can be defined as the fourth cycle. During the entire fourth cycle, the drive voltage VDRVN is output to the gate of the floating switch. The gate voltage of the floating switch is VBASE+VDD, and its source voltage is the reference voltage VBASE. The floating switch is turned on, and this on state is driven by the fourth capacitor CE.
[0137] In practice, the entire floating switch drive circuit transitions between on and off states. The transition cycle includes an on-cycle and an off-cycle. The on-cycle can be divided into a third cycle and a fourth cycle. The on-cycle corresponding to the third cycle is driven by the third capacitor CD, and the on-cycle corresponding to the fourth cycle is driven by the fourth capacitor CE. The specific duration of the third and fourth cycles can be determined by the discharge time of the corresponding third capacitor CD or fourth capacitor CE. The third and fourth cycles are approximately equal and roughly half the transition cycle, while the off-cycle duration is short, approximately zero.
[0138] The switching cycle sequence is the third cycle, the turn-off cycle, and the fourth cycle. After each on-state ends, it first enters the turn-off state before entering the next on-state. The on-state is driven alternately by the third capacitor CD and the fourth capacitor CE. For the on-state driven by the third capacitor CD, the fourth capacitor CE is charged, with the second charging voltage being the reference voltage VBASE. For the on-state driven by the fourth capacitor CE, the third capacitor CD is charged, also with the second charging voltage. The two bootstrap capacitors alternately discharge and charge, ensuring the stability of the entire floating switch drive circuit's cyclic operation.
[0139] In addition, the above-mentioned floating switch drive circuit adopts a single-branch architecture, which is simple in structure and avoids the limitation of the existing technology that uses a dual-branch architecture to detect the high or low voltage at both ends of the floating switch in order to generate a suitable drive voltage.
[0140] Corresponding to the above embodiments, this application also provides a floating switch driving method, which is applied to the above-described floating switch driving circuit 20. See also... Figure 6 The same implementation process can be found in Example 1, and will not be repeated here. Only the different implementation processes in Example 1 and Example 2 will be introduced here.
[0141] In specific implementation, the switching cycle of the timing control unit includes a turn-on cycle and a turn-off cycle, the turn-on voltage is a second turn-on sub-voltage, the turn-off voltage is a second turn-off sub-voltage, and the method includes:
[0142] During the conduction period, the timing control unit 22 outputs a third conduction control signal or a fourth conduction control signal to turn on the conduction subunit and generate the second conduction sub-voltage to turn on the floating switch. The magnitude of the second conduction sub-voltage is the sum of the reference voltage VBASE and the first voltage VDD.
[0143] During the shutdown period, the timing control unit 22 outputs a first shutdown control signal to control the eighth PMOS transistor MP8, the eighth NMOS transistor MN8, the ninth PMOS transistor MP9, and the ninth NMOS transistor MN9 to turn off, while the tenth NMOS transistor MN10 turns on, so that all MOS transistors in the turn-on sub-unit turn off, and the shutdown sub-unit turns on, generating the second shutdown sub-voltage to turn off the floating switch, wherein the second shutdown sub-voltage is equal to the magnitude of the second voltage GND.
[0144] In specific implementation, the conduction cycle includes a third cycle and a fourth cycle, and the conversion sequence of the switching cycle is the third cycle, the shutdown cycle, and the fourth cycle in sequence. The method includes:
[0145] During the third cycle, the timing control unit 22 outputs a third turn-on control signal to turn on the eighth PMOS transistor MP8 and the ninth NMOS transistor MN9, while turning off the eighth NMOS transistor MN8, the ninth PMOS transistor MP9, and the tenth NMOS transistor MN10, so that the sixth PMOS transistor MP6 and the seventh NMOS transistor MN7 turn on, generating the second turn-on sub-voltage to turn on the floating switch. During the third cycle, the fourth capacitor CE is charged, and the corresponding third charging voltage is equal to the magnitude of the reference voltage VBASE.
[0146] During the fourth cycle, the timing control unit 22 outputs a fourth turn-on control signal to turn on the eighth NMOS transistor MN8 and the ninth PMOS transistor MP9, while turning off the eighth PMOS transistor MP8, the ninth NMOS transistor MN9, and the tenth NMOS transistor MN10, so that the sixth NMOS transistor MN6 and the seventh PMOS transistor MP7 are turned on, generating the second turn-on sub-voltage to turn on the floating switch. During the fourth cycle, the third capacitor CD is charged, and the corresponding fourth charging voltage is equal to the magnitude of the reference voltage VBASE.
[0147] The floating switch driving method provided in this application operates periodically in three states at a frequency divider of the timing control unit's switching frequency. These three states are two on-states driven by either the third capacitor CD or the fourth capacitor CE, and one off-state. During the off-state period, the lower plates of both the third capacitor CD and the fourth capacitor CE are floating, minimizing capacitor charge leakage. During the on-state period, the third capacitor CD and the fourth capacitor CE are driven alternately, using the potential of the fixed end of the floating switch as a reference voltage, ensuring that the floating switch driving circuit can achieve fast switching operation. For a detailed description of the specific implementation process of the floating switch driving method provided in this application, please refer to the specific implementation process of the floating switch driving circuit provided in the above embodiments, which will not be repeated here.
[0148] In the several embodiments provided in this application, it should be understood that the disclosed circuits and methods can also be implemented in other ways. The circuit embodiments described above are merely illustrative; for example, the flowcharts and circuit diagrams in the accompanying drawings show the architecture, functionality, and operation of possible implementations of the circuits and methods according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that, as an alternative implementation, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.
[0149] In addition, the functional modules or units in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.
[0150] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.
Claims
1. A floating switch driving circuit, characterized in that, The circuit includes a reference voltage unit, a timing control unit, a bootstrap unit, and a drive voltage control unit; One end of the reference voltage unit is used to connect to either the source or the drain of the floating switch, and the other end of the reference voltage unit is connected to the drive voltage control unit. The reference voltage unit is used to take the voltage of the source or the drain of the floating switch connected to the reference voltage unit as a reference voltage and output it to the drive voltage control unit. The bootstrap unit is connected to the timing control unit and the drive voltage control unit respectively. The bootstrap unit outputs a corresponding bootstrap voltage to the drive voltage control unit according to different control signals output by the timing control unit. The drive voltage control unit is connected to the gate of the floating switch. The drive voltage control unit includes a turn-on subunit and a turn-off subunit. The turn-on subunit includes four cross-coupled MOS transistors. The turn-on subunit is used to control the turn-on or turn-off of different MOS transistors according to the reference voltage and the bootstrap voltage to generate a corresponding turn-on voltage to turn on the floating switch. The turn-off subunit is connected to the timing control unit. The turn-off subunit is used to turn on according to the control signal to generate a corresponding turn-off voltage to turn off the floating switch. The floating switch is a PMOS transistor, and the conducting subunit includes a first PMOS transistor and a first NMOS transistor connected via a first node, and a second PMOS transistor and a second NMOS transistor connected via a second node. The gates of the first PMOS transistor and the first NMOS transistor are connected to the second node, and the gates of the second PMOS transistor and the second NMOS transistor are connected to the first node; the drain of the first PMOS transistor and the source of the first NMOS transistor are connected to the first node, and the drain of the second PMOS transistor and the source of the first NMOS transistor are connected to the second node. The source of the first PMOS transistor and the source of the second PMOS transistor are connected to the output terminal of the reference voltage unit through a third node, and the drain of the first NMOS transistor and the drain of the second NMOS transistor are connected to the turn-off sub-unit through a fourth node. The turn-on subunit or the turn-off subunit outputs the corresponding turn-on voltage or turn-off voltage to the floating switch through the fourth node, so as to turn the floating switch on or off. The circuit also includes a signal generation unit, and the bootstrap unit includes a first branch and a second branch; The first branch includes a first capacitor and a third PMOS transistor and a third NMOS transistor connected via a fifth node; the second branch includes a second capacitor and a fourth PMOS transistor and a fourth NMOS transistor connected via a sixth node. The source of the third PMOS transistor and the source of the fourth PMOS transistor are used to receive the first voltage output by the signal generating unit, and the source of the third NMOS transistor and the source of the fourth NMOS transistor are used to receive the second voltage of the signal generating unit. The gates of the third PMOS transistor, the third NMOS transistor, the fourth PMOS transistor, and the fourth NMOS transistor are connected to the output terminal of the timing control unit; The upper plate of the first capacitor is connected to the first node, the lower plate of the first capacitor is connected to the fifth node, the upper plate of the second capacitor is connected to the second node, and the lower plate of the second capacitor is connected to the sixth node. The shutdown subunit includes a fifth PMOS transistor; The gate of the fifth PMOS transistor is connected to the output terminal of the timing control unit, the drain of the fifth PMOS transistor is connected to the fourth node, and the source of the fifth PMOS transistor is used to receive the third voltage output by the signal generation unit, wherein the third voltage is greater than or equal to the first voltage.
2. The circuit according to claim 1, characterized in that, The floating switch is an NMOS transistor, and the conducting sub-unit includes a sixth PMOS transistor and a sixth NMOS transistor connected via a seventh node, and a seventh PMOS transistor and a seventh NMOS transistor connected via an eighth node; The gates of the sixth PMOS transistor and the sixth NMOS transistor are connected to the seventh node, and the gates of the seventh PMOS transistor and the seventh NMOS transistor are connected to the eighth node. The source of the sixth NMOS transistor and the source of the seventh NMOS transistor are connected to the output terminal of the reference voltage unit through the ninth node, and the drain of the sixth PMOS transistor and the drain of the sixth PMOS transistor are connected to the turn-off sub-unit through the tenth node. The turn-on subunit or the turn-off subunit outputs the corresponding turn-on voltage or turn-off voltage to the floating switch through the tenth node, so that the floating switch is turned on or off.
3. The circuit according to claim 2, characterized in that, The circuit also includes a signal generation unit, and the bootstrap unit includes a third branch and a fourth branch; The third branch includes a third capacitor and an eighth PMOS transistor and an eighth NMOS transistor connected via an eleventh node; the fourth branch includes a fourth capacitor and a ninth PMOS transistor and a ninth NMOS transistor connected via a twelfth node. The source of the eighth PMOS transistor and the source of the ninth PMOS transistor are used to receive the first voltage output by the signal generating unit, and the source of the eighth NMOS transistor and the source of the eighth NMOS transistor are used to receive the second voltage of the signal generating unit. The gates of the eighth PMOS transistor, the eighth NMOS transistor, the ninth PMOS transistor, and the ninth NMOS transistor are connected to the output terminal of the timing control unit; The upper plate of the third capacitor is connected to the seventh node, the lower plate of the fourth capacitor is connected to the eleventh node, the upper plate of the fourth capacitor is connected to the eighth node, and the lower plate of the fourth capacitor is connected to the twelfth node.
4. The circuit according to claim 3, characterized in that, The shutdown subunit includes a tenth NMOS transistor; The gate of the tenth NMOS transistor is connected to the output terminal of the timing control unit, and the source of the tenth NMOS transistor is used to receive the second voltage output by the signal generation unit.
5. A method for driving a floating switch, characterized in that, The method, applied to the floating switch driving circuit of claim 4, comprises: The reference voltage unit takes the voltage of the source or drain connected to the reference voltage unit in the floating switch as the reference voltage and outputs it to the drive voltage control unit. The bootstrap unit outputs a corresponding bootstrap voltage to the drive voltage control unit based on the different control signals output by the timing control unit. The turn-on subunit controls the turn-on or turn-off of different MOS transistors according to the reference voltage and the bootstrap voltage, and generates a corresponding drive voltage and outputs it to the floating switch to turn on the floating switch. The turn-off subunit turns on according to the control signal, generates a corresponding drive voltage and outputs it to the floating switch to turn off the floating switch.
6. The floating switch driving method according to claim 5, characterized in that, The switching cycle of the timing control unit includes a turn-on cycle and a turn-off cycle, the turn-on voltage is a first turn-on sub-voltage, the turn-off voltage is a first turn-off sub-voltage, and the method includes: During the conduction period, the timing control unit outputs a first conduction control signal or a second conduction control signal to turn on the conduction subunit and generate a first conduction sub-voltage to turn on the floating switch. The magnitude of the first conduction sub-voltage is the difference between the reference voltage and the first voltage. During the shutdown period, the timing control unit outputs a first shutdown control signal to control the third PMOS transistor, the third NMOS transistor, the fourth PMOS transistor, and the fourth NMOS transistor to turn off, while the fifth PMOS transistor turns on, so that all MOS transistors in the turn-on sub-unit turn off, and the shutdown sub-unit turns on, generating a first shutdown sub-voltage to turn off the floating switch, wherein the magnitude of the first shutdown sub-voltage is equal to that of the third voltage.
7. The method according to claim 6, characterized in that, The conduction cycle includes a first cycle and a second cycle, and the conversion sequence of the switching cycle is the first cycle, the shutdown cycle, and the second cycle in sequence. The method includes: During the first cycle, the timing control unit outputs a first turn-on control signal to control the third NMOS transistor and the fourth PMOS transistor to turn on, and the third PMOS transistor, the fourth NMOS transistor, and the fifth PMOS transistor to turn off, so that the first NMOS transistor and the second PMOS transistor turn on, generating the first turn-on sub-voltage to turn on the floating switch. The second capacitor is charged during the first cycle, and the magnitude of the corresponding first charging voltage is the difference between the reference voltage and the first voltage. During the second cycle, the timing control unit outputs a second turn-on control signal to control the third PMOS transistor and the fourth NMOS transistor to turn on, and the third NMOS transistor, the fourth PMOS transistor, and the fifth PMOS transistor to turn off, so that the first PMOS transistor and the second NMOS transistor turn on, generating the first turn-on sub-voltage to turn on the floating switch. The first capacitor is charged during the second cycle, and the magnitude of the corresponding second charging voltage is the difference between the reference voltage and the first voltage.
8. The floating switch driving method according to claim 7, characterized in that, Applied to the floating switch driving circuit of claim 7, the switching cycle of the timing control unit includes a turn-on period and a turn-off period, the turn-on voltage is a second turn-on sub-voltage, the turn-off voltage is a second turn-off sub-voltage, and the method includes: During the conduction cycle, the timing control unit outputs a third conduction control signal or a fourth conduction control signal to turn on the conduction subunit, generating the second conduction sub-voltage to turn on the floating switch, wherein the magnitude of the second conduction sub-voltage is the sum of the reference voltage and the first voltage; During the shutdown period, the timing control unit outputs a first shutdown control signal to control the eighth PMOS transistor, the eighth NMOS transistor, the ninth PMOS transistor, and the ninth NMOS transistor to turn off, while the tenth NMOS transistor turns on, so that all MOS transistors in the turn-on sub-unit turn off, and the shutdown sub-unit turns on, generating a second shutdown sub-voltage to turn off the floating switch, wherein the second shutdown sub-voltage is equal in magnitude to the second voltage.
9. The method according to claim 8, characterized in that, The conduction cycle includes a third cycle and a fourth cycle, and the conversion sequence of the switching cycle is the third cycle, the shutdown cycle, and the fourth cycle in sequence. The method includes: During the third cycle, the timing control unit outputs a third turn-on control signal to turn on the eighth PMOS transistor and the ninth NMOS transistor, and turn off the eighth NMOS transistor, the ninth PMOS transistor, and the tenth NMOS transistor, so that the sixth PMOS transistor and the seventh NMOS transistor are turned on, generating the second turn-on sub-voltage to turn on the floating switch. The fourth capacitor is charged during the third cycle, and the corresponding third charging voltage is equal to the magnitude of the reference voltage. During the fourth cycle, the timing control unit outputs a fourth turn-on control signal to turn on the eighth NMOS transistor and the ninth PMOS transistor, and turns off the eighth PMOS transistor, the ninth NMOS transistor, and the tenth NMOS transistor, so that the sixth NMOS transistor and the seventh PMOS transistor turn on, generating the second turn-on sub-voltage to turn on the floating switch. The third capacitor is charged during the fourth cycle, and the corresponding fourth charging voltage is equal to the magnitude of the reference voltage.