Semiconductor device and method for manufacturing structure

Abstract

The semiconductor device comprises: a substrate; a Group III nitride layer formed on the substrate and composed of a Group III nitride; a recess formed in the Group III nitride layer, the Group III nitride layer comprising: a channel layer; a barrier layer formed on the channel layer, forming a two-dimensional electron gas in the channel layer, the barrier layer comprising: a first layer composed of aluminum gallium nitride; a second layer formed on the first layer and composed of aluminum gallium nitride to which n-type impurities are added, the recess being formed by removing all or part of the thickness of the second layer, and at least a part of the thickness of the first layer being arranged below the recess.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor device and a structure. Background Art

[0002] Group III nitrides are used as materials for manufacturing semiconductor devices such as high electron mobility transistors (HEMTs). One technique for making Group III nitride HEMTs normally off is to form a recess (gate recess) in the region where the gate electrode is to be formed.

[0003] As a new technology for etching group III nitrides, photoelectrochemical (PEC) etching has been proposed (see, for example, Non-Patent Document 1). PEC etching is a wet etching method that causes less damage than conventional dry etching. Furthermore, compared to special dry etching methods that cause less damage, such as neutral particle beam etching (see, for example, Non-Patent Document 2) and atomic layer etching (see, for example, Non-Patent Document 3), PEC etching is more convenient due to its simpler equipment.

[0004] Prior art literature

[0005] Non-patent literature

[0006] Non-patent document 1: J.Murata et al., "Photo-electrochemical etching of free-standing GaN wafer surfaces grown by hydride vapor phase epitaxy", Electrochimica Acta 171 (2015) 89-95

[0007] Non-patent document 2: S. Samukawa, JJAP, 45 (2006) 2395.

[0008] Non-patent document 3: T. Faraz, ECS J. Solid Stat. Scie. & Technol., 4, N5023 (2015). Summary of the Invention

[0009] Problems to be solved by the invention

[0010] An object of the present invention is to provide a suitable technique for forming a recess (gate recess) in a semiconductor device (HEMT) formed using Group III nitride by PEC etching.

[0011] Means of solving the problem

[0012] According to one embodiment of the present invention, there is provided a semiconductor device having:

[0013] substrate;

[0014] a group III nitride layer formed on the substrate and composed of group III nitride;

[0015] a recess formed in the group III nitride layer,

[0016] The group III nitride layer has:

[0017] channel layer;

[0018] formed on the channel layer, forming a two-dimensional electron gas blocking layer on the channel layer,

[0019] The barrier layer has:

[0020] The first layer is composed of aluminum gallium nitride;

[0021] A second layer formed on the first layer and composed of aluminum gallium nitride doped with n-type impurities,

[0022] The recessed portion is formed by removing all or part of the thickness of the second layer, and at least part of the thickness of the first layer is arranged below the recessed portion.

[0023] According to another aspect of the present invention, a method for manufacturing a structure is provided.

[0024] The structure has a stacked structure including a first layer composed of aluminum gallium nitride and a second layer composed of aluminum gallium nitride to which n-type impurities are added and formed on the first layer;

[0025] a recess formed in the stacked structure,

[0026] The recess is formed by removing all or part of the thickness of the second layer, and at least part of the thickness of the first layer is disposed below the recess.

[0027] In this method of manufacturing a structure, the recessed portion is formed by etching the second layer by photoelectrochemical etching using the first layer as an etching stopper.

[0028] Effects of the Invention

[0029] Provided is a suitable technique for forming a recess (gate recess) in a semiconductor device (HEMT) formed using Group III nitride by PEC etching. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 (a) is a schematic cross-sectional view illustrating a HEMT according to one embodiment of the present invention. Figure 1(b) is a schematic cross-sectional view illustrating a wafer used as a HEMT material according to one embodiment.

[0031] Figure 2 (a) is a schematic cross-sectional view of an etching object illustrating one embodiment. Figure 2 (b) is a schematic cross-sectional view of a PEC etching apparatus illustrating a PEC etching process.

[0032] Figure 3 (a) is a schematic cross-sectional view of an etching object illustrating an embodiment of the present invention, showing a state where a PEC etching process is completed. Figure 3 (b) is a schematic cross-sectional view of a planarization etching apparatus illustrating a planarization etching step.

[0033] Figure 4 This is a schematic cross-sectional view of an etching object illustrating one embodiment, showing a state where a planarization etching step is completed.

[0034] Figure 5 (a) is a graph showing the relationship between etching time and etching depth of PEC etching in an experimental example, Figure 5 (b) is an AFM image of the epitaxial layer surface in the experimental example.

[0035] Figure 6 (a) is an AFM image of the unplanarized bottom surface of the experimental example. Figure 6 (b) is an AFM image of the flattened bottom surface of the experimental example.

[0036] Figure 7 This is a cross-sectional image of the epitaxial layer in which the recessed portion was formed in the experimental example observed by TEM.

[0037] Figure 8 This is an example of SIMS distribution of the Al composition and n-type impurity concentration (Si concentration) near the barrier layer. DETAILED DESCRIPTION

[0038] <Implementation Method>

[0039] A semiconductor device 200 according to one embodiment of the present invention will be described. Specifically, the semiconductor device 200 is a high electron mobility transistor (HEMT). Semiconductor device 200 is also referred to as HEMT 200. As described below, one feature of the HEMT 200 of this embodiment is that the recess 110 (gate recess) 110 for arranging the gate electrode 212 is formed by photoelectrochemical (PEC) etching.

[0040] First, the structures of the HEMT 200 and the group III nitride multilayer substrate 100 (hereinafter also referred to as the wafer 100 ) used as a material of the HEMT 200 will be described. Figure 1(a) is a schematic cross-sectional view illustrating a HEMT 200. Figure 1 (b) is a schematic cross-sectional view of an example wafer 100. Figure 1 (a) illustrates one of the multiple HEMTs 200 formed on the surface of the wafer 100 .

[0041] The wafer 100 includes a substrate 10 and a group III nitride layer 60 (hereinafter also referred to as epitaxial layer 60 ) formed by epitaxial growth on the substrate 10 and composed of a group III nitride.

[0042] As the substrate 10, for example, a semi-insulating silicon carbide (SiC) substrate is used. Here, the term "semi-insulating" means, for example, a substrate having a resistivity of 10 5 Ωcm or more. Alternatively, a thick semi-insulating epitaxial layer formed on a conductive substrate (for example, a 10μm thick carbon (C)-doped semi-insulating GaN layer formed on an n-type conductive gallium nitride (GaN) substrate) may be used as the semi-insulating substrate 10. The substrate 10 is not limited to a SiC substrate; other substrates (sapphire substrates, silicon (Si) substrates, (semi-insulating) GaN substrates, etc.) may also be used. The stacked structure of the epitaxial layer 60 can be appropriately selected depending on the type of substrate 10, the desired characteristics of the HEMT 200, and other factors.

[0043] When a SiC substrate is used as substrate 10, a stacked structure of, for example, a nucleation layer 20 composed of aluminum nitride (AlN), a thick channel layer 30 composed of gallium nitride (GaN), a barrier layer 40 composed of aluminum gallium nitride (AlGaN), and a cap layer 50 composed of GaN is used as epitaxial layer 60. Alternatively, cap layer 50 may be omitted.

[0044] Epitaxial layer 60 constituting HEMT 200 includes at least channel layer 30 and barrier layer 40 formed on the channel layer. Barrier layer 40 is formed on channel layer 30 to form a two-dimensional electron gas (2DEG) near the upper surface of channel layer 30, which serves as the channel of HEMT 200.

[0045] The barrier layer 40 of this embodiment has a stacked structure including a lower layer 41 composed of AlGaN and an upper layer 42 formed on (directly above) the lower layer 41 and composed of AlGaN doped with n-type impurities.

[0046] The lower layer 41 is a non-conductive layer, preferably composed of i-type AlGaN to which no impurities (especially conductive impurities) are intentionally added. Hereinafter, the lower layer 41 is also referred to as the i-type layer 41. The lower layer 41 is composed of AlGaN with a lower n-type impurity concentration than the upper layer 42. In order to suppress the conductivity of the i-type layer 41, the n-type impurity concentration of the i-type layer 41 is preferably less than 5×10 16 / cm 3 , more preferably less than 1×10 16 / cm 3 Here, regarding the lower layer 41 , “non-conductive” means having lower conductivity than the upper layer 42 , which means that the n-type impurity concentration is preferably suppressed as described above.

[0047] The upper layer 42 is a conductive layer, preferably made of n-type AlGaN that has been made conductive by adding n-type impurities. Hereinafter, the upper layer 42 is also referred to as the n-type layer 42. In order to obtain appropriate conductivity of the n-type layer 42, the n-type impurity concentration of the n-type layer 42 is preferably 1×10 17 / cm 3 In order to suppress the decrease in the crystallinity of the n-type layer 42, it is preferable that the n-type impurity concentration of the n-type layer 42 is less than 1×10 19 / cm 3 .

[0048] Here, the n-type impurity concentration of i-type layer 41 is defined as, for example, the sum of the silicon (Si) concentration and the germanium (Ge) concentration in i-type layer 41. Furthermore, the n-type impurity concentration of n-type layer 42 is defined as, for example, the sum of the Si concentration and the Ge concentration in n-type layer 42. The n-type impurity concentration of i-type layer 41 is defined as, for example, the average n-type impurity concentration within the total thickness of i-type layer 41. Furthermore, the n-type impurity concentration of n-type layer 42 is defined as, for example, the average n-type impurity concentration within the total thickness of n-type layer 42.

[0049] Al constituting the i-type layer 41 x Ga 1－x The Al composition x of N is, for example, 0.1≤x≤0.3. Similarly, the Al constituting the n-type layer 42 is y Ga 1－yThe Al composition y in N is, for example, 0.1≤x≤0.3. From the perspective of suppressing the formation of unnecessary 2DEG at the interface between the i-type layer 41 and the n-type layer 42, the Al composition x of the i-type layer 41 and the Al composition y of the n-type layer 42 are preferably equal at least near the interface between the i-type layer 41 and the n-type layer 42. The Al composition x of the i-type layer 41 and the Al composition y of the n-type layer 42 being equal at least near the interface between the i-type layer 41 and the n-type layer 42 means that the difference between the Al composition x and the Al composition y (the absolute value of the difference) is preferably 0.01 or less. In addition, near the interface, the Al composition x of the i-type layer 41 and the Al composition y of the n-type layer 42 are each specified as the average Al composition in a thickness of 1 nm from the interface, for example.

[0050] The total thickness of barrier layer 40, i.e., the combined thickness of i-type layer 41 and n-type layer 42, is preferably, for example, 10 nm or greater to form a 2DEG at a suitably high concentration. Furthermore, the total thickness of barrier layer 40 is preferably, for example, 100 nm or less to prevent degradation of the crystallinity of barrier layer 40 heteroepitaxially grown on channel layer 30.

[0051] As described later, the bottom surface 111 of the recess 110 is located near the upper surface of the i-type layer 41. In other words, the thickness of the i-type layer 41 roughly corresponds to the remaining thickness of the barrier layer 40 below the recess 110, which serves as the gate recess. The thickness of the i-type layer 41 is preferably set to a thickness that allows the HEMT 200 to be normally-off, and is preferably 10 nm or less, for example. Furthermore, the thickness of the i-type layer 41 is preferably set to a thickness that stably ensures the remaining thickness of the barrier layer 40 below the recess 110, and is preferably 2 nm or more, for example. The location of the i-type layer 41 can be determined using secondary ion mass spectrometry (SIMS), for example, as follows. For example, the location where the Al composition of the bulk of the barrier layer 40 (not near the upper and lower interfaces) reaches halfway on the channel layer 30 side is determined to be the boundary between the i-type layer 41 and the channel layer (GaN layer) 30, i.e., the lower end of the i-type layer 41. In addition, for example, near the interface between the n-type layer 42 and the i-type layer 41, the n-type impurity concentration decreasing from the n-type layer 42 side is less than 5×10 16 / cm 3 The position of is determined to be the interface (boundary) between the n-type layer 42 and the i-type layer 41 , that is, the upper end of the i-type layer 41 . Figure 8 shows an example of SIMS distribution of the Al composition and n-type impurity concentration (here, Si concentration) near the barrier layer 40. The barrier layer 40 is represented as "AlGaN", the i-type layer 41 as "i-AlGaN", and the n-type layer 42 as "n-AlGaN".

[0052] The thickness of the n-type layer 42 roughly corresponds to the depth of the recessed portion 110 serving as the gate recess, that is, the difference between the thickness of the barrier layer 40 below the source electrode 211 and the drain electrode 213 and the thickness of the barrier layer 40 below the gate electrode 212. The thickness of the n-type layer 42 is preferably set to a thickness that satisfies this difference, preferably being 5 nm or greater, for example. Furthermore, the thickness of the n-type layer 42 is preferably set to avoid excessive thickness of the barrier layer 40 as a whole (e.g., 100 nm or less, as described above), preferably being 90 nm or less, for example.

[0053] The cap layer 50 is a conductive layer, for example, made of GaN having conductivity by adding n-type impurities. The thickness of the cap layer 50 is appropriately set as needed, for example, 5 nm.

[0054] In the stacked structure of the barrier layer 40 and the cap layer 50 , the i-type layer 41 is a non-conductive layer, and the stacked portion of the n-type layer 42 and the cap layer 50 is a conductive layer.

[0055] In this embodiment, the case where the surface 61 of the epitaxial layer 60 is composed of the c-plane of the group III nitride constituting the epitaxial layer 60 is exemplified. "Composed of the c-plane" herein means that the lowest-index crystal plane closest to the surface 61 is the c-plane of the group III nitride crystal constituting the epitaxial layer 60. The group III nitride constituting the epitaxial layer 60 has dislocations (threading dislocations), and the dislocations are distributed on the surface 61 at a predetermined density.

[0056] HEMT 200 includes an epitaxial layer 60 of wafer 100 (at least a channel layer 30 and a barrier layer 40 serving as operating layers through which operating current flows in HEMT 200), a source electrode 211, a gate electrode 212, and a drain electrode 213. Furthermore, HEMT 200 of this embodiment includes a recess 110 formed in epitaxial layer 60, more specifically, in barrier layer 40.

[0057] Recess 110 is formed in surface (upper surface) 61 of epitaxial layer 60 by (when epitaxial layer 60 includes cap layer 50, removing the entire thickness of cap layer 50 and) partially removing the thickness of barrier layer 40. Recess 110 is formed by removing all or part of the thickness of n-type layer (upper layer of barrier layer 40) 42. Below recess 110, at least a portion of the thickness of i-type layer (lower layer of barrier layer 40) 41 is disposed.

[0058] As will be described in detail later, recess 110 is formed by etching barrier layer 40 using PEC etching. In this PEC etching, n-type layer 42 is etched using i-type layer 41 as an etching stopper, thereby forming recess 110 having bottom surface 111 located near the upper surface of i-type layer 41. Figure 1In (a), as a typical (ideal) condition, the condition in which the depth direction position of the bottom surface 111 of the recess 110 is consistent with the position of the upper surface of the i-type layer 41 is illustrated, that is, the recess 110 is formed by removing the total thickness of the n-type layer 42, and the total thickness of the i-type layer 41 is arranged below the recess 110.

[0059] A gate electrode 212 is formed on the bottom surface 111 of the recess 110. A source electrode 211 and a drain electrode 213 are formed on the surface 61 of the epitaxial layer 60. The gate electrode 212 is formed, for example, from a Ni / Au layer, in which a gold (Au) layer is stacked on a nickel (Ni) layer. The source electrode 211 and the drain electrode 213 are each formed, for example, from a Ti / Al / Au layer, in which an Al layer is stacked on a titanium (Ti) layer, and an Au layer is stacked on the Al layer.

[0060] The HEMT 200 may further include a protective film 220 and an element isolation region 230. The protective film 220 is formed to have openings on the upper surfaces of the source electrode 211, the gate electrode 212, and the drain electrode 213. The element isolation region 230 isolates adjacent HEMTs 200 (individual elements). The element isolation region 230 can be formed, for example, as an element isolation trench. The element isolation trench is positioned so that its bottom surface is deeper than the upper surface of the channel layer 30, that is, the 2DEG between adjacent elements is disconnected by the element isolation trench 230. Furthermore, the element isolation region 230 is not limited to being formed by an element isolation trench; for example, ion implantation can also be used to form the element isolation region 230.

[0061] Next, an exemplary method for manufacturing the HEMT 200 will be described. In the method for manufacturing the HEMT 200, a step of forming the recess 110 by PEC etching (hereinafter also referred to as a PEC etching step) is performed.

[0062] Before the PEC etching process, a structure 150 (hereinafter also referred to as etching object 150 ) as an object to be processed by PEC etching is prepared. Figure 2 (a) is a schematic cross-sectional view illustrating an etching object 150 .

[0063] The etching object 150 has a structure in which a cathode spacer 160 and a mask 170 are provided on the epitaxial layer 60 of the wafer 100. In this embodiment, the cathode spacer 160 is used as (at least one of) the source electrode 211 and the drain electrode 213 of the HEMT 200. In other words, the source electrode 211 and the drain electrode 213 of the HEMT 200 are used as (at least one of) the cathode spacer 160. Specifically, the etching object 150 has a structure in which a mask 170 for PEC etching is formed on a stepped member having the source electrode 211 and the drain electrode 213 formed on the surface 61 of the epitaxial layer 60.

[0064] Mask 170 is formed on surface 61 of epitaxial layer 60. It has an opening in region 62 (hereinafter also referred to as etched region 62) where recess 110 is to be formed. It also has an opening that exposes the upper surface of cathode pad 160 (source electrode 211 and drain electrode 213). Mask 170 is formed of a non-conductive material such as resist or silicon oxide.

[0065] The cathode pad 160 is a conductive member formed of a conductive material, is electrically connected to the etched region 62 , and is provided in contact with at least a portion of the surface of the conductive region (of the epitaxial layer 60 ) of the wafer 100 .

[0066] Figure 2 (b) is a schematic cross-sectional view showing a PEC etching process, showing a PEC etching apparatus 300. The PEC etching apparatus 300 includes a container 310 for storing an etching solution 301 and a light source 320 for emitting ultraviolet (UV) light 321.

[0067] In the PEC etching process, the etching object 150 is immersed in the etching solution 301, and UV light 321 is irradiated onto the surface 61 of the epitaxial layer 60 through the etching solution 301 while the etched area 62 and the cathode gasket 160 (at least a portion of the cathode gasket 160, such as the upper surface) are in contact with the etching solution 301.

[0068] Thus, recess 110 is formed by PEC etching the group III nitride constituting etched region 62. More specifically, recess 110 is formed by PEC etching (the total thickness including cap layer 50, if present, and a portion of barrier layer 40).

[0069] Here, the principle of PEC etching is described, and the etching solution 301, cathode spacer 160, etc. are described in more detail. The principle of PEC etching is first described by taking the etching of GaN as an example.

[0070] As the etching solution 301 for PEC etching, an alkaline or acidic etching solution 301 is used which contains oxygen used in the generation of the oxide of the group III element contained in the group III nitride constituting the etched area 62 (meaning the bottom surface 111 after the formation of the recess 110 begins), and also contains an oxidant that accepts electrons.

[0071] As the oxidizing agent, peroxydisulfate ion (S2O8 2－ ). Below, the example of supplying S2O8 from potassium persulfate (K2S2O8) is given. 2－ way, but S2O8 2－Alternatively, it can be supplied from, for example, sodium peroxodisulfate (Na2S2O8), ammonium peroxodisulfate (ammonium persulfate, (NH4)2S2O8), or the like.

[0072] A first example of etching solution 301 is a mixture of an aqueous potassium hydroxide (KOH) solution and an aqueous potassium persulfate (K2S2O8) solution, which exhibits alkalinity at the start of PEC etching. Such etching solution 301 can be prepared, for example, by mixing a 0.01M aqueous KOH solution and a 0.05M aqueous K2S2O8 solution in a 1:1 ratio. The concentration of the aqueous KOH solution, the concentration of the aqueous K2S2O8 solution, and the mixing ratio of these solutions can be adjusted as needed. Furthermore, etching solution 301 comprising a mixture of aqueous KOH and aqueous K2S2O8 can be made acidic at the start of PEC etching by, for example, lowering the concentration of the aqueous KOH solution.

[0073] The principle of PEC etching when using the etching solution 301 of the first example is described. By irradiating the surface 61 to be PEC-etched with UV light 321 having a wavelength of 365 nm or less, holes and electrons are paired in the GaN constituting the etched area 62. The generated holes decompose the GaN into GaN. 3+ With N2 (chemical formula 1), Ga 3+ Further hydroxyl ions (OH － ) is oxidized to form gallium oxide (Ga2O3) (Chemical Formula 2). The generated Ga2O3 then dissolves in an alkali (or acid). This progresses PEC etching of GaN. Furthermore, the generated holes react with water, decomposing the water and generating oxygen (Chemical Formula 3).

[0074]

Chemical Formula 1

[0075]

[0076]

Chemical Formula 2

[0077]

[0078]

Chemical Formula 3

[0079]

[0080] In addition, K2S2O8 dissolves in water to generate persulfate ions (S2O8 2－ )(Chemical Formula 4), by S2O8 2－ Irradiation with UV light 321 generates sulfate ion radicals (SO4 －＊ Free radicals) (chemical formula 5). The electrons generated by pairing with holes are the same as SO4 －＊The free radicals react with water, the water is decomposed, and hydrogen is generated (chemical formula 6). －＊ Free radicals can consume electrons that are paired with holes in GaN, thus enabling PEC etching to proceed smoothly. In addition, as shown in (Chemical Formula 6), as PEC etching proceeds, sulfate ions (SO4 2－ ) increases, thereby making the etching solution 301 more acidic (pH value decreases).

[0081]

Chemical Formula 4

[0082]

[0083]

Chemical Formula 5

[0084]

[0085]

Chemical Formula 6

[0086]

[0087] A second example of etching solution 301 is a mixture of an aqueous phosphoric acid (H₃PO₄) solution and an aqueous potassium persulfate (K₂S₂O₄) solution, which exhibits acidity at the start of PEC etching. Such etching solution 301 can be prepared, for example, by mixing a 0.01M aqueous H₃PO₄ solution and a 0.05M aqueous K₂S₂O₂ solution in a ratio of 1:1. The concentration of the aqueous H₃PO₄ solution, the concentration of the aqueous K₂S₂O₂ solution, and the mixing ratio of these aqueous solutions can be adjusted as needed. Both aqueous H₃PO₄ and aqueous K₂S₂O₂ solutions are acidic, so the etching solution 30 obtained by mixing the aqueous H₃PO₄ and aqueous K₂S₂O₂ solutions is acidic at any mixing ratio. Furthermore, since aqueous K₂S₂O₂ solutions themselves are acidic, aqueous K₂S₂O₂ solutions alone can be used as the etching solution 301 that exhibits acidity at the start of etching. In this case, the concentration of the aqueous K₂S₂O₂ solution can be, for example, 0.025M.

[0088] The etching solution 301 is preferably acidic from the start of PEC etching, as this facilitates the use of the resist as the mask 170. This is because an alkaline etching solution 301 facilitates the peeling of the resist mask. Furthermore, when silicon oxide is used as the mask 170, whether the etching solution 301 is acidic or alkaline does not particularly matter.

[0089] The principle of PEC etching when using the etching solution 301 of the second example is presumably that (Chemical Formula 1) to (Chemical Formula 3) described when using the etching solution 301 of the first example are replaced by (Chemical Formula 7). In other words, GaN reacts with the holes generated by the irradiation of UV light 321 and water to generate Ga2O3 and hydrogen ions (H + ), N2 (chemical formula 7). Then, the generated Ga2O3 dissolves in acid. In this way, the PEC etching of GaN proceeds. In addition, as shown in (chemical formula 4) to (chemical formula 6), the electrons generated in pairs with holes are removed by S2O8 2－ The principle of consumption is the same as that when the etching solution 301 of the first example is used.

[0090]

Chemical Formula 7

[0091]

[0092] As can be understood from (Chemical Formula 1) and (Chemical Formula 2) or (Chemical Formula 7), etched region 62 (bottom surface 111 of recess 110) produced by PEC etching is considered to function as an anode that consumes holes. Furthermore, as can be understood from (Chemical Formula 6), the surface of cathode pad 160, a conductive member electrically connected to etched region 62, that contacts etching solution 301 is considered to function as a cathode that consumes (emit) electrons.

[0093] Without cathode gasket 160, it is difficult to ensure an area that functions as a cathode, making PEC etching difficult to perform. In this embodiment, by providing cathode gasket 160, PEC etching can be performed well. In addition, mask 170 has an opening on the upper surface of cathode gasket 160. In other words, a large area of the upper surface of cathode gasket 160 functions as a cathode, thereby enabling PEC etching to be performed more effectively.

[0094] As shown in (Chemical Formula 5), as S2O8 2－ Generate SO4 －＊ The free radical method can use at least one of the irradiation of UV light 321 and heating. When using the irradiation of UV light 321, in order to increase the S2O8 2－ The light absorption of SO4 is efficiently generated －＊ The wavelength of UV light 321 is preferably 200 nm or more and less than 310 nm. In other words, holes are generated in the group III nitride in the epitaxial layer 60 by irradiation of UV light 321, and S2O8 is generated in the etching solution 301. 2－ Generate SO4 －＊ From the viewpoint of efficient radical formation, it is preferable to set the wavelength of UV light 321 to be 200 nm or more and less than 310 nm. 2－Generate SO4 －＊ When the radical generation is carried out by heating, the wavelength of the UV light 321 may be set to 310 nm or more (365 nm or less).

[0095] By irradiation of UV light 321 from S2O8 2－ SO4 －＊ When the radicals are generated, the distance (wafer placement depth) L from the surface 61 of the epitaxial layer 60 (of the wafer 100) to the upper surface of the etching solution 301 (refer to Figure 2 (b)), for example, preferably 1 mm or more and 100 mm or less. If the distance L is too short, for example, less than 1 mm, the SO4 generated in the etching solution 301 above the wafer 100 －＊ The amount of free radicals may become unstable due to the change of the distance L. If the distance L is short, it is difficult to control the liquid level. Therefore, the distance L is preferably 1 mm or more, more preferably 3 mm or more, and even more preferably 5 mm or more. In addition, if the distance L is too long, for example, more than 100 mm, a large amount of SO4 that does not contribute to PEC etching will be wasted in the etching solution 301 above the wafer 100. －＊ The free radicals are generated and the utilization efficiency of the etching solution 301 is reduced.

[0096] Surface 61 of epitaxial layer 60 (of wafer 100) is preferably arranged parallel (horizontally) to the surface of etching solution 301. Furthermore, UV light 321 is preferably irradiated perpendicularly to surface 61 of epitaxial layer 60. In order to form multiple devices within the surface of wafer 100, multiple etched regions 62 are arranged spaced apart from each other across the entire surface of wafer 100. By arranging surface 61 of epitaxial layer 60 parallel to the surface of etching solution 301 and irradiating surface 61 of epitaxial layer 60 with UV light 321 perpendicularly, the uniformity of the light irradiation conditions for each etched region 62 can be improved.

[0097] It is preferable to irradiate the surface 61 of the epitaxial layer 60 with UV light 321 while the wafer 100 and the etching solution 301 are stationary, in other words, without stirring the etching solution 301. This can suppress the SO4 supplied to each etched area 62. －＊ The supply state of free radicals fluctuates due to the movement of the etching solution 301, which can convert SO4 －＊ Free radicals are appropriately supplied by diffusing into each etched region 62. This improves the uniformity of etching conditions (uniformity between isolated etched regions 62) and the flatness of the etching. Furthermore, if necessary, a waiting step may be performed to allow the etching solution 301 to settle before irradiating the surface 61 of the epitaxial layer 60 with UV light 321.

[0098] The inventors of the present application have come to the following understanding: if the edge of the mask used for PEC etching is made of a conductive material, the shape of the edge of the recess formed by PEC etching is likely to become a chaotic shape that does not follow the edge of the mask. However, by making the edge of the mask made of a non-conductive material, it is easy to control the shape of the edge of the recess formed by PEC etching to a shape that follows the edge of the mask. Therefore, the mask end that defines the etched area 62 (in other words, the edge of the recess 110) is preferably defined by a mask 170 made of a non-conductive material. The cathode gasket 160 is preferably arranged at a position (when viewed from above) that is away from the edge of the recess 110 (the position where the edge of the recess 110 is not defined). From the viewpoint of well controlling the shape of the edge of the recess 110, the distance D between the edge of the mask 170 (when viewed from above) and the edge of the cathode gasket 160 is preferably less than 0. OFF (Refer to Figure 2 (a)) is preferably 5 μm or more, more preferably 10 μm or more.

[0099] PEC etching can also be performed on group III nitrides other than GaN as exemplified. The group III element contained in the group III nitride can be at least one of aluminum (Al), gallium (Ga), and indium (In). The concept of PEC etching for the Al component or the In component in the group III nitride is the same as the concept described for the Ga component with reference to (Chemical Formula 1), (Chemical Formula 2), or (Chemical Formula 7). In other words, by irradiating UV light 321, holes are generated, Al oxide or In oxide is generated, and these oxides are dissolved in alkali or acid, thereby enabling PEC etching. The wavelength of UV light 321 (light 321) can be appropriately changed according to the composition of the group III nitride to be etched. Taking PEC etching of GaN as a standard, when Al is contained, shorter wavelength light can be used, and when In is contained, longer wavelength light can be used. In other words, according to the composition of the group III nitride to be processed, light of a wavelength that is suitable for PEC etching of the group III nitride can be appropriately selected.

[0100] In the etching object 150 of this embodiment, the etched region 62 (bottom surface 111 of the recess 110), which serves as an anode, and the cathode pad 160, which serves as a cathode, can be electrically connected in the in-plane direction via the conductive cap layer 50 and the n-type layer 42. Since the etched region 62 and the cathode pad 160 are electrically connected via the cap layer 50 and the n-type layer 42, the cap layer 50 is subjected to PEC etching. After the total thickness of the cap layer 50 is etched, further electrical connection is established via the n-type layer 42, resulting in PEC etching of the n-type layer 42.

[0101] As PEC etching progresses, when the full thickness of n-type layer 42 is etched, the conductivity between etched region 62 (bottom surface 111 of recess 110) and cathode pad 160 is disrupted. Consequently, PEC etching stops, leaving non-conductive i-type layer 41 below recess 110. Thus, in this embodiment, the formation of recess 110 can be completed by automatically stopping PEC etching using i-type layer 41 as an etch stop layer.

[0102] Figure 3 (a) is a schematic cross-sectional view of the etching object 150, showing the state at the end of the PEC etching process. As described above, dislocations are distributed at a predetermined density on the surface 61 of the epitaxial layer 60. Since the lifetime of holes in dislocations is short, PEC etching is less likely to occur. Therefore, at the position corresponding to the dislocations on the bottom surface 111 of the recess 110, a convex portion 182 is easily formed as a portion not dissolved by PEC etching. In other words, during the PEC etching process, a flat portion 181 (a portion where PEC etching proceeds without dislocations) and a convex portion 182, which is more difficult to PEC-etch than the flat portion 181 and thus rises relative to the flat portion 181, are formed on the bottom surface 111 of the recess 110. Since the convex portion 182 is a portion not dissolved by PEC etching, its maximum height is less than the depth of the recess 110.

[0103] The recessed portions 110 formed during the PEC etching process are likely to form protrusions 182, which are undissolved portions during the PEC etching. Therefore, after the PEC etching process, it is preferable to perform etching (hereinafter also referred to as a planarization etching process) to remove the protrusions 182 and improve the flatness of the bottom surface 111. Specifically, the planarization etching process involves etching the protrusions 182 (selectively with respect to the flat portion 181) through planarization etching, thereby reducing the protrusions 182.

[0104] As the planarization etching, for example, wet etching using an acidic or alkaline etching solution (not PEC etching) can be used. As the etching solution for the planarization etching, for example, a hydrochloric acid (HCl) aqueous solution, a mixed aqueous solution of hydrochloric acid (HCl) and hydrogen peroxide (H2O2) (perhydrochloric acid), a mixed aqueous solution of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2) (piranha solution), a tetramethylammonium hydroxide (TMAH) aqueous solution, a hydrogen fluoride aqueous solution (hydrofluoric acid), a potassium hydroxide (KOH) aqueous solution, etc. can be used.

[0105] The epitaxial layer 60 is grown heteroepitaxially on a substrate 10 such as a SiC substrate, a sapphire substrate, or a Si substrate. 8 / cm 2Therefore, when the substrate 10 is used as a different substrate, the protrusions 182 are easily formed by PEC etching in the PEC etching process, and therefore it is particularly preferable to planarize the bottom surface 111 by a planarizing etching process.

[0106] Figure 3 (b) is a schematic cross-sectional view of a planarization etching apparatus 400 showing a planarization etching process. The planarization etching apparatus 400 includes a container 410 for storing an etching solution 401. In the planarization etching process, the object 150 is immersed in the etching solution 401 so that the recess 110 contacts the etching solution 401, and the protrusion 182 is etched. As a result, the bottom surface 111 of the recess 110 is planarized. Planarization etching is not PEC etching. Therefore, in the planarization etching process, UV light is not irradiated on the surface 61 of the epitaxial layer 60 (it is not necessary to irradiate the surface 61 of the epitaxial layer 60 with UV light).

[0107] While etching the c-plane (+c-plane) of a Group III nitride such as GaN is difficult, PEC etching can etch Group III nitrides regardless of their crystal orientation, making it possible to etch even the c-plane. The PEC etching process is performed while irradiating UV light 321 from above the surface 61 of the epitaxial layer 60, which is the c-plane, to etch the Group III nitride constituting the epitaxial layer 60 in a direction perpendicular to the surface 61 (in other words, in the thickness direction of the epitaxial layer 60).

[0108] In contrast, planarization etching is performed as a conventional wet etching method, not PEC etching, using an etchant such as perhydrochloric acid. Conventional wet etching is difficult to etch the c-plane of group III nitrides, so the flat portion 181 formed by the c-plane in the bottom surface 111 of the recess 110 is not etched. However, the convex portion 182 on the bottom surface 111 is composed of crystal planes other than the c-plane and can therefore be etched by conventional etching. Therefore, planarization etching allows the convex portion 182 to be selectively etched relative to the flat portion 181 on the bottom surface 111 of the recess 110.

[0109] The planarization etching is performed on crystal planes other than the c-plane, in other words, on crystal planes intersecting the c-plane, and the protrusion 182 is etched from a direction that is not perpendicular to the c-plane (in other words, a direction intersecting the thickness direction of the epitaxial layer 60 (lateral direction)).

[0110] By etching the protrusions 182 through planarization etching, the protrusions 182 can be lowered, making the bottom surface 111 nearly flat. In other words, the protrusions 182 can be brought closer to the c-plane that constitutes the flat portion 181. If the protrusions 182 are etched closer to the c-plane, etching becomes difficult. Therefore, in the planarization etching process of this embodiment, excessive etching of the protrusions 182 is easily suppressed, and the planarization etching is completed with the bottom surface 111 substantially flat.

[0111] The mask 170 used in the PEC etching process may be removed in the planarization etching process, or a separate mask removal process for removing the mask 170 may be provided.

[0112] Figure 4 1 is a schematic cross-sectional view of the etching object 150 showing a state where the planarization etching step is completed. The protrusions 182 are removed, and the bottom surfaces 111 of the recesses 110 are planarized.

[0113] After the planarization etching process is completed, other processes for completing the HEMT 200 are performed (see Figure 1 (a) As other steps, a step of forming the gate electrode 212 on the bottom surface 111 of the recess 110 , a step of forming the element isolation region 230 , and a step of forming the protective film 220 are performed. In this way, the HEMT 200 is manufactured.

[0114] In addition, the etching object 150 ( Figure 2 (a) Refer), in other words, it is a method of forming the element separation groove after the PEC etching process, but it is also possible to use the etching object 150 in a state where the element separation area 230 is formed by forming the element separation groove before the PEC etching process.

[0115] Reference Figure 4 The features of recess 110 of HEMT 200 will be further described by way of example. As described above, in the PEC etching process for forming recess 110 in this embodiment, i-type layer 41 serves as an etch stop layer. Therefore, recess 110 is typically (ideally) formed by removing the entire thickness of n-type layer 42 and disposing the entire thickness of i-type layer 41 below recess 110.

[0116] However, in actual PEC etching, due to errors, the thickness of the barrier layer 40 arranged below the recess 110 may not be completely consistent with the total thickness of the i-type layer 41 , and the bottom surface 111 of the recess 110 is arranged near the upper surface of the i-type layer 41 .

[0117] For example, the bottom surface 111 of the recess 110 may reach the upper surface of the i-type layer 41. In this case, the entire thickness of the n-type layer 42 is removed, thereby forming the recess 110 with the i-type layer 41 exposed on the bottom surface 111. The bottom surface 111 is located near the upper surface of the i-type layer 41 and is located below the upper surface. More specifically, the thickness (depth) TL (refer to Figure 4 ) (is greater than 0 nm) is preferably less than 1 nm. Figure 4 In FIG. 4 , the bottom surface 111 located below the upper surface of the i-type layer 41 is indicated by a dotted line.

[0118] For example, the bottom surface 111 of the recess 110 may not reach the upper surface of the i-type layer 41. In this case, a portion of the thickness of the n-type layer 42 is removed, thereby forming the recess 110 with the n-type layer 42 exposed on the bottom surface 111. The bottom surface 111 is located near the upper surface of the i-type layer 41 and is arranged at a position higher than the upper surface. More specifically, the thickness (depth) TU (refer to Figure 4 ), (higher than 0nm) preferably less than 1nm. Figure 4 The bottom surface 111 located above the upper surface of the i-type layer 41 is indicated by a dotted line.

[0119] Furthermore, the bottom surface 111 of the recess 110 formed by PEC etching (and planarization etching) has high flatness. For example, the arithmetic mean roughness (Ra) of the bottom surface 111 of the recess 110 measured by observing a 1000 nm square area of the bottom surface 111 of the recess 110 using an atomic force microscope (AFM) is preferably 0.4 nm or less, and more preferably 0.3 nm or less.

[0120] For example, the difference (the absolute value of the difference) between the arithmetic mean roughness (Ra) of the surface 61 of the epitaxial layer 60 measured by observing a 1000 nm square area of the surface 61 and the arithmetic mean roughness (Ra) of the bottom surface 111 of the recess 110 measured by observing a 1000 nm square area of the bottom surface 111 with AFM is preferably less than 0.2 nm, and more preferably less than 0.1 nm.

[0121] For example, when observing a cross section that is perpendicular to the upper surface of the barrier layer 40 and intersects the bottom surface 111 of the recess 110 (perpendicular to the edge of the recess 110 when viewed from above) using a transmission electron microscope (TEM), the difference between the maximum and minimum values of the height of the bottom surface 111 (the thickness of the barrier layer 40 arranged below the recess 110) (maximum value - minimum value) within a range of more than 30 nm along the length of the bottom surface 111 within the cross section is preferably less than 0.2 nm, and more preferably less than 0.1 nm.

[0122] In addition, the side surface 112 of the recess 110 formed by PEC etching (and planarization etching) has a tapered shape that is inclined upward toward the outside (in a plan view) of the bottom surface 111 of the recess 110. The inclination angle θ of the side surface 112 of the recess 110 relative to the normal direction of the bottom surface 111 of the recess 110 (see Figure 4 ), for example, 30° or more, and for example, 40° or more. The tilt angle θ is defined as, for example, the average angle of the side surface 112 from the height of the bottom surface 111 of the recess 110 to the height of the edge of the recess 110 (the surface 61 of the epitaxial layer 60).

[0123] Dry etching is a conventional method for forming a recessed portion serving as a gate groove in a HEMT. However, dry etching to form this recess degrades the crystallinity of the Group III nitride that forms the bottom surface of the gate groove. Furthermore, the halogen element used in the dry etching process remains on the bottom surface of the recessed portion. This reduced crystallinity and residual halogen element lead to reduced HEMT performance.

[0124] In this embodiment, recessed portion 110 is formed by wet etching using PEC etching (and planarization etching). Therefore, the reduction in crystallinity at bottom surface 111 of recessed portion 110 due to etching is suppressed compared to the reduction in crystallinity that would be achieved using dry etching. Therefore, the band-edge peak intensity of the photoluminescence spectrum at bottom surface 111 of recessed portion 110 preferably has an intensity of 90% or greater relative to the band-edge peak intensity of the photoluminescence spectrum at surface 61 of epitaxial layer 60 (an unetched region).

[0125] Furthermore, in this embodiment, the amount of halogen elements remaining on the bottom surface 111 of the recess 110 is suppressed compared to the amount of halogen elements remaining when dry etching is used. The concentration of halogen elements caused by PEC etching (and planarization etching) as wet etching to form the recess 110 is preferably below the detection limit in, for example, secondary ion mass spectrometry (SIMS) measurement. The concentration of halogen elements (e.g., chlorine (Cl)) on the bottom surface 111 of the recess 110 is preferably less than 1×10 15 / cm 3 , more preferably less than 5×10 14 / cm 3 , more preferably less than 2×10 14 / cm 3 .

[0126] Thus, in the HEMT 200 of the present embodiment, a decrease in crystallinity and residual halogen elements caused by etching to form the recess 110 are suppressed. Therefore, a decrease in the performance of the HEMT 200 caused by etching to form the recess 110 can be suppressed.

[0127] As described above, according to this embodiment, a suitable technique for forming a recess (gate recess) 110 in a semiconductor device (HEMT) 200 formed using a group III nitride by PEC etching is provided. More specifically, recess 110 can be formed by forming barrier layer 40 with a stacked structure including i-type layer 41 and n-type layer 42, and performing PEC etching using i-type layer 41 as an etch stop layer.

[0128] <Experimental Example>

[0129] Next, an experimental example of PEC etching and planarization etching is described. In this experimental example, a wafer having the following substrate and epitaxial layer is used. As a substrate, a semi-insulating SiC substrate is used. As an epitaxial layer, the following stacked structure is formed: a nucleation layer composed of AlN; a channel layer composed of GaN with a thickness of 0.75μm; a barrier layer composed of AlGaN with a thickness of 24nm; and a cap layer composed of GaN with a thickness of 5nm. The thickness (depth) from the upper surface of the cap layer to the lower surface of the barrier layer is 29nm. As a barrier layer, the following stacked structure is formed: a lower layer (i-type layer) composed of i-type AlGaN with an Al composition of 0.22 and a thickness of 5nm; an upper layer (n-type layer) composed of n-type AlGaN with an Al composition of 0.22 and a thickness of 19nm. In this upper layer (n-type layer), as an n-type impurity, 1×10 18 / cm 3 Si is added at a concentration of 1.5-2.5 %.

[0130] On the epitaxial layer, a recess is formed by PEC etching. In PEC etching, a 0.025M K2S2O8 aqueous solution is used as an etchant, while the 2 UV light with a wavelength of 260 nm was irradiated at an intensity of 100 nm for 120 minutes. The wafer was placed at a depth of 5 mm. The mask was made of silicon oxide, and the cathode pad was made of titanium.

[0131] After the PEC etching, the bottom of the recess is flattened by planarization etching. The planarization etching is performed for 10 minutes using perhydrochloric acid (for example, a mixture of 30% HCl and 30% H2O2 at a ratio of 1:1) as an etchant.

[0132] Figure 5 (a) is a graph showing the relationship between etching time and etching depth during PEC etching. The horizontal axis represents etching time, and the vertical axis represents etching depth. From the start of etching until approximately 40 minutes, the etching depth increases in direct proportion to the etching time. After approximately 40 minutes from the start of etching, the etching depth remains constant. In other words, PEC etching automatically ceases approximately 40 minutes after the start of etching.

[0133] The difference between the PEC etching stop depth (approximately 24nm) and the depth of the lower surface of the barrier layer (denoted as "AlGaN") (29nm) is approximately 5nm. This suggests that the lower layer of the barrier layer (denoted as "i-AlGaN") serves as the etching stop layer, and that PEC etching stops near the upper surface of the lower barrier layer when the approximate total thickness of the upper layer of the barrier layer (denoted as "n-AlGaN") is removed.

[0134] A 1000 nm square area was observed using AFM for the surface of the epitaxial layer before PEC etching (hereinafter referred to as the epitaxial layer surface), the bottom surface of the recessed portion formed by PEC etching but not subjected to planarization etching (hereinafter referred to as the unplanarized bottom surface), and the bottom surface of the recessed portion subjected to planarization etching after PEC etching (hereinafter referred to as the planarized bottom surface).

[0135] Figure 5 (b) is an AFM image of the epitaxial layer surface. The arithmetic mean roughness (Ra) of the epitaxial layer surface measured by AFM is 0.14 nm. Because the epitaxial layer is desired to have high crystallinity, the Ra of the epitaxial layer surface is preferably 0.4 nm or less, more preferably 0.3 nm or less, and even more preferably 0.2 nm or less.

[0136] Figure 6 (a) is an AFM image of the unplanarized bottom surface. Protrusions are observed at locations corresponding to dislocations. The heights of the multiple protrusions distributed across the unplanarized bottom surface tend to vary. The largest protrusion is over 10 nm in height.

[0137] The Ra of the unflattened bottom surface measured by AFM is 0.22nm. The Ra of the epitaxial layer surface is, for example, 0.14nm, while the Ra of the unflattened bottom surface is, for example, 0.22nm. Although the unflattened bottom surface has a convex portion, the Ra is, for example, less than 2 times the Ra of the epitaxial layer surface and does not increase that much. The reason for this can be said to be that PEC etching is performed in a manner that makes the flat portion occupying most of the area of the unflattened bottom surface have high flatness, in other words, in a manner that the high flatness of the epitaxial layer surface is basically not damaged in the flat portion. The Ra of the unflattened bottom surface is preferably less than 0.4nm, and more preferably less than 0.3nm.

[0138] Figure 6 (b) is an AFM image of the flattened bottom surface. The convex portions observed on the unflattened bottom surface are not clearly visible on the flattened bottom surface, indicating that the bottom surfaces of the concave portions have been flattened. On the flattened bottom surface, locations presumably corresponding to convex portions, in other words, locations corresponding to dislocations, are observed as bright areas, distinct from the flattened portions.

[0139] The Ra of the flattened bottom surface measured by AFM is 0.24nm. The Ra of the unflattened bottom surface is, for example, 0.22nm. In contrast, the Ra of the flattened bottom surface is slightly larger, for example, 0.24nm. However, such a difference is believed to be an error caused by the difference in the measurement area of the unflattened bottom surface and the measurement area of the flattened bottom surface. The Ra of the unflattened bottom surface and the Ra of the flattened bottom surface are considered to be of the same degree. It can be said that it is difficult to clearly distinguish the unflattened bottom surface from the flattened bottom surface by Ra alone. It can be seen from the AFM image of the flattened bottom surface that the flatness of the flat portion is not reduced by flattening etching, but the convex portion can be selectively etched. The Ra of the flattened bottom surface is preferably less than 0.4nm, and more preferably less than 0.3nm.

[0140] The bottom surface of the resulting recess, i.e., the flattened bottom surface, has high flatness. The difference (absolute value of the difference) between the Ra of the epitaxial layer surface and the Ra of the flattened bottom surface (or the Ra of the unflattened surface) is preferably 0.2 nm or less (0 nm or more), and more preferably 0.1 nm or less.

[0141] Figure 7 This is a cross-sectional image of an epitaxial layer with a concave portion formed therein, observed by TEM. This cross-sectional image is perpendicular to the upper surface of the barrier layer and intersects with the bottom surface of the concave portion (in a manner perpendicular to the edge of the concave portion when viewed from above). Figure 7 In FIG, the channel layer is represented as “GaN”, the lower layer of the barrier layer (i-type layer) is represented as “i-AlGaN”, the upper layer of the barrier layer (n-type layer) is represented as “n-AlGaN”, and the cap layer is represented as “GaN cap”. Figure 7 The left side of the figure shows the cross-sectional image of the side surface of the concave portion. Figure 7 The right side portion shows a cross-sectional image of the bottom portion of the recess.

[0142] The flatness of the bottom surface of the recess can also be confirmed by TEM observation. A cross-sectional image of the bottom surface shows a range of approximately 35 nm (or greater than 30 nm) in length in the in-plane direction of the bottom surface. The thickness of the barrier layer (remaining thickness of the barrier layer) located below the recess was measured at five locations; four showed a value of 4.9 nm, and one showed a value of 4.8 nm. This indicates that the difference between the maximum and minimum values of the remaining thickness of the barrier layer within this range—in other words, the difference between the maximum and minimum values of the height of the bottom surface of the recess (the upper surface of the remaining thickness portion of the barrier layer) within this range—is as small as 0.1 nm, achieving high uniformity of the remaining thickness of the barrier layer, or in other words, high flatness of the recess bottom surface. Thus, within a range of greater than 30 nm along the length of the bottom surface as measured by TEM cross-sectional images of the recess bottom, the difference between the maximum and minimum values of the height of the recess bottom, or the remaining thickness of the barrier layer (maximum value minus minimum value), is preferably 0.2 nm or less, and more preferably 0.1 nm or less.

[0143] As can be seen from the cross-sectional image of the side portion, the side of the concave portion has a tapered shape that is inclined from the upper side toward the outer side of the bottom surface of the concave portion (when viewed from above). The inclination angle of the side surface is expressed as the angle of inclination from the normal direction of the bottom surface of the concave portion (refer to Figure 4 ). In this example, a change in the inclination angle is observed, such that the inclination angle of the lower portion of the side surface becomes larger (approximately 90°) than the inclination angle of the upper portion of the side surface. The inclination angle of the upper portion of the side surface is about 45°, and the inclination angle of the entire side surface averaged from the height of the bottom surface of the recess to the height of the recess edge can be said to be 45° or more. As one feature of the tapered side surface of the recess, the inclination angle can be cited, for example, 30° or more, and another example is 40° or more.

[0144] <Other implementation methods>

[0145] The embodiments of the present invention have been specifically described above. However, the present invention is not limited to the above-described embodiments, and various changes, improvements, and combinations can be made without departing from the spirit of the present invention.

[0146] For example, in the above embodiment, the cathode spacer 160 is used as at least one of the source electrode 211 and the drain electrode 213 of the HEMT 200 . However, the cathode spacer 160 may be a conductive member different from the source electrode 211 or the drain electrode 213 of the HEMT 200 .

[0147] For example, in the above embodiment, wet etching using an acidic or alkaline etching solution (non-PEC etching) is used as an example of planarization etching. In other words, chemical etching of the protrusions 182 is used. However, the principle of planarization etching is not particularly limited as long as the protrusions 182 are etched to flatten the bottom surface 111. Therefore, planarization etching can also be performed using etching based on principles other than chemical etching. A combination of etching based on multiple principles can also be used to achieve more effective planarization etching.

[0148] Planarization etching can also be performed, for example, by mechanically removing the protrusions 182. As mechanical planarization etching, for example, bubble cleaning can be used, and for example, brush cleaning can also be used. As an etching solution (cleaning solution) for bubble cleaning, for example, perhydrochloric acid illustrated in the above-mentioned embodiment can be cited. When etching the protrusions 182 with perhydrochloric acid, bubbles are generated violently. Therefore, the impact formed by the generation of bubbles can destroy and remove the protrusions 182. Perhydrochloric acid can be said to be an etching solution that chemically and mechanically etches the protrusions 182. In addition, when performing planarization etching, at least one of generating flow (motion) in the etching solution 401 and applying vibration (such as ultrasonic vibration) to the etching solution 401 can also be performed to enhance the effect of mechanically etching the protrusions 182.

[0149] For example, in the above embodiment, a method of performing planarization etching to planarize the bottom surface 111 of the recess 110 is described as follows: after the PEC etching for forming the recess 110 is completed, planarization etching may be performed before the PEC etching for forming the recess 110 is completed, in other words, when the recess 110 is formed to a certain depth, and then PEC etching may be performed again to further deepen the recess 110. In other words, the PEC etching process and the planarization etching process may be repeated alternately, and the planarization etching process may be performed multiple times as needed.

[0150] Furthermore, while the above embodiment illustrates the technique of forming a recess (gate recess) 110 in the barrier layer 40 of the HEMT 200 through PEC etching, this technique can also be used to form structures other than semiconductor devices. In other words, this technique can be applied to a stacked structure consisting of a lower layer (i-type layer) and an upper layer (n-type layer), similar to the barrier layer 40 described above, by performing PEC etching with the lower layer (i-type layer) serving as an etch stop. This technique can be widely used as a technique for obtaining a structure having a recess in the stacked structure. Furthermore, the term "recess" refers to the region within the stacked structure where PEC etching is performed.

[0151] <Preferred Embodiments of the Invention>

[0152] Hereinafter, preferred embodiments of the present invention will be described.

[0153] (Note 1)

[0154] A semiconductor device comprising:

[0155] substrate;

[0156] a group III nitride layer formed on the substrate and composed of group III nitride;

[0157] a recess formed in the group III nitride layer,

[0158] The group III nitride layer has:

[0159] channel layer;

[0160] formed on the channel layer, forming a two-dimensional electron gas blocking layer on the channel layer,

[0161] The barrier layer comprises:

[0162] a first layer composed of aluminum gallium nitride (preferably composed of i-type aluminum gallium nitride);

[0163] A second layer formed on the first layer and composed of (n-type) aluminum gallium nitride doped with n-type impurities,

[0164] The recessed portion is formed by removing all or part of the thickness of the second layer, and at least part of the thickness of the first layer is arranged below the recessed portion.

[0165] (Note 2)

[0166] The semiconductor device according to Supplementary Note 1, wherein the recess is formed by removing the entire thickness of the second layer.

[0167] (Note 3)

[0168] The semiconductor device according to Supplementary Note 2, wherein a thickness from an upper surface of the first layer to a bottom surface of the recess is 1 nm or less.

[0169] (Note 4)

[0170] The semiconductor device according to Supplementary Note 1, wherein the recess is formed by removing a portion of the thickness of the second layer.

[0171] The thickness from the bottom surface of the recess to the upper surface of the first layer is 1 nm or less.

[0172] (Note 5)

[0173] The semiconductor device according to any one of Appendixes 1 to 4, wherein the arithmetic mean roughness (Ra) of the bottom surface of the recessed portion measured by observing a 1000 nm square region of the bottom surface with an atomic force microscope is preferably 0.4 nm or less, more preferably 0.3 nm or less.

[0174] (Note 6)

[0175] A semiconductor device according to any one of Notes 1 to 5, wherein the difference between the arithmetic mean roughness (Ra) of the surface of the group III nitride layer measured by observing a 1000 nm square area of the surface with an atomic force microscope and the arithmetic mean roughness (Ra) of the bottom surface of the recessed portion measured by observing a 1000 nm square area of the bottom surface with an atomic force microscope is preferably less than 0.2 nm, and more preferably less than 0.1 nm.

[0176] (Note 7)

[0177] A semiconductor device according to any one of Notes 1 to 6, wherein when a cross section perpendicular to the upper surface of the barrier layer and intersecting the bottom surface of the recess is observed with a transmission electron microscope, the difference between the maximum and minimum values of the height of the bottom surface of the recess (the thickness of the barrier layer arranged below the recess) within a range of 30 nm or more along the bottom surface in the cross section is preferably 0.2 nm or less, and more preferably 0.1 nm or less.

[0178] (Note 8)

[0179] The semiconductor device according to any one of Supplementary Notes 1 to 7, wherein the side surface of the recess has a tapered shape with an upper side inclined toward an outer side of a bottom surface of the recess.

[0180] (Note 9)

[0181] The semiconductor device according to Supplementary Note 8, wherein an inclination angle of the side surface of the recess with respect to a normal direction of the bottom surface of the recess is 30° or more (or 40° or more).

[0182] (Note 10)

[0183] The semiconductor device according to any one of Supplementary Notes 1 to 9, wherein a band edge peak intensity of the photoluminescence spectrum of the bottom surface of the recess has an intensity of 90% or more relative to a band edge peak intensity of the photoluminescence spectrum of the surface of the Group III nitride layer.

[0184] (Note 11)

[0185] The semiconductor device according to any one of Supplementary Notes 1 to 10, wherein the concentration of the halogen element at the bottom surface of the recess is preferably less than 1×10 15 / cm 3 , more preferably less than 5×10 14 / cm 3 , further preferably less than 2×10 14 / cm 3 .

[0186] (Note 12)

[0187] The semiconductor device according to any one of Supplementary Notes 1 to 11, wherein the n-type impurity concentration of the second layer is 1×10 17 / cm 3 Above and below 1×10 19 / cm 3 .

[0188] (Note 13)

[0189] The semiconductor device according to any one of Supplementary Notes 1 to 12, wherein the Alx Ga 1－x The aluminum composition x of N is 0.1≤x≤0.3, and the Al y Ga 1－y The aluminum composition y of N is 0.1≤x≤0.3.

[0190] (Note 14)

[0191] The semiconductor device according to any one of Supplementary Notes 1 to 13, wherein the aluminum composition of the aluminum gallium nitride constituting the first layer is equal to the aluminum composition of the aluminum gallium nitride constituting the second layer.

[0192] (Note 15)

[0193] The semiconductor device according to any one of Supplementary Notes 1 to 14, wherein the thickness of the first layer is greater than or equal to 2 nm and less than or equal to 10 nm.

[0194] (Note 16)

[0195] The semiconductor device according to any one of Supplementary Notes 1 to 15, wherein the second layer has a thickness of 5 nm to 90 nm.

[0196] (Note 17)

[0197] The semiconductor device according to any one of Appendix 1 to 16, comprising a source electrode, a gate electrode, and a drain electrode,

[0198] The gate electrode is formed on the bottom surface of the recess.

[0199] (Note 18)

[0200] A method for manufacturing a semiconductor device, the semiconductor device comprising:

[0201] substrate;

[0202] a group III nitride layer formed on the substrate and composed of group III nitride;

[0203] a recess formed in the group III nitride layer,

[0204] The group III nitride layer has:

[0205] channel layer;

[0206] formed on the channel layer, forming a two-dimensional electron gas blocking layer on the channel layer,

[0207] The barrier layer has:

[0208] a first layer composed of aluminum gallium nitride (preferably composed of i-type aluminum gallium nitride);

[0209] A second layer formed on the first layer and composed of (n-type) aluminum gallium nitride doped with n-type impurities,

[0210] The recess is formed by removing all or part of the thickness of the second layer, and at least part of the thickness of the first layer is disposed below the recess, wherein:

[0211] The recess is formed by etching the second layer by photoelectrochemical etching using the first layer as an etching stopper.

[0212] (Note 19)

[0213] The method for manufacturing a semiconductor device according to Supplementary Note 18, wherein planarization etching is performed by removing protrusions that are portions not dissolved by the photoelectrochemical etching.

[0214] (Note 20)

[0215] A structure having:

[0216] A stacked structure comprising: a first layer composed of aluminum gallium nitride (preferably composed of i-type aluminum gallium nitride); and a second layer composed of aluminum gallium nitride doped with n-type impurities (n-type) formed on the first layer;

[0217] a recess formed in the stacked structure,

[0218] The recessed portion is formed by removing all or part of the thickness of the second layer, and at least part of the thickness of the first layer is arranged below the recessed portion.

[0219] (Note 21)

[0220] A method for manufacturing a structure, the structure comprising:

[0221] A stacked structure comprising: a first layer composed of aluminum gallium nitride (preferably composed of i-type aluminum gallium nitride); and a second layer composed of aluminum gallium nitride doped with n-type impurities (n-type) formed on the first layer;

[0222] a recess formed in the stacked structure,

[0223] The recess is formed by removing all or part of the thickness of the second layer, and at least part of the thickness of the first layer is disposed below the recess, wherein:

[0224] The recess is formed by etching the second layer by photoelectrochemical etching using the first layer as an etching stopper.

[0225] Explanation of symbols

[0226] 10…substrate, 20…nucleation layer, 30…channel layer, 40…barrier layer, 41…lower layer (i-type layer) (of the barrier layer), 42…upper layer (n-type layer) (of the barrier layer), 50…cap layer, 60…epitaxial layer, 61…surface (of the epitaxial layer), 62…etched area, 100…wafer, 110…recess, 111…bottom surface (of the recess), 112…side surface (of the recess), 150…etching object, 160…cathode pad, 170…mask , 181…flat portion (of the bottom surface of the concave portion), 182…convex portion (of the bottom surface of the concave portion), 200…semiconductor device (HEMT), 211…source electrode, 212…gate electrode, 213…drain electrode, 220…protective film, 230…element isolation region, 300…PEC etching device, 301…etching liquid, 310…container, 320…light source, 321…light, 400…planarization etching device, 401…etching liquid, 410…container.

Claims

1. A semiconductor device comprising: substrate; a group III nitride layer formed on the substrate and composed of group III nitride; a recess formed in the group III nitride layer, The group III nitride layer has: channel layer; formed on the channel layer, forming a two-dimensional electron gas blocking layer on the channel layer, The barrier layer has: A non-conductive first layer composed of aluminum gallium nitride; A conductive second layer formed on the first layer and made of aluminum gallium nitride doped with n-type impurities, The recess is formed by removing all or part of the thickness of the second layer, and at least part of the thickness of the first layer is disposed below the recess. The arithmetic mean roughness Ra of the bottom surface measured by observing a 1000 nm square area of the bottom surface of the recessed portion with an atomic force microscope is 0.4 nm or less.

2. The semiconductor device according to claim 1, wherein The recessed portion is formed by removing the entire thickness of the second layer.

3. The semiconductor device according to claim 2, wherein The thickness from the upper surface of the first layer to the bottom surface of the recessed portion is 1 nm or less.

4. The semiconductor device according to claim 1, wherein The recess is formed by removing a portion of the thickness of the second layer. The thickness from the bottom surface of the recess to the upper surface of the first layer is 1 nm or less.

5. The semiconductor device according to any one of claims 1 to 4, wherein The difference between the arithmetic mean roughness Ra of the surface of the group III nitride layer and the arithmetic mean roughness Ra of the bottom surface of the recess is less than 0.2 nm, wherein the arithmetic mean roughness Ra of the surface is measured by observing a 1000 nm square area of the surface of the group III nitride layer with an atomic force microscope, and the arithmetic mean roughness Ra of the bottom surface is measured by observing a 1000 nm square area of the bottom surface of the recess with an atomic force microscope.

6. The semiconductor device according to any one of claims 1 to 4, wherein When a cross section perpendicular to the upper surface of the barrier layer and intersecting the bottom of the recess is observed using a transmission electron microscope, the difference between the maximum and minimum values of the height of the bottom of the recess within a range of more than 30 nm along the bottom in the cross section is less than 0.2 nm.

7. The semiconductor device according to any one of claims 1 to 4, wherein The side surface of the recess has a tapered shape with an upper side inclined toward the outside of the bottom surface of the recess.

8. The semiconductor device according to claim 7, wherein The inclination angle of the side surface of the recessed portion with respect to the normal direction of the bottom surface of the recessed portion is greater than or equal to 30°.

9. The semiconductor device according to any one of claims 1 to 4, wherein The band edge peak intensity of the photoluminescence spectrum of the bottom surface of the recess has an intensity of 90% or more relative to the band edge peak intensity of the photoluminescence spectrum of the surface of the group III nitride layer.

10. The semiconductor device according to any one of claims 1 to 4, wherein The concentration of the halogen element at the bottom of the concave portion is less than 1×10 15 / cm 3 .

11. The semiconductor device according to any one of claims 1 to 4, wherein The aluminum composition of the aluminum gallium nitride constituting the first layer is equivalent to the aluminum composition of the aluminum gallium nitride constituting the second layer.

12. A method for manufacturing a structure, the structure comprising: A stacked structure comprising a non-conductive first layer composed of aluminum gallium nitride and a conductive second layer formed on the first layer and composed of aluminum gallium nitride to which n-type impurities are added; a recess formed in the stacked structure, The recess is formed by removing all or part of the thickness of the second layer, and at least part of the thickness of the first layer is disposed below the recess. In the method for manufacturing the structure, The recess is formed by etching the second layer by photoelectrochemical etching using the first layer as an etching stopper. Planarization etching is performed by removing the protrusions that are portions not dissolved by the photoelectrochemical etching.

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