Test circuit, method for testing hot carrier injection effect, and test device

Abstract

The embodiment of the present application provides a test circuit, a method for testing the hot carrier injection effect, and a test device. The device includes: N resistor units, which are connected in series to form a resistor string structure; a current detection unit for detecting the current flowing through the resistor string structure; a first electrode, a second electrode, a switching device, and N test electrodes, wherein the first end of the resistor string structure is electrically connected to the power supply end, the second end of the resistor string structure is electrically connected to the first electrode and the first end of the switching device respectively, and the second end of the switching device is grounded; the second ends of the N resistor units are used to be electrically connected to the gates of the N MOS devices to be tested in a one-to-one correspondence; the N test electrodes are used to be electrically connected to the drains of the N MOS devices to be tested in a one-to-one correspondence. This test circuit can measure the HCI of different gate voltages or drain voltages of multiple MOS devices to be tested at one time, thereby improving the test efficiency.

Description

Technical Field

[0001] The embodiments of the present application relate to the semiconductor field, and in particular, to a test circuit, a method for testing hot carrier injection effects, a test device, and an electronic device. Background Art

[0002] In related technologies, HCI testing of devices takes a long time, typically taking 1E+04s or even 1E+05s for a single device. Mainstream test equipment can only measure one test value per device at a time. Considering the Vg / Vd ratio under different voltage conditions and the test volume under each voltage condition, the test equipment requires a long time to complete. Summary of the Invention

[0003] The embodiments of the present application provide a test circuit, a method for testing the hot carrier injection effect, a test device and an electronic device to at least partially solve the problem in the related art that it takes a lot of time to perform HCI testing on devices, that is, the test efficiency is low.

[0004] According to one aspect of an embodiment of the present application, a device for testing the HCI of a MOS device is provided, comprising: N resistance units, wherein the N resistance units are connected in series to form a resistance string structure; a current detection unit, electrically connected to the resistance string structure, for detecting the current flowing through the resistance string structure; a first electrode, a second electrode, a switching device and N test electrodes, where N is an integer greater than or equal to 2, wherein the first end of the resistance string structure is electrically connected to a power supply end, the second end of the resistance string structure is electrically connected to the first electrode and the first end of the switching device respectively, the second end of the switching device is grounded, and the third end of the switching device is electrically connected to the second electrode; the second ends of the N resistance units are used to be electrically connected one-to-one with the gates of N MOS devices to be tested; the N test electrodes are used to be electrically connected one-to-one with the drains of the N MOS devices to be tested, and the sources and substrates of the N MOS devices to be tested are grounded.

[0005] Optionally, the test electrode includes a test pad.

[0006] Optionally, the resistance values ​​of the N resistance units are equal.

[0007] Optionally, the resistance unit includes one or more resistors.

[0008] Optionally, the switching device is one of the following: PMOS, NMOS, NPN BJT, PNP BJT.

[0009] Optionally, the MOS device to be tested is PMOS or NMOS.

[0010] According to another aspect of an embodiment of the present application, a method for testing a hot carrier injection effect is provided, comprising: applying a first voltage to a second electrode to cut off a switching device; applying a gate operating voltage to a power supply terminal and the first electrode, and simultaneously applying a drain climbing voltage to N test electrodes; applying a drain operating voltage to N test electrodes, and simultaneously applying a gate climbing voltage to the power supply terminal and the first electrode.

[0011] Optionally, after applying a drain operating voltage to the N test electrodes and applying a gate climbing voltage to the power supply terminal and the first electrode, the method further includes: applying a second voltage to the second electrode to turn on the switching device; applying a third voltage to the power supply terminal, applying a fourth voltage to the second electrode, not applying a voltage to the first electrode, and applying different drain voltages to the N test electrodes.

[0012] Optionally, the method further includes: determining a resistance value of the resistance unit.

[0013] Optionally, determining the resistance value of the resistance unit includes: applying a fifth voltage to the power supply end and simultaneously applying a sixth voltage to the first electrode; obtaining a current flowing through the resistance unit; and determining the resistance value of the resistance unit based on the fifth voltage, the sixth voltage and the current.

[0014] Optionally, after applying a third voltage to the power supply end, applying a fourth voltage to the second electrode, not applying a voltage to the first electrode, and applying different drain voltages to the N test electrodes, the method further includes: applying the first voltage to the second electrode to cut off the switching device; applying the gate operating voltage to the power supply end and the first electrode, and applying a drain climbing voltage to the N test electrodes; applying a drain operating voltage to the N test electrodes, and applying a gate climbing voltage to the power supply end and the first electrode.

[0015] According to another aspect of the embodiments of the present application, a testing device is provided, comprising any one of the above-mentioned testing circuits.

[0016] According to another aspect of the embodiments of the present application, an electronic device is provided, comprising the above-mentioned testing apparatus and N MOS devices to be tested.

[0017] Applying the technical solution of the embodiment of the present application, the test circuit includes N resistance units, the N resistance units are connected in series to form a resistance string structure, a current detection unit, a first electrode, a second electrode, a switching device and N test electrodes, the first end of the resistance string structure is electrically connected to the power supply end, the second end of the resistance string structure is electrically connected to the first electrode and the first end of the switching device respectively, the second end of the switching device is grounded, and the third end of the switching device is electrically connected to the second electrode; the second ends of the N resistance units are used to be electrically connected to the gates of the N MOS devices to be tested in a one-to-one correspondence; the N test electrodes are used to be electrically connected to the drains of the N MOS devices to be tested in a one-to-one correspondence, and the sources and substrates of the N MOS devices to be tested are grounded. When the switching device is off, a gate operating voltage is applied to the power supply terminal and the first electrode, while a drain ramping voltage is applied to N test electrodes to obtain a first drain current-drain ramping voltage curve. When the switching device is off, a drain operating voltage is applied to the N test electrodes, while a gate ramping voltage is applied to the power supply terminal and the first electrode to obtain a second drain current-gate ramping voltage curve. When the switching device is on, different acceleration voltages are applied to the gates of the N MOS devices under test by adjusting the voltages applied to the power supply terminal and the second electrode. Similarly, different acceleration voltages are applied to the drains of the N MOS devices under test. After performing HCI acceleration on the N MOS devices under test, the switching device is then controlled to be off, and the relationship between the drain current and the drain ramping voltage and the relationship between the drain current and the gate ramping voltage are re-obtained. Through these steps, degradation curves for different gate acceleration voltages and drain acceleration voltages are obtained. This allows HCI testing of multiple MOS devices under test to be performed simultaneously. This saves testing time, fully utilizes test equipment resources, and improves test equipment utilization efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The drawings that constitute part of this application are used to provide a further understanding of this application. The illustrative embodiments of this application and their descriptions are used to explain this application and do not constitute an improper limitation on this application. In the drawings:

[0019] Figure 1 shows a schematic diagram of a single device according to an embodiment of the present application;

[0020] Figure 2 shows a schematic diagram of a test circuit according to an embodiment of the present application;

[0021] Figure 3 shows a voltage waveform diagram according to an embodiment of the present application;

[0022] Figure 4 A flow chart of a method for testing HCI according to an embodiment of the present application is shown.

[0023] The above drawings include the following reference numerals:

[0024] 10. Resistor unit; 20. First electrode; 30. Second electrode; 40. MOS device to be tested; 50. Test electrode; 60. Switching device. DETAILED DESCRIPTION

[0025] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present application belongs.

[0026] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof.

[0027] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element or intervening elements may be present. Moreover, in the specification and claims, when it is described that an element is "connected to" another element, the element may be "directly connected to" the other element or "connected to" the other element through a third element.

[0028] For ease of description, some nouns or terms involved in the embodiments of the present application are explained below:

[0029] Hot Carrier Injection (HCI): As process geometries continue to shrink, the supply voltage fails to decrease proportionally with device dimensions like channel length, junction depth, and gate oxide thickness, as well as with increases in substrate doping concentration. This leads to a significant increase in the lateral and longitudinal electric fields in the channel. The high electric field accelerates carrier motion, transforming them into high-energy hot carriers. When the excess carrier energy exceeds three times the bandgap, impact ionization between the carriers and the crystal lattice becomes a major form of energy dissipation. When the carrier energy exceeds the Si-SiO2 barrier height (3.5 eV), the carriers can be injected directly or tunneled into the SiO2, causing parameters like the MOSFET's threshold voltage (Vth) and linear region transconductance (gm) to drift or degrade, impacting device reliability and ultimately leading to circuit failure. Hot carriers in MOS devices are mainly divided into channel hot carriers (CHE), substrate hot carriers (SHE), drain avalanche hot carriers (DAHC), and secondary generated hot electrons (SGHE).

[0030] In some embodiments, it takes a lot of time to perform HCI testing on a device, that is, the test efficiency is low. In order to solve the problem that it takes a lot of time to perform HCI testing on a device, that is, the test efficiency is low, the embodiments of the present application provide a test circuit, a method for testing hot carrier injection effect, a test device and an electronic device.

[0031] A typical embodiment of the present application provides a test circuit, such as Figure 2 Shown, including:

[0032] N resistor units 10, wherein the N resistor units 10 are connected in series to form a resistor string structure;

[0033] a current detection unit, electrically connected to the resistor string structure, and configured to detect a current flowing through the resistor string structure;

[0034] The first electrode 20, the second electrode 30, the switch device 60 and N test electrodes 50, N is an integer greater than or equal to 2, wherein,

[0035] A first end of the resistor string structure is electrically connected to a power supply terminal, a second end of the resistor string structure is electrically connected to the first electrode 20 and a first end of the switch device 60, respectively, a second end of the switch device 60 is grounded, and a third end of the switch device 60 is electrically connected to the second electrode 30;

[0036] The second ends of the N resistor units 10 are used to be electrically connected to the gates of the N MOS devices 40 to be tested in a one-to-one correspondence;

[0037] The N test electrodes 50 are used to be electrically connected to the drains of the N MOS devices 40 to be tested in a one-to-one correspondence, and the sources and substrates of the N MOS devices 40 to be tested are grounded.

[0038] Specifically, the switching device is one of the following: PMOS, NMOS, NPN BJT, PNP BJT.

[0039] Specifically, the MOS device to be tested is PMOS or NMOS.

[0040] Specifically, when the switch device is NMOS and the MOS device to be tested is NMOS, Figure 2 As shown, the first end of the first resistor unit 10 is electrically connected to the power supply terminal Vpower, and the Nth ( Figure 2 The second ends of the above-mentioned resistance units 10 are respectively electrically connected to the above-mentioned first electrode 20 and the drain of the switching device NMOS, the source and substrate of the switching device NMOS are grounded, and the gate of the switching device NMOS is electrically connected to the second electrode; the second ends of the four resistance units 10 are respectively electrically connected to the gate of the MOS device 40 to be tested.

[0041] Specifically, when the switch device is an NPN BJT and the MOS device to be tested is an NMOS, the first end of the first resistor unit is electrically connected to the power supply terminal Vpower, and the Nth ( Figure 2 The second end of the above-mentioned resistance unit is electrically connected to the above-mentioned first electrode and the collector of the switching device NPN BJT, respectively. The emitter of the switching device NPN BJT is grounded, and the base of the switching device NMOS is electrically connected to the second electrode; the second end of each resistance unit is used to be electrically connected to the gate of the MOS device to be tested.

[0042] Specifically, the resistance values ​​of the N above-mentioned resistance units are equal. When the switch device is turned on, Figure 2As shown, N is equal to 4. The voltage at the power supply terminal Vpower minus the voltage at the first electrode equals the divided voltage across the N resistor units connected in series. The divided voltage divided by N equals the divided voltage across each resistor unit. The voltage at the power supply terminal minus the divided voltage across the first resistor unit equals the gate voltage of the first MOS device to be tested. The voltage at the power supply terminal minus the divided voltage across the first resistor unit and the divided voltage across the second resistor unit equals the gate voltage of the second MOS device to be tested. The voltage at the power supply terminal minus the divided voltage across the first resistor unit, the divided voltage across the second resistor unit, and the divided voltage across the third resistor unit equals the gate voltage of the third MOS device to be tested. The gate voltage of the fourth MOS device to be tested equals the voltage at the first electrode 20. This allows different voltages to be applied to the gates of the N MOS devices to be tested. Similarly, different voltages can be applied directly to the N test electrodes to apply different voltages to the drains of the N MOS devices to be tested. This allows degradation curves of Idsat (saturated drain-source current) or Vt (saturated gate-source voltage) to be obtained under different gate acceleration voltages and drain acceleration voltages.

[0043] In the above scheme, the test circuit includes N resistance units, the N resistance units are connected in series to form a resistance string structure, a current detection unit, a first electrode, a second electrode, a switching device and N test electrodes, the first end of the resistance string structure is electrically connected to the power supply end, the second end of the resistance string structure is electrically connected to the first electrode and the first end of the switching device respectively, the second end of the switching device is grounded, and the third end of the switching device is electrically connected to the second electrode; the second ends of the N resistance units are used to be electrically connected to the gates of the N MOS devices to be tested in a one-to-one correspondence; the N test electrodes are used to be electrically connected to the drains of the N MOS devices to be tested in a one-to-one correspondence, and the sources and substrates of the N MOS devices to be tested are grounded. When the switching device is off, a gate operating voltage is applied to the power supply terminal and the first electrode, while a drain ramping voltage is applied to N test electrodes to obtain a first drain current-drain ramping voltage curve. When the switching device is off, a drain operating voltage is applied to the N test electrodes, while a gate ramping voltage is applied to the power supply terminal and the first electrode to obtain a second drain current-gate ramping voltage curve. When the switching device is on, different acceleration voltages are applied to the gates of the N MOS devices under test by adjusting the voltages applied to the power supply terminal and the second electrode. Similarly, different acceleration voltages are applied to the drains of the N MOS devices under test. After performing HCI acceleration on the N MOS devices under test, the switching device is then controlled to be off, and the relationship between the drain current and the drain ramping voltage and the relationship between the drain current and the gate ramping voltage are re-obtained. Through these steps, degradation curves for different gate acceleration voltages and drain acceleration voltages are obtained. This allows HCI testing of multiple MOS devices under test to be performed simultaneously. This saves testing time, fully utilizes test equipment resources, and improves test equipment utilization efficiency.

[0044] In some embodiments, for the HCI test of a single device (MOS device), the test process includes a voltage application test phase and a monitoring phase. Figure 1 As shown, in the stress test phase: the source (S) and the substrate (B) are grounded, a voltage Vg_stress is applied to the gate (G), and a voltage Vd_stress is applied to the drain (D). In the monitoring phase: the source (S) and the substrate (B) are grounded, a voltage Vg_op is applied to the gate (G), and a voltage Vd_op is applied to the drain (D). Among them, Vg_stress>Vg_op, Vd_stress>Vd_op. Then the degradation curve of Idsat (saturated drain-source current) or Vt (saturated gate-source voltage) is obtained. It takes a long time to test a single device. The use of the embodiments of the present application can save test time, make full use of the resources of the test equipment, and improve the utilization efficiency of the test equipment.

[0045] Specifically, the test electrode includes a test pad. Specifically, a voltage is applied to the test pad.

[0046] In a specific embodiment, the resistance unit includes one or more resistors, and the resistance value of the resistance unit can be set according to actual needs.

[0047] In a specific embodiment, Figure 2 and Figure 3 As shown, four resistor units 10 are resistors of the same resistance value. The four resistor units 10 are connected in series and in series with an NMOS. The main function of the NMOS is to adjust the voltage values ​​of Vg1 / Vg2 / Vg3 / Vg4. Among them, Vg1 represents the gate voltage of the first MOS device to be tested, Vg2 represents the gate voltage of the second MOS device to be tested, Vg3 represents the gate voltage of the third MOS device to be tested, and Vg4 represents the gate voltage of the fourth MOS device to be tested. The entire HCI test process is roughly divided into three stages:

[0048] 1) Initial stage

[0049] A voltage of 0 V is applied to the second electrode V_trim2 to turn off the NMOS transistor, a gate operating voltage (Vop) is applied to the power supply terminal Vpower and the first electrode Vtrim1, and a drain climbing voltage is applied to the N test electrodes to obtain a first curve, which is used to represent the relationship between the first drain current and the drain climbing voltage;

[0050] Alternatively, a drain operating voltage (Vop) is applied to the N test electrodes, and at the same time, a gate climbing voltage is applied to the power supply terminal and the first electrode to obtain a second curve, which is used to characterize the relationship between the second drain current and the gate climbing voltage.

[0051] 2) Acceleration phase

[0052] A voltage Vset is applied to the second electrode V_trim2 to turn on the NMOS tube, Vstress is applied to the power supply terminal, no voltage is applied to the first electrode Vtrim1 (Floating), and different drain voltages (Vd1 / 2 / 3 / 4) are applied to the N test electrodes.

[0053] 3) Monitoring phase

[0054] A voltage of 0 V is applied to the second electrode V_trim2 to turn off the NMOS transistor, and a gate operating voltage (Vop) is applied to the power supply terminal Vpower and the first electrode Vtrim1. At the same time, a drain climbing voltage is applied to the N test electrodes to obtain a third curve, which is used to represent the relationship between the third drain current and the drain climbing voltage;

[0055] Alternatively, a drain operating voltage (Vop) is applied to the N test electrodes, and at the same time, a gate climbing voltage is applied to the power supply terminal and the first electrode to obtain a fourth curve, which is used to characterize the relationship between the fourth drain current and the gate climbing voltage.

[0056] Another typical embodiment of the present application is as follows: Figure 4 As shown, a method for testing HCI using the above-mentioned device is provided, comprising:

[0057] Step S101, applying a first voltage to the second electrode to turn off the switching device;

[0058] Step S102, applying a gate operating voltage to the power supply terminal and the first electrode, and simultaneously applying a drain ramp voltage to the N test electrodes;

[0059] In the above steps, a first curve is obtained by applying a gate operating voltage to the power supply terminal and the first electrode and applying a drain climbing voltage to the N test electrodes. The first curve is used to represent the relationship between the first drain current and the drain climbing voltage.

[0060] Step S103: applying a drain operating voltage to the N test electrodes, and at the same time, applying a gate climbing voltage to the power supply terminal and the first electrode.

[0061] In the above steps, a second curve is obtained by applying a drain operating voltage to N test electrodes and applying a gate climbing voltage to the power supply end and the first electrode. The second curve is used to characterize the relationship between the second drain current and the gate climbing voltage.

[0062] Specifically, if Figure 2As shown, when the switching device is NMOS, the first voltage is equal to 0V, and when the switching device is PMOS, the first voltage is equal to the turn-on voltage of PMOS. The gate operating voltage Vg_op is applied to the power supply terminal Vpower and the first electrode V_trim1, so that the voltage on the gate of the MOS device to be tested is Vg_op, and at the same time, the same drain climbing voltage is applied to Vd1, Vd2, Vd3, and Vd4 to obtain Id-Vd (first curve); similarly, the same drain operating voltage Vd_op is applied to Vd1, Vd2, Vd3, and Vd4, and the gate climbing voltage is applied to the power supply terminal Vpower and the first electrode V_trim1, to obtain the second curve Id-Vg.

[0063] In the above scheme, when the switching device is turned off, the relationship between the first drain current and the drain climbing voltage is obtained by applying a gate operating voltage to the power supply terminal and the first electrode, and at the same time, applying a drain climbing voltage to N test electrodes; the relationship between the second drain current and the gate climbing voltage is obtained by applying a drain operating voltage to N test electrodes and at the same time, applying a gate climbing voltage to the power supply terminal and the first electrode.

[0064] In one embodiment, after applying a drain operating voltage to N test electrodes and applying a gate ramp voltage to the power supply terminal and the first electrode, the method further includes: applying a second voltage to the second electrode to turn on the switching device; applying a third voltage to the power supply terminal, applying a fourth voltage to the second electrode, and not applying a voltage to the first electrode (i.e., in a floating state), while applying different drain voltages to the N test electrodes. That is, when the switching device is turned on, by adjusting the voltages on the power supply terminal and the second electrode, the voltage on the gate of the MOS device to be tested reaches the desired acceleration voltage. Similarly, different drain acceleration voltages can be applied to the drains of multiple MOS devices to be tested.

[0065] In one embodiment, the method further includes: determining a resistance value of the resistance unit.

[0066] In one embodiment, determining the resistance of the resistor unit includes: applying a fifth voltage to the power supply terminal and simultaneously applying a sixth voltage to the first electrode; obtaining a current flowing through the resistor unit; and determining the resistance of the resistor unit based on the fifth voltage, the sixth voltage, and the current. Subtracting the sixth voltage from the fifth voltage yields a voltage difference, dividing the voltage difference by the current yields a total resistance of N resistor units, and dividing the total resistance by N yields a resistance of each resistor.

[0067] In one embodiment, after applying a third voltage to the power supply terminal, a fourth voltage to the second electrode, no voltage to the first electrode, and applying different drain voltages to N test electrodes, the method further includes: applying the first voltage to the second electrode to turn off the switching device; applying the gate operating voltage to the power supply terminal and the first electrode, and simultaneously applying a drain ramping voltage to the N test electrodes, to obtain a third curve representing the relationship between the third drain current and the drain ramping voltage; or applying the drain operating voltage to the N test electrodes, and simultaneously applying a gate ramping voltage to the power supply terminal and the first electrode, to obtain a fourth curve representing the relationship between the fourth drain current and the gate ramping voltage. That is, after the acceleration phase, the HCI monitoring phase is entered, and Id-Vd and Id-Vg are re-obtained. By comparing the Id-Vd and Id-Vg values ​​obtained in the initial phase and the monitoring phase, degradation curves of Idsat (saturated drain-source current) or Vt (saturated gate-source voltage) for different gate acceleration voltages and drain acceleration voltages can be obtained.

[0068] Another typical embodiment of the present application provides a testing device, comprising any one of the above-mentioned testing circuits.

[0069] Another typical embodiment of the present application provides an electronic device comprising any of the above-mentioned test devices and N MOS devices to be tested. In the electronic device, when a switching device is turned off, a gate operating voltage is applied to a power supply terminal and a first electrode, and a drain climbing voltage is applied to the N test electrodes, to obtain a first drain current-drain climbing voltage curve; when the switching device is turned off, a drain operating voltage is applied to the N test electrodes, and a gate climbing voltage is applied to the power supply terminal and the first electrode, to obtain a second drain current-gate climbing voltage curve; when the switching device is turned on, different acceleration voltages are applied to the gates of the N MOS devices to be tested by adjusting the voltages applied to the power supply terminal and the second electrode, and similarly, different acceleration voltages are applied to the drains of the N MOS devices to be tested; after performing HCI acceleration on the N MOS devices to be tested, the switching device is controlled to be turned off, and the relationship between the drain current and the drain climbing voltage and the relationship between the drain current and the gate climbing voltage are re-obtained. Through the above steps, degradation curves for different gate acceleration voltages and drain acceleration voltages are obtained. That is, HCI tests can be performed on multiple MOS devices to be tested at one time, which saves test time, fully utilizes the resources of the test equipment, and improves the utilization efficiency of the test equipment.

[0070] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0071] 1) The test circuit of the embodiment of the present application includes N resistance units, the N resistance units are connected in series to form a resistance string structure, a current detection unit, a first electrode, a second electrode, a switching device and N test electrodes, the first end of the resistance string structure is electrically connected to the power supply end, the second end of the resistance string structure is electrically connected to the first electrode and the first end of the switching device respectively, the second end of the switching device is grounded, and the third end of the switching device is electrically connected to the second electrode; the second ends of the N resistance units are used to be electrically connected to the gates of the N MOS devices to be tested in a one-to-one correspondence; the N test electrodes are used to be electrically connected to the drains of the N MOS devices to be tested in a one-to-one correspondence, and the sources and substrates of the N MOS devices to be tested are grounded. When the switching device is off, a gate operating voltage is applied to the power supply terminal and the first electrode, while a drain ramping voltage is applied to N test electrodes to obtain a first drain current-drain ramping voltage curve. When the switching device is off, a drain operating voltage is applied to the N test electrodes, while a gate ramping voltage is applied to the power supply terminal and the first electrode to obtain a second drain current-gate ramping voltage curve. When the switching device is on, different acceleration voltages are applied to the gates of the N MOS devices under test by adjusting the voltages applied to the power supply terminal and the second electrode. Similarly, different acceleration voltages are applied to the drains of the N MOS devices under test. After performing HCI acceleration on the N MOS devices under test, the switching device is then controlled to be off, and the relationship between the drain current and the drain ramping voltage and the relationship between the drain current and the gate ramping voltage are re-obtained. Through these steps, degradation curves for different gate acceleration voltages and drain acceleration voltages are obtained. This allows HCI testing of multiple MOS devices under test to be performed simultaneously. This saves testing time, fully utilizes test equipment resources, and improves test equipment utilization efficiency.

[0072] 2) The method for testing the HCI of the MOS device in an embodiment of the present application, when the switching device is turned off, is to apply a gate operating voltage to the power supply terminal and the first electrode, and at the same time, apply a drain climbing voltage to N test electrodes, thereby obtaining a relationship between the first drain current and the drain climbing voltage; and is to apply a drain operating voltage to N test electrodes, and at the same time, apply a gate climbing voltage to the power supply terminal and the first electrode, thereby obtaining a relationship between the second drain current and the gate climbing voltage.

[0073] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A test circuit, characterized in that: include: N resistance units, wherein the N resistance units are connected in series to form a resistance string structure; a current detection unit, electrically connected to the resistor string structure, and configured to detect a current flowing through the resistor string structure; a first electrode, a second electrode, a switching device, and N test electrodes, where N is an integer greater than or equal to 2, wherein: A first end of a first resistor unit in the resistor string structure is electrically connected to a power supply terminal, a second end of a last resistor unit in the resistor string structure is electrically connected to the first electrode and the first end of the switching device respectively, a second end of the switching device is grounded, and a third end of the switching device is electrically connected to the second electrode; The second ends of the N resistor units are used to be electrically connected to the gates of the N MOS devices to be tested in a one-to-one correspondence; The N test electrodes are used to be electrically connected to the drains of the N MOS devices to be tested in a one-to-one correspondence, and the sources and substrates of the N MOS devices to be tested are grounded.

2. The circuit according to claim 1, wherein: The test electrode includes a test pad.

3. The circuit according to claim 1, wherein: The resistance values ​​of the N resistance units are equal.

4. The circuit according to any one of claims 1 to 3, characterized in that The resistance unit includes one or more resistors.

5. The circuit according to any one of claims 1 to 3, characterized in that The switching device is one of the following: PMOS, NMOS, NPN BJT, PNP BJT.

6. The circuit according to any one of claims 1 to 3, characterized in that The MOS device to be tested is PMOS or NMOS.

7. A method for testing hot carrier injection effect using the circuit according to any one of claims 1 to 6, characterized in that: include: Applying a first voltage to the second electrode to turn off the switching device; Applying a gate operating voltage to the power supply terminal and the first electrode, and applying a drain climbing voltage to the N test electrodes; Applying a drain operating voltage to the N test electrodes, and at the same time, applying a gate climbing voltage to the power supply terminal and the first electrode; After applying a drain operating voltage to the N test electrodes and applying a gate ramp voltage to the power supply terminal and the first electrode, the method further includes: Applying a second voltage to the second electrode to turn on the switching device; A third voltage is applied to the power supply terminal, a fourth voltage is applied to the second electrode, no voltage is applied to the first electrode, and different drain voltages are applied to the N test electrodes.

8. The method according to claim 7, characterized in that The method further comprises: The resistance value of the resistance unit is determined.

9. The method according to claim 8, characterized in that Determining the resistance value of the resistance unit includes: applying a fifth voltage to the power supply terminal and simultaneously applying a sixth voltage to the first electrode; obtaining a current flowing through the resistance unit; The resistance value of the resistance unit is determined according to the fifth voltage, the sixth voltage, and the current.

10. The method according to claim 7, characterized in that After applying a third voltage to the power supply terminal, applying a fourth voltage to the second electrode, and applying no voltage to the first electrode, and applying different drain voltages to the N test electrodes, the method further includes: applying the first voltage to the second electrode to turn off the switching device; Applying the gate operating voltage to the power supply terminal and the first electrode, and applying a drain climbing voltage to the N test electrodes; A drain operating voltage is applied to the N test electrodes, and at the same time, a gate climbing voltage is applied to the power supply terminal and the first electrode.

11. A testing device, characterized in that: The test circuit comprises the test circuit according to any one of claims 1 to 6.

12. An electronic device, characterized in that: The device comprises the test device according to claim 11 and N MOS devices to be tested.

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