Data processing devices, data processing methods and related products

Abstract

This disclosure discloses a data processing apparatus, a data processing method, and related products. The data processing apparatus can be implemented as a computing device included in a combined processing device, which may further include an interface device and other processing devices. The computing device interacts with the other processing devices to jointly complete user-specified computational operations. The combined processing device may also include a storage device connected to both the computing device and the other processing devices to store data from them. The disclosed solution provides an instruction set involving tensor data, which can increase processing flexibility and improve machine processing efficiency.

Description

Technical Field

[0001] This disclosure relates to the field of processors, and in particular to a data processing device, a data processing method, a chip, and a board. Background Technology

[0002] The instruction set is the interface between computer software and hardware, and a crucial part of the computer system architecture. With the continuous development of artificial intelligence technology, the amount and dimensionality of data to be processed are constantly increasing. Therefore, how to rationally and scientifically design instructions that provide sufficient information while saving storage space, shortening instruction fetch time, and improving machine performance is a significant issue in instruction design. Summary of the Invention

[0003] To address one or more of the technical problems mentioned above, this disclosure proposes an instruction set involving tensor data in several aspects. This instruction set increases processing flexibility, thereby improving machine processing efficiency.

[0004] In a first aspect, this disclosure provides a data processing apparatus, including a control unit, an address calculation unit, and an execution unit, wherein: the control unit is configured to acquire a decoded processing instruction, the processing instruction including an opcode and operands, the operands including at least one flag bit for indicating the information source for calculating a data address during the execution of the processing instruction; the address calculation unit is configured to calculate the data address using the corresponding information source according to the indication of the flag bit; and the execution unit is configured to execute the processing instruction according to the data address and the opcode.

[0005] In a second aspect, this disclosure provides a chip that includes the data processing apparatus of any of the embodiments of the first aspect.

[0006] In a third aspect, this disclosure provides a board including the chip of any of the embodiments of the second aspect above.

[0007] In a fourth aspect, this disclosure provides a data processing method, the method comprising: acquiring a decoded processing instruction, the processing instruction including an opcode and operands, the operands including at least one flag bit for indicating the information source for calculating a data address during the execution of the processing instruction; calculating the data address using the corresponding information source according to the indication of the flag bit; and executing the processing instruction according to the data address and the opcode.

[0008] By using the data processing apparatus, data processing method, chip, and board provided above, the embodiments disclosed herein add at least one instruction field to the instruction to identify the source of address calculation during instruction execution, thereby increasing processing flexibility and improving machine processing efficiency. Attached Figure Description

[0009] The above and other objects, features, and advantages of exemplary embodiments of this disclosure will become readily apparent upon reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of this disclosure are illustrated by way of example and not limitation, and like or corresponding reference numerals denote like or corresponding portions wherein:

[0010] Figure 1 A schematic diagram of a data storage space according to an embodiment of this disclosure is shown;

[0011] Figure 2 A schematic diagram of data blocks in a data storage space according to an embodiment of this disclosure is shown;

[0012] Figure 3 A schematic block diagram of a data processing apparatus according to an embodiment of this disclosure is shown;

[0013] Figure 4 A schematic flowchart illustrating a data processing method according to an embodiment of this disclosure is shown;

[0014] Figure 5 A structural diagram of a combined processing apparatus according to an embodiment of the present disclosure is shown; and

[0015] Figure 6 A schematic diagram of the structure of a board card according to an embodiment of this disclosure is shown. Detailed Implementation

[0016] The technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0017] It should be understood that the terms "first," "second," "third," and "fourth," etc., that may be used in the claims, specification, and drawings of this disclosure are used to distinguish different objects, not to describe a specific order. The terms "comprising" and "including" as used in the specification and claims of this disclosure indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or collections thereof.

[0018] It should also be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this disclosure. As used in this disclosure and claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this disclosure and claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations.

[0019] As used in this specification and claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [described condition or event] is detected," or "in response to detection of [described condition or event]."

[0020] Computers process various types of data by executing instructions. To indicate the source of the data, the destination of the operation's result, and the operation performed, an instruction typically contains the following information:

[0021] (1) Operation Code (OP): This code represents the operation to be performed by the instruction (e.g., addition, subtraction, multiplication, division, data transfer, etc.). It specifically describes the nature and function of the operation. A computer may have dozens to hundreds of instructions, and each instruction has a corresponding opcode. The computer performs different operations by recognizing the opcode.

[0022] (2) Operands, used to describe the operands of the instruction. Operands may involve the data type, memory address, addressing mode, etc. of the operand. Operands can directly specify the operand, or indicate the memory address or register address (i.e., register name) of the operand.

[0023] Traditional processor instructions are designed to perform basic single-data scalar operations. Here, a single-data scalar operation means that each operand of the instruction is a scalar data item. However, with the development of artificial intelligence, tasks such as image processing and pattern recognition often involve operands of multi-dimensional vector data (i.e., tensor data). Using only scalar operations is insufficient for the hardware to efficiently complete these computational tasks. Furthermore, due to the multi-dimensional nature of tensor data, sometimes it is only necessary to operate on a portion of the tensor data, rather than the entire tensor. Therefore, how to efficiently perform multi-dimensional tensor data processing is a pressing problem in the field of computing.

[0024] In the embodiments disclosed herein, an instruction system is provided in which at least one instruction field is added to the operands of a processing instruction to indicate the source of information for calculating the data address during the execution of the processing instruction. By adding an instruction field to indicate the source of information for calculating the data address, the data object operated on by the processing instruction can be indicated more flexibly. For example, the instruction field can indicate whether the data being operated on is the entire tensor data or a portion of the tensor data. Thus, by configuring the new instruction field, the software-side programming method can be made more flexible and efficient.

[0025] This instruction field can be a flag indicating either the source of information from the following sources: the parameters of the processing instruction; or the parameters of a descriptor within the processing instruction, where the descriptor indicates information about the tensor data associated with the processing instruction. In other words, this flag identifies whether address calculation during instruction execution uses information from the instruction (the instruction's parameters) or information from the descriptor (the descriptor's parameters). The flag can be either "0" or "1". For example, a flag value of "0" indicates that the instruction's parameters are used; a flag value of "1" indicates that the descriptor's parameters are used; and vice versa.

[0026] In some embodiments disclosed herein, the flag bit can indicate the source of information used to calculate the data address at different granularities. Due to the multidimensional nature of tensor data, sometimes it is necessary to operate on the entire tensor data, and sometimes only a portion of the data needs to be operated on. Therefore, the source of information used to calculate the data address can be indicated at different granularities according to the operational needs. In the embodiments disclosed herein, the granularity can be the entire tensor data, one or more dimensions of the tensor data, parameters of the entire tensor, or parameters of one or more dimensions of the tensor data, etc.

[0027] The following description uses a tensor addition operation instruction as an example, providing examples of flag indications at various granularities. The decoded tensor addition operation instruction includes the opcode `Add` and operands. The operands involve at least three tensors: input tensor 1, input tensor 2, and output tensor. These tensors are three-dimensional data and can be indicated by corresponding descriptors. The information used to compute the data addresses of these tensors can include various parameters, which we can assume to be parameters A and B. These parameters may be included as arguments in the processing instruction or as parameters in the corresponding descriptor of the processing instruction.

[0028] In one possible implementation, the flags can indicate the source of information about the data addresses used to compute the entire tensor data. In this implementation, the flags could, for example, indicate the source of information about the data addresses of the individual tensor data involved in the processing instruction.

[0029] Taking the tensor addition operation instruction above as an example, in this implementation, the tensor addition operation instruction can have the following instruction field added:

[0030] Input tensor 1 flag; Input tensor 2 flag; Output tensor flag.

[0031] These flags are used to indicate the source of information for calculating the data addresses of each tensor. For example, whether the address calculation uses information from the tensor addition operation instruction (the instruction's parameters) or information from the respective descriptors (e.g., the parameters of the descriptor for input tensor 1, the parameters of the descriptor for input tensor 2, and the parameters of the descriptor for the output tensor).

[0032] In another possible implementation, the flags can indicate the source of information used to compute the data addresses of each dimension of the tensor data. Continuing with the tensor addition operation instruction above as an example, in this implementation, the tensor addition operation instruction could, for example, have the following instruction field added:

[0033] Input the flags for dimension 1 of tensor 1; input the flags for dimension 2 of tensor 1; input the flags for dimension 3 of tensor 1;

[0034] Input the flags for the first dimension of the 2-dimensional tensor; Input the flags for the second dimension of the 2-dimensional tensor; Input the flags for the third dimension of the 2-dimensional tensor;

[0035] Output the flags for tensor dimension 1; output the flags for tensor dimension 2; output the flags for tensor dimension 3.

[0036] These flags are used to indicate the source of information for the data addresses of each dimension of the tensor. By using flags at the tensor dimension level, the data operated on by the instructions can also be accessed based on this dimension level, thereby increasing processing flexibility.

[0037] In another possible implementation, the flag bit can indicate the source of information for the different parameters used to calculate the data address. The parameters used to calculate the data address can include parameters of different forms, which may include, for example, at least one of the following: the offset of the entire or partial storage area of ​​the tensor data; and the size of the entire or partial storage area of ​​the tensor data. The meaning of each parameter will be described in detail below with reference to the accompanying drawings.

[0038] Taking the tensor addition operation instruction above as an example, in this implementation, the tensor addition operation instruction can have the following instruction field added:

[0039] Input the flag bits of parameter A in tensor 1; input the flag bits of parameter B in tensor 1;

[0040] Input the flag bits for parameter A in tensor 2; input the flag bits for parameter B in tensor 2;

[0041] Output the flags of parameter A in the tensor; output the flags of parameter B in the tensor.

[0042] These flags are used to indicate the source of information for the parameters used to calculate the data addresses of each tensor. In these implementations, the objects of the instruction operations can be flexibly set according to the parameters used to calculate the data addresses. In the example above, parameter A could be, for example, an offset, and parameter B could be, for example, a size.

[0043] In another possible implementation, the flags can indicate the source of information for different parameters used to compute the data addresses of each dimension of the tensor data. In this implementation, the source of information for the computed data addresses can be set from both the tensor data dimensions and the parameters of the computed addresses.

[0044] Taking the tensor addition operation instruction above as an example, in this implementation, the tensor addition operation instruction can have the following instruction field added:

[0045] Input the flag bits of parameter A in dimension 1 of tensor 1; input the flag bits of parameter B in dimension 1 of tensor 1;

[0046] Input the flag bits of parameter A in dimension 2 of tensor 1; input the flag bits of parameter B in dimension 2 of tensor 1;

[0047] Input the flag bits of parameter A in tensor 1 with dimension 3; input the flag bits of parameter B in tensor 1 with dimension 3;

[0048] Input the flag bits of parameter A in the 2-dimensional 1-dimensional tensor; input the flag bits of parameter B in the 2-dimensional 1-dimensional tensor;

[0049] Input the flag bits of parameter A in the 2-dimensional tensor; input the flag bits of parameter B in the 2-dimensional tensor.

[0050] Input the flag bits of parameter A in the 2-dimensional, 3-dimensional tensor; input the flag bits of parameter B in the 2-dimensional, 3-dimensional tensor;

[0051] Output the flags of parameter A in the first dimension of the tensor; output the flags of parameter B in the first dimension of the tensor.

[0052] Output the flags of parameter A in tensor dimension 2; output the flags of parameter B in tensor dimension 2;

[0053] Output the flags of parameter A in the 3rd dimension of the tensor; output the flags of parameter B in the 3rd dimension of the tensor.

[0054] Those skilled in the art will understand that although the various features are described individually in various implementations, these features can be combined in various ways without conflict, and this remains within the scope of this disclosure. For example, the flags of various granularities mentioned above can be used in arbitrary combinations, such as identifying the source of information for the data addresses of each dimension of input tensor 1 and input tensor 2 respectively, and identifying the source of information for the entire data address of the output tensor. Those skilled in the art can construct various combined implementation methods based on the disclosure of this material.

[0055] As described above, the embodiments disclosed herein provide an instruction system in which at least one flag bit is included in the operands of the instruction. This flag bit allows for flexible setting of the information source used to calculate data addresses during instruction execution, thereby enabling more flexible indication of the data object operated on by the processing instruction and facilitating a more flexible and efficient programming approach on the software side. Various possible implementations of descriptors for indicating tensor data information will now be described in detail with reference to the accompanying drawings.

[0056] Tensors can contain various forms of data composition. Tensors can be of different dimensions; for example, a scalar can be considered a 0-dimensional tensor, a vector a 1-dimensional tensor, and a matrix a 2-dimensional or higher tensor. The shape of a tensor includes information such as its dimensions and the size of each dimension. For example, for a 3D tensor:

[0057] x3=[[[1,2,3],[4,5,6]];[[7,8,9],[10,11,12]]]

[0058] The shape or dimensions of this tensor can be represented as X3 = (2, 2, 3), meaning that the tensor is a three-dimensional tensor indicated by three parameters, with the first dimension having a size of 2, the second dimension having a size of 2, and the third dimension having a size of 3. When storing tensor data in memory, the shape of the tensor data cannot be determined based on its data address (or storage area), and consequently, the relationships between multiple tensor data cannot be determined, resulting in low processor efficiency in accessing tensor data.

[0059] In one possible implementation, a descriptor can be used to indicate the shape of N-dimensional tensor data, where N is a positive integer, such as N = 1, 2, or 3, or zero. The three-dimensional tensor in the example above can be represented by the descriptor (2, 2, 3). It should be noted that this disclosure does not impose any restrictions on how the descriptor indicates the shape of the tensor.

[0060] In one possible implementation, the value of N can be determined based on the dimension (also known as the order) of the tensor data, or it can be set according to the needs of using the tensor data. For example, when N is 3, the tensor data is three-dimensional, and the descriptor can be used to indicate the shape (e.g., offset, size, etc.) of the three-dimensional tensor data in the three dimensions. It should be understood that those skilled in the art can set the value of N according to actual needs, and this disclosure does not limit this.

[0061] Although tensor data can be multidimensional, because the layout of memory is always one-dimensional, there is a correspondence between tensors and their storage in memory. Tensor data is typically allocated in contiguous storage space, meaning that tensor data can be expanded in one dimension (e.g., row-major order) and stored in memory.

[0062] The relationship between a tensor and its underlying storage can be represented by the dimension offset, dimension size, and dimension stride. The dimension offset refers to the offset relative to a reference position within that dimension. The dimension size refers to the number of elements in that dimension. The dimension stride refers to the interval between adjacent elements within that dimension. For example, the stride of the three-dimensional tensor above is (6, 3, 1), meaning the stride of the first dimension is 6, the stride of the second dimension is 3, and the stride of the third dimension is 1.

[0063] Figure 1 A schematic diagram of a data storage space according to an embodiment of this disclosure is shown. Figure 1 As shown, data storage space 21 stores two-dimensional data in row-major order, which can be represented by (x, y) (where the X-axis is horizontal to the right and the Y-axis is vertical downwards). The size in the X-axis direction (size of each row, or total number of columns) is ori_x (not shown in the figure), and the size in the Y-axis direction (total number of rows) is ori_y (not shown in the figure). The starting address PA_start (base address) of data storage space 21 is the physical address of the first data block 22. Data block 23 is a portion of the data in data storage space 21. Its offset 25 in the X-axis direction is denoted as offset_x, its offset 24 in the Y-axis direction is denoted as offset_y, its size in the X-axis direction is denoted as size_x, and its size in the Y-axis direction is denoted as size_y.

[0064] In one possible implementation, when using a descriptor to define data block 23, the data reference point of the descriptor can be the first data block of data storage space 21, and the reference address of the descriptor can be agreed to be the starting address PA_start of data storage space 21. Then, the content of the descriptor of data block 23 can be determined by combining the size of data storage space 21 on the X-axis (ori_x), the size of data storage space 21 on the Y-axis (ori_y), and the offsets of data block 23 on the Y-axis (offset_y), X-axis (offset_x), X-axis (size_x), and Y-axis (size_y).

[0065] In one possible implementation, the content of the descriptor can be represented using the following formula (1):

[0066]

[0067] It should be understood that although the content of the descriptor in the above example represents a two-dimensional space, those skilled in the art can set the specific dimension represented by the content of the descriptor according to the actual situation, and this disclosure does not limit this.

[0068] In one possible implementation, the reference address of the data reference point of the descriptor in the data storage space can be agreed upon. Based on the reference address, the content of the tensor data descriptor is determined according to the positions of at least two vertices at diagonal positions in N dimensional directions relative to the data reference point.

[0069] For example, the base address PA_base of the data reference point in the data storage space can be agreed upon. For instance, a piece of data (e.g., data at position (2, 2)) can be selected in data storage space 21 as the data reference point, and the physical address of that data in the data storage space can be used as the base address PA_base. The position of the two diagonally opposite vertices relative to the data reference point can be used to determine... Figure 1 The contents of the descriptor for data block 23 are determined first. This involves identifying the positions of at least two diagonal vertices of data block 23 relative to the data reference point. For example, the positions of the diagonal vertices from the top left to the bottom right relative to the data reference point are used, where the relative positions of the top left vertex are (x_min, y_min) and the bottom right vertex are (x_max, y_max). Then, the contents of the descriptor for data block 23 can be determined based on the reference address PA_base, the relative positions of the top left and bottom right vertices (x_min, y_min), and (x_max, y_max).

[0070] In one possible implementation, the contents of the descriptor (based on the base address PA_base) can be represented using the following formula (2):

[0071]

[0072] It should be understood that although the above example uses the top left and bottom right corners as the two diagonal vertices to determine the content of the descriptor, those skilled in the art can set the specific vertices of at least two diagonal vertices according to actual needs, and this disclosure does not limit this.

[0073] In one possible implementation, the content of the tensor data descriptor can be determined based on the reference address of the descriptor's data reference point in the data storage space, and the mapping relationship between the data description location and the data address of the tensor data indicated by the descriptor. The mapping relationship between the data description location and the data address can be set according to actual needs. For example, when the tensor data indicated by the descriptor is three-dimensional spatial data, the function f(x, y, z) can be used to define the mapping relationship between the data description location and the data address.

[0074] In one possible implementation, the content of the descriptor can be represented using the following formula (3):

[0075]

[0076] In one possible implementation, the descriptor is also used to indicate the address of N-dimensional tensor data, wherein the content of the descriptor also includes at least one address parameter representing the address of the tensor data, for example, the content of the descriptor can be the following equation (4):

[0077]

[0078] PA is the address parameter. The address parameter can be a logical address or a physical address. When resolving the descriptor, PA can be any one of the vertices, midpoints, or preset points of the vector shape, combined with the shape parameters in the X and Y directions to obtain the corresponding data address.

[0079] In one possible implementation, the address parameter of the tensor data includes the reference address of the data reference point of the descriptor in the data storage space of the tensor data, and the reference address includes the starting address of the data storage space.

[0080] In one possible implementation, the descriptor may also include at least one address parameter representing the address of the tensor data, for example, the content of the descriptor may be the following equation (5):

[0081]

[0082] PA_start is the base address parameter, which will not be elaborated further.

[0083] It should be understood that those skilled in the art can set the mapping relationship between data description location and data address according to the actual situation, and this disclosure does not impose any restrictions on this.

[0084] In one possible implementation, a pre-defined base address can be set within a task. All descriptors in instructions within this task use this base address, and the descriptor content can include shape parameters based on this base address. This base address can be determined by setting environment parameters for this task. For a description and usage of the base address, please refer to the above embodiments. In this implementation, the descriptor content can be mapped to data addresses more quickly.

[0085] In one possible implementation, the base address can be included in the content of each descriptor, allowing each descriptor to have a different base address. Compared to using environment parameters to set a common base address, this approach allows descriptors to describe data more flexibly and utilize a larger data address space.

[0086] In one possible implementation, the data address in the data storage space corresponding to the operand of the processing instruction can be determined based on the content of the descriptor. The calculation of the data address is automatically performed by the hardware, and the calculation method will differ depending on the representation of the descriptor content. This disclosure does not limit the specific calculation method of the data address.

[0087] For example, if the content of the descriptor in the operand is represented using formula (1), and the offsets of the tensor data indicated by the descriptor in the data storage space are offset_x and offset_y respectively, and the size is size_x*size_y, then the starting data address PA1 of the tensor data indicated by the descriptor in the data storage space is... (x,y) The following formula (6) can be used to determine it:

[0088] PA1 (x,y) =PA_start+(offset_y-1)*ori_x+offset_x (6)

[0089] The data starting address PA1 is determined according to the above formula (6). (x,y) By combining the offsets offset_x and offset_y, as well as the storage area sizes size_x and size_y, the storage area of ​​the tensor data indicated by the descriptor in the data storage space can be determined.

[0090] In one possible implementation, when the operand also includes a data description location for the descriptor, the data address of the corresponding data in the data storage space can be determined based on the content of the descriptor and the data description location. In this way, a portion (e.g., one or more data items) of the tensor data indicated by the descriptor can be processed.

[0091] For example, the content of the descriptor in the operand is represented using formula (2), the tensor data indicated by the descriptor has offsets of offset_x and offset_y in the data storage space, and the size is size_x*size_y. The data description position of the descriptor included in the operand is (x q y q If the tensor data indicated by the descriptor is located at the data storage address PA2, then... (x,y) The following formula (7) can be used to determine it:

[0092] PA2 (x,y) =PA_start+(offset_y+y q -1)*ori_x+(offset_x+x q (7)

[0093] In one possible implementation, a descriptor can indicate chunks of data. Data chunking can effectively speed up computation and improve processing efficiency in many applications. For example, in graphics processing, convolution operations often use data chunking for fast processing.

[0094] Figure 2 This diagram illustrates data blocks in a data storage space according to embodiments of this disclosure. Figure 2 As shown, data storage space 200 also uses a row-major approach to store two-dimensional data, which can be represented by (x, y) (where the X-axis is horizontal to the right and the Y-axis is vertical downwards). The dimension along the X-axis (the dimension of each row, or the total number of columns) is ori_x (not shown in the figure), and the dimension along the Y-axis (the total number of rows) is ori_y (not shown in the figure). Unlike Figure 1 tensor data, Figure 2 The tensor data stored in it consists of multiple data blocks.

[0095] In this case, the descriptor needs more parameters to represent these data tiles. Taking the X-axis (X dimension) as an example, it can involve the following parameters: ori_x, x.tile.size (size in the tile 202), x.tile.stride (stride in the tile 204, i.e., the distance between the first point of the first tile and the first point of the second tile), x.tile.num (number of tiles, ... Figure 2The diagram shows three blocks), x.stride (the overall stride, i.e., the distance from the first point in the first row to the first point in the second row), etc. Other dimensions can similarly include corresponding parameters.

[0096] In one possible implementation, the descriptor may also indicate compression information for the associated tensor data. For example, the descriptor may include a compression flag, such as `compress_en`, which indicates whether the associated tensor data is compressed. Optionally or additionally, the descriptor may also indicate the compression or encoding method used. For example, the descriptor may record the compression method `compress_base`.

[0097] In one possible implementation, the descriptor may include an identifier and / or content. The identifier is used to distinguish descriptors; for example, the identifier may be a number. The content may include at least one shape parameter representing the shape of the tensor data. For example, if the tensor data is 3-dimensional, and the shape parameters of two of its three dimensions are fixed, the content of its descriptor may include the shape parameter representing the other dimension of the tensor data.

[0098] In one possible implementation, the identifier and / or content of the descriptor can be stored in descriptor storage space (internal memory), such as registers, on-chip SRAM, or other media caches. The tensor data indicated by the descriptor can be stored in data storage space (internal or external memory), such as on-chip cache or under-chip memory. This disclosure does not limit the specific location of the descriptor storage space or the data storage space.

[0099] In one possible implementation, the descriptor's identifier, content, and the tensor data indicated by the descriptor can be stored in the same area of ​​internal memory. For example, a contiguous area of ​​on-chip cache, with addresses ADDR0-ADDR1023, can be used to store the descriptor's content. Addresses ADDR0-ADDR63 can be used as the descriptor storage space to store the descriptor's identifier and content, while addresses ADDR64-ADDR1023 can be used as the data storage space to store the tensor data indicated by the descriptor. Within the descriptor storage space, addresses ADDR0-ADDR31 can be used to store the descriptor's identifier, and addresses ADDR32-ADDR63 can be used to store the descriptor's content. It should be understood that address ADDR is not limited to one bit or one byte; it is used here to represent an address, a unit of address. Those skilled in the art can determine the descriptor storage space, data storage space, and their specific addresses based on actual circumstances, and this disclosure does not impose any limitations in this regard.

[0100] In one possible implementation, the descriptor's identifier, content, and the tensor data it points to can be stored in different areas of internal memory. For example, registers can be used as descriptor storage space, storing the descriptor's identifier and content, while on-chip caches can be used as data storage space, storing the tensor data pointed to by the descriptor.

[0101] In one possible implementation, when using registers to store the identifier and content of descriptors, the register number can be used to represent the descriptor's identifier. For example, when the register number is 0, the identifier of the descriptor it stores is set to 0. When the descriptor in the register is valid, a region in the cache space can be allocated to store the tensor data according to the size of the tensor data indicated by the descriptor.

[0102] In one possible implementation, the identifier and content of the descriptor can be stored in internal memory, while the tensor data pointed to by the descriptor can be stored in external memory. For example, the identifier and content of the descriptor can be stored on-chip, and the tensor data pointed to by the descriptor can be stored off-chip.

[0103] In one possible implementation, the data address of the data storage space corresponding to each descriptor can be a fixed address. For example, a separate data storage space can be allocated for tensor data, and the starting address of each tensor data in the data storage space corresponds one-to-one with a descriptor. In this case, the circuit or module responsible for parsing computation instructions (e.g., an entity outside the computing device disclosed herein) can determine the data address of the data corresponding to the operand in the data storage space based on the descriptor.

[0104] In one possible implementation, when the data address of the data storage space corresponding to the descriptor is a variable address, the descriptor can also be used to indicate the address of N-dimensional tensor data. The content of the descriptor may further include at least one address parameter representing the address of the tensor data. For example, if the tensor data is 3-dimensional, when the descriptor points to the address of the tensor data, the content of the descriptor may include one address parameter representing the address of the tensor data, such as the starting physical address of the tensor data, or it may include multiple address parameters representing the address of the tensor data, such as the starting address of the tensor data plus an address offset, or address parameters based on each dimension of the tensor data. Those skilled in the art can set the address parameters according to actual needs, and this disclosure does not impose any limitations on this.

[0105] In one possible implementation, the address parameter of the tensor data may include the reference address of the data reference point of the descriptor within the data storage space of the tensor data. The reference address may vary depending on the data reference point. This disclosure does not impose any restrictions on the selection of the data reference point.

[0106] In one possible implementation, the base address may include the starting address of the data storage space. When the data base point of the descriptor is the first data block in the data storage space, the base address of the descriptor is the starting address of the data storage space. When the data base point of the descriptor is data other than the first data block in the data storage space, the base address of the descriptor is the address of that data block in the data storage space.

[0107] In one possible implementation, the shape parameters of the tensor data include at least one of the following: the size of the data storage space in at least one of the N-dimensional directions, the size of the storage region in at least one of the N-dimensional directions, the offset of the storage region in at least one of the N-dimensional directions, the positions of at least two vertices at diagonal positions in the N-dimensional directions relative to the data reference point, and the mapping relationship between the data description location of the tensor data indicated by the descriptor and the data address. Here, the data description location is the mapped position of a point or region in the tensor data indicated by the descriptor. For example, when the tensor data is 3D data, the descriptor can use three-dimensional spatial coordinates (x, y, z) to represent the shape of the tensor data, and the data description location of the tensor data can be the position of a point or region mapped to the tensor data in three-dimensional space, represented by three-dimensional spatial coordinates (x, y, z).

[0108] It should be understood that those skilled in the art can choose the shape parameters representing tensor data according to the actual situation, and this disclosure does not impose any restrictions on this. By using descriptors during data access, associations between data can be established, thereby reducing the complexity of data access and improving instruction processing efficiency.

[0109] Figure 3 A schematic block diagram of a data processing apparatus according to an embodiment of this disclosure is shown. Figure 3 As shown, the data processing device 300 includes a control unit 310, an address calculation unit 320, and an execution unit 330.

[0110] The control unit 310 can be configured to control the operation of the data processing device 300, such as reading instructions from memory or external sources, decoding instructions, and sending micro-operation control signals to corresponding components. Specifically, the control unit 310 can be configured to control the address calculation unit 320 to calculate the corresponding data address based on the received processing instructions, and to control the execution unit 330 to perform corresponding processing based on the data address. Instructions may include, but are not limited to, data access instructions, arithmetic instructions, descriptor management instructions, and synchronization instructions. This disclosure does not limit the specific type of instructions or the specific method of decoding.

[0111] The decoded processing instruction includes an opcode and operands. The operands include at least one flag bit, which indicates the source of information for calculating the data address during the execution of the processing instruction.

[0112] Address calculation unit 320 can be configured to calculate a corresponding data address based on the indication of a flag bit using a corresponding information source. The flag bit can indicate any of the following information sources: parameters of the processing instruction; or parameters of a descriptor in the processing instruction, wherein the descriptor is used to indicate information about tensor data associated with the processing instruction.

[0113] In some embodiments, the flag bits can indicate the source of information used to calculate the data address at different granularities. In one implementation, the flag bits can indicate the source of information used to calculate the data address of the entire tensor data. In another implementation, the flag bits can indicate the source of information used to calculate the data address of each dimension of the tensor data. In yet another implementation, the flag bits can indicate the source of information for different parameters used to calculate the data address. In yet another implementation, the flag bits can indicate the source of information for different parameters used to calculate the data address of each dimension of the tensor data. The address calculation unit 320 can obtain the corresponding parameters directly from the processing instructions or from the descriptor of the processing instructions according to the indication of the flag bits, and calculate the corresponding data address based on these parameters.

[0114] Depending on the specific implementation, the calculation of the data address can rely on different parameters. In some implementations, these parameters may include, but are not limited to: the offset of the entire or part of the storage area of ​​the tensor data; and the size of the entire or part of the storage area of ​​the tensor data.

[0115] The execution unit 330 can be configured to execute specific instructions under the control of the control unit 310. Specifically, the execution unit 330 can be configured to execute the processing instruction based on the data address calculated by the address calculation unit 320 and the opcode in the decoded instruction. The execution unit 330 may include, but is not limited to, an arithmetic and logic unit (ALU), a memory access unit (MAU), and a neural functional unit (NFU). This disclosure does not limit the specific hardware type of the execution unit.

[0116] Optionally or additionally, the data processing apparatus 300 may further include a Tensor Interface Unit (TIU) 340, which can be configured to perform operations associated with descriptors under the control of the control unit 310. These operations may include, but are not limited to, registering, modifying, deregistering, and parsing descriptors; reading and writing descriptor contents, etc. This disclosure does not limit the specific hardware type of the Tensor Interface Unit. In this way, operations associated with descriptors can be implemented through dedicated hardware, further improving the efficiency of tensor data access.

[0117] Despite Figure 3 The control unit 310, address calculation unit 320 and tensor interface unit 340 are shown as separate modules, but those skilled in the art will understand that these three units can also be implemented as a single module or recombined and split into more modules, and this disclosure is not limited in this respect.

[0118] Optionally or additionally, the data processing apparatus 300 may further include a storage unit 350. The storage unit 350 may be configured to store various types of information, including but not limited to instructions, descriptor-associated information, tensor data, etc. The storage unit 350 may include various storage resources, including but not limited to internal memory and external memory. Internal memory may include, for example, registers, on-chip SRAM, or other media caches. External memory may include, for example, under-chip memory. This disclosure does not limit the specific implementation of the storage unit.

[0119] The data processing device 300 may be implemented using a general-purpose processor (such as a central processing unit CPU, a graphics processing unit GPU) and / or a special-purpose processor (such as an artificial intelligence processor, a scientific computing processor, or a digital signal processor, etc.), and this disclosure does not limit the specific type of data processing device.

[0120] Figure 4 An exemplary flowchart of a data processing method 400 according to an embodiment of this disclosure is shown. The data processing method 400 may, for example, be... Figure 3 The data processing device 300 is used to achieve this.

[0121] like Figure 4 As shown, method 400 begins at step S410, obtaining the decoding processing instructions. This step can, for example, be performed by... Figure 3 The control unit 310 performs the operation.

[0122] In the embodiments disclosed herein, the decoded processing instruction includes an opcode and operands, wherein the operands include at least one flag bit used to indicate the source of information for calculating the data address during the execution of the processing instruction.

[0123] Next, in step S420, the data address is calculated using the corresponding information source according to the indication of the flag bit. This step can be, for example, performed by... Figure 3 The address calculation unit 320 is used for execution. The specific implementation of the flag bits can be found in the previous description, and will not be repeated here.

[0124] Finally, in step S430, the processing instruction is executed based on the data address and opcode. This step can be, for example, performed by... Figure 3 The execution unit 330 is used to execute it.

[0125] The data processing method performed by the data processing apparatus of this disclosure embodiment has been described above with reference to the flowchart. It should be noted that, for the foregoing method embodiments, for the sake of simplicity, they are all described as a series of actions. However, those skilled in the art should understand that this disclosure is not limited to the described order of actions, because according to this disclosure, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily essential to this disclosure.

[0126] It should be further explained that, although Figure 4 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 4 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0127] Figure 5 This is a structural diagram illustrating a combined processing apparatus 500 according to an embodiment of this disclosure. Figure 5 As shown, the combined processing device 500 includes a computing processing device 502, an interface device 504, other processing devices 506, and a storage device 508. Depending on the application scenario, the computing processing device may include one or more computing devices 510, which can be configured to... Figure 3 The data processing device 300 shown is used to perform the functions described herein in conjunction with the appendix. Figure 4 The described operation.

[0128] In different embodiments, the computing processing apparatus disclosed herein can be configured to perform user-specified operations. In exemplary applications, the computing processing apparatus can be implemented as a single-core artificial intelligence processor or a multi-core artificial intelligence processor. Similarly, one or more computing devices included within the computing processing apparatus can be implemented as an artificial intelligence processor core or a portion of the hardware structure of an artificial intelligence processor core. When multiple computing devices are implemented as artificial intelligence processor cores or portions of the hardware structure of artificial intelligence processor cores, the computing processing apparatus disclosed herein can be considered to have a single-core structure or a homogeneous multi-core structure.

[0129] In exemplary operation, the computing processing device disclosed herein can interact with other processing devices through an interface device to jointly complete user-specified operations. Depending on the implementation, the other processing devices disclosed herein may include one or more types of processors such as a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), and an artificial intelligence processor, both general-purpose and / or special-purpose processors. These processors may include, but are not limited to, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field-Programmable Gate Arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc., and their number can be determined according to actual needs. As mentioned above, the computing processing device disclosed herein can be considered to have a single-core structure or a homogeneous multi-core structure. However, when the computing processing device and other processing devices are considered together, they can be considered to form a heterogeneous multi-core structure.

[0130] In one or more embodiments, the other processing device may serve as an interface between the computing processing device disclosed herein (which may be specifically embodied in artificial intelligence, such as neural network operations) and external data and control, performing basic controls including but not limited to data transfer, starting and / or stopping the computing device. In another embodiment, the other processing device may also cooperate with the computing processing device to jointly complete computational tasks.

[0131] In one or more embodiments, the interface device can be used to transfer data and control commands between a computing processing device and other processing devices. For example, the computing processing device can obtain input data from other processing devices via the interface device and write it to on-chip storage (or memory) of the computing processing device. Further, the computing processing device can obtain control commands from other processing devices via the interface device and write them to on-chip control cache of the computing processing device. Alternatively or optionally, the interface device can also read data from the storage device of the computing processing device and transmit it to other processing devices.

[0132] Additionally or optionally, the combined processing apparatus disclosed herein may further include a storage device. As shown in the figures, the storage device is connected to both the computing processing device and the other processing device. In one or more embodiments, the storage device may be used to store data from the computing processing device and / or the other processing device. For example, the data may be data that cannot be fully stored in the internal or on-chip storage of the computing processing device or other processing device.

[0133] In some embodiments, this disclosure also discloses a chip (e.g. Figure 6 The chip shown is 602. In one implementation, the chip is a system-on-chip (SoC) and integrates one or more such... Figure 5 The combined processing unit shown is illustrated. This chip can be connected to external interface devices (such as...). Figure 6 The external interface device 606 shown is connected to other related components. These related components may be, for example, a camera, monitor, mouse, keyboard, network card, or Wi-Fi interface. In some applications, the chip may integrate other processing units (e.g., video codecs) and / or interface modules (e.g., DRAM interfaces). In some embodiments, this disclosure also discloses a chip package structure that includes the aforementioned chip. In some embodiments, this disclosure also discloses a board that includes the aforementioned chip package structure. The following will be combined with… Figure 6 This board is described in detail.

[0134] Figure 6 This is a schematic diagram illustrating the structure of a board 600 according to an embodiment of this disclosure. Figure 6As shown, the board includes a storage device 604 for storing data, which includes one or more storage cells 610. This storage device can be connected and transmit data with the controller 608 and the aforementioned chip 602 via, for example, a bus. Furthermore, the board also includes an external interface device 606, configured for data relay or switching between the chip (or a chip in a chip package) and an external device 612 (e.g., a server or computer). For example, data to be processed can be transferred from the external device to the chip via the external interface device. Alternatively, the calculation results of the chip can be transmitted back to the external device via the external interface device. Depending on the application scenario, the external interface device can have different interface forms, such as a standard PCIe interface.

[0135] In one or more embodiments, the controller in the disclosed board can be configured to regulate the state of the chip. Therefore, in one application scenario, the controller may include a microcontroller (MCU) for regulating the operating state of the chip.

[0136] Based on the above combination Figure 5 and Figure 6 Based on the description, those skilled in the art will understand that this disclosure also discloses an electronic device or apparatus that may include one or more of the aforementioned boards, one or more of the aforementioned chips, and / or one or more of the aforementioned combined processing apparatus.

[0137] Depending on the application scenario, the electronic devices or apparatus disclosed herein may include servers, cloud servers, server clusters, data processing devices, robots, computers, printers, scanners, tablets, smart terminals, PC devices, IoT terminals, mobile terminals, mobile phones, dashcams, navigators, sensors, cameras, video cameras, projectors, watches, headphones, mobile storage, wearable devices, visual terminals, autonomous driving terminals, vehicles, home appliances, and / or medical devices. The vehicles include airplanes, ships, and / or vehicles; the home appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, lights, gas stoves, and range hoods; the medical devices include MRI scanners, ultrasound machines, and / or electrocardiographs. The electronic devices or apparatus disclosed herein can also be applied in fields such as the Internet, IoT, data centers, energy, transportation, public management, manufacturing, education, power grids, telecommunications, finance, retail, construction sites, and healthcare. Furthermore, the electronic devices or apparatus disclosed herein can also be used in application scenarios related to artificial intelligence, big data, and / or cloud computing, such as cloud computing, edge computing, and terminal applications. In one or more embodiments, the high-computing-power electronic devices or apparatuses according to the present disclosure can be applied to cloud devices (e.g., cloud servers), while the low-power electronic devices or apparatuses can be applied to terminal devices and / or edge devices (e.g., smartphones or cameras). In one or more embodiments, the hardware information of the cloud devices and the hardware information of the terminal devices and / or edge devices are compatible with each other, so that suitable hardware resources can be matched from the hardware resources of the cloud devices to simulate the hardware resources of the terminal devices and / or edge devices based on the hardware information of the terminal devices and / or edge devices, so as to complete the unified management, scheduling and collaborative work of end-to-cloud or cloud-edge-end integration.

[0138] It should be noted that, for the sake of brevity, this disclosure describes some methods and their embodiments as a series of actions and combinations thereof. However, those skilled in the art will understand that the solutions disclosed herein are not limited by the order of the described actions. Therefore, based on the disclosure or teachings of this document, those skilled in the art will understand that some steps can be performed in a different order or simultaneously. Furthermore, those skilled in the art will understand that the embodiments described in this disclosure can be considered optional embodiments, that is, the actions or modules involved are not necessarily essential for the implementation of one or more solutions disclosed herein. In addition, depending on the solution, the description of some embodiments in this disclosure may have different emphases. In view of this, those skilled in the art will understand that parts not described in detail in a certain embodiment of this disclosure can also be referred to the relevant descriptions of other embodiments.

[0139] In terms of specific implementation, based on the disclosure and teachings of this document, those skilled in the art will understand that several embodiments disclosed herein can also be implemented in other ways not disclosed herein. For example, regarding the various units in the electronic device or apparatus embodiments described above, this document divides them based on logical functions, but in actual implementation, there may be other division methods. As another example, multiple units or components can be combined or integrated into another system, or some features or functions in a unit or component can be selectively disabled. Regarding the connection relationships between different units or components, the connections discussed above in conjunction with the accompanying drawings can be direct or indirect couplings between units or components. In some scenarios, the aforementioned direct or indirect couplings involve communication connections utilizing interfaces, where the communication interface can support electrical, optical, acoustic, magnetic, or other forms of signal transmission.

[0140] In this disclosure, the units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units. The aforementioned components or units may be located in the same location or distributed across multiple network units. Furthermore, depending on actual needs, some or all of the units can be selected to achieve the purpose of the solution described in the embodiments of this disclosure. Additionally, in some scenarios, multiple units in the embodiments of this disclosure may be integrated into one unit or each unit may exist physically independently.

[0141] In some implementation scenarios, the integrated unit described above can be implemented as a software program module. If implemented as a software program module and sold or used as an independent product, the integrated unit can be stored in a computer-readable storage device (CMSDD). Therefore, when the disclosed solution is embodied in a software product (e.g., a computer-readable storage medium), the software product can be stored in a memory, which may include several instructions to cause a computer device (e.g., a personal computer, server, or network device) to execute some or all of the steps of the method described in the embodiments of this disclosure. The aforementioned memory may include, but is not limited to, various media capable of storing program code, such as USB flash drives, flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0142] In other implementation scenarios, the integrated units described above can also be implemented in hardware, i.e., as specific hardware circuits, which may include digital circuits and / or analog circuits. The physical implementation of the circuit's hardware structure may include, but is not limited to, physical devices, which may include, but are not limited to, transistors or memristors. Therefore, the various devices described herein (e.g., computing devices or other processing devices) can be implemented using appropriate hardware processors, such as CPUs, GPUs, FPGAs, DSPs, and ASICs. Furthermore, the aforementioned storage units or storage devices can be any suitable storage medium (including magnetic storage media or magneto-optical storage media), such as resistive random access memory (RRAM), dynamic random access memory (DRAM), static random access memory (SRAM), enhanced dynamic random access memory (EDRAM), high-bandwidth memory (HBM), hybrid memory cube (HMC), ROM, and RAM.

[0143] The foregoing can be better understood in accordance with the following terms:

[0144] Clause 1. A data processing apparatus, comprising a control unit, an address calculation unit, and an execution unit, wherein:

[0145] The control unit is configured to acquire decoding processing instructions, the processing instructions including opcodes and operands, the operands including at least one flag bit for indicating the source of information for calculating the data address during the execution of the processing instructions;

[0146] The address calculation unit is configured to calculate the data address based on the indication of the flag bit and using the corresponding information source; and

[0147] The execution unit is configured to execute the processing instructions based on the data address and the opcode.

[0148] Clause 2. The data processing apparatus according to Clause 1, wherein the flag indicates any of the following information sources:

[0149] The parameters of the processing instruction; or

[0150] The parameters of the descriptor in the processing instruction, wherein the descriptor is used to indicate information about the tensor data associated with the processing instruction.

[0151] Clause 3. The data processing apparatus according to Clause 2, wherein the flag bits indicate the source of information used to calculate the data address at different granularities.

[0152] Clause 4. The data processing apparatus according to any one of Clauses 2-3, wherein the flag indicates the source of information for calculating the data address of the entire tensor data.

[0153] Clause 5. The data processing apparatus according to any one of Clauses 2-4, wherein the flag indicates the source of information for calculating the data addresses of each dimension of the tensor data.

[0154] Clause 6. The data processing apparatus according to any one of Clauses 2-5, wherein the flag indicates the source of information for calculating different parameters of the data address.

[0155] Clause 7. The data processing apparatus according to any one of Clauses 2-6, wherein the flag indicates the source of information for different parameters used to calculate the data addresses of each dimension of the tensor data.

[0156] Clause 8. The data processing apparatus according to any one of Clauses 2-7, wherein said parameters include at least one of the following:

[0157] The offset of the entire or part of the storage area of ​​the tensor data; and

[0158] The size of the entire or part of the storage area for tensor data.

[0159] Clause 9. The data processing apparatus according to any one of Clauses 2-8, wherein the descriptor indicates shape information of the tensor data, the shape information of the tensor data including at least one shape parameter representing the shape of the N-dimensional tensor data, where N is a positive integer, and the shape parameter of the tensor data including at least one of the following:

[0160] The dimensions of the data storage space containing the tensor data in at least one of the N dimensions, the dimensions of the storage area of ​​the tensor data in at least one of the N dimensions, the offset of the storage area in at least one of the N dimensions, the positions of at least two vertices at diagonal positions in the N dimensions relative to the data reference point, and the mapping relationship between the data description location and the data address of the tensor data.

[0161] Clause 10. A chip, characterized in that the chip includes a data processing device as described in any one of Clauses 1-9.

[0162] Clause 11. A board, characterized in that the board comprises the chip described in Clause 10.

[0163] Clause 12. A data processing method, the method comprising:

[0164] Obtain the decoding processing instruction, the processing instruction including an opcode and operands, the operands including at least one flag bit for indicating the source of information for calculating the data address during the execution of the processing instruction;

[0165] Based on the indication of the flag bit, the data address is calculated using the corresponding information source; and

[0166] The processing instruction is executed based on the data address and the opcode.

[0167] Clause 13. The data processing method according to Clause 12, wherein the flag indicates any of the following information sources:

[0168] The parameters of the processing instruction; or

[0169] The parameters of the descriptor in the processing instruction, wherein the descriptor is used to indicate information about the tensor data associated with the processing instruction.

[0170] Clause 14. The data processing method according to Clause 13, wherein the flag bits indicate the source of information used to calculate the data address at different granularities.

[0171] Clause 15. The data processing method according to any of Clauses 13-14, wherein the flag indicates the source of information for calculating the data address of the entire tensor data.

[0172] Clause 16. The data processing method according to any one of Clauses 13-15, wherein the flag indicates the source of information for calculating the data address of each dimension of the tensor data.

[0173] Clause 17. The data processing method according to any one of Clauses 13-16, wherein the flag indicates the source of information for calculating different parameters of the data address.

[0174] Clause 18. The data processing method according to any one of Clauses 13-17, wherein the flag indicates the source of information for different parameters used to compute the data addresses of each dimension of the tensor data.

[0175] Clause 19. The data processing method according to any one of Clauses 13-18, wherein the parameters include at least one of the following:

[0176] The offset of the entire or part of the storage area of ​​the tensor data; and

[0177] The size of the entire or part of the storage area for tensor data.

[0178] Clause 20. The data processing method according to any one of Clauses 13-19, wherein the descriptor indicates shape information of the tensor data, the shape information of the tensor data including at least one shape parameter representing the shape of the N-dimensional tensor data, where N is a positive integer, and the shape parameter of the tensor data including at least one of the following:

[0179] The dimensions of the data storage space containing the tensor data in at least one of the N dimensions, the dimensions of the storage area of ​​the tensor data in at least one of the N dimensions, the offset of the storage area in at least one of the N dimensions, the positions of at least two vertices at diagonal positions in the N dimensions relative to the data reference point, and the mapping relationship between the data description location and the data address of the tensor data.

Claims

1. A data processing apparatus, comprising a control unit, an address calculation unit, and an execution unit, wherein: The control unit is configured to acquire decoding processing instructions, the processing instructions including an opcode and operands, the operands including at least one flag bit for indicating the source of information for calculating the data address during the execution of the processing instructions, wherein the flag bit indicates any of the following information sources: The parameters of the processing instruction; or The parameters of the descriptor in the processing instruction, wherein the descriptor is used to indicate information about the tensor data associated with the processing instruction; The address calculation unit is configured to calculate the data address based on the indication of the flag bit and using the corresponding information source; as well as The execution unit is configured to execute the processing instructions based on the data address and the opcode.

2. The data processing apparatus according to claim 1, wherein the flag bits indicate the information source used to calculate the data address according to different granularities.

3. The data processing apparatus according to any one of claims 1-2, wherein the flag indicates the source of information for calculating the data address of the entire tensor data.

4. The data processing apparatus according to claim 2, wherein the flag bit indicates the information source for calculating the data address of each dimension of the tensor data.

5. The data processing apparatus according to claim 2, wherein the flag bit indicates the source of information for calculating different parameters of the data address.

6. The data processing apparatus according to claim 2, wherein the flag indicates the information source of different parameters used to calculate the data addresses of each dimension of the tensor data.

7. The data processing apparatus of claim 2, wherein the parameter includes at least one of the following: the offset of the entire or part of the storage area of ​​the tensor data; and the size of the entire or part of the storage area of ​​the tensor data.

8. The data processing apparatus according to claim 2, wherein the descriptor indicates the shape information of the tensor data, the shape information of the tensor data includes at least one shape parameter representing the shape of the N-dimensional tensor data, where N is a positive integer, and the shape parameter of the tensor data includes at least one of the following: the size of the data storage space where the tensor data is located in at least one of the N-dimensional directions, the size of the storage area of ​​the tensor data in at least one of the N-dimensional directions, the offset of the storage area in at least one of the N-dimensional directions, the position of at least two vertices at diagonal positions in the N-dimensional directions relative to the data reference point, and the mapping relationship between the data description position and the data address of the tensor data.

9. A chip, characterized in that, The chip includes the data processing device as described in any one of claims 1-8.

10. A circuit board, characterized in that, The board includes the chip described in claim 9.

11. A data processing method, the method comprising: Obtain the decoding processing instruction, which includes an opcode and operands. The operands include at least one flag bit used to indicate the source of information for calculating the data address during the execution of the processing instruction. The flag bit indicates any of the following information sources: The parameters of the processing instruction; or The parameters of the descriptor in the processing instruction, wherein the descriptor is used to indicate information about the tensor data associated with the processing instruction; The data address is calculated based on the indication of the flag bit and the corresponding information source; as well as The processing instruction is executed based on the data address and the opcode.

12. The data processing method according to claim 11, wherein the flag bits indicate the information source used to calculate the data address according to different granularities.

13. The data processing method according to any one of claims 11-12, wherein the flag indicates the source of information used to calculate the data address of the entire tensor data.

14. The data processing method according to any one of claims 11-12, wherein the flag indicates the source of information for calculating the data address of each dimension of the tensor data.

15. The data processing method according to any one of claims 11-12, wherein the flag bit indicates the source of information for calculating different parameters of the data address.

16. The data processing method according to any one of claims 11-12, wherein the flag indicates the information source of different parameters used to calculate the data addresses of each dimension of the tensor data.

17. The data processing method according to any one of claims 11-12, wherein the parameter includes at least one of the following: the offset of the entire or part of the storage area of ​​the tensor data; and the size of the entire or part of the storage area of ​​the tensor data.

18. The data processing method according to any one of claims 11-12, wherein the descriptor indicates the shape information of the tensor data, the shape information of the tensor data includes at least one shape parameter representing the shape of the N-dimensional tensor data, where N is a positive integer, and the shape parameter of the tensor data includes at least one of the following: the size of the data storage space where the tensor data is located in at least one of the N-dimensional directions, the size of the storage area of ​​the tensor data in at least one of the N-dimensional directions, the offset of the storage area in at least one of the N-dimensional directions, the position of at least two vertices at diagonal positions in the N-dimensional directions relative to the data reference point, and the mapping relationship between the data description position and the data address of the tensor data.

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