Real-time solution method of hardware logic for first-order linear differential equation based on FPGA

Abstract

The present invention discloses a first-order linear differential equation hardware logic real-time solving method based on FPGA, comprising the following steps: S1, constructing a differential equation module to be solved; S2, based on an improved fourth-order Runge-Kutta algorithm numerical iteration solving model and the module in the above S1, constructing a parameter update module of full hardware and local parallel calculation; S3, based on the parameter update module in S2, constructing an algorithm sub-top-level module for calculation; S4, based on a state register, constructing a real-time control module, having functions such as operation control of the sub-top-level module and iterative calculation of x variables; S5, based on all modules in S1 to S4, constructing a top-level module of an algorithm calculation model, and reserving necessary parameter user interfaces. While the present invention ensures high solving accuracy, it alleviates the calculation delay problem caused by the inherent high seriality of the algorithm numerical iteration model to a certain extent.

Description

Technical Field

[0001] The invention belongs to the field of FPGA mathematical operation library IP design and relates to a first-order linear differential equation hardware logic real-time solving method based on FPGA. Background Art

[0002] In the process of hardware acceleration of certain complex algorithms using FPGA, solving differential equations is an indispensable operation. In most cases, the analytical expression of the differential equation is found in the analog domain, and then it is discretized into the digital domain for implementation. This method not only requires designers to be familiar with the differential equation solution method, but also the implemented hardware logic is not universal. On the other hand, the IDEs of FPGA manufacturers such as Xilinx and Altera lack relevant IPs for solving differential equations. In order to effectively solve the above problems, the present invention proposes a real-time solution method for first-order linear differential equations based on FPGA hardware logic. Users only need to configure relevant parameter parameters in the top-level module and change the differential equation implementation module diffEqu, and they can obtain real-time high-precision approximate solutions of first-order linear differential equations after a small number of clock cycles. Summary of the invention

[0003] In view of the problem that the process of solving differential equations in the field of FPGA algorithm acceleration is relatively complicated and there is a lack of relevant general IP, the present invention proposes a real-time solution method for first-order linear differential equations based on FPGA hardware logic. This method innovatively uses a fully hardware-based, improved Runge-Kutta algorithm as the core computing framework, uses an FPGA high-performance floating-point arithmetic unit as the computing engine, incorporates a local parallel computing mechanism, and reserves user configuration ports to ensure high solution accuracy. At the same time, it alleviates the computational delay problem caused by the inherent high seriality of the numerical iteration model of the algorithm to a certain extent, and provides a core functional component for related engineering designs. The technical solution of the present invention is a real-time solution method for first-order linear differential equations based on FPGA hardware logic, comprising the following steps:

[0004] S1, construct the differential equation to be solved HDL module diffEqu;

[0005] S1, constructs the differential equation to be solved The HDL module diffEqu includes the following steps:

[0006] S11, the first-order linear differential equation to be solved Rewrite as form;

[0007] S12, calling various floating-point operation IPs or writing FPGA logic, and implementing the f(x, y) part in S11 with an HDL module, wherein the module uses floating-point numbers x, y with configurable precision and their valid indication signals x_vld, y_vld as input signals, and uses floating-point numbers res in the same format and their valid indication signal res_vld as output signals;

[0008] S2, based on the improved fourth-order Runge-Kutta algorithm numerical iterative solution model and the diffEqu module in S1 above, build a fully hardware-based, locally parallel computing K1, K2, K3, K4 parameter update module;

[0009] The fourth-order Runge-Kutta algorithm in S2 numerically iterates the solution model, that is,

[0010] K1=f(x n ,y n ) (1)

[0011]

[0012]

[0013] K4=f(x n +s,y n +s*K3) (4)

[0014]

[0015] Where s is the step size of one iteration of x, which comes from the user-defined parameter STEP.

[0016] The S2 constructs a fully hardware-based, locally parallel calculation K1, K2, K3, K4 parameter update module, including the following steps:

[0017] S21, construct a generalized parameter update module Kx_calc, the input signal of which is the output signal of the previous parameter update module, the (half) step size, and the initial values ​​of x and y of one iteration, and the output signal is the Kx parameter. The module first adds the step size information and the parameter information calculated by the previous module to the x and y values ​​of this iteration in a parallel calculation manner to obtain x' and y', and then sends x' and y' to the instantiated diffEqu module for Kx parameter calculation;

[0018] S22, for the K1 parameter update module K1_calc, directly instantiate the diffEqu module;

[0019] S23, for the K2, K3, K4 parameter updating modules K2_calc, K3_calc, K4_calc, respectively instantiate the generalized parameter updating module Kx_calc described in S21;

[0020] S24, the above four parameter update modules run in parallel, and the register group Kx_res_cache is used to cache the calculation results of each parameter update module in one iteration cycle;

[0021] The improved fourth-order Runge-Kutta algorithm in S2 is used to numerically iterate the solution model, that is, The calculation formula of the Kx parameter is simplified to the first-order linear differential equation of the form:

[0022] K1=f(x n ) (6)

[0023]

[0024]

[0025] K4=f(x n +s) (9)

[0026] Relying on the parallel computing characteristics of FPGA, the above Kx parameters can be calculated in parallel, so that the number of clocks consumed by the calculation is reduced to 1 / 4 of the original. The 4-bit status register calc_complete is used to indicate that the parallel calculation is completed, and the calculation results are stored in the Kx_res_cache register group described in S24;

[0027] S3, based on the parameter update module in S2, is constructed to calculate y n+1 The algorithm sub-top level module RK_calc_subtop;

[0028] The S3 construct is used to calculate y n+1 The algorithm sub-top module RK_calc_subtop includes the following steps:

[0029] S31, using the output valid signal (high valid) of the K4_calc module in S23 as an enable signal, receiving the parallel data from the register group Kx_res_cache in S24, and sending it to the multiplication-addition tree for parallel calculation, the calculation formula is as shown in formula (5);

[0030] S32, using the output data valid signal of the last floating-point multiplication and addition unit as an iteration completion signal, and sending the data y obtained in one iteration to the n+1 The valid signal of the data is sent to the real-time control module RK_CTRL in S4;

[0031] S4, based on the status register, build the real-time control module RK_CTRL, which has the functions of operating control of the RK_calc_subtop module and iterative calculation of the x variable;

[0032] The 1-bit status register runtime_flag in S4 is used to indicate the iteration status. Specifically, "0" indicates that the iteration is finished or not started, and "1" indicates that iterative calculation is in progress. Its value comes from the sign bit of the difference between the x variable and the end value X_END set by the user.

[0033] The real-time control module RK_CTRL is constructed in S4, which has the functions of operating control of the RK_calc_subtop module, iterative calculation of the x variable, etc., including the following steps:

[0034] S41, calculate the sum of x and the step size parameter STEP set by the user to obtain the initial value x of the next iteration n+1 ;

[0035] S42, x n+1 Same as S32 n+1 After data alignment, it is sent to RK_calc_subtop together with the start pulse start_one_Kx_calc as the output signal of the real-time control module RK_CTRL to instruct the RK_calc_subtop module to perform the next iterative calculation;

[0036] S5, based on all modules in S1 to S4, builds the top-level module of the algorithm calculation model and reserves the necessary parameter user interface.

[0037] The universality of the generalized parameter updating module Kx_calc in S21 is mainly reflected in:

[0038] 1) The data format of the internal floating-point unit is configurable, supporting half-precision floating-point numbers (16bit), single-precision floating-point numbers (32bit) and double-precision floating-point numbers (64bit) of the IEEE754 standard, and supporting custom data formats; 2) Based on the similarity of the parameter calculation structures of K2, K3, and K4, the above three types of parameter calculation functions can be implemented by changing only one input signal (step size or half-step size); 3) There is a one-to-one correspondence between the input and output signals of the Kx_calc module, which is suitable for cascade operations between modules.

[0039] Preferably, the step of sending the parallel data of the register group Kx_res_cache into the multiply-add tree for parallel calculation in S31 includes the following steps:

[0040] S311, the first level parallel structure, includes two floating point multiplication and addition units, which are used to calculate K1+2K2 and 2K3+K4 in formula (5), and the results are recorded as R1 and R2;

[0041] S312, the second level parallel structure includes a floating point addition unit and a floating point division unit, which are used to calculate the sum of K1+2K2 and 2K3+K4 in S311, and the result is recorded as R3, and The result is recorded as R4;

[0042] S313, the third level parallel structure, includes a floating point multiplication and addition unit, which implements the whole formula (5), that is, to obtain y n+1 =y n +R3*R4.

[0043] Preferably, the necessary parameter user interface is reserved in S5, including the following user-configurable parameters: 1) data width DATAWIDTH: used to specify the data width and floating point format; 2) step size STEP: used to configure the step length of each iteration of x; 3) half step size HALF_STEP: that is, half of the step size STEP, used for calculation of K parameter; 4) x starting value X_START: used to configure the horizontal coordinate value of the starting point; 5) x ending value X_END: ​​used to configure the horizontal coordinate value of the ending point; 6) y starting value Y_INIT: used to configure the vertical coordinate value of the starting point, and together with X_START, it constitutes the boundary condition of the function.

[0044] Preferably, there is a one-to-one correspondence between the input and output signals of the Kx_calc module, specifically: in addition to the necessary clock and reset signals, the input signals are the calculated value of the previous parameter update module, the valid signal of the calculated value, the initial value of x and the initial value of y in this iteration cycle, and the corresponding output signals are the calculated value of the current parameter update module, the valid signal of the calculated value, the initial value of x and the initial value of y in this iteration cycle.

[0045] The beneficial effects of the present invention are as follows: The present invention is a hardware logic real-time solution method for first-order linear differential equations based on FPGA, which uses the fully hardwareized Runge-Kutta algorithm as the core computing framework, integrates the local parallel computing mechanism, and reserves user configuration ports to ensure high solution accuracy while alleviating the problem of computing delay to a certain extent. Users only need to configure the relevant parameter parameters in the top-level module and change the differential equation implementation module diffEqu, and they can obtain a real-time high-precision approximate solution of the first-order linear differential equation after a small number of clock cycles (about 13 clks). BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1This is a flowchart of the steps of a method for solving a first-order linear differential equation in real time based on FPGA hardware logic according to an embodiment of the present invention;

[0047] Figure 2 This is a schematic diagram of the multiplication-add tree parallel calculation described in S31 in the FPGA-based hardware logic real-time solution method for first-order linear differential equations in an embodiment of the present invention.

[0048] Figure 3 The RTL architecture diagram of the FPGA-based hardware logic real-time solution method for first-order linear differential equations according to an embodiment of the present invention. DETAILED DESCRIPTION

[0049] The technical solution of the present invention is further described in detail below through specific embodiments in conjunction with the accompanying drawings.

[0050] Example 1

[0051] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0052] On the contrary, the present invention covers any substitution, modification, equivalent method and scheme made on the essence and scope of the present invention as defined by the claims. Further, in order to make the public have a better understanding of the present invention, some specific details are described in detail in the detailed description of the present invention below. Those skilled in the art can fully understand the present invention without the description of these details.

[0053] First of all, it should be understood that the FPGA-based hardware logic real-time solution method for first-order linear differential equations described in the present invention is used to solve the problem that the process of solving differential equations in the field of FPGA algorithm acceleration is relatively complicated and lacks relevant general IP in this embodiment. By adopting this solution method, while ensuring high solution accuracy, relying on the parallel characteristics of FPGA logic, the problem of calculation delay can be alleviated to a certain extent. Specifically, after a small number of clock cycles (about 13 clks), a real-time high-precision approximate solution of the first-order linear differential equation can be obtained.

[0054] See also Figure 1 , is an embodiment of the present invention, the technical solution is a flowchart of the step of the hardware logic real-time solution method of the first-order linear differential equation based on FPGA, combined with Figure 2 The multiplication-add tree parallel computing diagram and Figure 3 The RTL architecture diagram includes the following steps:

[0055] S1, construct the differential equation to be solved HDL module diffEqu;

[0056] S1, constructs the differential equation to be solved The HDL module diffEqu includes the following steps:

[0057] S11, the first-order linear differential equation to be solved Rewrite as form;

[0058] S12, calling various floating-point operation IPs or writing FPGA logic, and implementing the f(x, y) part in S11 with an HDL module, wherein the module uses floating-point numbers x, y with configurable precision and their valid indication signals x_vld, y_vld as input signals, and uses floating-point numbers res in the same format and their valid indication signal res_vld as output signals;

[0059] S2, based on the improved fourth-order Runge-Kutta algorithm numerical iterative solution model and the diffEqu module in S1 above, build a fully hardware-based, locally parallel computing K1, K2, K3, K4 parameter update module;

[0060] The fourth-order Runge-Kutta algorithm in S2 iteratively solves the model, that is

[0061] K1=f(x n ,y n ) (1)

[0062]

[0063]

[0064] K4=f(x n +s,y n +s*K3) (4)

[0065]

[0066] Where s is the step size of one iteration of x, which comes from the user-defined parameter STEP.

[0067] The S2 constructs a fully hardware-based, locally parallel calculation K1, K2, K3, K4 parameter update module, including the following steps:

[0068] S21, construct a generalized parameter update module Kx_calc, the input signal of which is the output signal of the previous parameter update module, the (half) step size, and the initial values ​​of x and y of one iteration, and the output signal is the Kx parameter. The module first adds the step size information and the parameter information calculated by the previous module to the x and y values ​​of this iteration in a parallel calculation manner to obtain x' and y', and then sends x' and y' to the instantiated diffEqu module for Kx parameter calculation;

[0069] The universal parameter updating module Kx_calc in S21 is mainly embodied in the following aspects:

[0070] (1) The data format of the internal floating-point unit is configurable, supporting IEEE754 standard half-precision floating-point numbers (16 bits), single-precision floating-point numbers (32 bits), and double-precision floating-point numbers (64 bits), and supports custom data formats;

[0071] (2) Based on the similarity of the parameter calculation structures of K2, K3, and K4, the above three types of parameter calculation functions can be realized by changing only one input signal (step size or half step size);

[0072] (3) There is a one-to-one correspondence between the input and output signals of the Kx_calc module, which is suitable for cascade operation between modules;

[0073] There is a one-to-one correspondence between the input and output signals of the Kx_calc module. Specifically, in addition to the necessary clock and reset signals, the input signals are the calculated value of the previous parameter update module, the valid signal of the calculated value, the initial value of x and the initial value of y in this iteration cycle, and the corresponding output signals are the calculated value of the current parameter update module, the valid signal of the calculated value, the initial value of x and the initial value of y in this iteration cycle.

[0074] S22, for the K1 parameter update module K1_calc, directly instantiate the diffEqu module;

[0075] S23, for the K2, K3, K4 parameter updating modules K2_calc, K3_calc, K4_calc, respectively instantiate the generalized parameter updating module Kx_calc described in S21;

[0076] S24, the above four parameter update modules run in parallel, and the register group Kx_res_cache is used to cache the calculation results of each parameter update module in one iteration cycle;

[0077] The improved fourth-order Runge-Kutta algorithm in S2 is used to numerically iterate the solution model, that is, The calculation formula of the Kx parameter is simplified to the first-order linear differential equation of the form:

[0078] K1=f(x n ) (6)

[0079]

[0080]

[0081] K4=f(x n +s) (9)

[0082] Relying on the parallel computing characteristics of FPGA, the above Kx parameters can be calculated in parallel, so that the number of clocks consumed by the calculation is reduced to 1 / 4 of the original. The 4-bit status register calc_complete is used to indicate that the parallel calculation is completed, and the calculation results are stored in the Kx_res_cache register group described in S24;

[0083] S3, based on the parameter update module in S2, is constructed to calculate y n+1 The algorithm sub-top level module RK_calc_subtop;

[0084] The S3 construct is used to calculate y n+1 The algorithm sub-top module RK_calc_subtop includes the following steps:

[0085] S31, using the output valid signal (high effective) of the K4_calc module in S23 as the enable signal, receives the parallel data from the register group Kx_res_cache in S24, and sends it to the multiplication-addition tree for parallel calculation. The calculation formula is as shown in (5), and the parallelization structure diagram is as shown in Figure 2 As shown;

[0086] In S31, the parallel data of the register group Kx_res_cache is sent to the multiplication-addition tree for parallel calculation, which includes the following steps:

[0087] S311, the first level parallel structure, includes two floating point multiplication and addition units, which are used to calculate K1+2K2 and 2K3+K4 in formula (5), and the results are recorded as R1 and R2;

[0088] S312, the second level parallel structure includes a floating point addition unit and a floating point division unit, which are used to calculate the sum of K1+2K2 and 2K3+K4 in S311, and the result is recorded as R3, and The result is recorded as R4;

[0089] S313, the third level parallel structure, includes a floating point multiplication and addition unit, which implements the whole formula (5), that is, to obtain yn+1 =y n +R3*R4;

[0090] S32, using the output data valid signal of the last floating-point multiplication and addition unit as an iteration completion signal, and sending the data y obtained in one iteration to the n+1 The valid signal of the data is sent to the real-time control module RK_CTRL in S4;

[0091] S4, based on the status register, build the real-time control module RK_CTRL, which has the functions of operating control of the RK_calc_subtop module and iterative calculation of the x variable;

[0092] The 1-bit status register runtime_flag in S4 is used to indicate the iteration status. Specifically, "0" indicates that the iteration is finished or not started, and "1" indicates that iterative calculation is in progress. Its value comes from the sign bit of the difference between the x variable and the end value X_END set by the user.

[0093] The real-time control module RK_CTRL is constructed in S4, which has the functions of operating control of the RK_calc_subtop module, iterative calculation of the x variable, etc., including the following steps:

[0094] S41, calculate the sum of x and the step size parameter STEP set by the user to obtain the initial value x of the next iteration n+1 ;

[0095] S42, x n+1 Same as S32 n+1 After data alignment, it is sent to RK_calc_subtop together with the start pulse start_one_Kx_calc as the output signal of the real-time control module RK_CTRL to instruct the RK_calc_subtop module to perform the next iterative calculation;

[0096] S5, based on all modules in S1 to S4, builds the top-level module of the algorithm calculation model and reserves the necessary parameter user interface. The overall RTL architecture is as follows: Figure 3 As shown;

[0097] The necessary parameter user interface is reserved in S5, including the following user-configurable parameters:

[0098] (1) Data width DATAWIDTH: used to specify the data width and floating point format;

[0099] (2) Step size STEP: used to configure the step length of each iteration of x;

[0100] (3) Half step length HALF_STEP: half of the step length STEP, used for calculating the K parameter;

[0101] (4) x start value X_START: used to configure the horizontal coordinate value of the starting point;

[0102] (5) x end value X_END: ​​used to configure the horizontal coordinate value of the end point;

[0103] (6) y starting value Y_INIT: used to configure the vertical coordinate value of the starting point, and together with X_START constitute the boundary condition of the function.

[0104] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A hardware logic real-time solution method for first-order linear differential equations based on FPGA, characterized in that: The following steps are involved: S1, construct the differential equation to be solved HDL module diffEqu; S2, based on the improved fourth-order Runge-Kutta algorithm numerical iterative solution model and the diffEqu module in S1 above, build a fully hardware-based, locally parallel computing K1, K2, K3, K4 parameter update module; S3, based on the parameter update module in S2, is constructed to calculate y n+1 The algorithm sub-top level module RK_calc_subtop; S4, based on the status register, build the real-time control module RK_CTRL, which has the functions of operating control of the RK_calc_subtop module and iterative calculation of the x variable; S5, based on all modules in S1 to S4, build the top-level module of the algorithm calculation model and reserve the necessary parameter user interface; The S1 includes the following steps: S11, the first-order linear differential equation to be solved Rewrite as form; S12, calling various floating-point operation IPs or writing FPGA logic, and implementing the f(x, y) part in S11 with an HDL module, wherein the module uses floating-point numbers x, y with configurable precision and their valid indication signals x_vld, y_vld as input signals, and uses floating-point numbers res in the same format and their valid indication signal res_vld as output signals; The fourth-order Runge-Kutta algorithm in S2 numerically iterates the solution model, that is, K1=f(x n ,y n ) (1) K4=f(x n +s,y n +s*K3) (4) Where s is the step size of one iteration of x, which comes from the user-defined parameter STEP; The S2 constructs a fully hardware-based, locally parallel calculation K1, K2, K3, K4 parameter update module, including the following steps: S21, construct a generalized parameter update module Kx_calc, the input signal of the module is the output signal of the previous parameter update module, the (half) step size and the initial value of x, y of one iteration, and the output signal is the Kx parameter; the module first adds the step size information and the parameter information calculated by the previous module to the x, y values ​​of this iteration in a parallel calculation manner to obtain x' and y', and then sends x' and y' to the instantiated diffEqu module to calculate the Kx parameter; S22, for the K1 parameter update module K1_calc, directly instantiate the diffEqu module; S23, for the K2, K3, K4 parameter updating modules K2_calc, K3_calc, K4_calc, respectively instantiate the generalized parameter updating module Kx_calc described in S21; S24, the above four parameter update modules run in parallel, and the register group Kx_res_cache is used to cache the calculation results of each parameter update module in one iteration cycle; the improved fourth-order Runge-Kutta algorithm numerical iterative solution model in S2, that is, for The calculation formula of the Kx parameter is simplified to the first-order linear differential equation of the form: K1=f(x n ) (6) K4=f(x n +s) (9) The above Kx parameters are calculated in parallel, so that the number of clocks consumed by the calculation is reduced to 1 / 4 of the original, and the 4-bit status register calc_complete is used to indicate that the parallel calculation is completed, and the calculation result is stored in the Kx_res_cache register group described in S24; The S3 construct is used to calculate y n+1 The algorithm sub-top module RK_calc_subtop includes the following steps: S31, using the output valid signal (high valid) of the K4_calc module in S23 as an enable signal, receiving the parallel data from the register group Kx_res_cache in S24, and sending it to the multiplication-addition tree for parallel calculation, the calculation formula is as shown in formula (5); S32, using the output data valid signal of the last floating-point multiplication and addition unit as an iteration completion signal, and sending the data y obtained in one iteration to the n+1 The valid signal of the data is sent to the real-time control module RK_CTRL in S4; The 1-bit status register runtime_flag in S4 is used to indicate the iteration status. Specifically, "0" indicates that the iteration is finished or not started, and "1" indicates that the iteration is in progress. Its value comes from the sign bit of the difference between the x variable and the end value X_END set by the user. The real-time control module RK_CTRL is constructed in S4, which has the functions of operating control of the RK_calc_subtop module, iterative calculation of the x variable, etc., including the following steps: S41, calculate the sum of x and the step size parameter STEP set by the user to obtain the initial value x of the next iteration n+1 ; S42, x n+1 Same as S32 n+1 After data alignment, it is sent to RK_calc_subtop together with the start pulse start_one_Kx_calc as the output signal of the real-time control module RK_CTRL to instruct the RK_calc_subtop module to perform the next iterative calculation; In S31, the parallel data of the register group Kx_res_cache is sent to the multiplication-addition tree for parallel calculation, which includes the following steps: S311, the first level parallel structure, includes two floating point multiplication and addition units, which are used to calculate K1+2K2 and 2K3+K4 in formula (5), and the results are recorded as R1 and R2; S312, the second level parallel structure includes a floating point addition unit and a floating point division unit, which are used to calculate the sum of K1+2K2 and 2K3+K4 in S311, and the result is recorded as R3, and The result is recorded as R4; S313, the third level parallel structure, includes a floating point multiplication and addition unit, which implements the whole formula (5), that is, to obtain y n+1 =y n +R3*R4.

2. The method for solving the first-order linear differential equation in real time based on hardware logic of FPGA according to claim 1, characterized in that: The necessary parameter user interface is reserved in S5, including the following user-configurable parameters: 1) Data width DATAWIDTH: used to specify data width and floating point format; 2) Step size STEP: used to configure the step length of each iteration of x; 3) Half step length HALF_STEP: half of the step length STEP, used for calculating the K parameter; 4) x start value X_START: used to configure the horizontal coordinate value of the starting point; 5) x end value X_END: ​​used to configure the horizontal coordinate value of the end point; 6) y starting value Y_INIT: used to configure the vertical coordinate value of the starting point, and together with X_START constitute the boundary condition of the function.

3. The method for solving the first-order linear differential equation in real time based on hardware logic of FPGA according to claim 1, characterized in that: There is a one-to-one correspondence between the input and output signals of the Kx_calc module. The input signal is the calculated value of the previous parameter update module, the valid signal of the calculated value, the initial value of x and the initial value of y in this iteration cycle. The corresponding output signal is the calculated value of the current parameter update module, the valid signal of the calculated value, the initial value of x and the initial value of y in this iteration cycle.

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