Semiconductor memory device and operating method thereof

Abstract

The present application relates to a semiconductor memory device and an operation method thereof. According to an embodiment of the present disclosure, the semiconductor memory device includes: a first buffer circuit, adapted to receive a command / address signal according to a first control signal to output a first buffer signal; a first setting / holding circuit, adapted to delay the first buffer signal according to a second control signal to output an internal command / address signal; a command decoder, adapted to generate a plurality of internal signals by decoding the internal command / address signal according to a third control signal and an internal clock signal; and a timing controller, adapted to delay a clock enable signal to generate first to third control signals, and control the first to third control signals to be deactivated in a first order when entering a power-down mode, and activated in a second order different from the first order when exiting the power-down mode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2020-0140154, filed on October 27, 2020, which is hereby incorporated by reference in its entirety.

[0003] Technical Area

[0004] The present disclosure relates to semiconductor design technology, and in particular to a semiconductor device capable of supporting an asynchronous power-down mode. Background Art

[0005] Recently, since semiconductor devices may have a period in which no operation is performed, semiconductor devices may have a power-down mode to reduce current consumption. For example, during a period in which no data is input or output, a memory device may enter a power-down mode in which no operation is performed on a memory block other than a specific internal block.

[0006] In addition, the memory device in the semiconductor device uses the clock enable signal to perform the operation of entering / exiting the power-down mode. Such a memory device receives a clock enable signal provided from the outside, and generates a plurality of internal signals for controlling an internal circuit (e.g., a buffer) by synchronizing the clock enable signal with an internal clock signal, thereby performing the entry / exit operation of entering / exiting the power-down mode. That is, by synchronizing the asynchronously input clock enable signal with the internal clock signal, the generation of abnormal glitches that may occur on the internal signal can be prevented.

[0007] However, this requires switching the internal clock signal all the time, which results in a larger current consumption. In addition, when the clock buffer is changed due to a change between high-speed operation and low-speed operation, the buffer change operation is performed before the clock enable signal reaches a logic low level, and the frequency change operation is performed after the clock enable signal enters the power-down mode, i.e., during the power-down mode. At this time, the clock buffer can be used as a buffer that is not suitable for the operating frequency during the interval before the frequency change operation is performed after the buffer change operation. For example, the clock buffer may be used as a low-speed buffer in high-speed operation, or may be used as a high-speed buffer in low-speed operation. Therefore, the clock buffer may not be able to generate a normal internal clock signal, and therefore, the internal signal generated by synchronizing the internal clock signal during the entry / exit operation of entering / exiting the power-down mode is also abnormally generated, which may cause a malfunction of the memory device. Summary of the invention

[0008] According to various embodiments of the present disclosure, a semiconductor memory device and an operating method thereof are provided, which can generate an internal signal for entering / exiting operation of entering / exiting a power-down mode by asynchronously controlling a clock enable signal input from the outside without synchronizing to an internal clock signal.

[0009] According to one embodiment of the present disclosure, a semiconductor memory device includes a first buffer circuit, adapted to receive a command / address signal according to a first control signal to output a first buffer signal; a first set / hold circuit, adapted to delay the first buffer signal according to a second control signal to output an internal command / address signal; a command decoder, adapted to generate a plurality of internal signals by decoding the internal command / address signal according to a third control signal and an internal clock signal; and a timing controller, adapted to delay a clock enable signal to generate first to third control signals, and to control the first to third control signals to be deactivated in a first sequence when entering a power-down mode, and to be activated in a second sequence different from the first sequence when exiting the power-down mode.

[0010] According to one embodiment of the present disclosure, an operating method of a semiconductor memory device includes: delaying a clock enable signal to generate first to third control signals; receiving a command / address signal according to the first control signal to output a first buffer signal; delaying the first buffer signal by a target setup / hold time according to a second control signal to output an internal command / address signal; generating a plurality of internal signals by decoding the internal command / address signal according to a third control signal and an internal clock signal; and controlling the first to third control signals to be deactivated in a first sequence when entering a power-down mode, and to be activated in a second sequence different from the first sequence when exiting the power-down mode.

[0011] According to one embodiment of the present disclosure, a semiconductor memory device includes: a first circuit capable of operating according to a first control signal; a second circuit capable of operating according to a second control signal; a third circuit capable of operating according to a third control signal; and a control circuit suitable for disabling first to third control signals in a first sequence and enabling the first to third control signals in a second sequence asynchronously with an internal clock signal generated in the semiconductor memory device.

[0012] According to an embodiment of the present disclosure, a semiconductor memory device can reduce current consumption due to switching of an internal clock signal by controlling an entry / exit operation into / out of a power-down mode in an asynchronous manner that is not synchronized with the internal clock signal.

[0013] According to an embodiment of the present disclosure, a semiconductor memory device can asynchronously control entry / exit operations into / out of a power-down mode by preventing abnormal generation of an internal signal when changing between a high-speed operation and a low-speed operation, thereby preventing malfunctions. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a block diagram showing a semiconductor memory device according to an embodiment of the present invention.

[0015] Figure 2 It is shown Figure 1 Circuit diagram of the timing controller.

[0016] Figure 3 Is used to describe Figure 2 A waveform diagram of the operation of the timing controller. DETAILED DESCRIPTION

[0017] The following describes various embodiments of the present disclosure with reference to the accompanying drawings. However, these embodiments can be implemented in different forms and should not be interpreted as being limited to the embodiments set forth herein. Throughout this disclosure, the same reference numerals represent the same components in the various drawings and embodiments of the present invention. It should be noted that reference to "an embodiment", or "another embodiment", etc. does not necessarily mean only one embodiment, and different references to any such terms do not necessarily mean the same embodiment. The term "embodiment" used herein does not necessarily refer to all embodiments.

[0018] It will be understood that although the terms "first," "second," "third," etc. may be used herein to identify various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element that otherwise has the same or similar name. Thus, a first element in one instance may also be referred to as a second or third element in another instance without indicating any change in the element itself.

[0019] It will also be understood that when an element is referred to as being "connected to" or "coupled to" another element, it can be directly on the other element, connected to or coupled to the other element, or there can be one or more intervening elements. In addition, it will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or there can also be one or more intervening elements. Unless otherwise specified or context dictates otherwise, communication between two elements, whether directly or indirectly connected / coupled, can be wired or wireless.

[0020] As used herein, singular forms may also include plural forms and vice versa, unless the context clearly indicates otherwise.

[0021] It will also be understood that the terms "including", "having" and the like used in this specification illustrate the presence of the stated elements, but do not exclude the presence or addition of one or more other elements. As used herein, the term "and / or" includes any and all combinations of one or more associated listed items.

[0022] Figure 1 is a block diagram showing a semiconductor memory device 100 according to an embodiment of the present invention.

[0023] Reference Figure 1 The semiconductor memory device 100 may include a first buffer circuit 112, a second buffer circuit 114, a third buffer circuit 116, a fourth buffer circuit 118, a first setup / hold circuit 122, a second setup / hold circuit 124, a first synchronization circuit 132, a second synchronization circuit 134, a command decoder 140, a timing controller 150 and an internal circuit 160.

[0024] The first buffer circuit 112 may receive the command / address signal CA<0:5> according to the first control signal BUFEN to output the first buffer signal CA_BUF<0:5>. The first buffer circuit 112 may have a plurality of buffer circuits corresponding to the bits in the command / address signal CA<0:5>, respectively. For example, when the command / address signal CA<0:5> consists of 6 bits, 6 buffer circuits 112_0 to 112_5 may be provided. Each of the first buffer circuits 112_0 to 112_5 may be implemented by a differential amplifier, which receives the corresponding bit of the command / address signal CA<0:5> through a first input terminal (+), and receives the reference voltage VREF through a second input terminal (-).

[0025] The second buffer circuit 114 may receive the chip selection signal CS according to the first control signal BUFEN to output the second buffer signal CS_BUF. The second buffer circuit 114 may be implemented by a differential amplifier that receives the chip selection signal CS through a first input terminal (+) and receives a reference voltage VREF through a second input terminal (-).

[0026] The third buffer circuit 116 may receive the clock enable signal CKE based on the reference voltage VREF to output the third buffer signal CKE_BUF. The third buffer circuit 116 may be implemented by a differential amplifier that receives the clock enable signal CKE through a first input terminal (+) and receives the reference voltage VREF through a second input terminal (-). For reference, the reference voltage VREF provided to the first to third buffer circuits 112, 114, and 116 may have the same voltage level, or voltage levels different from each other.

[0027] The fourth buffer circuit 118 may receive the differential clock signals CK_t and CK_b input from the outside to output the internal clock signal ICLK according to the third buffer signal CKE_BUF. According to one embodiment, the fourth buffer circuit 118 may receive a single-ended clock signal instead of the differential clock signals CK_t and CK_b. According to one embodiment, an internal clock generation circuit may be provided to generate the internal clock signal ICLK based on the output of the fourth buffer circuit 118. The internal clock generation circuit may be composed of a delay locked loop (DLL) or a phase locked loop (PLL).

[0028] The first set / hold circuit 122 may delay the first buffer signal CA_BUF<0:5> according to the second control signal CA_ON to output the internal command / address signal ICA<0:5>. The first set / hold circuit 122 may have a plurality of buffer circuits corresponding to the bits in the command / address signal CA<0:5>, respectively. The first set / hold circuit 122 may have a plurality of set / hold circuits corresponding to the bits in the command / address signal CA<0:5>, respectively. For example, when the command / address signal CA<0:5> consists of 6 bits, 6 set / hold circuits 122_0 to 122_5 may be provided.

[0029] The second setting / holding circuit 124 may delay the second buffer signal CS_BUF to output the internal chip selection signal ICS according to the second control signal CA_ON.

[0030] Each of the set / hold circuits 122_0 to 122_5 in the first set / hold circuit 122 may have substantially the same configuration as the second set / hold circuit 124, and thus the second set / hold circuit 124 will be described. The second set / hold circuit 124 may include a delay compensator SH_D and an output controller 124_0.

[0031] The delay compensator SH_D may delay the second buffer signal CS_BUF by a delay amount corresponding to the target setup / hold time. The output controller 124_0 may output the output of the delay compensator SH_D as the internal chip select signal ICS according to the second control signal CA_ON. The output controller 124_0 may output the output of the delay compensator SH_D as the internal chip select signal ICS when the second control signal CA_ON is activated, and mask the output of the delay compensator SH_D and output the internal chip select signal ICS having a logic low level when the second control signal CA_ON is deactivated. The second control signal CA_ON may be activated during normal mode, and deactivated during power-down mode to mask the output of the internal chip select signal ICS. The output controller 124_0 may include a logic NAND gate ND1 and an inverter INV1 to perform a logic AND operation on the output of the delay compensator SH_D and the second control signal CA_ON to output the internal chip select signal ICS.

[0032] The first synchronization circuit 132 may output the internal command / address signal ICA<0:5> by synchronizing with the internal clock signal ICLK. The first synchronization circuit 132 may have a plurality of synchronization circuits corresponding to the bits in the command / address signal CA<0:5>, respectively. For example, when the command / address signal CA<0:5> consists of 6 bits, 6 synchronization circuits 132_0 to 132_5 may be provided.

[0033] The second synchronization circuit 134 may output the internal chip selection signal ICS by synchronizing with the internal clock signal ICLK.

[0034] The command decoder 140 may generate a plurality of internal signals by decoding the internal command / address signal ICA<0:5> and the internal chip selection signal ICS according to the third control signal PWDDB and the internal clock signal ICLK. The internal signals may include an activation signal ACT, a precharge signal PCG, a read signal RD, a write signal WT, a refresh signal REF, a first mode register (MR) signal MRR, and a second MR signal MRW. The command decoder 140 may generate the internal signal by decoding the internal command / address signal ICA<0:5> and the internal chip selection signal ICS in synchronization with the internal clock signal ICLK during the normal mode. The command decoder 140 may deactivate or initialize the internal signal according to the third control signal PWDDB during the power-down mode.

[0035] The internal circuit 160 may operate in response to an internal signal. In the case of a semiconductor memory device, the internal circuit 160 may include a plurality of memory cells (not shown) and a peripheral circuit (not shown) for accessing the memory cells. The internal circuit 160 may perform normal operations, such as read or write operations, during a normal mode. For example, the internal circuit 160 may store write data DQ in a memory cell specified by an address in the internal command / address signal ICA<0:5> in response to an internal signal during a write operation. The internal circuit 160 may output read data DQ from a memory cell specified by an address in the internal command / address signal ICA<0:5> in response to an internal signal during a read operation. The internal circuit 160 may control any other peripheral circuits other than a specific peripheral circuit not to operate in response to an internal signal during a power-down mode.

[0036] In one implementation, the fourth buffer circuit 118 may include a first operation clock buffer 118_L and a second operation clock buffer 118_H. When the third buffer signal CKE_BUF is activated, the first operation clock buffer 118_L may buffer the differential clock signals CK_t and CK_b in response to at least one signal (e.g., the second MR signal MRW) selected from the internal signals to output an internal clock signal ICLK having a first frequency. The second operation clock buffer 118H may operate mutually exclusively with the first operation clock buffer 118_L. When the third buffer signal CKE_BUF is activated, the second operation clock buffer 118_H may buffer the differential clock signals CK_t and CK_b in response to the second MR signal MRW to output an internal clock signal ICLK having a second frequency higher than the first frequency. That is, during an interval in which the clock enable signal CKE is a logic high level, the fourth buffer circuit 118 may generate an internal clock signal ICLK having any frequency of a high frequency and a low frequency according to the value of the second MR signal MRW.

[0037] The timing controller 150 may delay the clock enable signal CKE to generate the first to third control signals BUFEN, CA_ON and PWDDB. In particular, since the timing controller 150 does not receive the internal clock signal ICLK, the timing controller 150 may output the first to third control signals BUFEN, CA_ON and PWDDB by asynchronously delaying the clock enable signal CKE regardless of the internal clock signal ICLK. The timing controller 150 may control the first to third control signals BUFEN, CA_ON and PWDDB to be deactivated in a first order when entering the power-down mode. The timing controller 150 may control the first to third control signals BUFEN, CA_ON and PWDDB to be activated in a second order different from the first order when exiting the power-down mode. For example, when entering the power-down mode, the timing controller 150 may sequentially deactivate the third control signal PWDDB, the second control signal CA_ON and the first control signal BUFEN according to the first order. When exiting the power down mode, the timing controller 150 may sequentially activate the third control signal PWDDB, the first control signal BUFEN, and the second control signal CA_ON according to the second order.

[0038] For reference, the first control signal BUFEN may be used as a buffer enable signal for controlling the first and second buffer circuits 112 and 114 to receive the command / address signal CA<0:5> and the chip select signal CS. That is, during the power-down mode, the first control signal BUFEN is deactivated to a logic low level so that the first and second buffer circuits 112 and 114 are disabled. The second control signal CA_ON may be used as an output control signal for masking the output control signal from the first and second setting / holding circuits 122 and 124. That is, during the power-down mode, the second control signal CA_ON is deactivated to a logic low level to output the internal command / address signal ICA<0:5> and the internal chip select signal ICS to be fixed to a logic low level. The third control signal PWDDB may be used as a power-down signal for setting the power-down mode of the internal circuit 160. That is, during the power-down mode, the third control signal PWDDB is deactivated to a logic low level so that the command decoder 140 deactivates the internal signal to set the internal circuit 160 to operate in the power-down mode.

[0039] Figure 2 It is shown Figure 1 1 is a circuit diagram of a timing controller 150.

[0040] Reference Figure 2 , the timing controller 150 may include a first delay circuit DLY1 , ​​a second delay circuit DLY2 , a third delay circuit DLY3 , a first logic circuit 151 , a second logic circuit 152 , and a third logic circuit 153 .

[0041] The first delay circuit DLY1 may delay the third buffer signal CKE_BUF by a first delay amount to output a first delay signal CKED1. The second delay circuit DLY2 may delay the first delay signal CKED1 by a second delay amount to output a second delay signal CKED2. The third delay circuit DLY3 may delay the second delay signal CKED2 by a third delay amount to output a third delay signal CKED3. For example, the first to third delay amounts may be substantially the same. However, the present invention is not limited thereto, and one or more delay amounts may be controlled to have different delay times.

[0042] The first logic circuit 151 may output a first control signal BUFEN according to the third buffer signal CKE_BUF and the third delay signal CKED3. For example, the first logic circuit 151 may include a first buffer BF1 for buffering the third buffer signal CKE_BUF and a first logic gate OR1 for performing a logic OR operation on the output of the first buffer BF1 and the third delay signal CKED3. In one embodiment, the first buffer BF1 may include an even number (e.g., 2) of inverters coupled in series, and the first logic gate OR1 may be composed of a logic OR gate. At this time, the delay time caused by the first buffer BF1 may be less than the first to third delay amounts. As described above, the first logic circuit 151 may output a first control signal BUFEN, which is deactivated to a logic low level when the third delay signal CKED3 is deactivated, and is activated to a logic high level after the third buffer signal CKE_BUF is activated.

[0043] The second logic circuit 152 may output the second control signal CA_ON by buffering the second delay signal CKED2. The second logic circuit 152 may include an even number (e.g., 2) of inverters coupled in series. As described above, the second logic circuit 152 may output the second control signal CA_ON, which is deactivated to a logic low level after the second delay signal CKED2 is deactivated, and is activated to a logic high level after the second delay signal CKED2 is activated.

[0044] The third logic circuit 153 may output the third control signal PWDDB according to the third buffer signal CKE_BUF and the first delay signal CKED1. For example, the third logic circuit 153 may include a second logic gate OR2 for performing a logic OR operation on the third buffer signal CKE_BUF and the first delay signal CKED1. In one embodiment, the second logic gate OR2 may be composed of a logic OR gate. As described above, the third logic circuit 153 may output the third control signal PWDDB, which is deactivated to a logic low level when the first delay signal CKED1 is deactivated, and is activated to a logic high level when the third buffer signal CKE_BUF is activated.

[0045] Figure 3 Is used to describe Figure 2 1 is a waveform diagram of the operation of the timing controller 150.

[0046] Reference Figure 3 , the first to third delay circuits DLY1 to DLY3 sequentially delay the third buffer signal CKE_BUF to output first to third delay signals CKED1 to CKED3.

[0047] The third logic circuit 153 deactivates the third control signal PWDDB to a logic low level when the first delay signal CKED1 is deactivated. The second logic circuit 152 deactivates the second control signal CA_ON to a logic low level after a preset time from the deactivation of the second delay signal CKED2. The first logic circuit 151 deactivates the first control signal BUFEN to a logic low level when the third delay signal CKED3 is deactivated. Therefore, when entering the power-down mode, the timing controller 150 can control the first to third control signals BUFEN, CA_ON and PWDDB to be deactivated according to the first order in which the third control signal PWDDB, the second control signal CA_ON and the first control signal BUFEN are sequentially deactivated.

[0048] Thereafter, the third logic circuit 153 activates the third control signal PWDDB to a logic high level when the third buffer signal CKE_BUF is activated. The first logic circuit 151 activates the first control signal BUFEN to a logic high level after a preset time from the activation of the third buffer signal CKE_BUF. The second logic circuit 152 activates the second control signal CA_ON to a logic high level after a preset time from the activation of the second delay signal CKED2. Therefore, when exiting the power-down mode, the timing controller 150 can control the first to third control signals BUFEN, CA_ON, and PWDDB to be activated according to the second order in which the third control signal PWDDB, the first control signal BUFEN, and the second control signal CA_ON are sequentially activated.

[0049] As described above, since the second control signal CA_ON is deactivated prior to the first control signal BUFEN when entering the power-down mode, the internal command / address signal ICA<0:5> and the internal chip select signal ICS can be masked before the first and second buffer circuits 112 and 114 are disabled. Therefore, the generation of abnormal glitches that occur when the first and second buffer circuits 112 and 114 are disabled can be prevented. In addition, since the third control signal PWDDB is deactivated prior to the second control signal CA_ON, the command decoder 140 can be prevented from generating unexpected internal signals due to the internal command / address signal ICA<0:5> and the internal chip select signal ICS.

[0050] In addition, when exiting the power down mode, the third control signal PWDDB is first activated to enable the command decoder 140. Thereafter, since the first control signal BUFEN is activated prior to the second control signal CA_ON, the generation of abnormal glitches occurring when the first and second buffer circuits 112 and 114 are enabled can be masked by the second control signal CA_ON.

[0051] As described above, according to an embodiment of the present disclosure, a semiconductor memory device can reduce current consumption due to switching of an internal clock signal by controlling an entry / exit operation of entering / exiting a power-down mode in an asynchronous manner that is not synchronized with an internal clock signal. According to an embodiment of the present disclosure, a semiconductor memory device can prevent malfunctions by asynchronously controlling an entry / exit operation of entering / exiting a power-down mode and by preventing abnormal generation of an internal signal when changing between a high-speed operation and a low-speed operation.

[0052] It should be noted that although the technical spirit of the present disclosure has been described in conjunction with the various embodiments of the present disclosure, this is for descriptive purposes only and should not be interpreted as limiting. A person skilled in the art should recognize that various changes can be made without departing from the technical spirit of the present disclosure.

[0053] For example, different positions and types of logic gates and transistors provided as examples in the above embodiments may be implemented according to the polarity of the input signal.

[0054] While the present teachings have been illustrated and described with respect to the particular embodiments, it will be apparent to those skilled in the art that, in light of this disclosure, various changes and modifications may be made without departing from the spirit and scope of the disclosure as defined in the appended claims.

Claims

1. A semiconductor memory device, comprising: A first buffer circuit, adapted to receive a command / address signal according to a first control signal to output a first buffer signal; a first set / hold circuit adapted to delay the first buffer signal to output an internal command / address signal according to a second control signal; a command decoder adapted to generate a plurality of internal signals by decoding the internal command / address signal according to a third control signal and an internal clock signal; as well as A timing controller, adapted to: delay a clock enable signal to generate the first control signal to a third control signal, and control the first control signal to the third control signal to be deactivated in the order of the third control signal, the second control signal and the first control signal when entering a power-down mode, and to be activated in the order of the third control signal, the first control signal and the second control signal when exiting the power-down mode.

2. The semiconductor memory device according to claim 1, wherein: The timing controller does not receive the internal clock signal, and outputs the first to third control signals by asynchronously delaying the clock enable signal independently of the internal clock signal.

3. The semiconductor memory device according to claim 1, further comprising: a second buffer circuit, adapted to receive a chip selection signal according to the first control signal to output a second buffer signal; The second setting / holding circuit is adapted to delay the second buffer signal according to the second control signal to output an internal chip selection signal.

4. The semiconductor memory device according to claim 3, wherein: Each of the first set / hold circuit and the second set / hold circuit comprises: a delay compensator adapted to delay a corresponding buffered signal of the first buffered signal and the second buffered signal by an amount corresponding to a target setup / hold time; An output controller is adapted to: output the output of the delay compensator as a corresponding internal signal between the internal command / address signal and the internal chip select signal when the second control signal is activated, and mask the output of the delay compensator and fix the corresponding internal signal to a preset logic level when the second control signal is deactivated.

5. The semiconductor memory device according to claim 3, in, The command decoder generates the internal signal by further decoding the internal chip select signal in synchronization with the internal clock signal during a normal mode, and The command decoder deactivates the internal signal according to the third control signal during the power-down mode.

6. The semiconductor memory device according to claim 1, further comprising an internal circuit adapted to operate in response to the internal signal. 7 . The semiconductor memory device according to claim 1 , further comprising a third buffer circuit adapted to receive the clock enable signal based on a reference voltage to output a third buffer signal.

8. The semiconductor memory device according to claim 7, further comprising: a first operational clock buffer adapted to: buffer an external clock signal in response to at least one internal signal selected from the internal signals to output the internal clock signal having a first frequency when the third buffer signal is activated; as well as The second operational clock buffer is adapted to buffer the external clock signal in response to the selected internal signal to output an internal clock signal having a second frequency higher than the first frequency when the third buffer signal is activated.

9. The semiconductor memory device according to claim 7, in, The timing controller receives the third buffer signal, Wherein, the timing controller comprises: A first delay circuit, adapted to delay the third buffer signal by a first delay amount to output a first delayed signal; A second delay circuit, adapted to delay the first delay signal by a second delay amount to output a second delay signal; a third delay circuit, adapted to delay the second delayed signal by a third delay amount to output a third delayed signal; a first logic circuit, adapted to output the first control signal according to the third buffered signal and the third delayed signal; a second logic circuit adapted to output the second control signal by buffering the second delayed signal; and The third logic circuit is adapted to output the third control signal according to the third buffer signal and the first delay signal.

10. The semiconductor memory device according to claim 9, wherein: The first delay circuit comprises: a first buffer adapted to buffer the third buffer signal; and A first logic gate is used to perform a logic OR operation on the output of the first buffer and the third delayed signal.

11. The semiconductor memory device according to claim 9, wherein: The second delay circuit includes a second logic gate configured to perform a logic OR operation on the third buffered signal and the first delayed signal.

12. A method for operating a semiconductor memory device, comprising: delaying a clock enable signal to generate first to third control signals; receiving a command / address signal according to the first control signal to output a first buffer signal; delaying the first buffer signal by a target setup / hold time according to the second control signal to output an internal command / address signal; generating a plurality of internal signals by decoding the internal command / address signal according to the third control signal and the internal clock signal; as well as The first to third control signals are controlled to be deactivated in the order of the third control signal, the second control signal and the first control signal when entering the power-down mode, and to be activated in the order of the third control signal, the first control signal and the second control signal when exiting the power-down mode.

13. The operating method according to claim 12, wherein: The clock enable signal is asynchronously delayed independent of the internal clock signal.

14. The operating method according to claim 12, further comprising: receiving a chip selection signal according to the first control signal to output a second buffer signal; as well as The second buffer signal is delayed by the target setup / hold time according to the second control signal to output an internal chip selection signal.

15. The operating method according to claim 14, in, generating the internal signal during a normal mode by further decoding the internal chip select signal in synchronization with the internal clock signal, and Also included is deactivating the internal signal according to the third control signal during the power down mode.

16. The operating method according to claim 12, further comprising: When a clock enable signal is activated, in response to at least one internal signal selected from the internal signals, an external clock signal is buffered to output the internal clock signal having a first frequency or a second frequency higher than the first frequency.

17. The operating method according to claim 12, further comprising operating an internal circuit in response to the internal signal.

18. The operating method according to claim 12, wherein: Delaying the clock enable signal includes: receiving the clock enable signal based on a reference voltage to output a third buffered signal; delaying the third buffered signal by a first delay amount to output a first delayed signal; Delaying the first delayed signal by a second delay amount to output a second delayed signal; delaying the second delayed signal by a third delay amount to output a third delayed signal; outputting the first control signal according to the third buffered signal and the third delayed signal; outputting the second control signal by buffering the second delayed signal; and The third control signal is output according to the third buffered signal and the first delayed signal.

19. A semiconductor memory device comprising: a first circuit capable of operating according to a first control signal; a second circuit capable of operating according to a second control signal; a third circuit capable of operating according to a third control signal; as well as A control circuit is adapted to: asynchronously with an internal clock signal generated in the semiconductor memory device, disable the first control signal to the third control signal in the order of the third control signal, the second control signal and the first control signal and enable the first control signal to the third control signal in the order of the third control signal, the first control signal and the second control signal.

20. The semiconductor memory device according to claim 19, in, The first circuit is adapted to generate a first operating signal, wherein the second circuit is adapted to generate a second operation signal based on the first operation signal, and The third circuit is adapted to perform an operation based on the second operation signal.

21. The semiconductor memory device according to claim 19, wherein: The control circuit disables control signals in the order of the third control signal, the second control signal, and the first control signal when the semiconductor memory device enters a power-down mode.

22. The semiconductor memory device according to claim 21, wherein The control circuit enables control signals in the order of the third control signal, the first control signal, and the second control signal when the semiconductor memory device exits the power-down mode.

23. The semiconductor memory device according to claim 20, wherein: The first circuit is a buffer circuit adapted to generate a first buffer signal as the first operation signal according to a command / address signal.

24. The semiconductor memory device according to claim 23, wherein: The second circuit is a set / hold circuit adapted to delay the first buffer signal to generate an internal command / address signal as the second operation signal.

25. The semiconductor memory device according to claim 24, wherein: The third circuit is a command decoder adapted to decode the internal command / address signal to generate a plurality of internal signals.

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