eFuse storage unit, security key device and key setting method thereof, and electronic device

Abstract

The present invention relates to an eFuse storage unit, a security key device, a key setting method thereof, and an electronic device. The eFuse storage unit includes: a first transistor, the source of which is connected to a programming voltage output terminal; a ferroelectric capacitor, one end of which is connected to the drain of the first transistor and the other end of which is connected to a pulse voltage output terminal; and a programming bit line connected to the gate of the first transistor. The eFuse storage unit can be read and programmed multiple times, that is, it can be reused multiple times.

Description

Technical Field

[0001] The present invention relates to the field of efuse technology, and in particular to an eFuse storage unit, a security key device, a reading and writing method thereof, and an electronic device. Background Art

[0002] eFuse (electrically programmable fuse) technology is a one-time programmable memory technology widely used within chips. Similar to EEPROM, eFuse uses fuses to store information, which is written to the chip before it leaves the factory. Within a chip, eFuse capacity is typically very small, with some chips having only 128 bits. eFuse can be used to store memory repair data and chip information such as the chip's operating power supply voltage, chip version number, and production date. It can also be used for circuit security, as a circuit key, or to control the on / off state of on-chip circuits.

[0003] However, an eFuse can only be operated once, changing from storing a "1" to storing a "0" and cannot be changed. The fuse in an eFuse can be made of silicon or metal, and both work through electromigration, which is the phenomenon in which an electric current causes the conductive material to move. Over time, the "fuse debris" generated during programming will grow in the opposite direction. The same electromigration that caused the metal wire to disconnect can also cause the metal wire to inadvertently reconnect, thereby changing the data originally intended to be stored and causing incorrect behavior. This characteristic limits the number of times the eFuse can be read. At the same time, in terms of circuit safety, the programmed state of the eFuse can be detected through a microscope, making it relatively unsafe. Summary of the Invention

[0004] The present application provides an eFuse storage unit, a security key device, a reading and writing method thereof, and an electronic device. The eFuse storage unit can be read and programmed multiple times, thereby enabling the eFuse storage unit to be reused multiple times.

[0005] A first aspect provides an eFuse storage unit, comprising:

[0006] a first transistor, wherein a source of the first transistor is connected to a programming voltage output terminal;

[0007] a ferroelectric capacitor, one end of which is connected to the drain of the first transistor, and the other end of which is connected to the pulse voltage output end;

[0008] A programming bit line is connected to the gate of the first transistor.

[0009] In some embodiments, the eFuse storage unit further includes:

[0010] a second transistor, wherein the drain of the second transistor is connected to the other end of the ferroelectric capacitor, and the source of the second transistor is connected to the pulse voltage output end;

[0011] A word line is connected to the gate of the second transistor.

[0012] In some embodiments, the second transistor is an NMOS transistor.

[0013] In some embodiments, the first transistor is a PMOS transistor.

[0014] A second aspect provides a security key device, comprising:

[0015] A plurality of eFuse storage units, each of which corresponds to a key, and the eFuse storage unit is the eFuse storage unit described in the first aspect;

[0016] a programming voltage generator connected to the source of the first transistor and configured to output a programming voltage;

[0017] a pulse voltage generator connected to the other end of the ferroelectric capacitor and configured to output a pulse voltage;

[0018] A sensitive amplifier is connected to a node where the first transistor of each eFuse storage unit and the ferroelectric capacitor are connected, and is used for sampling the storage information of each ferroelectric capacitor.

[0019] In some embodiments, the security key device further comprises:

[0020] a first voltage sensor connected to the source of the first transistor of each eFuse storage unit, configured to sample the voltage input to the source of the first transistor, and output corresponding alarm information to the programming generator and the pulse voltage generator when an abnormal voltage is sampled;

[0021] The second voltage sensor is connected to the other end of the ferroelectric capacitor of each eFuse storage unit and is used to sample the voltage at the other end of the ferroelectric capacitor. When an abnormal voltage is sampled, the second voltage sensor outputs corresponding alarm information to the programming generator and the pulse voltage generator.

[0022] In some embodiments, the plurality of eFuse memory cells are arranged in a matrix.

[0023] A third aspect provides a key setting method for a security key device, which is applied to the above-mentioned security key device, including:

[0024] Controlling the first transistor to be turned off, the pulse signal generator to output a pulse voltage, and the sense amplifier to extract the key information of each eFuse storage unit;

[0025] After the key extraction is completed, the first transistor is controlled to be turned on, so that the source of the first transistor is grounded, and the pulse signal generator outputs a pulse voltage to write the overwriting information into the ferroelectric capacitor to overwrite the key information stored in the ferroelectric capacitor;

[0026] The first transistor is controlled to be turned on, and according to the preset key information of each eFuse storage unit, a programming voltage generator is controlled to output a programming voltage corresponding to the preset key information, and a pulse signal generator is controlled to output a pulse voltage so that the preset key information is written into the ferroelectric capacitor.

[0027] In some embodiments, the key setting method further includes, when an abnormal voltage is detected at the source of the first transistor and / or the other end of the ferroelectric capacitor, turning on the first transistor, grounding the source of the first transistor, and outputting a pulse voltage to the other end of the ferroelectric capacitor.

[0028] A fourth aspect provides an electronic device comprising the security key device as described above.

[0029] The above-mentioned eFuse storage unit, security key device and its reading and writing method, and electronic device, the circuit element for storing data in the eFuse storage unit uses ferroelectric capacitors to replace electric fuses. Ferroelectric capacitors, as a new type of memory, have the advantages of high-speed reading and writing, low power consumption, long service life, non-volatile storage, good radiation resistance, secondary reading and recovery of ferroelectric charges, etc. Therefore, the eFuse storage unit can be re-encoded, thereby realizing the reuse of the eFuse storage unit, and can then be used for chip security keys, and has broad application prospects in the field of chip security. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A circuit diagram of an eFuse storage unit provided in one embodiment;

[0031] Figure 2 This is an operation timing diagram of each eFuse storage unit in a key setting method of a security key device provided in one embodiment. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0033] It will be understood that the terms "first," "second," etc. used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element.

[0034] like Figure 1 As shown, Figure 1 The following is a schematic diagram of the circuit structure of an eFuse storage unit. In one embodiment, an eFuse storage unit may include:

[0035] a first transistor, wherein a source of the first transistor is connected to a programming voltage output terminal;

[0036] a ferroelectric capacitor, one end of the ferroelectric capacitor being connected to the drain of the first transistor, and the other end being connected to the pulse voltage output end;

[0037] A programming bit line is connected to the gate of the first transistor.

[0038] In this embodiment, the circuit element used to store data uses ferroelectric capacitors to replace electric fuses. As a new type of memory, ferroelectric capacitors have the advantages of high-speed reading and writing, low power consumption, long service life, non-volatile storage, good radiation resistance, secondary reading and recovery of ferroelectric charges, etc. Therefore, the eFuse storage unit can be re-encoded, thereby realizing the reuse of the eFuse storage unit, which has broad application prospects.

[0039] In the above embodiment, the programming bit line is used to connect the on and off control terminals of the first transistor, and is a signal line that controls the programming operation. When programming the eFuse memory cell, the first transistor is turned on through the programming bit line, and a programming voltage VDD or 0 is applied to the source of the first transistor. Then, a pulse voltage (positive pulse waveform) is applied to the other end of the ferroelectric capacitor to realize programming of the eFuse memory cell.

[0040] In some embodiments, the eFuse storage unit may further include:

[0041] a second transistor, wherein the drain of the second transistor is connected to the other end of the ferroelectric capacitor, and the source of the second transistor is connected to the pulse voltage output end;

[0042] A word line is connected to the gate of the second transistor.

[0043] In this embodiment, the word line is used to connect the on and off control terminals of the second transistor, and is a control line that controls the on and off of the second transistor. The word line controls the second transistor to be turned off when not working, so as to reduce leakage current and reduce the overall power consumption of the eFuse storage unit.

[0044] Under the same size, the saturation current (Idsat) of the NMOS transistor is larger than that of the PMOS transistor. Therefore, in order to reduce leakage current, in an application scenario, the second transistor is an NMOS transistor and the first transistor is a PMOS transistor.

[0045] Of course, in another application scenario, the first transistor may be an NMOS transistor and the second transistor may be a PMOS transistor.

[0046] In one embodiment, a security key device may include:

[0047] A plurality of eFuse storage units, each eFuse storage unit being an eFuse storage unit of the above embodiment;

[0048] a programming voltage generator connected to the source of the first transistor and configured to output a programming voltage;

[0049] a pulse voltage generator connected to the other end of the ferroelectric capacitor and configured to output a pulse voltage;

[0050] The sensitive amplifier is connected to the node where the first transistor of each eFuse storage unit and the ferroelectric capacitor are connected, and is used for sampling the storage information of each ferroelectric capacitor.

[0051] In this embodiment, the eFuse memory cells are used for chip security keys (security key devices) by leveraging the secondary read and restore properties of ferroelectric charges. Each eFuse memory cell corresponds to one key. A programming voltage generator outputs a voltage of VDD or 0, which, in conjunction with a pulse generator outputting a pulse voltage, writes the key into the eFuse memory cell. When setting the key for the security key device, the key is written to each eFuse memory cell in sequence. The eFuse memory cells can be rewritten with keys, and before writing a new key to an eFuse memory cell, the current key in each eFuse memory cell is cleared (overwritten) in sequence.

[0052] In one application scenario, the process of writing key information to each eFuse storage unit can be: controlling the first transistor and the second transistor of each eFuse storage unit to be turned on, making the programming voltage VQ = VDD or = 0 according to the key information, and then controlling the pulse voltage VK to pass a positive pulse waveform with an amplitude = VDD. When VQ = VDD, the voltage across the ferroelectric capacitor (ferroic memory) C0 is initially = +VDD, C0 is in a positive polarization state, and the initial data "0" is stored. When VQ = 0, the voltage across the ferroelectric capacitor C0 is = -VDD, C0 is in a negative polarization state, and the initial data "1" is stored, completing the writing of the key in the eFuse.

[0053] During use, each eFuse storage unit can be periodically tested for faults. Figure 1 The eFuse storage unit in the may specifically include:

[0054] Each eFuse memory cell is opened in sequence through the programming bit line BL and word line WL. When the corresponding eFuse memory cell fails, the transmitted VQ = 0, and the periodic detection signal VK sends a positive pulse. At this time, when the pulse arrives, the voltage across the ferroelectric capacitor C0 = -VDD, which is in negative polarization and stores data 1. Then the first transistor is turned off, the sensitive amplifier SA is turned on, and a positive pulse voltage is applied to VK. Regardless of whether the storage information of the ferroelectric capacitor C0 is "0" or "1", the polarization state of the ferroelectric capacitor will reach a positive saturation state. If the storage information of the eFuse memory cell is "0", the sensitive amplifier SA detects signal 0 and does not prompt fault information. If the storage information of the eFuse memory cell is "1", the sensitive amplifier SA detects signal 1, and the circuit prompts fault information.

[0055] In some embodiments, the security key device may further include:

[0056] a first voltage sensor connected to the source of the first transistor of each eFuse storage unit, for sampling the voltage input to the source of the first transistor, and outputting corresponding alarm information to the programming generator and the pulse voltage generator when an abnormal voltage is sampled;

[0057] The second voltage sensor is connected to the other end of the ferroelectric capacitor of each eFuse storage unit and is used to sample the voltage at the other end of the ferroelectric capacitor. When an abnormal voltage is sampled, the second voltage sensor outputs corresponding alarm information to the programming generator and the pulse voltage generator.

[0058] In this embodiment, when a key attacker captures key information through chip detection, the voltage sensor captures the external signal and samples an abnormal voltage. For example, the source voltage of the first transistor is greater than VDD. At this time, the source of the first transistor is controlled to be grounded, and a positive pulse waveform is passed into the source of the second transistor to complete the overwriting of the key information and protect information security.

[0059] like Figure 2 As shown, a key setting method for a security key device according to an embodiment may include: key information overwriting and key information writing, wherein:

[0060] Key information coverage includes:

[0061] Controlling the first transistor to be turned off, the pulse signal generator to output a pulse voltage, and the sense amplifier to extract the key information of each eFuse storage unit;

[0062] After the key extraction is completed, the first transistor is controlled to be turned on, so that the source of the first transistor is grounded, and the pulse signal generator outputs a pulse voltage to write the overwriting information into the ferroelectric capacitor to overwrite the key information stored in the ferroelectric capacitor;

[0063] Key information writing includes:

[0064] The first transistor is controlled to be turned on, and according to the preset key information of each eFuse storage unit, the programming voltage generator is controlled to output a programming voltage corresponding to the preset key information, and the pulse signal generator is controlled to output a pulse voltage to write the preset key information into the ferroelectric capacitor.

[0065] In this embodiment, the security key device corresponds to an n-bit key, and n eFuse storage units can be made to correspond one to one. Taking the key setting method of the security key device in the above embodiment as an example:

[0066] The key information is written (in factory programming mode) by controlling the programming bit line BL and word line WL of each eFuse storage unit to turn on the first transistor and the second transistor, and make VQ = VDD or = 0 according to the key information. Then, VK is controlled to pass a positive pulse waveform with amplitude = VDD. When VQ = VDD, the voltage across the ferroelectric capacitor C0 is initially = +VDD, and the ferroelectric capacitor C0 is in a positive polarization state, storing the initial data "0". When VQ = 0, the voltage across the ferroelectric capacitor C0 is = -VDD, and the ferroelectric capacitor C0 is in a negative polarization state, storing the initial data "1", completing the writing of the key in the eFuse storage unit.

[0067] During key information overwriting (operating mode), each eFuse memory cell is opened by controlling the programming bit line BL and word line WL of each eFuse memory cell. When the entire device is placed in a security module to extract the key, the first transistor P0 is turned off, the sense amplifier SA is turned on, and a positive pulse voltage is applied to the source electrode VK of the second transistor. At this time, regardless of whether the stored information in the ferroelectric capacitor C0 is "0" or "1", the polarization state of the ferroelectric capacitor will reach a positive saturation state. If the eFuse memory cell stores "0", the sense amplifier SA detects a signal of 0 and extracts the key bit "0". If the FeRAM stores "1", the SA detects a signal of 1 and extracts the key bit "1".

[0068] When the key extraction is completed, the first transistor P0 is turned on again, making VQ = 0, and then VK passes a positive pulse waveform with amplitude = VDD, so that the voltage across the ferroelectric capacitor C0 = -VDD, C0 is in a negative polarization state, overwriting the information previously stored in C0, and completing the purpose of one-time reading and writing.

[0069] After the working mode operation is completed, the eFuse module can be reprogrammed for reuse.

[0070] In some embodiments, the key setting method further includes, when an abnormal voltage is detected at the source of the first transistor and / or the other end of the ferroelectric capacitor, turning on the first transistor, grounding the source of the first transistor, and outputting a pulse voltage to the other end of the ferroelectric capacitor.

[0071] In this embodiment, a sensor can be added to the VQ end and the VK end. When a key attacker wants to capture key information through chip detection, the sensor captures the external signal, controls the VQ end to input 0, and passes a positive pulse waveform into the VK end to complete the overwriting of the key information and protect information security.

[0072] An electronic device includes the security key device of the above embodiment.

[0073] Those skilled in the art will appreciate that all or part of the processes in the above-described method embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium. When executed, the program can include the processes in the above-described method embodiments. The aforementioned storage medium can be a non-volatile storage medium such as a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

[0074] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0075] The above embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make numerous modifications and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A security key device, characterized in that: include: A plurality of eFuse storage units, each of the eFuse storage units corresponding to a key; The eFuse storage unit includes: a first transistor, wherein the source of the first transistor is used to connect to the programming voltage output terminal; a ferroelectric capacitor, wherein one end of the ferroelectric capacitor is connected to the drain of the first transistor, and the other end is used to connect to the pulse voltage output terminal; a programming bit line, which is connected to the gate of the first transistor; a second transistor, wherein the drain of the second transistor is connected to the other end of the ferroelectric capacitor, and the source of the second transistor is used to connect to the pulse voltage output terminal; and a word line, which is connected to the gate of the second transistor. a programming voltage generator connected to the source of the first transistor and configured to output a programming voltage; a pulse voltage generator connected to the other end of the ferroelectric capacitor and configured to output a pulse voltage; a sensitive amplifier connected to a node where the first transistor of each eFuse storage unit and the ferroelectric capacitor are connected, and configured to sample storage information of each ferroelectric capacitor; The security key device further comprises: a first voltage sensor connected to the source of the first transistor of each eFuse storage unit, configured to sample a voltage input to the source of the first transistor, and output corresponding alarm information to the programming voltage generator and the pulse voltage generator when an abnormal voltage is sampled; The second voltage sensor is connected to the other end of the ferroelectric capacitor of each eFuse storage unit and is used to sample the voltage at the other end of the ferroelectric capacitor. When an abnormal voltage is sampled, the second voltage sensor outputs corresponding alarm information to the programming voltage generator and the pulse voltage generator.

2. The security key device according to claim 1, wherein: The multiple eFuse storage units are arranged in a matrix.

3. A key setting method for a security key device, characterized in that: The security key device according to any one of claims 1 to 2 comprises: Controlling the first transistor to be turned off, the pulse signal generator to output a pulse voltage, and the sense amplifier to extract the key information of each eFuse storage unit; After the key extraction is completed, the first transistor is controlled to be turned on, so that the source of the first transistor is grounded, and the pulse signal generator outputs a pulse voltage to write the overwriting information into the ferroelectric capacitor to overwrite the key information stored in the ferroelectric capacitor; The first transistor is controlled to be turned on, and according to the preset key information of each eFuse storage unit, a programming voltage generator is controlled to output a programming voltage corresponding to the preset key information, and a pulse signal generator is controlled to output a pulse voltage so that the preset key information is written into the ferroelectric capacitor.

4. The key setting method of the security key device according to claim 3, characterized in that: The key setting method further includes, when detecting abnormal voltage of the source of the first transistor and / or the other end of the ferroelectric capacitor, turning on the first transistor, grounding the source of the first transistor, and outputting a pulse voltage to the other end of the ferroelectric capacitor.

5. An electronic device, characterized in that: Comprising the security key device according to any one of claims 1 to 2.

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