Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same include: providing a substrate comprising adjacent device regions and dummy pattern regions, the device region substrate having device mask sidewalls and the dummy pattern region substrate having dummy mask sidewalls; forming a filling layer on the substrate to cover the device mask sidewalls and the dummy mask sidewalls; etching the filling layer and a portion of the height of the dummy mask sidewalls in the dummy pattern region to form remaining dummy mask sidewalls, wherein the remaining dummy mask sidewalls and the filling layer form a trench; forming a sidewall protection layer on the sidewalls of the trench; etching away the remaining dummy mask sidewalls; removing the sidewall protection layer; removing the filling layer; and etching the substrate using the device mask sidewalls as a mask. The present invention removes the dummy mask sidewalls through two etching steps, and after forming the sidewall protection layer, a second etching step is performed. Under the protective effect of the sidewall protection layer, the probability of the device mask sidewalls being erroneously etched is reduced, so that the device mask sidewalls have a lower line width roughness, thereby improving the performance of the semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Driven by Moore's Law, semiconductor technology continues to advance toward smaller process nodes. While device functionality continues to grow with advancements in semiconductor technology, the complexity of semiconductor manufacturing also increases. Photolithography is a critical production technology in semiconductor manufacturing. As semiconductor process nodes continue to shrink, existing light source lithography technology is no longer able to meet the demands of semiconductor manufacturing.

[0003] As Moore's Law continues its irreversible march forward, self-aligned double patterning (SADP) has become a favored patterning method in recent years. This technology can increase the density of patterns formed on a substrate and further reduce the pitch between two adjacent patterns, thereby enabling the photolithography process to overcome the limits of photolithography resolution. Summary of the Invention

[0004] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the semiconductor structure.

[0005] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, comprising adjacent device areas and pseudo-pattern areas, wherein a device mask sidewall is formed on the substrate of the device area, and a pseudo-mask sidewall is formed on the substrate of the pseudo-pattern area; forming a filling layer on the substrate, wherein the filling layer covers the device mask sidewall and the pseudo-mask sidewall; in the pseudo-pattern area, etching the filling layer and a portion of the height of the pseudo-mask sidewall to form a remaining pseudo-mask sidewall, wherein the remaining pseudo-mask sidewall and the filling layer form a groove; forming a sidewall protection layer on the sidewall of the groove; after forming the sidewall protection layer, etching away the remaining pseudo-mask sidewall; removing the sidewall protection layer; after removing the sidewall protection layer, removing the filling layer; after removing the filling layer, etching the substrate using the device mask sidewall as a mask.

[0006] Correspondingly, an embodiment of the present invention also provides a semiconductor structure, including: a substrate, including adjacent device areas and pseudo-graphic areas; a device mask sidewall, located on the substrate of the device area, the device mask sidewall being used as a mask for etching the substrate; the remaining pseudo-mask sidewall to be etched and removed, located on the substrate of the pseudo-graphic area, the top of the remaining pseudo-mask sidewall being lower than the top of the device mask sidewall; a filling layer, located on the substrate, the filling layer covering the device mask sidewall and exposing the top of the remaining pseudo-mask sidewall, the filling layer and the remaining pseudo-mask sidewall forming a groove; and a sidewall protection layer located on the sidewall of the groove.

[0007] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0008] In the formation method provided by the embodiment of the present invention, a filling layer and a pseudo mask sidewall of a partial height are first etched in the pseudo pattern area to form a remaining pseudo mask sidewall, wherein the remaining pseudo mask sidewall and the filling layer form a trench, and then a sidewall protection layer is formed on the sidewall of the trench. After the sidewall protection layer is formed, the remaining pseudo mask sidewall is etched away. Compared with the solution of etching away the pseudo mask sidewall in the same etching step, the embodiment of the present invention etches away the pseudo mask sidewall through two etching steps, and the second etching step is performed after the sidewall protection layer is formed. Under the protection of the sidewall protection layer, during the process of etching away the remaining pseudo mask sidewall, the lateral etching of the sidewall of the trench by the etching process can be reduced, thereby reducing the probability of the device mask sidewall adjacent to the pseudo mask sidewall being mistakenly etched, and correspondingly making the device mask sidewall have a lower line width roughness (LWR). The device mask sidewalls are used as a mask for etching the substrate, thereby improving the line width uniformity of the target pattern formed after etching the substrate, reducing the line width roughness of the target pattern, and thus improving the performance of the semiconductor structure.

[0009] In an optional solution, after etching away the remaining pseudo-mask side walls and before removing the sidewall protection layer, a sacrificial layer is formed on the substrate where the filling layer is exposed, and the sacrificial layer exposes the sidewall protection layer. The sacrificial layer can protect the substrate during the process of removing the sidewall protection layer, thereby reducing the probability of the substrate being damaged during the process of removing the sidewall protection layer. Accordingly, after subsequently etching the substrate with the device mask side walls as a mask, the line width uniformity of the target pattern formed can be improved, the line width roughness of the target pattern can be reduced, and the pitch walking (i.e., odd-even effect) problem of the target pattern can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figures 1 to 3 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;

[0011] Figures 4 to 13 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0012] The performance of current semiconductor structures needs to be improved. The reasons why the performance needs to be improved are analyzed in conjunction with a method for forming a semiconductor structure.

[0013] Figures 1 to 3 The present invention is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure.

[0014] refer to Figure 1 , providing a substrate (not marked), including adjacent device area I and dummy pattern area II, a mask sidewall 50 is formed on the substrate, wherein the mask sidewall 50 located in the device area I serves as a device mask sidewall 52, and the mask sidewall 50 located in the dummy pattern area II serves as a dummy mask sidewall 51.

[0015] As an example, the mask spacer 50 is formed by a self-aligned double patterning (SADP) process.

[0016] In this embodiment, the substrate includes an initial substrate 10, a buffer layer 20 located on the initial substrate 10, and a hard mask material layer 30 located on the buffer layer 20. An etch stop layer 40 is also formed on the substrate, and the device mask sidewalls 52 and the dummy mask sidewalls 51 are located on the etch stop layer 40.

[0017] Combined with reference Figure 1 and Figure 2 , a cutting process is performed to remove part of the pseudo mask sidewall 51 in the pseudo pattern area II.

[0018] Specifically, the cutting process includes: forming a filling layer 60 on the substrate, the filling layer 60 covering the device mask side wall 52 and the pseudo mask side wall 51; forming a blocking layer 61 on the filling layer 60, an opening 62 being formed in the blocking layer 61, the opening 62 exposing a portion of the filling layer 60 in the pseudo graphic area II; using the blocking layer 61 as a mask, etching the filling layer 60 and the pseudo mask side wall 51 along the opening 62; and removing the blocking layer 61 and the filling layer 60.

[0019] refer to Figure 3 , repeat the cutting process once or multiple times to remove the dummy mask sidewalls 51 in the remaining dummy pattern area II.

[0020] Subsequent steps also include: using the device mask sidewall 52 as a mask, etching the etch stop layer 40 and the hard mask material layer 30, and patterning the hard mask material layer 30 into a hard mask layer; using the hard mask layer as a mask, etching the buffer layer 20 and the initial substrate 10, and patterning the initial substrate 10 into a substrate and a fin protruding from the substrate.

[0021] As the feature size of integrated circuits continues to decrease, the spacing between adjacent mask sidewalls 50 continues to decrease. Therefore, in the process of etching the filling layer 60 and the dummy mask sidewalls 51 along the opening 62, it takes a long time to etch the dummy mask sidewalls 51. The process of removing the dummy mask sidewalls 51 is likely to cause the device mask sidewalls 52 adjacent to the dummy mask sidewalls 51 to be mistakenly etched, which can easily lead to an increase in the line width roughness of the device mask sidewalls 52 and a decrease in the line width uniformity of the device mask sidewalls 52. In particular, when there is overlay shift in the process of forming the opening 62, the probability of the above problems occurring is higher. Therefore, when the pattern of the device mask sidewalls 52 is subsequently transferred to the substrate, it is easy to cause a decrease in the accuracy of the pattern transfer, for example, resulting in a low line width accuracy of the fin and a high line width roughness of the fin, thereby causing a decrease in the performance of the semiconductor structure.

[0022] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, comprising adjacent device areas and pseudo-pattern areas, wherein a device mask sidewall is formed on the substrate of the device area, and a pseudo-mask sidewall is formed on the substrate of the pseudo-pattern area; forming a filling layer on the substrate, wherein the filling layer covers the device mask sidewall and the pseudo-mask sidewall; in the pseudo-pattern area, etching the filling layer and a portion of the height of the pseudo-mask sidewall to form a remaining pseudo-mask sidewall, wherein the remaining pseudo-mask sidewall and the filling layer form a groove; forming a sidewall protection layer on the sidewall of the groove; after forming the sidewall protection layer, etching away the remaining pseudo-mask sidewall; removing the sidewall protection layer; after removing the sidewall protection layer, removing the filling layer; after removing the filling layer, etching the substrate using the device mask sidewall as a mask.

[0023] The embodiment of the present invention etches away the pseudo-mask sidewalls through two etching steps, and after forming a sidewall protection layer, a second etching step is performed. Under the protection of the sidewall protection layer, in the process of etching away the remaining pseudo-mask sidewalls, the lateral etching of the sidewalls of the trench by the etching process can be reduced, thereby reducing the probability of the device mask sidewalls adjacent to the pseudo-mask sidewalls being mistakenly etched, and correspondingly making the device mask sidewalls have lower line width roughness, thereby improving the line width uniformity of the device mask sidewalls. Since the substrate is subsequently etched using the device mask sidewalls as a mask, this improves the accuracy of the pattern transfer, thereby improving the performance of the semiconductor structure.

[0024] In order to make the above-mentioned objects, features and advantages of the embodiments of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0025] Figures 4 to 13 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0026] refer to Figure 4 , providing a substrate (not marked), including adjacent device area I and dummy pattern area II, wherein a device mask sidewall 220 is formed on the substrate of the device area I, and a dummy mask sidewall 210 is formed on the substrate of the dummy pattern area II.

[0027] After the subsequent patterning process, the substrate is used to form a target pattern. In this embodiment, the substrate includes an initial substrate 100 and a hard mask material layer 120 located on the initial substrate 100. The initial substrate 100 is used to form a fin, that is, the target pattern is a fin.

[0028] In other embodiments, the base may also include a substrate and a gate material layer located on the substrate, wherein the gate material layer is used to form a gate structure, that is, the target pattern is a gate structure.

[0029] In this embodiment, the material of the initial substrate 100 is silicon. In other embodiments, the material of the initial substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium. The initial substrate may also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0030] In subsequent manufacturing processes, a pattern is first defined in hard mask material layer 120 to form a patterned hard mask layer, which serves as a mask for etching initial substrate 100. By first transferring the pattern to hard mask material layer 120 and then to initial substrate 100, the accuracy of the pattern transfer is improved. Furthermore, in the subsequent planarization process to form the isolation layer, the top surface of the hard mask layer is used to define the stop position of the planarization process.

[0031] The material of the hard mask material layer 120 is a nitrogen-containing material, resulting in high hardness and density. In this embodiment, the material of the hard mask material layer 120 includes one or more of silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. These materials have high density and hardness, and during the subsequent etching process of the initial substrate 100, the initial substrate 100 material has a high etching selectivity compared to these materials. As an example, the material of the hard mask material layer 120 is silicon nitride.

[0032] It should be noted that the base also includes a buffer layer 110 located between the initial substrate 100 and the hard mask material layer 120. The buffer layer 110 has good adhesion to the hard mask material layer 120, and also to the initial substrate 100. Furthermore, the buffer layer 110 is used to provide a stress buffer during the formation of the hard mask material layer 120, thereby alleviating the problem of dislocations generated during the formation of the hard mask material layer 120. In this embodiment, the material of the buffer layer 110 is silicon oxide.

[0033] The device mask sidewalls 220 are used as a mask for subsequent etching of the substrate. The material of the device mask sidewalls 220 may include one or more of silicon oxide, silicon nitride, silicon, titanium oxide, titanium nitride, and tungsten carbide. In this embodiment, the material of the device mask sidewalls 220 is silicon nitride.

[0034] The pseudo mask sidewall 210 is located on the substrate of the pseudo pattern area II. The pseudo mask sidewall 210 and the device mask sidewall 220 constitute the mask sidewall 200 (eg, Figure 4 By forming the dummy mask spacers 210, the pattern density of the mask spacers 200 is increased. This improves the etching load effect caused by the pattern density during the formation of the device mask spacers 220 and the dummy mask spacers 210, thereby improving the line width uniformity of the device mask spacers 220. The dummy mask spacers 210 and the device mask spacers 220 are formed in the same step, and therefore, the dummy mask spacers 210 and the device mask spacers 220 are made of the same material.

[0035] In this embodiment, a self-aligned multi-patterning process is used to form the dummy mask spacers 210 and the device mask spacers 220. This increases the density of target patterns formed on the substrate and further reduces the pitch between adjacent target patterns, thereby enabling the photolithography process to overcome the limitations of photolithography resolution. For example, the self-aligned multi-patterning process can be a self-aligned double patterning (SADP) process or a self-aligned quadruple patterning (SAQP) process.

[0036] Specifically, taking the SADP process as an example, the steps of forming the device mask sidewalls 220 and the dummy mask sidewalls 210 include: forming a core layer (not shown) on a substrate; forming mask sidewalls 200 on the sidewalls of the core layer, wherein the mask sidewalls 200 located in the device region I serve as the device mask sidewalls 220, and the mask sidewalls 200 located in the dummy pattern region II serve as the dummy mask sidewalls 210; and removing the core layer. In other embodiments, the material layers corresponding to the dummy mask sidewalls and the device mask sidewalls can be directly etched using photolithography and etching processes to form the dummy mask sidewalls and the device mask sidewalls, respectively. For example, the LELE (photolithography-etching-photolithography-etching) process can be used to form the dummy mask sidewalls and the device mask sidewalls.

[0037] It should also be noted that before forming the device mask spacers 220 and the dummy mask spacers 210 , the forming method further includes: forming an etch stop layer 130 on the substrate. Specifically, the etch stop layer 130 is formed on the hard mask material layer 120 .

[0038] The process of forming the device mask sidewall 220 and the pseudo mask sidewall 210 includes an etching process. During the etching process, the etch stop layer 130 can define the etching stop position in the etching process, thereby reducing the probability of etching damage to the hard mask material layer 120, thereby reducing the probability of height inconsistency problems on the top surface of the hard mask material layer 120, which is correspondingly beneficial to improving the accuracy of subsequent graphic transfer.

[0039] The material of the etch stop layer 130 includes one or more of silicon nitride, titanium nitride, tungsten carbide, silicon oxide, silicon oxycarbide, and silicon oxycarbonitride. In this embodiment, the material of the etch stop layer 130 is silicon oxide.

[0040] refer to Figure 5 A filling layer 300 is formed on the substrate (not shown), and the filling layer 300 covers the device mask spacer 220 and the dummy mask spacer 210 .

[0041] The filling layer 300 is used to protect the device mask sidewalls 220 during the subsequent etching process of the dummy mask sidewalls 210. In addition, the filling layer 300 is also used to provide a flat surface for the subsequent formation of a shielding layer.

[0042] The material used for the filling layer 300 has good filling properties and easily fills the space between adjacent mask sidewalls. Furthermore, the filling layer 300 has a high degree of flatness and is easily etched, thereby reducing the difficulty of etching the filling layer 300 and the subsequent removal of the filling layer 300. Furthermore, the material of the filling layer 300 has a high etch selectivity with the material of the device mask sidewalls 220. This means that the probability of damage to the device mask sidewalls 220 during etching of the filling layer 300 is low. The material of the filling layer 300 also has a high etch selectivity with the material of the etch-stop layer 130, thereby reducing the probability of damage to the etch-stop layer 130 during etching or removal of the filling layer 300.

[0043] Therefore, the material of the filling layer 300 is an organic material. Specifically, the material of the filling layer 300 includes a spin-on carbon (SOC) material, a bottom anti-reflective coating (BARC) material, a dielectric anti-reflective coating (DARC) material, a deep UV light absorbing oxide (DUO) material, or an advanced patterning film (APF) material.

[0044] In this embodiment, the filling layer 300 is made of an advanced pattern film material. Subsequent processes further include etching the filling layer 300 and a portion of the dummy mask sidewall 210 in the dummy pattern region II to form a remaining dummy mask sidewall. The remaining dummy mask sidewall and the filling layer 300 form a trench. Due to the excellent physical properties of the advanced pattern film material, the trench sidewalls exhibit low line edge roughness (LER) after formation, thereby improving the trench sidewall topography and line width uniformity (CDU).

[0045] In this embodiment, the forming method further includes: forming a shielding layer 310 on the filling layer 300 , wherein an opening 320 is formed in the shielding layer 310 to expose the filling layer 300 of the dummy pattern region II.

[0046] When the filling layer 300 and a portion of the height of the dummy mask sidewall spacer 210 are subsequently etched, the blocking layer 310 is used as an etching mask, and the opening 320 defines the area to be etched.

[0047] In this embodiment, the opening 320 is formed in the shielding layer 310 using a LELE (lithography-etching-lithography-etching) process, thereby enabling the lithography process to overcome the limitations of lithography resolution. The LELE process follows a lithography-etching-lithography-etching process sequence. Its main principles are: first, a first partial pattern is formed on a first layer of photoresist through exposure and development. Next, the first partial pattern is transferred to the underlying shielding layer 310 through etching. Then, a second layer of photoresist is spin-coated and exposed and developed to form a second partial pattern. Finally, the second partial pattern is transferred to the underlying shielding layer 310 through etching.

[0048] In this embodiment, along a direction parallel to the substrate surface and perpendicular to the side wall of the dummy mask side wall 210 , the width of the opening 320 is greater than the width of the dummy mask side wall 210 , thereby increasing the process window for forming the opening 320 and making it easier for the opening 320 to be located above the dummy mask side wall 210 .

[0049] The width difference between the opening 320 and the dummy mask sidewall 210 should not be too small or too large. If the width difference between the opening 320 and the dummy mask sidewall 210 is too small, the relative positions of the opening 320 and the dummy mask sidewall 210 may easily shift, for example, causing a serious overlay shift during the formation of the opening 320. If the width difference between the opening 320 and the dummy mask sidewall 210 is too large, when the filling layer 300 and a portion of the height of the dummy mask sidewall 210 are subsequently etched along the opening 320, the device mask sidewall 220 may be exposed after etching the filling layer 300, thereby causing the device mask sidewall 220 to be mistakenly etched. Therefore, in this embodiment, the width difference between the opening 320 and the dummy mask sidewall 210 is 3 to 4 nanometers.

[0050] The material of the shielding layer 310 includes one or more of silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the material of the shielding layer 310 is silicon oxide. Silicon nitride has a higher etching selectivity than silicon oxide. Moreover, silicon oxide is easy to remove.

[0051] refer to Figure 6 In the dummy pattern region II, the filling layer 300 and a portion of the dummy mask sidewall 210 are etched to form a remaining dummy mask sidewall 230 . The remaining dummy mask sidewall 230 and the filling layer 300 form a trench 330 .

[0052] The groove 330 is used to provide a space for the subsequent formation of a sidewall protection layer.

[0053] Subsequently, after a sidewall protection layer is formed on the sidewall of the trench 330, the remaining pseudo-mask sidewall 230 is etched away. That is, in this embodiment, the pseudo-mask sidewall 210 is removed through two etching steps, and a second etching step is performed after the sidewall protection layer is formed. Under the protection of the sidewall protection layer, during the process of etching away the remaining pseudo-mask sidewall 230, the lateral etching of the sidewall of the trench 330 by the etching process can be reduced, thereby reducing the probability of the device mask sidewall 220 adjacent to the pseudo-mask sidewall 210 being mistakenly etched, and accordingly making the device mask sidewall 220 have a lower line width roughness, thereby improving the line width uniformity of the device mask sidewall 220. Since the substrate is subsequently etched using the device mask sidewall 220 as a mask, the accuracy of the graphic transfer is improved, thereby improving the performance of the semiconductor structure.

[0054] In this embodiment, an anisotropic etching process is used to etch the filling layer 300 and a portion of the height of the dummy mask sidewall 210. The vertical etching rate of the anisotropic etching process is greater than its lateral etching rate, thereby improving the sidewall morphology quality of the trench 330, reducing the amount of lateral etching, and correspondingly reducing the possibility of exposing the device mask sidewall 220.

[0055] It should be noted that, in the step of etching a portion of the height of the pseudo-mask sidewall 210, the ratio of the amount of vertical etching of the pseudo-mask sidewall 210 to the height of the pseudo-mask sidewall 210 should not be too small or too large. If the ratio is too small, that is, the height of the remaining pseudo-mask sidewall 230 is still relatively large, and the time required for subsequent etching of the remaining pseudo-mask sidewall 230 is relatively long. In the process of etching the remaining pseudo-mask sidewall 230, not only the vertical etching is performed, but also a certain amount of lateral etching is generated. Therefore, the probability of the device mask sidewall 220 being mistakenly etched is still relatively high. If the ratio is too small, that is, in the process of forming the trench 330, the amount of vertical etching of the pseudo-mask sidewall 210 is relatively large. In the process of etching the pseudo-mask sidewall 210, not only the vertical etching is performed, but also a certain amount of lateral etching is generated. This also increases the probability of the device mask sidewall 220 being mistakenly etched. Therefore, in this embodiment, in the step of etching a portion of the height of the dummy mask spacer 210, the longitudinal etching amount of the dummy mask spacer 210 is 1 / 3 to 1 / 2 of the height of the dummy mask spacer 210. The longitudinal direction refers to a direction perpendicular to the substrate surface, and the transverse direction refers to a direction parallel to the substrate surface and perpendicular to the sidewalls of the dummy mask spacer 210.

[0056] In this embodiment, in the step of etching the filling layer 300 and a portion of the height of the dummy mask sidewall spacer 210 , etching is performed along the opening 320 using the blocking layer 310 as a mask.

[0057] It should be noted that, compared with the solution of repeating multiple etching processes, in which each etching process is used to etch the pseudo mask sidewall of a part of the pseudo graphic area, this embodiment etches the filling layer 300 and the pseudo mask sidewall 210 of a partial height in one etching process, thereby improving the etching uniformity.

[0058] It should also be noted that after the groove 330 is formed, the shielding layer 310 is retained, so that in the subsequent process, the shielding layer 310 can protect the top of the filling layer 300, thereby reducing the probability of damage to the top of the filling layer 300, and further reducing the probability of the device mask side wall 220 being exposed.

[0059] Combined with reference Figure 7 and Figure 8 , forming a sidewall protection layer 350 (such as Figure 8 shown).

[0060] In the subsequent process of etching and removing the remaining pseudo-mask sidewalls 230, the sidewall protection layer 350 is used to protect the sidewalls of the trench 330, which can reduce the lateral etching of the sidewalls of the trench 330 by the process of etching the remaining pseudo-mask sidewalls 230, thereby reducing the probability of the device mask sidewalls 220 adjacent to the remaining pseudo-mask sidewalls 230 being mistakenly etched, and accordingly makes the device mask sidewalls 220 have lower line width roughness, thereby improving the line width uniformity of the device mask sidewalls 220. Since the substrate is subsequently etched using the device mask sidewalls 220 as a mask, this improves the accuracy of the graphic transfer, thereby improving the performance of the semiconductor structure.

[0061] When the remaining dummy mask sidewalls 230 are subsequently etched, a high etching selectivity is achieved between the remaining dummy mask sidewalls 230 and the sidewall protection layer 350, thereby enabling the sidewall protection layer 350 to protect the sidewalls of the trench 330. Specifically, the etching selectivity between the remaining dummy mask sidewalls 230 and the sidewall protection layer 350 is greater than 5:1.

[0062] Therefore, the material of the sidewall protection layer 350 includes one or more of silicon nitride, silicon carbonitride, silicon carbon nitride oxide, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the material of the sidewall protection layer 350 is silicon oxide. The material of the remaining dummy mask sidewall 230 is silicon nitride. The etching selectivity between silicon nitride and silicon oxide is relatively high, and silicon oxide is easy to remove.

[0063] In addition, in this embodiment, the sidewall protection layer 350 and the shielding layer 310 are made of the same material, which facilitates the subsequent removal of the sidewall protection layer 350 and the shielding layer 310 in the same step.

[0064] It should be noted that the thickness of the sidewall protection layer 350 should not be too small or too large. If the thickness of the sidewall protection layer 350 is too small, then during the subsequent etching process to remove the remaining pseudo-mask sidewall 230, the sidewall protection layer 350 has a low ability to protect the sidewalls of the trench 330, and the probability of the device mask sidewall 220 adjacent to the pseudo-mask sidewall 210 being mistakenly etched is correspondingly high; if the thickness of the sidewall protection layer 350 is too large, then the sidewall protection layer 350 is likely to block the remaining pseudo-mask sidewall 230, thereby affecting the subsequent etching of the remaining pseudo-mask sidewall 230. For this reason, in this embodiment, the thickness of the sidewall protection layer 350 is to For example, the thickness of the sidewall protection layer 350 is or

[0065] In this embodiment, the step of forming the sidewall protection layer 350 on the sidewall of the trench 330 includes: Figure 7 As shown, a sidewall protection material layer 340 is formed to conformally cover the bottom and sidewalls of the trench 330 and the top of the filling layer 300; Figure 8 As shown, the sidewall protection material layer 340 at the bottom of the trench 330 and the top of the filling layer 300 is removed, and the remaining sidewall protection material layer 340 at the sidewall of the trench 330 is retained as the sidewall protection layer 350. Specifically, the sidewall protection material layer 340 covers the top of the blocking layer 310.

[0066] In this embodiment, the sidewall protection material layer 340 is formed using an atomic layer deposition (ALD) process. The sidewall protection material layer 340 formed using the ALD process has good thickness uniformity and good step coverage. In other embodiments, a high aspect ratio chemical vapor deposition process can be used to form the sidewall protection material layer, which also provides good step coverage.

[0067] In this embodiment, a maskless anisotropic etching process is used to longitudinally etch the sidewall protection material layer 340 in a direction perpendicular to the substrate surface to form the sidewall protection layer 350. By using a maskless etching process, the thickness restrictions imposed by the photolithography process on the sidewall protection material layer 340 are reduced, allowing the thickness of the sidewall protection material layer 340 to be reduced. Furthermore, the longitudinal etching rate of the anisotropic etching process is greater than its lateral etching rate, thereby allowing the sidewall protection material layer 340 located at the top of the blocking layer 310 and the bottom of the trench 330 to be removed while retaining the sidewall protection material layer 340 located on the sidewalls of the trench 330.

[0068] A shielding layer 310 is formed on the top of the filling layer 300. Therefore, during the etching process of the sidewall protection material layer 340, the shielding layer 310 protects the top of the filling layer 300, thereby reducing the probability of the device mask sidewall 220 being exposed.

[0069] refer to Figure 9 After forming the sidewall protection layer 350, the remaining pseudo mask sidewall 230 is removed by etching (eg Figure 8 shown).

[0070] By removing the remaining dummy mask sidewalls 230, the pattern of the remaining dummy mask sidewalls 230 is prevented from being transferred to the substrate. A sidewall protection layer 350 is formed on the sidewalls of the trench 330. This reduces the lateral etching of the sidewalls of the trench 330 during the etching process to remove the remaining dummy mask sidewalls 230, thereby reducing the probability of the device mask sidewalls 220 adjacent to the dummy mask sidewalls 210 being mistakenly etched.

[0071] It should be noted that, affected by the etching process, the sidewalls of the groove 330 have a certain inclination, and after the remaining pseudo-mask sidewalls 230 are etched away, the angle between the sidewalls of the filling layer 300 exposed by the sidewall protection layer 350 and the substrate surface is usually also an obtuse angle, that is, in the direction from the top of the filling layer 300 to its bottom, the lateral distance between the sidewalls of the filling layer 300 exposed by the sidewall protection layer 350 and the device mask sidewalls 220 gradually increases. Therefore, even if the sidewall protection layer 350 only covers the sidewalls of the groove 330, the probability of the device mask sidewalls 220 being mistakenly etched is also low during the process of etching away the remaining pseudo-mask sidewalls 230.

[0072] In this embodiment, an anisotropic etching process is used to etch away the remaining dummy mask sidewalls 230 , thereby reducing the amount of lateral etching and further reducing the probability of the device mask sidewalls 220 being mistakenly etched.

[0073] It should be noted that, during the process of etching the remaining dummy mask sidewalls 230 , the filling layer 300 at the bottom of the trench 330 will also be etched.

[0074] Combined with reference Figure 10 and Figure 11 , remove the sidewall protection layer 350 (such as Figure 10 shown).

[0075] The sidewall protection layer 350 is removed to prepare for the subsequent removal of the filling layer 300 .

[0076] As an example, a wet etching process is used to etch away the sidewall protection layer 350. The wet etching process has the characteristic of isotropic etching, which is conducive to completely removing the sidewall protection layer 350.

[0077] It should be noted that the shielding layer 310 (such as Figure 10 As shown) is formed on the top of the filling layer 300, therefore, when the remaining pseudo mask sidewall 230 (as shown) is removed by etching, Figure 8 As shown), after removing the filling layer 300, the forming method further includes: removing the blocking layer 310.

[0078] Specifically, the blocking layer 310 and the sidewall protection layer 350 are made of the same material. Therefore, the blocking layer 310 and the sidewall protection layer 350 are removed in the same step, thereby simplifying the process steps.

[0079] like Figure 10 As shown, in this embodiment, after etching away the remaining pseudo mask sidewall 230 and before removing the sidewall protection layer 350 , the formation method further includes: forming a sacrificial layer 360 on the substrate exposed by the filling layer 300 , and the sacrificial layer 360 exposes the sidewall protection layer 350 .

[0080] The sacrificial layer 360 is used to protect the substrate during the process of removing the sidewall protection layer 350, thereby reducing the probability of the substrate being damaged during the process of removing the sidewall protection layer 350. Accordingly, after the substrate is subsequently etched using the device mask sidewall 220 as a mask, the line width uniformity of the formed target pattern can be improved, the line width roughness of the target pattern can be reduced, and the pitch walking (i.e., odd-even effect) problem of the target pattern can be improved.

[0081] The material of the sacrificial layer 360 is an organic material, thereby reducing the difficulty of forming the sacrificial layer 360 and the difficulty of subsequently removing the sacrificial layer 360. Moreover, the organic material can easily fill the space below the trench 330. Specifically, the material of the sacrificial layer 360 includes a spin-on carbon layer material, a bottom anti-reflective coating material, a dielectric anti-reflective coating material, a deep ultraviolet light absorbing oxide layer material, or an advanced patterned film material.

[0082] In this embodiment, the sacrificial layer 360 and the filling layer 300 are made of different materials. The sacrificial layer 360 exposes the sidewall protection layer 350. Therefore, the process of forming the sacrificial layer 360 generally includes an etch-back step. By making the sacrificial layer 360 and the filling layer 300 of different materials, damage to the filling layer 300 is reduced during the etch-back process, thereby reducing the probability of the device mask sidewall 220 being exposed or mistakenly etched.

[0083] In this embodiment, the sacrificial layer 360 is made of a carbon coating material. The carbon coating material is formed by a spin coating process, so that the sacrificial layer 360 can be easily filled into the space below the trench 330 .

[0084] Specifically, the step of forming the sacrificial layer 360 includes: forming a sacrificial material layer covering the filling layer 300 and the substrate; etching back the sacrificial material layer so that the remaining sacrificial material layer exposes the sidewall protection layer 350, and the remaining sacrificial material layer 360 serves as a sacrificial layer.

[0085] In this embodiment, an anisotropic etching process is used to etch back the sacrificial material layer.

[0086] It should be noted that the thickness of the sacrificial layer 360 should not be too small or too large. If the thickness of the sacrificial layer 360 is too small, the protective effect of the sacrificial layer 360 on the substrate is poor, and the probability of the substrate being damaged is correspondingly high during the removal of the sidewall protection layer 350; if the thickness of the sacrificial layer 360 is too large, it is easy to contact with the sidewall protection layer 350, thereby affecting the subsequent removal effect of the sidewall protection layer 350. For this reason, in this embodiment, the thickness of the sacrificial layer 360 is to For example, the thickness of the sacrificial layer 360 is or

[0087] refer to Figure 12 , remove the sidewall protection layer 350 (such as Figure 10 After that, the filling layer 300 (as shown) is removed. Figure 11 shown).

[0088] By removing the filling layer 300 , preparation is made for etching the substrate using the device mask sidewalls 220 as a mask.

[0089] As an example, the material of the filling layer 300 is an advanced pattern film material, and therefore, an ashing process is used to remove the filling layer 300 .

[0090] In this embodiment, after removing the sidewall protection layer 350, the forming method further includes: removing the sacrificial layer 360 (such as Figure 11 As shown), thereby preparing for and subsequent etching of the substrate.

[0091] As an example, the material of the sacrificial layer 360 is a carbon coating layer material, and therefore, an ashing process is used to remove the sacrificial layer 360 .

[0092] In this embodiment, the materials of the filling layer 300 and the sacrificial layer 360 are both organic materials. Therefore, the filling layer 300 and the sacrificial layer 360 are removed in the same ashing step, thereby simplifying the process steps.

[0093] refer to Figure 13 , remove the filling layer 300 (such as Figure 11 As shown) and sacrificial layer 360 (as Figure 11 As shown), the substrate is etched using the device mask sidewall 220 as a mask.

[0094] The pattern of the device mask sidewall 220 is transferred to the substrate to form a target pattern. The device mask sidewall 220 has a low line width roughness and high line width uniformity, thereby improving the accuracy of the pattern transfer, and correspondingly improving the line width uniformity of the formed target pattern, reducing the line width roughness of the target pattern, and improving the pitch walking (i.e., odd-even effect) problem of the target pattern, thereby improving the performance of the semiconductor structure.

[0095] Specifically, the step of etching the substrate using the device mask sidewall 220 as a mask includes: etching the hard mask material layer 120 (such as Figure 12 As shown in FIG), a hard mask layer 125 is formed. The hard mask layer 125 is used as a substrate for subsequent etching of the initial substrate 100 (as shown in FIG). Figure 12 ) mask.

[0096] Accordingly, the forming method further includes: using the hard mask layer 125 as a mask, etching the initial substrate 100 to form a substrate 400 and a fin 410 protruding from the substrate 400. In other words, the target pattern is the fin 410.

[0097] In this embodiment, an etch stop layer 130 is formed on the hard mask material layer 120, and a buffer layer 110 is formed between the hard mask material layer 120 and the initial substrate 100. Therefore, before etching the hard mask material layer 120, the etch stop layer 130 is first etched, and before etching the initial substrate 100, the buffer layer 110 is first etched.

[0098] In this embodiment, a dry etching process (e.g., an anisotropic dry etching process) is used to sequentially etch the etch-stop layer 130, the hard mask material layer 120, the buffer layer 110, and the initial substrate 100. The dry etching process has anisotropic etching characteristics, which is beneficial for improving the morphological quality and dimensional accuracy of the fin 410. Moreover, during the dry etching process, by adjusting the etching gas and etching parameters, the stop layer 130, the hard mask material layer 120, the buffer layer 110, and the initial substrate 100 can be sequentially etched in the same etching equipment, resulting in a simple process and no need to change equipment.

[0099] In this embodiment, the initial substrate 100 is an integral structure. Therefore, a portion of the thickness of the initial substrate 100 is etched, and the remaining initial substrate 100 serves as the substrate 400. The protrusions on the substrate 400 serve as the fins 410. The fins 410 and the substrate 400 are an integral structure, and the fins 410 and the substrate 400 are made of the same material.

[0100] It should be noted that the height of the dummy mask sidewalls 210 is generally greater than the thickness of the hard mask material layer 120 . Therefore, the dummy mask sidewalls 210 can be easily removed through two etching steps, and the process feasibility is high.

[0101] In other embodiments, depending on actual conditions, the patterns of the device mask side walls and the pseudo mask side walls can also be transferred to the hard mask material layer to form a first hard mask layer corresponding to the device mask side walls and a second hard mask layer corresponding to the pseudo mask side walls. After that, the second hard mask layer is removed through two etching steps, and a step of forming a side wall protection layer is provided between the two etching steps.

[0102] Accordingly, an embodiment of the present invention further provides a semiconductor structure. Figure 8 , showing a structural schematic diagram of an embodiment of a semiconductor structure of the present invention.

[0103] The semiconductor structure includes: a substrate (not labeled), including adjacent device region I and pseudo-pattern region II; a device mask sidewall 220, located on the substrate 100 in device region I, the device mask sidewall 220 being used as a mask for etching the substrate; a remaining pseudo-mask sidewall 230 to be etched and removed, located on the substrate in pseudo-pattern region II, the top of the remaining pseudo-mask sidewall 230 being lower than the top of the device mask sidewall 220; a filling layer 300, located on the substrate, the filling layer covering the device mask sidewall 220 and exposing the top of the remaining pseudo-mask sidewall 230, the filling layer 300 and the remaining pseudo-mask sidewall 230 forming a trench 330; and a sidewall protection layer 350, located on the sidewalls of the trench 330.

[0104] During the formation of the semiconductor structure, during the process of forming the device mask sidewalls 220, a dummy mask sidewall is formed on the substrate of the dummy pattern region II, and a portion of the thickness of the dummy mask sidewall is etched to form the remaining dummy mask sidewall 230. The remaining dummy mask sidewall 230 is subsequently removed by etching. Under the protection of the sidewall protection layer 350, the lateral etching of the sidewalls of the trench 330 by the etching process can be reduced during the process of removing the remaining dummy mask sidewall 230, thereby reducing the probability of the device mask sidewall 220 adjacent to the dummy pattern region II being mistakenly etched. Accordingly, the device mask sidewall 220 has a lower line width roughness, and the line width uniformity of the device mask sidewall 220 is improved. Since the device mask sidewall 220 is used as a mask for etching the substrate, this improves the accuracy of pattern transfer, thereby improving the performance of the semiconductor structure.

[0105] After the substrate undergoes a patterning process, it is used to form a target pattern. In this embodiment, the substrate includes an initial substrate 100 and a hard mask material layer 120 located on the initial substrate 100. The initial substrate 100 is used to form a fin, that is, the target pattern is a fin. In other embodiments, the substrate may also include a substrate and a gate material layer located on the substrate. The gate material layer is used to form a gate structure, that is, the target pattern is a gate structure.

[0106] In this embodiment, the material of the initial substrate 100 is silicon. In other embodiments, the material of the initial substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium. The initial substrate may also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0107] In the subsequent process, a pattern is first defined in the hard mask material layer 120 to form a patterned hard mask layer, so that the hard mask layer serves as a mask for etching the initial substrate 100. The material of the hard mask material layer 120 is a nitrogen-containing material, so that the hard mask material layer 120 has high hardness and density. In this embodiment, the material of the hard mask material layer 120 includes one or more of silicon nitride, silicon carbonitride, silicon carbonitride oxide, silicon oxynitride, boron nitride, and boron carbonitride. These materials have high density and hardness, and in the subsequent process of etching the initial substrate 100, the etching selectivity of the material of the initial substrate 100 and the above materials is relatively high. As an example, the material of the hard mask material layer 120 is silicon nitride.

[0108] It should be noted that the base also includes a buffer layer 110 located between the initial substrate 100 and the hard mask material layer 120. The buffer layer 110 has good adhesion to the hard mask material layer 120, and also to the initial substrate 100. Furthermore, the buffer layer 110 is used to provide a stress buffer during the formation of the hard mask material layer 120, thereby alleviating the problem of dislocations generated during the formation of the hard mask material layer 120. In this embodiment, the material of the buffer layer 110 is silicon oxide.

[0109] The device mask sidewalls 220 are used as a mask for subsequent etching of the substrate. The material of the device mask sidewalls 220 may include one or more of silicon oxide, silicon nitride, silicon, titanium oxide, titanium nitride, and tungsten carbide. In this embodiment, the material of the device mask sidewalls 220 is silicon nitride.

[0110] The remaining pseudo mask sidewall 230 is located on the substrate of the pseudo graphic area II. The remaining pseudo mask sidewall 230 is formed by etching a pseudo mask sidewall of a partial thickness, and the pseudo mask sidewall and the device mask sidewall 220 are formed in the same step. Therefore, the remaining pseudo mask sidewall 230 and the device mask sidewall 220 are made of the same material.

[0111] The ratio of the height difference between the device mask sidewall 220 and the remaining dummy mask sidewall 230 to the height of the device mask sidewall 220 should not be too small or too large. If the ratio is too small, that is, the height of the remaining dummy mask sidewall 230 is relatively large, and the time required for subsequent etching of the remaining dummy mask sidewall 230 is relatively long. In the process of etching the remaining dummy mask sidewall 230, not only vertical etching is performed, but also a certain amount of lateral etching is generated. Therefore, the probability of the device mask sidewall 220 being mistakenly etched is still relatively high. If the ratio is too small, that is, in the process of etching the dummy mask sidewall to form the remaining dummy mask sidewall 230, the vertical etching amount of the dummy mask sidewall is relatively large. In the process of etching the dummy mask sidewall, not only vertical etching is performed, but also a certain amount of lateral etching is generated, which also increases the probability of the device mask sidewall 220 being mistakenly etched. Therefore, in this embodiment, the height difference between the device mask spacer 220 and the remaining dummy mask spacer 230 accounts for 1 / 3 to 1 / 2 of the height of the device mask spacer 220. The longitudinal direction refers to the direction perpendicular to the substrate surface, and the transverse direction refers to the direction parallel to the substrate surface and perpendicular to the sidewalls of the device mask spacer 220.

[0112] The filling layer 300 is used to protect the device mask sidewalls 220 and the substrate during the formation of the trench 330 and the subsequent etching of the remaining dummy mask sidewalls 230. The filling layer 300 is made of an organic material. Specifically, the filling layer 300 includes a spin-on carbon layer material, a bottom anti-reflective coating material, a dielectric anti-reflective coating material, a deep ultraviolet light absorbing oxide layer material, or an advanced patterned film material.

[0113] In this embodiment, the filling layer 300 is made of an advanced patterned film material. Advanced patterned film materials have excellent physical properties, resulting in low line edge roughness on the sidewalls of the trench 330 , which in turn improves the morphology quality of the sidewalls of the trench 330 and also helps improve the line width uniformity of the trench 330 .

[0114] In this embodiment, the semiconductor structure also includes: a blocking layer 310, located on the filling layer 300, an opening 320 is formed in the blocking layer 310, the bottom of the opening 320 is connected to the top of the groove 330, and the blocking layer 310 is used as a mask for forming the groove 330.

[0115] In this embodiment, the width of the opening 320 is greater than the width of the remaining dummy mask sidewalls 230 in a direction parallel to the substrate surface and perpendicular to the sidewalls of the remaining dummy mask sidewalls 230, thereby increasing the process window for forming the opening 320 and facilitating positioning the opening 320 above the remaining dummy mask sidewalls 230. The width difference between the opening 320 and the remaining dummy mask sidewalls 230 should not be too small or too large. If the width difference is too small, the relative positions of the opening 320 and the dummy mask sidewalls 230 may be offset during etching of the dummy mask sidewalls to form the remaining dummy mask sidewalls 230, thereby affecting the morphology and dimensional accuracy of the remaining dummy mask sidewalls 230. If the width difference is too large, the device mask sidewalls 220 may be exposed during formation of the trenches 330, resulting in incorrect etching of the device mask sidewalls 220. Therefore, in this embodiment, the width difference between the opening 320 and the remaining dummy mask sidewall spacer 230 is 3 nm to 4 nm.

[0116] The material of the shielding layer 310 includes one or more of silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the material of the shielding layer 310 is silicon oxide. Silicon nitride has a higher etching selectivity than silicon oxide. Moreover, silicon oxide is easy to remove.

[0117] In the subsequent process of etching and removing the remaining pseudo-mask sidewalls 230, the sidewall protection layer 350 is used to protect the sidewalls of the trench 330, which can reduce the lateral etching of the sidewalls of the trench 330 by the process of etching the remaining pseudo-mask sidewalls 230, thereby reducing the probability of the device mask sidewalls 220 adjacent to the remaining pseudo-mask sidewalls 230 being mistakenly etched, and accordingly makes the device mask sidewalls 220 have lower line width roughness, thereby improving the line width uniformity of the device mask sidewalls 220. Since the device mask sidewalls 220 are used as a mask for etching the substrate, this improves the accuracy of graphic transfer, thereby improving the performance of the semiconductor structure.

[0118] Therefore, when the remaining pseudo-mask sidewall 230 is subsequently etched, there is a high etching selectivity between the remaining pseudo-mask sidewall 230 and the sidewall protection layer 350, so that the sidewall protection layer 350 can protect the sidewall of the trench 330. Specifically, the etching selectivity between the remaining pseudo-mask sidewall 230 and the sidewall protection layer 350 is greater than 5:1. The material of the sidewall protection layer 350 includes one or more of silicon nitride, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride and boron carbonitride. As an example, the material of the sidewall protection layer 350 is silicon oxide. The material of the remaining pseudo-mask sidewall 230 is silicon nitride, and the etching selectivity between silicon nitride and silicon oxide is relatively high. Moreover, the silicon oxide material is easy to be removed.

[0119] In addition, in this embodiment, the sidewall protection layer 350 and the shielding layer 310 are made of the same material, which facilitates the subsequent removal of the sidewall protection layer 350 and the shielding layer 310 in the same step.

[0120] In this embodiment, the sidewall protection layer 350 is also located on the sidewalls of the opening 320. Therefore, during the formation of the sidewall protection layer 350, the shielding layer 310 protects the top of the filling layer 300, thereby reducing the probability of damage to the top of the filling layer 300, and further reducing the probability of the device mask sidewall 220 being exposed.

[0121] It should be noted that the thickness of the sidewall protection layer 350 should not be too small or too large. If the thickness of the sidewall protection layer 350 is too small, then during the subsequent etching process to remove the remaining pseudo-mask sidewall 230, the sidewall protection layer 350 has a low ability to protect the sidewalls of the trench 330, and the probability of the device mask sidewall 220 being mistakenly etched is correspondingly high; if the thickness of the sidewall protection layer 350 is too large, then the sidewall protection layer 350 is likely to block the remaining pseudo-mask sidewall 230, thereby affecting the subsequent etching of the remaining pseudo-mask sidewall 230. For this reason, in this embodiment, the thickness of the sidewall protection layer 350 is to For example, the thickness of the sidewall protection layer 350 is or

[0122] It should also be noted that the semiconductor structure further includes an etch-stop layer 130 positioned between the remaining dummy mask sidewalls 230 and the substrate, between the device mask sidewalls 220 and the substrate, and between the filler layer 300 and the substrate. The process for forming the device mask sidewalls 220 and the dummy mask sidewalls includes an etching process. During the etching process, the etch-stop layer 130 defines the etching stop position to prevent etching damage to the hard mask material layer 120. This reduces the probability of height inconsistencies on the top surface of the hard mask material layer 120, thereby improving the accuracy of subsequent pattern transfer.

[0123] The material of the etch stop layer 130 includes one or more of silicon nitride, titanium nitride, tungsten carbide, silicon oxide, silicon oxycarbide, and silicon oxycarbonitride. In this embodiment, the material of the etch stop layer 130 is silicon oxide.

[0124] The semiconductor structure can be formed by the formation method described in the above embodiment, or by other formation methods. For the detailed description of the semiconductor structure of this embodiment, reference can be made to the corresponding description in the above embodiment, and this embodiment will not be repeated here.

[0125] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, comprising adjacent device regions and dummy pattern regions, wherein a device mask sidewall is formed on the substrate of the device region, and a dummy mask sidewall is formed on the substrate of the dummy pattern region; forming a filling layer on the substrate, wherein the filling layer covers the device mask sidewalls and the dummy mask sidewalls; In the dummy pattern area, etching the filling layer and a portion of the dummy mask sidewall to form a remaining dummy mask sidewall, wherein the remaining dummy mask sidewall and the filling layer form a trench; forming a sidewall protection layer on the sidewall of the trench; After forming the sidewall protection layer, etching to remove the remaining pseudo mask sidewalls; removing the sidewall protective layer; After removing the sidewall protection layer, removing the filling layer; After removing the filling layer, the substrate is etched using the device mask sidewalls as a mask.

2. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming a sidewall protection layer on the sidewall of the trench comprises: forming a sidewall protection material layer conformally covering the bottom and sidewall of the trench and the top of the filling layer; The sidewall protection material layer located at the bottom of the trench and the top of the filling layer is removed, and the remaining sidewall protection material layer located at the sidewall of the trench is retained as a sidewall protection layer.

3. The method for forming a semiconductor structure according to claim 2, wherein: The protective material layer is formed by adopting an atomic layer deposition process or a high aspect ratio chemical vapor deposition process.

4. The method for forming a semiconductor structure according to claim 1, wherein: After etching away the remaining pseudo mask sidewalls and before removing the sidewall protection layer, the forming method further comprises: forming a sacrificial layer on the substrate where the filling layer is exposed, wherein the sacrificial layer exposes the sidewall protection layer; After removing the sidewall protection layer and before etching the substrate using the device mask sidewall as a mask, the forming method further includes: removing the sacrificial layer.

5. The method for forming a semiconductor structure according to claim 4, wherein: The step of forming the sacrificial layer includes: forming a sacrificial material layer covering the filling layer and the substrate; The sacrificial material layer is etched back to expose the remaining sacrificial material layer from the sidewall protection layer, and the remaining sacrificial material layer serves as a sacrificial layer.

6. The method for forming a semiconductor structure according to claim 1, wherein: The base comprises an initial substrate and a hard mask material layer located on the initial substrate, wherein the initial substrate is used to form a fin; The step of etching the substrate using the device mask sidewall as a mask comprises: etching the hard mask material layer using the device mask sidewall as a mask to form a hard mask layer; The forming method further includes: etching the initial substrate using the hard mask layer as a mask to form a substrate and a fin protruding from the substrate.

7. The method for forming a semiconductor structure according to claim 1, wherein: The steps of forming the device mask sidewalls and the dummy mask sidewalls include: forming a core layer on the substrate; forming mask sidewalls on the sidewalls of the core layer, wherein the mask sidewalls located in the device area serve as device mask sidewalls, and the mask sidewalls located in the dummy pattern area serve as dummy mask sidewalls; The core layer is removed.

8. The method for forming a semiconductor structure according to claim 1, wherein: Before etching the filling layer and the dummy mask sidewalls of a portion of their height, the forming method further comprises: forming a shielding layer on the filling layer, wherein an opening is formed in the shielding layer to expose the filling layer of the dummy pattern area; In the step of etching the filling layer and a portion of the height of the dummy mask sidewall, etching is performed along the opening using the blocking layer as a mask; After etching away the remaining dummy mask sidewalls and before removing the filling layer, the forming method further includes: removing the blocking layer.

9. The method for forming a semiconductor structure according to claim 8, wherein: The shielding layer and the sidewall protection layer are made of the same material; In the same step, the shielding layer and the sidewall protection layer are removed.

10. The method for forming a semiconductor structure according to claim 4, wherein: The thickness of the sacrificial layer is to 11. The method for forming a semiconductor structure according to claim 4, wherein: The material of the sacrificial layer includes a spin-on carbon layer material, a bottom anti-reflective coating material, a dielectric anti-reflective coating material, a deep ultraviolet light absorbing oxide layer material or an advanced patterned film material.

12. The method for forming a semiconductor structure according to claim 1, wherein: Using an anisotropic etching process to etch the filling layer and a portion of the height of the pseudo mask sidewall; An anisotropic etching process is adopted to etch away the remaining pseudo mask sidewalls.

13. A semiconductor structure, characterized in that include: a substrate, including an adjacent device region and a dummy pattern region; A device mask sidewall is located on the substrate in the device area, and the device mask sidewall is used as a mask for etching the substrate; The remaining dummy mask sidewalls to be etched and removed are located on the substrate of the dummy pattern area, and the tops of the remaining dummy mask sidewalls are lower than the tops of the device mask sidewalls; a filling layer located on the substrate, the filling layer covering the device mask sidewalls and exposing the tops of the remaining dummy mask sidewalls, the filling layer and the remaining dummy mask sidewalls forming a trench; The sidewall protection layer is located on the sidewall of the trench.

14. The semiconductor structure according to claim 13, wherein: The semiconductor structure further includes: a blocking layer located on the filling layer, an opening formed in the blocking layer, a bottom of the opening communicating with a top of the trench, and the blocking layer serving as a mask for forming the trench; The sidewall protection layer is also located on the sidewalls of the opening.

15. The semiconductor structure according to claim 14, wherein: Along a direction parallel to the substrate surface and perpendicular to the sidewalls of the remaining dummy mask sidewalls, the width of the opening is greater than the width of the remaining dummy mask sidewalls, and the width difference between the opening and the remaining dummy mask sidewalls is 3 nanometers to 4 nanometers.

16. The semiconductor structure according to claim 13, wherein: The thickness of the sidewall protection layer is to 17. The semiconductor structure according to claim 13, wherein: The height difference between the device mask sidewall and the remaining dummy mask sidewall is 1 / 3 to 1 / 2 of the height of the device mask sidewall.

18. The semiconductor structure according to claim 13, wherein: The material of the filling layer includes a spin-on carbon layer material, a bottom anti-reflection coating material, a dielectric anti-reflection coating material, a deep ultraviolet light absorbing oxide layer material or an advanced patterned film material.

19. The semiconductor structure according to claim 13, wherein: The material of the sidewall protection layer includes one or more of silicon nitride, silicon carbonitride, silicon carbonitride oxide, silicon oxynitride, boron nitride and boron carbonitride.

20. The semiconductor structure according to claim 13, wherein The base includes an initial substrate and a hard mask material layer located on the initial substrate.

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