Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a substrate; forming a gate electrode layer on the substrate; performing a defluorination treatment on the gate electrode layer; and forming a barrier layer on a part of a surface of the gate electrode layer after the defluorination treatment, the barrier layer including titanium in a material thereof. Thus, the performance of the semiconductor structure is improved by the defluorination treatment.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and particularly relates to a forming method of semiconductor structure. BACKGROUND

[0002] With the development of integrated circuit manufacturing to ultra large scale integrated circuit, the density of internal circuit is larger and larger, the number of components is increasing, and the size of device is shrinking.

[0003] The manufacturing process of semiconductor integrated circuit is extremely complex, and various electronic components required by specific circuit need to be manufactured on a small area of silicon wafer, and appropriate internal connecting wires need to be manufactured between components to form electrical connection, so as to play the expected function. Transistors, as the most basic semiconductor devices, are widely used, and the transistors include: a substrate; a gate structure on the substrate; source / drain doped regions on both sides of the gate structure. In order to realize the electrical connection between the transistor and other semiconductor devices on the substrate, a large number of conductive structures need to be manufactured, for example, conductive plugs or electrical interconnection lines on the top surface of the gate structure, and the performance of these conductive structures has an important influence on the overall performance of the circuit.

[0004] However, the performance of the semiconductor structure formed by the prior art needs to be improved. SUMMARY

[0005] The technical problem solved by the present application is to provide a forming method of semiconductor structure to improve the performance of semiconductor structure.

[0006] To solve the above technical problem, the technical scheme of the present application provides a forming method of semiconductor structure, comprising: providing a substrate; forming a gate electrode layer on the substrate; performing fluorine removal treatment on the gate electrode layer; after the fluorine removal treatment, forming a barrier layer on part of the surface of the gate electrode layer, and the material of the barrier layer includes titanium element.

[0007] Optionally, the process of the fluorine removal treatment includes an annealing process, the gas used in the annealing process includes at least one of hydrogen and nitrogen, and the temperature of the annealing process is 150 DEG C to 1100 DEG C.

[0008] Optionally, the temperature range of the annealing process is 450 DEG C to 800 DEG C.

[0009] Optionally, the process parameters of the annealing process further include: the time range is 2 hours to 8 hours. Optionally, the process of the fluorine removal treatment includes a plasma treatment process, and the ions used in the plasma treatment process include at least one of hydrogen ions and boron ions.

[0010] Optionally, the parameters of the plasma treatment process further include a temperature range of 35 degrees Celsius to 65 degrees Celsius.

[0011] Optionally, the material of the barrier layer includes at least one of titanium and titanium nitride.

[0012] Optionally, the process parameters of the fluorine removal treatment include a pressure range of 1 mTorr to 100 mTorr.

[0013] Optionally, the material of the gate electrode layer includes tungsten, the process of forming the material of the gate electrode layer includes a chemical vapor deposition process, and the gas source used in the chemical vapor deposition process includes tungsten fluoride.

[0014] Optionally, the method further includes, after forming the gate electrode layer and before the fluorine removal treatment, forming an interlayer dielectric layer on the surface of the gate electrode layer, the interlayer dielectric layer having a conductive opening therein, the conductive opening exposing the top surface of the gate electrode layer.

[0015] Optionally, the method further includes, after the fluorine removal treatment, forming an interlayer dielectric layer on the surface of the gate electrode layer, the interlayer dielectric layer having a conductive opening therein, the conductive opening exposing the top surface of the gate electrode layer.

[0016] Optionally, the method of forming the barrier layer includes, after the fluorine removal treatment, forming a barrier material film in the conductive opening and on the surface of the interlayer dielectric layer; planarizing the barrier material film until the interlayer dielectric layer is exposed, thereby forming the barrier layer in the conductive opening.

[0017] Optionally, the method further includes, during the formation of the barrier layer, forming a conductive structure on the surface of the barrier layer, the conductive structure filling the conductive opening.

[0018] Optionally, the substrate includes a base and a plurality of fin structures on the base, the gate electrode layer extending across the fin structures.

[0019] Optionally, the method further includes, after the fluorine removal treatment and before the formation of the conductive structure, forming a contact layer on the surfaces of the fin structures on both sides of the gate electrode layer.

[0020] Optionally, the material of the contact layer includes a metal silicide.

[0021] Compared with the prior art, the technical scheme of the present application has the following beneficial effects:

[0022] The forming method of the semiconductor structure provided in the technical scheme reduces the content of fluorine elements in the material of the gate electrode layer through the defluorination treatment before the forming of the barrier layer, so that the fluorine elements capable of reacting with titanium elements in the barrier layer are reduced, thereby reducing the gaseous titanium fluoride formed between the gate electrode layer and the barrier layer. Since the gaseous titanium fluoride formed between the gate electrode layer and the barrier layer is reduced, the voids between the gate electrode layer and the barrier layer and the voids between the conductive structure formed on the surface of the barrier layer and the gate electrode layer in the subsequent process are reduced, thereby reducing the contact resistance between the conductive structure and the gate electrode layer and improving the performance of the semiconductor structure.

[0023] Further, since the process of the defluorination treatment includes an annealing process, the gas used in the annealing process includes at least one of hydrogen and nitrogen, and the temperature of the annealing process is 150 DEG C to 1100 DEG C, the defluorination treatment is realized. Specifically, through the annealing process at a temperature above 150 DEG C, the hydrogen or nitrogen can react with the fluorine elements on the surface of the gate electrode layer to form hydrogen fluoride gas or nitrogen fluoride gas, so as to reduce the fluorine elements on the surface of the gate electrode layer. Meanwhile, the fluorine in the material of the gate electrode layer is affected by the temperature of the annealing process and diffuses from the place with a high concentration to the surface of the gate electrode layer with a low concentration, and continues to react with the hydrogen or nitrogen to form hydrogen fluoride gas or nitrogen fluoride gas, so as to continue to reduce the fluorine elements diffused to the surface of the gate electrode layer, thereby reducing the content of the fluorine elements in the gate electrode layer.

[0024] Further, since the process of the defluorination treatment includes a plasma treatment process, the ions used in the plasma treatment process include at least one of hydrogen ions and boron ions, and the defluorination treatment is realized. Specifically, through the plasma process, the hydrogen ions or boron ions capable of reacting with the fluorine elements are bombarded into the gate electrode layer, so that the hydrogen ions or boron ions form hydrogen fluoride gas or boron fluoride gas with the fluorine elements in the gate electrode layer, thereby reducing the content of the fluorine elements in the gate electrode layer. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figures 1 to 3 is a structural schematic diagram of each step in the forming process of a semiconductor structure;

[0026] Figures 4 to 8 is a structural schematic diagram of each step in the forming method of the semiconductor structure in an embodiment of the present application. DETAILED DESCRIPTION

[0027] As described in the background, the performance of the existing semiconductor structure still needs to be improved.

[0028] The reasons for poor performance of the semiconductor structure are described in detail below with reference to the accompanying drawings, Figures 1 to 3 is a schematic diagram of the structure of each step of a method for forming a semiconductor structure.

[0029] Please refer to Figure 1 , a substrate (not shown) is provided; a gate structure is formed on the substrate, the gate structure comprising a gate electrode layer 100, the material of the gate electrode layer 100 being tungsten.

[0030] Please refer to Figure 2 , an interlayer dielectric layer 110 is formed on the surface of the gate structure; a conductive opening (not shown) is formed in the interlayer dielectric layer 110, the conductive opening exposing part of the top surface of the gate electrode layer 100; a barrier material layer 120 is deposited on the inner wall surface of the conductive opening and the surface of the interlayer dielectric layer 110, the material of the barrier material layer 120 comprising titanium and titanium nitride.

[0031] The barrier material layer 120 is used to provide material for forming a barrier layer 121 (as shown in Figure 3 ) on the inner wall surface of the conductive opening later. Since titanium and titanium nitride have good compactness, the compactness of the barrier layer 121 formed is good, so that after a conductive structure electrically connected to the gate electrode layer 100 is formed in the conductive opening later, the diffusion of elements of the material of the conductive structure can be reduced by the barrier of the barrier layer 121 in some subsequent high-temperature processes, and the influence of the high-temperature processes on the electrical properties of the semiconductor structure is reduced.

[0032] However, in the above embodiment, since the material of the gate electrode layer 100 is formed by using a chemical vapor deposition process, and the gas source used in the chemical vapor deposition process comprises tungsten fluoride, the material of the gate electrode layer 100 will have fluorine elements, and under the influence of the high-temperature environment in some subsequent high-temperature processes, such as high-temperature processing for forming metal silicide, the fluorine elements in the material of the gate electrode layer 100 will diffuse, so that the fluorine elements diffused to the surface of the gate electrode layer 100 will react with the titanium elements in the material of the barrier layer 121 under the high-temperature environment, forming gaseous titanium fluoride, resulting in the formation of a cavity 122 (as shown in Figure 3 region A) between the gate electrode layer 100 and the barrier layer 121, or breaking through the barrier layer 121, causing the contact resistance between the gate electrode layer 100 and the conductive structure to be large, and the performance of the semiconductor structure to be poor.

[0033] To solve the above technical problems, an embodiment of the present application provides a method for forming a semiconductor structure, which performs fluorine removal treatment on the gate electrode layer before forming the barrier layer, thereby improving the performance of the semiconductor structure.

[0034] In order to make the above objectives, characteristics and benefits of the present application more obvious and comprehensible, specific embodiments of the present application are described in detail below with reference to the drawings.

[0035] Figures 4 to 8 is a structural schematic diagram of each step of the method for forming a semiconductor structure in an embodiment of the present application.

[0036] Referring to Figure 4 , a substrate 200 is provided.

[0037] In the present embodiment, the substrate 200 comprises a base (not shown) and a plurality of fin structures (not shown) on the base.

[0038] In other embodiments, the base is a planar base.

[0039] The material of the substrate 200 comprises a semiconductor material.

[0040] In the present embodiment, the material of the substrate 200 is silicon.

[0041] In other embodiments, the material of the substrate comprises silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI) or germanium-on-insulator (GOI), etc. The multi-element semiconductor material composed of group III-V elements comprises InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP, etc.

[0042] Referring to Figure 5 , a gate electrode layer 210 is formed on the substrate 200.

[0043] In the present embodiment, while the gate electrode layer 210 is formed, a gate dielectric layer (not shown) and a work function layer (not shown) are also formed. The work function layer is on the surface of the gate dielectric layer, and the gate electrode layer 210 is on the surface of the work function layer. The gate electrode layer 210, the gate dielectric layer and the work function layer constitute a gate structure (not shown).

[0044] The gate structure spans the fin structures, and the gate electrode layer 210 also spans the fin structures.

[0045] The material of the gate electrode layer 210 comprises a metal material.

[0046] Specifically, in the present embodiment, the material of the gate electrode layer 210 comprises tungsten.

[0047] In the embodiment, the material of the gate dielectric layer includes high dielectric constant material (dielectric constant is greater than 3.9). The high dielectric constant material includes hafnium dioxide, hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, aluminum oxide, etc.

[0048] In the embodiment, the material of the work function layer includes titanium nitride, tantalum nitride or titanium aluminum.

[0049] In the embodiment, the method for forming the gate structure includes: forming a plurality of pseudo gate structures (not shown) across the fin structure 201 and gate sidewalls (not shown) on the sidewalls of the pseudo gate structures on the substrate; after forming the pseudo gate structures, forming a first dielectric material layer (not shown) covering the sidewalls of the pseudo gate structures on the surface of the substrate; planarizing the first dielectric material layer until the top surface of the pseudo gate structure is exposed to form a first dielectric layer 211; after forming the first dielectric layer 211, removing the pseudo gate structure to form a gate opening (not shown) in the first dielectric layer 211; forming a gate structure material layer in the gate opening and on the surface of the first dielectric layer 211; planarizing the gate structure material layer until the surface of the first dielectric layer 211 is exposed to form the gate structure in the gate opening.

[0050] In the embodiment, the gate structure material layer includes: a gate dielectric material layer (not shown) on the surface of the first dielectric layer 211 and the inner wall of the gate opening; a work function material layer (not shown) on the surface of the gate dielectric material layer; and a gate electrode material layer (not shown) on the surface of the work function material layer, which fills the gate opening.

[0051] The gate dielectric material layer provides material for forming the gate dielectric layer, the work function material layer provides material for forming the work function layer, and the gate electrode material layer provides material for forming the gate electrode layer 210.

[0052] In the embodiment, the process for forming the gate electrode material layer includes chemical vapor deposition process, and the gas source used in the chemical vapor deposition process includes tungsten fluoride. Therefore, the gate electrode layer 210 including tungsten can be formed. At the same time, since the gas source used includes tungsten fluoride, the material of the gate electrode layer 210 includes fluorine element.

[0053] In the embodiment, the process for forming the gate dielectric material layer includes oxidation process or deposition process, such as chemical vapor deposition process, physical vapor deposition process or atomic layer deposition process, etc.

[0054] In the embodiment, the process of forming the work function material layer includes a deposition process, such as a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, or the like.

[0055] In the embodiment, the process of planarizing the gate structure material layer includes a back-etching process or a chemical mechanical polishing process, or the like.

[0056] In the embodiment, the material of the first dielectric layer 211 includes silicon oxide.

[0057] In the embodiment, the material of the gate sidewall includes a low-k dielectric material (k less than 3.9).

[0058] In the embodiment, the method of forming the dummy gate structure includes: forming a dummy gate material film (not shown) covering the surface of the fin structure on the substrate; patterning the dummy gate material film until the substrate surface is exposed, thereby forming a dummy gate structure across the fin structure on the substrate, the top surface of the dummy gate structure being higher than the top surface of the fin structure.

[0059] In the embodiment, the method of forming the semiconductor structure further includes: before forming the dummy gate structure, forming a base dielectric layer (not shown) on the surface of the substrate 200, the base dielectric layer also being located on part of the sidewall of the fin structure; after forming the dummy gate structure and the gate sidewall, and before forming the first dielectric layer 211, forming a source / drain doped layer (not shown) in the fin structure on both sides of the dummy gate structure.

[0060] In the embodiment, the method of forming the source / drain doped layer includes: forming a source / drain opening (not shown) in the fin structure on both sides of the dummy gate structure; and forming a source / drain doped layer in the source / drain opening by an epitaxial process.

[0061] Please refer to Figure 6 After forming the gate electrode layer 210, and before subsequent fluorine removal, an interlayer dielectric layer 220 is formed on the surface of the gate electrode layer 210, the interlayer dielectric layer 220 having a conductive opening 221 therein, the conductive opening 221 exposing the top surface of the gate electrode layer 210.

[0062] The conductive opening 221 provides space for subsequent formation of a barrier layer and a conductive structure.

[0063] In the embodiment, the method for forming the interlayer dielectric layer 220 includes: forming an interlayer dielectric material layer (not shown) on the surface of the first dielectric layer 211 and the surface of the gate electrode layer 210; forming a conductive opening mask layer on the surface of the interlayer dielectric material layer, the conductive opening mask layer exposing the surface of the interlayer dielectric material layer on the gate electrode layer 210; etching the interlayer dielectric material layer with the conductive opening mask layer as a mask until the top surface of the gate electrode layer 210 is exposed, thereby forming the interlayer dielectric layer 220.

[0064] In the embodiment, the process for forming the interlayer dielectric material layer includes a spin coating process or a deposition process, such as a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, etc.

[0065] In the embodiment, the process for etching the interlayer dielectric material layer includes a dry etching process or a wet etching process.

[0066] In the embodiment, the material of the interlayer dielectric material layer 220 includes silicon oxide.

[0067] In other embodiments, the material of the interlayer dielectric material layer 220 further includes silicon nitride.

[0068] In the embodiment, the conductive opening mask layer is removed after the interlayer dielectric layer 220 is formed.

[0069] Please refer to Figure 7 The gate electrode layer 210 is subjected to a defluorination treatment.

[0070] In the embodiment, the process for the defluorination treatment includes an annealing process.

[0071] The annealing process uses a gas including at least one of hydrogen and nitrogen, and the temperature of the annealing process is 150-1100 °C.

[0072] Since the process of the fluorine removal treatment includes an annealing process, the annealing process uses a gas including at least one of hydrogen and nitrogen, and the annealing process has a temperature in a range of 150°C to 1100°C, the fluorine removal treatment is achieved. Specifically, by the annealing process at a temperature above 150°C, the hydrogen or the nitrogen can react with the fluorine element on the surface of the gate electrode layer 210 to form hydrogen fluoride gas or nitrogen fluoride gas, so as to reduce the fluorine element on the surface of the gate electrode layer 210, and meanwhile, the fluorine in the material of the gate electrode layer 210 is affected by the temperature of the annealing process, diffuses from a place with a higher concentration to the surface of the gate electrode layer 210 with a lower concentration, and continues to react with the hydrogen or the nitrogen to form hydrogen fluoride gas or nitrogen fluoride gas, so as to continue to reduce the fluorine element diffused to the surface of the gate electrode layer 210, thereby reducing the content of the fluorine element in the gate electrode layer 210.

[0073] The temperature of the annealing process is preferably in a range of 450°C to 800°C.

[0074] Specifically, if the temperature of the annealing process is too low, the reaction speed is reduced, and the efficiency of the fluorine removal treatment is poor. If the temperature of the annealing process is too high, the material properties of the gate structure are easily changed by the high temperature, and the electrical properties of the semiconductor device are affected. Therefore, the temperature of the annealing process is selected in a range of 450°C to 800°C, so as to reduce the influence of the annealing process on the electrical properties of the semiconductor device while considering the efficiency of the fluorine removal treatment.

[0075] In the embodiment, the process parameters of the annealing process further include a time range of 2 hours to 8 hours.

[0076] In the embodiment, the process parameters of the fluorine removal treatment further include a pressure range of 1 mTorr to 100 mTorr.

[0077] In another embodiment, the process of the fluorine removal treatment includes a plasma treatment process, and the plasma treatment process uses ions including at least one of hydrogen ions and boron ions.

[0078] Specifically, since the process of the fluorine removal treatment includes a plasma treatment process, the plasma treatment process uses ions including at least one of hydrogen ions and boron ions, and the fluorine removal treatment is achieved. Specifically, by the plasma process, the hydrogen ions or the boron ions that can react with the fluorine element are bombarded into the gate electrode layer, so that the hydrogen ions or the boron ions form hydrogen fluoride gas or boron fluoride gas with the fluorine element in the gate electrode layer, thereby reducing the content of the fluorine element in the gate electrode layer.

[0079] In another embodiment, the parameters of the plasma treatment process further include: a temperature range of 35 degrees Celsius to 65 degrees Celsius.

[0080] In yet another embodiment, the defluorination process comprises both the annealing process and the plasma treatment process. It is noted that the order of the annealing process and the plasma treatment process does not affect the defluorination effect.

[0081] In other embodiments, after the defluorination process, an interlayer dielectric layer is formed on the surface of the gate electrode layer, the interlayer dielectric layer has a conductive opening therein, and the conductive opening exposes the top surface of the gate electrode layer.

[0082] Reference is made to Figure 8 After the defluorination process, a barrier layer 230 is formed on part of the surface of the gate electrode layer 210, and the barrier layer 230 comprises titanium element in its material.

[0083] Since the defluorination process is performed on the gate electrode layer 210, and after the defluorination process, the barrier layer 230 is formed on part of the surface of the gate electrode layer 210, before the formation of the barrier layer 230, the content of fluorine element in the material of the gate electrode layer 210 is reduced by the defluorination process, so that the fluorine element that can react with the titanium element in the barrier layer 230 is reduced, thereby reducing the gaseous titanium fluoride formed between the gate electrode layer 210 and the barrier layer 230. Since the gaseous titanium fluoride formed between the gate electrode layer 210 and the barrier layer 230 is reduced, the voids between the gate electrode layer 210 and the barrier layer, and the voids between the conductive structure 240 formed on the surface of the barrier layer and the gate electrode layer 210 in the subsequent process are reduced, thereby reducing the contact resistance between the conductive structure 240 and the gate electrode layer 210 and improving the performance of the semiconductor structure.

[0084] Specifically, the method of forming the barrier layer 230 comprises: after the defluorination process, forming a barrier material film (not shown) in the conductive opening 221 and on the surface of the interlayer dielectric layer 220; and planarizing the barrier material film until the interlayer dielectric layer 220 is exposed, thereby forming the barrier layer 230 in the conductive opening 221.

[0085] In the present embodiment, the process of forming the barrier material film comprises a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0086] In the present embodiment, the process of planarizing the barrier material film comprises a chemical mechanical polishing process or an etch-back process.

[0087] In the embodiment, the method for forming the semiconductor structure further comprises: forming a conductive structure 240 on the surface of the barrier layer 230 in the process of forming the barrier layer 230, and the conductive structure 240 fills the conductive opening 221.

[0088] Specifically, the method for forming the conductive structure 240 comprises: after forming the barrier material film, forming a conductive structure material layer (not shown) on the surface of the barrier material film; before or simultaneously with planarizing the barrier material film, planarizing the conductive structure material layer until the interlayer dielectric layer 220 is exposed, and forming the conductive structure 240 on the surface of the barrier layer 230 in the conductive opening 221.

[0089] In the embodiment, the process of forming the barrier material film comprises one of a metal electroplating process, a metal electroless plating process, or a deposition process such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0090] In the embodiment, the material of the barrier layer 230 comprises at least one of titanium and titanium nitride.

[0091] Since titanium and titanium nitride have good compactness, the compactness of the barrier layer 230 formed is good, so that the diffusion of elements in the material of the conductive structure 240 can be reduced through the barrier of the barrier layer 230 in subsequent high-temperature processes, and the influence of the high-temperature processes on the electrical properties of the semiconductor structure is reduced.

[0092] In the embodiment, the method for forming the semiconductor structure further comprises: after the fluorine removal treatment, forming a contact layer (not shown) on the surface of the fin structure on both sides of the gate electrode layer 210.

[0093] Thus, the contact resistance between the source / drain conductive structure formed subsequently and the source / drain structure can be reduced through the contact layer, so as to improve the performance of the semiconductor structure.

[0094] In the embodiment, the material of the contact layer comprises a metal silicide. The metal silicide comprises titanium silicide or nickel silicide.

[0095] Specifically, the method for forming the contact layer comprises: simultaneously with or after forming the interlayer dielectric layer 220, forming a source / drain conductive opening in the interlayer dielectric layer 220, the source / drain conductive opening exposing the surface of the source / drain structure in the fin structure on both sides of the gate electrode layer 210; after forming the barrier material film and before forming the conductive structure material layer, forming the contact layer on the surface of the source / drain structure at the bottom of the source / drain conductive opening.

[0096] In the present embodiment, the conductive structure material layer is also on the surface of the contact layer within the source-drain conductive opening, and the conductive structure material layer also fills the source-drain conductive opening, so that, while the conductive structure material layer is planarized to form the conductive structure 240, a source-drain conductive structure is formed on the surface of the contact layer within the fin structure on both sides of the gate electrode layer 210, which is used to electrically connect with the source-drain structure.

[0097] Although the present application has been disclosed with reference to the above embodiments, it is not intended to limit the present application to the above embodiments. Any person skilled in the art, without departing from the spirit and scope of the present application, can make various modifications and changes, and the scope of protection of the present application should be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: Provide substrate; A gate electrode layer is formed on the substrate, and the gate electrode layer contains fluorine. The gate electrode layer is subjected to defluorination treatment to reduce the fluorine content within the gate electrode layer; After the defluorination treatment, an interlayer dielectric layer is formed on the surface of the gate electrode layer. The interlayer dielectric layer has conductive openings that expose the top surface of the gate electrode layer. The method of forming a barrier layer includes: after the defluorination treatment, forming a barrier material film inside the conductive opening and on the surface of the interlayer dielectric layer; The barrier material film is planarized until the interlayer dielectric layer is exposed, forming the barrier layer within the conductive opening; the material of the barrier layer includes titanium.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The defluorination process includes an annealing process, wherein the gas used in the annealing process includes at least one of hydrogen and nitrogen, and the temperature of the annealing process is between 150°C and 1100°C.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The annealing process has a temperature range of 450°C to 800°C.

4. The method for forming a semiconductor structure as described in claim 2, characterized in that, The process parameters for the annealing process also include a time range of 2 to 8 hours.

5. The method for forming a semiconductor structure as described in claim 1 or 2, characterized in that, The defluorination process includes a plasma treatment process, wherein the ions used in the plasma treatment process include at least one of hydrogen ions and boron ions.

6. The method for forming a semiconductor structure as described in claim 5, characterized in that, The parameters of the plasma processing technology also include a temperature range of 35 degrees Celsius to 65 degrees Celsius.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The barrier layer is made of at least one of titanium and titanium nitride.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process parameters for the defluorination treatment include a pressure range of 1 mTorr to 100 mTorr.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the gate electrode layer includes tungsten, and the process for forming the material of the gate electrode layer includes chemical vapor deposition, wherein the gas source used in the chemical vapor deposition process includes tungsten fluoride.

10. The method for forming a semiconductor structure as described in claim 1, characterized in that, Also includes: A conductive structure is formed during the formation of the barrier layer, the conductive structure being located on the surface of the barrier layer and filling the conductive opening.

11. The method for forming a semiconductor structure as described in claim 1, characterized in that, The substrate includes a base and a plurality of fin structures located on the base, the gate electrode layer spanning the fin structures.

12. The method for forming a semiconductor structure as described in claim 10, characterized in that, Also includes: After the defluorination process and before the formation of the conductive structure, a contact layer is formed on the fin structure surface on both sides of the gate electrode layer.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The material of the contact layer includes metal silicides.

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