A shielded gate MOSFET device and a manufacturing method thereof

Abstract

The present application discloses a shielded gate MOSFET device and a manufacturing method thereof, belonging to the field of semiconductor devices and manufacturing. The method comprises: after the shielded gate thick dielectric layer is formed, a shielded gate polysilicon generation area is formed by a photoresist of equal height, and after the photoresist is removed, the shielded gate polysilicon is deposited at its position to form a shielded gate polysilicon, and at the same time, the shielded gate thick dielectric layer is deposited close to the groove sidewall to form a gate polysilicon, so that the shielded gate polysilicon and the gate polysilicon are deposited in the next step without increasing the photolithography process, and the number of polysilicon deposition is reduced to solve the cost problem caused by the large number of photolithography times in the related technology; in addition, under the new structure and new process, the overlap capacitance between the two layers of polysilicon, the shielded gate polysilicon and the gate polysilicon, is reduced, thereby reducing the input capacitance.

Description

Technical Field

[0001] The present application relates to the field of semiconductor devices and manufacturing, and in particular to a shielded gate MOSFET device and a manufacturing method thereof. Background Art

[0002] With the growth of demand for electronic consumer products, the demand for MOSFET is increasing, such as in driver components, electronic communication equipment, power devices, etc. MOSFET devices control the drain current through gate voltage, and have the characteristics of low drive power, low drive current, high input impedance, fast switching speed and good thermal stability, and are widely used.

[0003] In the related technologies, the design and manufacturing methods of MOSFET devices have been continuously improved. As the market competition becomes more and more fierce, the requirements for cost control are also getting higher and higher. How to reduce manufacturing costs without reducing device performance is also an important research direction at present.

[0004] One of the main directions for controlling manufacturing costs is related to the number of photolithography times. Polysilicon deposition is achieved using a photolithography plate, and in related technologies, if polysilicon is deposited multiple times, the number of times the photolithography plate is used needs to be increased. Summary of the invention

[0005] The present application provides a shielded gate MOSFET device and a manufacturing method thereof, which can solve the cost problem caused by a large number of photolithography times in the related art.

[0006] On the one hand, an embodiment of the present application provides a method for manufacturing a shielded gate MOSFET device, comprising:

[0007] Providing a substrate with a groove etched therein, and depositing a shielding gate thick dielectric layer on the inner wall and bottom of the groove;

[0008] Filling the groove with photoresist and removing a portion of the thickness of the photoresist from the top, wherein the top of the remaining thickness of the photoresist in the groove is lower than the top of the shielding gate thick dielectric layer;

[0009] Etching the shield gate thick dielectric layer along the sidewall of the trench until the top is flush with the top of the remaining thickness of the photoresist;

[0010] Removing the hard mask layer above the substrate and the remaining thickness of the photoresist in the trench;

[0011] forming a gate dielectric layer above the shielding gate thick dielectric layer and on the inner wall of the trench;

[0012] Forming gate polysilicon and shielding gate polysilicon by depositing polysilicon in one step at the same time, wherein the gate polysilicon is formed above the shielding gate thick dielectric layer, and the shielding gate polysilicon is formed in the trench of the shielding gate thick dielectric layer;

[0013] forming wells on both sides of the gate dielectric layer, and forming a source electrode above the well;

[0014] Depositing a contact hole dielectric layer on the upper surfaces of the source, the well, the gate polysilicon and the shield gate polysilicon;

[0015] Etching the contact hole dielectric layer so that contact holes are formed above the well, the gate polysilicon and the shield gate polysilicon;

[0016] A backside metal is formed on the backside of the substrate, and a frontside metal is filled in the contact hole.

[0017] Optionally, the forming of the gate polysilicon 4 and the shield gate polysilicon 10 by depositing polysilicon in one step simultaneously includes:

[0018] Polysilicon 301 is deposited inside the trench 101 and on the top of the substrate 1, wherein a thin layer of polysilicon is formed on the flat area above the shielding gate thick dielectric layer 2 and on the top of the substrate 1, and a thick layer of polysilicon is formed in the trench of the shielding gate thick dielectric layer 2 and close to the sidewall of the gate dielectric layer 3;

[0019] The polysilicon 301 is etched to leave the gate polysilicon 4 and the shielding gate polysilicon 10, and there is no gate polysilicon (4) above the shielding gate polysilicon (10).

[0020] Optionally, etching the polysilicon 301 includes:

[0021] The thin layer of polysilicon formed on the flat area above the shielding gate thick dielectric layer 2 and on the top of the substrate 1 is etched, leaving the gate polysilicon 4 above the shielding gate thick dielectric layer 2 and the shielding gate polysilicon 10 in the trench of the shielding gate thick dielectric layer 2.

[0022] Optionally, providing a substrate 1 having a groove 101 etched therein comprises:

[0023] Providing the substrate 1, and forming a hard mask layer 102 on the upper surface of the substrate 1;

[0024] The hard mask layer 102 is etched by a photolithography process to determine a gate formation region, and then the substrate 1 is etched using the hard mask layer 102 as a mask to form the trench 101 .

[0025] On the other hand, an embodiment of the present application provides a shielded gate MOSFET device, including:

[0026] A substrate 1 having a groove 101; a shielding gate polysilicon 10 formed in the groove 101; a shielding gate thick dielectric layer 2 is provided on the sidewall and bottom of the shielding gate polysilicon 10, which is close to the inner wall of the groove 101, wherein the top of the shielding gate polysilicon 10 is flush with the top of the shielding gate thick dielectric layer 2; a contact hole dielectric layer 7 covering the top of the shielding gate polysilicon 10 and the top of the shielding gate thick dielectric layer 2, and the shielding gate thick dielectric layer 7 is filled in the groove 101;

[0027] A gate polysilicon 4 is formed above the shielding gate thick dielectric layer 2; a gate dielectric layer 3 is provided on the side walls of the gate polysilicon 4; a well 5 is formed on both sides of the gate dielectric layer 3; a source 6 is provided above the well 5; a back metal 8 is formed on the back side of the substrate 1; and a front metal 9 is filled in the contact hole 701 above the well 5, the gate polysilicon 4 and the shielding gate polysilicon 10.

[0028] Optionally, the gate polysilicon 4 is located above the shielding gate thick dielectric layer 2 , and the shielding gate polysilicon 10 is located in a trench of the shielding gate thick dielectric layer 2 .

[0029] Optionally, the substrate 1 is a silicon substrate, and an epitaxial layer is provided on the silicon substrate.

[0030] The technical solution of this application has at least the following advantages:

[0031] After the shielding gate thick dielectric layer is formed, a shielding gate polysilicon generation area is formed by using a photoresist of equal height. After the photoresist is removed, shielding gate polysilicon is deposited at its position. At the same time, gate polysilicon is deposited above the shielding gate thick dielectric layer close to the trench sidewall, thereby completing the deposition of shielding gate polysilicon and gate polysilicon in one step without increasing the photolithography process, reducing the number of polysilicon depositions to solve the cost problem caused by the large number of photolithography times in related technologies. In addition, under the new structure and new process, the overlap capacitance between the two layers of polysilicon, shielding gate polysilicon and gate polysilicon, is reduced, thereby reducing the input capacitance. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0033] Figure 1 is a flow chart of a method for manufacturing a shielded gate MOSFET device provided by an exemplary embodiment of the present application;

[0034] Figures 2 to 10 It is a schematic diagram of forming a shielded gate MOSFET device provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0035] The following will be combined with the accompanying drawings to clearly and completely describe the 9 technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0036] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0037] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0038] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0039] Please refer to Figure 1 , which shows a schematic flow chart of a method for manufacturing a shielded gate MOSFET device provided by an exemplary embodiment of the present application, the method comprising:

[0040] Step 101, providing a substrate with a groove etched therein, and depositing a shield gate thick dielectric layer on the inner wall and bottom of the groove.

[0041] Optionally, the contents of etching a substrate with grooves in step 101 include but are not limited to the following contents.

[0042] Content 1. Provide a substrate and form a hard mask layer on the upper surface of the substrate.

[0043] Content 2: The hard mask layer 102 is etched by photolithography to determine the gate formation area, and then the substrate 1 is etched using the hard mask layer 102 as a mask to form the trench 101.

[0044] refer to Figure 2 , which shows a cross-sectional schematic diagram of forming a trench on a substrate and depositing a shield gate thick dielectric layer in the trench. Figure 2 As shown, a substrate 1 is provided, and further, the substrate 1 is a silicon substrate and has an epitaxial layer formed thereon; when forming a groove 101, a hard mask layer 102 is first formed on the upper surface of the substrate 1, and then a photolithography process is used to define a gate forming area of ​​the groove 101, and then the hard mask layer 102 and the substrate 1 are sequentially etched to form the groove 101.

[0045] Furthermore, after forming the trench 101, as Figure 3 As shown, it shows a cross-sectional schematic diagram of depositing a thick dielectric layer of a shield gate. Figure 3 In the process, a shielding gate thick dielectric layer 2 is deposited on the inner wall and the bottom of the trench 101. Optionally, the shielding gate thick dielectric layer 2 can also be formed by oxidation.

[0046] Step 102, filling the trench with photoresist and removing a portion of the thickness of the photoresist from the top, wherein the top of the remaining thickness of the photoresist in the trench is lower than the top of the thick dielectric layer of the shielding gate.

[0047] refer to Figure 4 , Figure 4 Schematic diagram of the cross section after the photoresist is filled is shown. Figure 4 As shown, the groove 101 is filled with photoresist 103, and after filling, part of the thickness of the photoresist 103 is removed from the top. Due to insufficient exposure of the area above the shielding gate thick dielectric layer 2 near the groove 101, the photoresist 103 is still left after development, wherein the top of the remaining thickness of the photoresist 103 is lower than the top of the shielding gate thick dielectric layer 2, that is, the photoresist 103 is left above the bottom of the groove 101.

[0048] Step 103, etching the shield gate thick dielectric layer along the trench sidewalls until the top is flush with the top of the remaining thickness of the photoresist.

[0049] refer to Figure 5 , Figure 5 FIG. 4 shows a schematic cross-sectional view of the shield gate after etching of the thick dielectric layer. Figure 5 As shown, the top of the remaining portion of the shield gate thick dielectric layer 2 after being etched is flush with the top of the remaining portion of the photoresist 103 .

[0050] Step 104 , removing the hard mask layer above the substrate and the remaining thickness of the photoresist in the trench.

[0051] Please refer to Figure 6 , Figure 6 Schematic diagram of the cross section after the hard mask layer and the photoresist are removed. Figure 6 As shown, the hard mask layer 102 located above the substrate 1 is removed, and the photoresist 103 in the trench 101 is removed without any remaining part, and only the shielding gate thick dielectric layer 2 is left at the bottom of the trench 101 .

[0052] Step 105 , forming a gate dielectric layer above the shielding gate thick dielectric layer and on the inner wall of the trench.

[0053] Please refer to Figure 7 , Figure 7 Schematic diagram of the cross section of the gate dielectric layer is shown. Figure 7 As shown, the shielding gate thick dielectric layer 2 is located at the bottom of the trench 101 , and gate dielectric layers 3 are formed on the upper surfaces of both sides of the shielding gate thick dielectric layer 2 . The gate dielectric layers 3 are closely attached to the inner wall of the trench 101 .

[0054] Step 106, forming gate polysilicon and shielding gate polysilicon simultaneously by one-step deposition of polysilicon, wherein the gate polysilicon is formed above the shielding gate thick dielectric layer, and the shielding gate polysilicon is formed in the trench of the shielding gate thick dielectric layer.

[0055] Optionally, the content provided in step 106 includes but is not limited to the following.

[0056] Content 1: Polysilicon is deposited inside the trench and on the top of the substrate, wherein a thin layer of polysilicon is formed on the flat area above the shielding gate thick dielectric layer and on the top of the substrate, and a thick layer of polysilicon is formed in the trench of the shielding gate thick dielectric layer and close to the side wall of the gate dielectric layer.

[0057] Content 2: Etch the polysilicon to leave gate polysilicon and shielding gate polysilicon, with no gate polysilicon on the shielding gate polysilicon.

[0058] In one possible implementation, the thin layer of polysilicon formed on the flat area above the shielding gate thick dielectric layer and on the top of the substrate is removed, leaving the gate polysilicon above the shielding gate thick dielectric layer and the shielding gate polysilicon in the trench of the shielding gate thick dielectric layer, wherein there is no gate polysilicon above the shielding gate polysilicon.

[0059] Please continue to refer to Figure 7 , for example, Figure 7 As shown, polysilicon 301 is deposited along the inside of the trench 101 and the top of the substrate 1. At this time, a thin layer of polysilicon is left on the flat surface, including the flat surface above the shielding gate thick dielectric layer 2 and the flat surface on the top of the substrate 1; in addition, a thick layer of polysilicon is left in the trench of the shielding gate thick dielectric layer 2 and close to the side wall of the gate dielectric layer 3.

[0060] Further, such as Figure 8 As shown, Figure 8 The schematic cross-sectional view of the gate polysilicon and the shielding gate polysilicon is shown. In order to form the gate polysilicon 4 and the shielding gate polysilicon 10, the thin layer of polysilicon formed on the flat part above the shielding gate thick dielectric layer 2 and on the top of the substrate 1 is removed, so that the gate polysilicon 4 above the shielding gate thick dielectric layer 2 and the shielding gate polysilicon 10 in the trench of the shielding gate thick dielectric layer 2 are left.

[0061] Indicative, such as Fig. 9 As shown in FIG. 1 , it shows the etching process diagram of polysilicon. Fig. 9 The first figure from the left shows a schematic diagram of the substrate 1, the second figure from the left shows a schematic diagram of the polysilicon 301 after formation, and the third figure from the left shows a schematic diagram of the gate polysilicon with sidewalls left after the polysilicon 301 is etched.

[0062] Step 107 , forming wells on both sides of the gate dielectric layer, and forming a source electrode above the well.

[0063] Step 108 , depositing a contact hole dielectric layer on the upper surfaces of the source, the well, the gate polysilicon and the shield gate polysilicon.

[0064] Step 109, etching the contact hole dielectric layer to form contact holes above the well, gate polysilicon and shield gate polysilicon.

[0065] Step 110, forming a back metal on the back side of the substrate and filling the contact hole with a front metal.

[0066] Please refer to Fig.10 , Fig.10 FIG. 1 shows a cross-sectional schematic diagram corresponding to the processing from step 107 to step 110. Fig.10 As shown, after the gate polysilicon and the shielding gate polysilicon are formed, a well 5 and a source 6 are implanted on both sides of the gate dielectric layer 3, wherein the source 6 is located above the well 5; further, the contact hole dielectric layer 7 is etched to form a contact hole 701, as shown in FIG. Fig.10 As shown, the contact hole 701 is formed above the well 5 , the gate polysilicon 4 and the shield gate polysilicon 10 .

[0067] Furthermore, a metal layer is deposited on the substrate 1, wherein a back metal 8 is formed on the back side of the substrate 1, and a front metal 9 is filled in each contact hole 701, thereby performing metallization processing on the front and back sides of the substrate.

[0068] In summary, the present invention provides a device manufacturing method for a shielded gate MOSFET, comprising: after a shielding gate thick dielectric layer is formed, a shielding gate polysilicon generation area is formed by a photoresist of equal height, and after the photoresist is removed, shielding gate polysilicon is deposited at its position, and at the same time, gate polysilicon is deposited above the shielding gate thick dielectric layer close to the groove side wall to form gate polysilicon, so that the shielding gate polysilicon and gate polysilicon are deposited in a next step without increasing the photolithography process, reducing the number of polysilicon deposition times to solve the cost problem caused by the large number of photolithography times in related technologies; in addition, under the new structure and new process, the overlap capacitance between the two layers of polysilicon, the shielding gate polysilicon and the gate polysilicon, is reduced, thereby reducing the input capacitance.

[0069] Please refer to Fig.10 , which shows a cross-sectional schematic diagram of a shielded gate MOSFET device provided by an exemplary embodiment of the present application, the device is manufactured by any of the above method embodiments, and the device includes:

[0070] A substrate 1 is provided with a groove 101; a shielding gate polysilicon 10 is formed in the groove 101; a shielding gate thick dielectric layer 2 is provided on the sidewalls and bottom of the shielding gate polysilicon 10, which is close to the inner wall of the groove 101, wherein the top of the shielding gate polysilicon 10 is flush with the top of the shielding gate thick dielectric layer 2; a contact hole dielectric layer 7 covering the top of the shielding gate polysilicon 10 and the top of the shielding gate thick dielectric layer 2, and the shielding gate thick dielectric layer 7 is filled in the groove 101.

[0071] Optionally, the substrate 1 is a silicon substrate, and an epitaxial layer is provided on the silicon substrate.

[0072] A gate polysilicon 4 is formed above the shielding gate thick dielectric layer 2; a gate dielectric layer 3 is provided on the side walls of the gate polysilicon 4; a well 5 is formed on both sides of the gate dielectric layer 3; a source 6 is provided above the well 5; a back metal 8 is formed on the back side of the substrate 1; and a front metal 9 is filled in the contact hole 701 above the well 5, the gate polysilicon 4 and the shielding gate polysilicon 10.

[0073] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.

Claims

1. A method for manufacturing a shielded gate MOSFET device, characterized in that: include: Providing a substrate with a groove etched therein, and depositing a shielding gate thick dielectric layer on the inner wall and bottom of the groove; Filling the groove with photoresist and removing a portion of the thickness of the photoresist from the top, wherein the top of the remaining thickness of the photoresist in the groove is lower than the top of the shielding gate thick dielectric layer; Etching the shield gate thick dielectric layer along the sidewall of the trench until the top is flush with the top of the remaining thickness of the photoresist; Removing the hard mask layer above the substrate and the remaining thickness of the photoresist in the trench; forming a gate dielectric layer above the shielding gate thick dielectric layer and on the inner wall of the trench; Forming gate polysilicon and shielding gate polysilicon by depositing polysilicon in one step at the same time, wherein the gate polysilicon is formed above the shielding gate thick dielectric layer, and the shielding gate polysilicon is formed in the trench of the shielding gate thick dielectric layer; forming wells on both sides of the gate dielectric layer, and forming a source electrode above the well; Depositing a contact hole dielectric layer on the upper surfaces of the source, the well, the gate polysilicon and the shield gate polysilicon; Etching the contact hole dielectric layer so that contact holes are formed above the well, the gate polysilicon and the shield gate polysilicon; A backside metal is formed on the backside of the substrate, and a frontside metal is filled in the contact hole.

2. The method according to claim 1, characterized in that The method of forming gate polysilicon and shielding gate polysilicon by depositing polysilicon in one step comprises: Depositing polysilicon inside the trench and on the top of the substrate, wherein a thin layer of polysilicon is formed on the flat area above the shielding gate thick dielectric layer and on the top of the substrate, and a thick layer of polysilicon is formed in the trench of the shielding gate thick dielectric layer and close to the sidewall of the gate dielectric layer; The polysilicon is etched to leave the gate polysilicon and the shielding gate polysilicon, and there is no gate polysilicon above the shielding gate polysilicon.

3. The method according to claim 2, characterized in that The etching of the polysilicon comprises: The thin layer of polysilicon formed on the flat area above the shielding gate thick dielectric layer and on the top of the substrate is etched to leave the gate polysilicon above the shielding gate thick dielectric layer and the shielding gate polysilicon in the trench of the shielding gate thick dielectric layer.

4. The method according to claim 1, characterized in that The method of providing a substrate having grooves etched therein comprises: Providing the substrate, and forming a hard mask layer on the upper surface of the substrate; The hard mask layer is etched by a photolithography process to determine a gate formation region, and then the substrate is etched using the hard mask layer as a mask to form the groove.

5. A shielded gate MOSFET device, characterized in that: include: A substrate (1) provided with a groove (101); a shielding gate polysilicon (10) formed in the groove (101); a shielding gate thick dielectric layer (2) closely attached to the inner wall of the groove (101) is provided on the sidewall and bottom of the shielding gate polysilicon (10), wherein the top of the shielding gate polysilicon (10) is flush with the top of the shielding gate thick dielectric layer (2); a contact hole dielectric layer (7) covering the top of the shielding gate polysilicon (10) and the top of the shielding gate thick dielectric layer (2), wherein the shielding gate thick dielectric layer (2) is filled in the groove (101); A gate polysilicon (4) is formed, wherein a gate dielectric layer (3) is provided on the side wall of the gate polysilicon (4); a well (5) is formed on both sides of the gate dielectric layer (3); a source (6) is provided above the well (5); a back metal (8) is formed on the back side of the substrate (1); and a front metal (9) is filled in a contact hole (701) above the well (5), the gate polysilicon (4) and the shielding gate polysilicon (10).

6. The device according to claim 5, characterized in that The gate polysilicon (4) is located above the shielding gate thick dielectric layer (2), and the shielding gate polysilicon (10) is located in a trench of the shielding gate thick dielectric layer (2).

7. The device according to claim 5, characterized in that The substrate (1) is a silicon substrate, and an epitaxial layer is provided on the silicon substrate.

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