Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure comprises: providing a current wafer, the current wafer comprising a plurality of chip regions, and the current wafer sequentially comprising a to-be-etched layer and a core mold structure, the core mold structure comprising a sacrificial layer and a cover layer, and the cover layer of each chip region having a thickness difference; forming a side wall on a sidewall of the core mold structure; etching part of the cover layer and part of the sacrificial layer until a surface of the to-be-etched layer is exposed, thereby forming a first opening in the remaining core mold structure; obtaining an etching rate of the sacrificial layer of each chip region of the current wafer and feeding back to a control system, the etching rate of the sacrificial layer of each chip region having a difference; and the control system adjusting a thickness of the cover layer formed on a next wafer according to the etching rate of the sacrificial layer, and the thickness of the cover layer formed on the next wafer being sequentially increased as the etching rate of the sacrificial layer increases. The method for forming a semiconductor structure provided by the embodiment of the present application is beneficial to improving the pattern size uniformity and improving the performance of the semiconductor structure.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and particularly relates to a forming method of semiconductor structure. BACKGROUND

[0002] The semiconductor manufacturing technology needs to carry out a plurality of different physical and chemical processes on a semiconductor wafer, and a photolithography process is one of the most important processes in the semiconductor manufacturing technology. The photolithography process is a main process for removing a specific part of a wafer surface film through a series of production steps, and a film with a pattern structure can be formed on the wafer surface through photolithography and etching.

[0003] With the rapid growth of semiconductor technology, the semiconductor technology continues to move towards a smaller process node under the driving of Moore's law, so that the semiconductor develops in the direction of smaller volume, higher circuit precision and higher circuit complexity. With the continuous reduction of the size of semiconductor devices, the photolithography critical dimension gradually approaches or even exceeds the physical limit of photolithography, thereby posing more severe challenges to the photolithography technology.

[0004] At present, under the condition of continuously reducing the technology node, there is a problem of non-uniformity of the critical dimension of the pattern formed by photolithography, which leads to poor performance of the formed semiconductor structure. SUMMARY

[0005] The technical problem solved by the present application is to provide a forming method of semiconductor structure, which is beneficial to improve the pattern uniformity problem and improve the performance of the semiconductor structure.

[0006] To solve the above technical problem, the present application provides a forming method of semiconductor structure, comprising: providing a current wafer, the current wafer comprising a plurality of chip areas, and a to-be-etched layer formed on the current wafer; forming a plurality of mutually discrete core module structures on the to-be-etched layer of each chip area, the core module structure comprising a sacrificial layer on the to-be-etched layer and a cover layer on the surface of the sacrificial layer, the thickness of the cover layer of each chip area being different; forming a side wall on the sidewall of the core module structure; etching part of the cover layer and part of the sacrificial layer until the surface of the to-be-etched layer is exposed, forming a first opening in the remaining core module structure; obtaining the etching rate of the sacrificial layer of each chip area of the current wafer and feeding back to a control system, the etching rate of the sacrificial layer of each chip area being different; the control system adjusts the thickness of the cover layer formed on the next wafer according to the etching rate of the sacrificial layer, and the thickness of the cover layer formed on the next wafer increases in turn with the increase of the etching rate of the sacrificial layer.

[0007] Optionally, a relationship between the thickness of the cover layer formed on the next wafer and the etching rate of the sacrificial layer is d=λv, where d is the thickness of the cover layer formed on the next wafer, v is the etching rate of the sacrificial layer of the current wafer, and λ is a relationship coefficient of the thickness of the cover layer and the etching rate of the sacrificial layer.

[0008] Optionally, the method for obtaining the etching rate of the sacrificial layer of each chip area comprises: selecting m test points on each chip area, where m is a natural number greater than or equal to 1; obtaining the etching rate v1-vm of the sacrificial layer corresponding to each test point; and obtaining the etching rate of the sacrificial layer of each chip area by averaging the etching rates of the sacrificial layer corresponding to the m test points. m

[0009] Optionally, the method for obtaining the etching rate of the sacrificial layer corresponding to the test point comprises: obtaining the thickness TK1 of the sacrificial layer before etching; obtaining the thickness TK2 of the sacrificial layer after etching; obtaining the etching time t; and obtaining the etching rate of the sacrificial layer as (TK1-TK2) / t.

[0010] Optionally, the material of the cover layer comprises silicon oxide or silicon nitride.

[0011] Optionally, the process for forming the cover layer comprises a chemical vapor deposition process.

[0012] Optionally, a temperature control method is used to adjust the thickness of the cover layer formed on the next wafer.

[0013] Optionally, the temperature control method comprises: providing a temperature control substrate; placing the next wafer on the temperature control substrate; and controlling the temperature of each chip area on the next wafer through the temperature control substrate, and the temperature of each chip area decreases in turn as the etching rate of the sacrificial layer increases.

[0014] Optionally, the control system is an APC advanced control system.

[0015] Optionally, the method for forming the cover layer with different thicknesses on the current wafer comprises: obtaining the etching rate of the sacrificial layer of each chip area of the previous wafer and feeding back to a control system; the control system adjusts the thickness of the cover layer formed on the current wafer according to the etching rate of the sacrificial layer of each chip area of the previous wafer, and the thickness of the cover layer formed on the current wafer increases in turn as the etching rate of the sacrificial layer of each chip area of the previous wafer increases.

[0016] Optionally, the process for etching the cover layer and the sacrificial layer is a wet etching process.

[0017] ​Optionally, the step of forming the plurality of mutually separated core structures comprises: forming a sacrificial material layer and a cover material layer on the layer to be etched; forming a patterned layer on the cover material layer, the patterned layer having a patterned opening therein, the patterned opening exposing a top surface of the cover material layer; implanting dopant ions into the cover material layer and the sacrificial material layer; removing the cover material layer and the sacrificial material layer implanted with the dopant ions until the surface of the layer to be etched is exposed, forming the plurality of mutually separated core structures; and removing the patterned layer.

[0018] Optionally, the dopant ions comprise carbon ions, boron ions, arsenic ions, gallium ions or indium ions.

[0019] Optionally, the process of removing the cover material layer and the sacrificial material layer implanted with the dopant ions is a dry etching process.

[0020] Optionally, the step of forming the sidewall on the sidewall of the core structure comprises: forming a sidewall material layer on the surface of the layer to be etched and the sidewall and the top surface of the core structure; and removing the sidewall material layer on the surface of the layer to be etched and the top surface of the core structure, forming the sidewall on the sidewall of the core structure.

[0021] Optionally, the material of the sacrificial layer comprises amorphous silicon, amorphous carbon or polycrystalline silicon.

[0022] Optionally, the layer to be etched comprises a single material layer or a plurality of stacked material layers.

[0023] Optionally, the material of the sidewall comprises titanium oxide, titanium nitride, silicon nitride, silicon oxide or silicon oxynitride.

[0024] Optionally, the process of forming the sidewall comprises a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process.

[0025] Compared with the prior art, the technical scheme of the embodiment of the present application has the following beneficial effects:

[0026] The control system adjusts the thickness of the cover layer formed on each chip area of the next wafer by acquiring the etching rate of the sacrifice layer of each chip area of the current wafer, and the thickness of the cover layer formed in the chip area with a large etching rate is thick, and the thickness of the cover layer formed in the chip area with a small etching rate is small. When etching the sacrifice layer, the cover layer on the top surface of the sacrifice layer needs to be etched first. The thickness of the cover layer is thick, so the time required for etching the cover layer increases, resulting in a decrease in the time for etching the sacrifice layer. Therefore, the amount of sacrifice layer etched in the chip area with a large etching rate is consistent with the amount of sacrifice layer etched in the chip area with a small etching rate, limiting the lateral etching of the sacrifice layer in the chip area with a large etching rate, improving the uniformity of the size of the first opening formed, and further improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figures 1 to 5 is a structural schematic diagram of a semiconductor structure forming method in an embodiment;

[0028] Figure 6 is a flowchart of a semiconductor structure forming method in an embodiment of the present application;

[0029] Figures 7 to 12 is a structural schematic diagram corresponding to each step of a semiconductor structure forming method in an embodiment of the present application. DETAILED DESCRIPTION

[0030] As known from the background art, the size uniformity of the pattern structure formed by the current photolithography etching process is poor. Now the reasons for poor pattern uniformity will be analyzed in combination with specific drawings.

[0031] Reference Figure 1 , a wafer 100 is provided, which includes a plurality of chip areas.

[0032] In specific embodiments, the wafer 100 located in the chip area can form various semiconductor components, such as various appropriate transistors, memories, field effect tubes, etc.

[0033] For the convenience of subsequent description, two chip areas are taken as examples to illustrate the semiconductor forming process in this embodiment, including a first chip area A1 and a second chip area A2.

[0034] Reference Figure 2 , a wafer 100 is provided, which includes a plurality of chip areas.

[0035] Reference Figure 3, removing the first patterning layer 103; removing the ion-implanted sacrificial material layer 102 to form a plurality of mutually separated sacrificial layers 120, and a first opening 104 between adjacent sacrificial layers 120, the first opening 104 exposing the surface of the layer to be etched 101.

[0036] Referring to Figure 4 A sidewall material layer 105 is formed on the sidewalls and bottom surface of the first opening 104 and the top surface of the sacrificial layers 120.

[0037] Referring to Figure 5 The sidewall material layer 105 on the bottom surface of the first opening 104 and the top surface of the sacrificial layers 120 is removed; and part of the sacrificial layers 120 is etched until the surface of the layer to be etched 101 is exposed, forming a second opening 106 in the remaining sacrificial layers 120.

[0038] The inventor has found that in the formation of the semiconductor structure described above, the sacrificial layers 120 are usually etched using a wet etching process. However, since the wet etching process is isotropic, it will often be accompanied by lateral etching after reaching a certain depth. The etching rate of each chip area on the wafer 100 is not completely the same, and in the case of differences in etching rate, the amount of lateral etching of the sacrificial layers 120 will differ, directly leading to non-uniform sizes of the second openings 106 formed in each chip area on the wafer 100, and further affecting the performance of the semiconductor structure.

[0039] For example, when the etching rate of the first chip area Al is greater than that of the second chip area A2, then under the same etching time, the lateral etching of the first chip area Al is more obvious, leading to a larger lateral size dl of the second opening 106 formed in the first chip area Al than the lateral size d2 of the second opening 106 formed in the second chip area A2.

[0040] To solve the above problems, the embodiment of the present application provides a semiconductor structure forming method, a covering layer is formed on a sacrifice layer, and the thickness of the covering layer is dynamically adjusted in the etching process of different batches of wafers, the thickness of the covering layer formed on the next wafer is adjusted by acquiring the etching rate of the sacrifice layer of each chip area on the current wafer, and the thickness of the covering layer increases with the increase of the etching rate, the thickness of the covering layer formed in the chip area with a large etching rate is greater than the thickness of the covering layer formed in the chip area with a small etching rate, when etching the sacrifice layer, the covering layer on the top surface of the sacrifice layer needs to be etched first, because the thickness of the covering layer formed in the chip area with a large etching rate is relatively thick, the time required for removing the covering layer increases, the etching of the sacrifice layer is reduced, so that the amount of the sacrifice layer etched in the chip area with a large etching rate is consistent with the amount of the sacrifice layer etched in the chip area with a small etching rate, the lateral etching of the sacrifice layer in the chip area with a large etching rate is limited, the uniformity of the size of the first opening formed is improved, and the performance of the semiconductor structure is improved.

[0041] In order to make the above objects, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings.

[0042] Figure 6 is a flow chart of a semiconductor structure forming method in an embodiment of the present application, and the semiconductor structure forming method can include steps S1 to S6:

[0043] Step S1: providing a current wafer, the current wafer includes a plurality of chip areas, and a to-be-etched layer is formed on the current wafer;

[0044] Step S2: forming a plurality of mutually discrete core module structures on the to-be-etched layer of each chip area, the core module structure includes a sacrifice layer on the to-be-etched layer and a covering layer on the surface of the sacrifice layer, and the thickness of the covering layer of each chip area is different;

[0045] Step S3: forming a side wall on the side wall of the core module structure;

[0046] Step S4: etching part of the covering layer and part of the sacrifice layer until the surface of the to-be-etched layer is exposed, and forming a first opening in the remaining core module structure;

[0047] Step S5: acquiring the etching rate of the sacrifice layer of each chip area of the current wafer and feeding back to a control system, and the etching rate of the sacrifice layer of each chip area is different;

[0048] Step S6: The control system adjusts the thickness of the capping layer formed on the next wafer according to the etching rate of the sacrificial layer. As the etching rate of the sacrificial layer increases, the thickness of the capping layer formed on the next wafer increases sequentially.

[0049] In this embodiment, the method for forming a capping layer with different thicknesses on the current wafer includes: obtaining the etching rate of the sacrificial layer of each chip region of the previous wafer and feeding it back to the control system; the control system adjusts the thickness of the capping layer formed on the current wafer according to the etching rate of the sacrificial layer of each chip region of the previous wafer, and as the etching rate of the sacrificial layer of each chip region of the previous wafer increases, the thickness of the capping layer formed on the current wafer increases sequentially.

[0050] The following is combined Figures 7 to 12 The steps described above will be explained.

[0051] Figures 7 to 12 This is a schematic diagram of the structure corresponding to each step of the semiconductor structure formation method in one embodiment of the present invention.

[0052] refer to Figure 7 Provide a current wafer 200, the current wafer 200 including a plurality of chip regions, and an etchable layer 201 is formed on the current wafer 200.

[0053] The wafer 200 is made of materials including silicon, germanium, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). In this embodiment, the wafer 200 is made of silicon.

[0054] In a specific embodiment, the wafer 200 also includes dicing channels (not shown), which are located between the chip regions; the wafer 200 located in the chip regions can form various semiconductor devices, such as various suitable transistors, memories, field-effect transistors, etc.; the wafer located in the dicing channels often does not have semiconductor devices.

[0055] In this embodiment, the wafer 200 is described as having three chip regions, namely the first chip region A1, the second chip region A2, and the third chip region A3.

[0056] In this embodiment, the etching rates of each chip region are different.

[0057] In this embodiment, the etchable layer 201 covers the first chip region A1, the second chip region A2, and the third chip region A3.

[0058] The layer to be etched 201 can be a single-layer material layer or a multi-layer stacked material layer, specifically including dielectric materials, metallic materials or hard mask materials, etc.

[0059] In this embodiment, the layer to be etched 201 is a multi-layered stacked material layer, including: a first material layer (not shown in the figure) located on the surface of the wafer 200, and a second material layer (not shown in the figure) located on the surface of the first material layer.

[0060] The material of the first material layer includes: the k-th dielectric material (k is less than or equal to 3.9).

[0061] The second material layer is a hard mask layer, which includes one or more stacked layers of SiC, SiN, BD, tetraethyl orthosilicate (TEOS), and TiN.

[0062] The second material layer serves two purposes: firstly, it acts as an etching stop layer; secondly, since the material of the second material layer is a hard mask layer material, the etching loss on the second material layer is relatively small in subsequent etching processes, resulting in higher stability of pattern transfer during pattern transfer.

[0063] After the etchable layer 201 is formed, a plurality of mutually independent core mold structures are formed on the etchable layer 201 of each chip region. The core mold structure includes a sacrificial layer located on the etchable layer 201 and a cover layer located on the top surface of the sacrificial layer. The thickness of the cover layer of each chip region is different.

[0064] In this embodiment, the steps for forming the core mold structure specifically include:

[0065] refer to Figure 8 A sacrificial material layer 202 is formed on the layer to be etched 201.

[0066] In this embodiment, the sacrificial material layer 202 is used to subsequently form discrete sacrificial layers.

[0067] Subsequent processes include patterning the sacrificial material layer 202, thus achieving a high etching selectivity between the sacrificial material layer 202 and the layer to be etched 201, thereby enabling selective etching in subsequent processes. In this embodiment, the sacrificial material layer 202 and the layer to be etched 201 are made of different materials.

[0068] The material of the sacrificial material layer 202 includes amorphous silicon, amorphous carbon, or polycrystalline silicon. In this embodiment, the material of the sacrificial material layer 202 is amorphous silicon.

[0069] The process for forming the sacrificial material layer 202 includes chemical vapor deposition (CVD) or atomic layer deposition (ALD). In this embodiment, the process for forming the sacrificial material layer 202 is CVD.

[0070] Continue to refer to Figure 8 A covering material layer 203 is formed on the sacrificial material layer 202.

[0071] In this embodiment, the covering material layer 203 is used to subsequently form mutually independent covering layers 203.

[0072] The material of the cover material layer 203 includes silicon oxide or silicon nitride. In this embodiment, the material of the cover material layer 203 includes silicon oxide.

[0073] The process for forming the cover material layer 203 includes chemical vapor deposition (CVD) or atomic layer deposition (ALD). In this embodiment, the process for forming the cover material layer 203 is CVD.

[0074] In this embodiment, the thickness of the covering material layer 203 formed on each chip region on the current wafer 200 is different.

[0075] In this embodiment, the thickness of the cover material layer 203 formed on the current wafer 200 needs to be determined according to the etching rate of the sacrificial layer of each chip area of ​​the previous wafer. The specific method is the same as the method of adjusting the thickness of the cover material layer 203 formed on the next wafer according to the etching rate of the sacrificial layer of the current wafer 200.

[0076] In this embodiment, the distribution of etching rates on different wafers is fixed, and the distribution of etching rate magnitude on the previous wafer corresponds to the distribution of etching rate magnitude on the current wafer.

[0077] It should be noted that before etching the wafer, a simulated etching process is required using a photofilm. The etching rate distribution map of each region on the photofilm is obtained through the control system. The etching rate distribution on the photofilm corresponds to the etching rate distribution of the wafer to be etched.

[0078] In this embodiment, the etching rate of the first chip region A1 is greater than the etching rate of the second chip region A2 and the etching rate of the third chip region A3. Therefore, the thickness of the cover material layer 203 formed in the first chip region A1 is greater than the thickness of the cover material layer 203 formed in the second chip region A2 and the thickness of the cover material layer 203 formed in the third chip region A3.

[0079] Continue to refer to Figure 8 A patterned layer 204 is formed on the cover material layer 203, the patterned layer 204 having a patterned opening 240 that exposes a portion of the top surface of the cover material layer 203.

[0080] In this embodiment, the patterning layer 204 is a patterned photoresist layer.

[0081] In this embodiment, the patterned opening 240 exposes a portion of the surface of the cover material layer 203 of each chip region.

[0082] Continue to refer to Figure 8 Using the patterned layer 204 as a mask, doped ions are implanted into a portion of the cover material layer 203 and the sacrificial material layer 202.

[0083] In this embodiment, doped ions are specifically injected into the cover material layer 203 exposed by the patterned opening 240 and the sacrificial material layer 202 below it.

[0084] In this embodiment, implanting dopant ions into a portion of the cover material layer 203 and the sacrificial material layer 202 is suitable for increasing the removal selectivity ratio between the unimplanted cover material layer 203 and the unimplanted sacrificial material layer 202 and the dopant-implanted cover material layer 203 and the unimplanted sacrificial material layer 202. This helps to increase the process window of the removal process when removing the dopant-implanted cover material layer 203 and the unimplanted sacrificial material layer 202 in the subsequent process, thereby ensuring the pattern accuracy of the subsequently formed core mold structure.

[0085] The dopant ions include carbon ions, boron ions, arsenic ions, gallium ions, or indium ions. In this embodiment, the dopant ion is a boron ion.

[0086] In this embodiment, the process parameters for implanting dopant ions include: implantation energy of 5–11 keV and implantation dose of 1E15–2E15 atoms / cm. 2 .

[0087] refer to Figure 9 Remove the patterning layer 204; remove the cover material layer 203 and the sacrificial material layer 202 implanted with doped ions until the surface of the layer to be etched 201 is exposed, forming several discrete core mold structures on each chip region, the core mold structure including a discretely arranged sacrificial layer 220 and a cover layer 230 located on the top surface of the sacrificial layer.

[0088] In this embodiment, the process for removing the implanted doped ions from the cover material layer 203 and the sacrificial material layer 202 is a dry etching process.

[0089] In this embodiment, a first dry etching process is used to remove the cover material layer 203 with implanted doped ions until the surface of the sacrificial material layer 202 is exposed; then a second dry etching process is used to remove the sacrificial material layer 202 with implanted doped ions.

[0090] The parameters of the first dry etching process include: an etching atmosphere comprising a mixture of CF4, CHF3 and He, a power of 1000–1500 W, a pressure of 5–15 mTorr, a temperature of 30–50 °C, and a time of 5–10 s; the parameters of the second dry etching process include: an etching atmosphere comprising a mixture of Cl2, HBr, CF4 and O2, an etching power of 500–1000 W, a pressure of 5–8 mTorr, a temperature of 30–50 °C, and a time of 20–40 s.

[0091] In this embodiment, after the core mold structure is formed, the patterned layer 204 is removed by an ashing process.

[0092] refer to Figure 10 A sidewall material layer 205 is formed on the surface of the layer to be etched 201 and on the sidewalls and top surface of the core mold structure.

[0093] The process for forming the sidewall material layer 205 includes chemical vapor deposition, physical vapor deposition, or atomic layer deposition. In this embodiment, atomic layer deposition is used to form the sidewall material layer 205.

[0094] The sidewall material layer 205 formed by the atomic layer deposition process has good thickness uniformity, which makes the thickness of the sidewall material layer 205 located on the surface of the layer to be etched 201 and the top surface and sidewall surface of the core mold structure more consistent. This is beneficial to expose the surface of the layer to be etched 201 and the top surface of the core mold structure when etching the sidewall material layer 205 in the future.

[0095] The sidewall material layer 205 is made of titanium oxide, titanium nitride, silicon nitride, silicon oxide, or silicon oxynitride. In this embodiment, the sidewall material layer 205 is made of titanium oxide.

[0096] refer to Figure 11 Remove the sidewall material layer 205 from the surface of the layer to be etched 201 and the top surface of the core mold structure, and form a sidewall 250 on the sidewall of the core mold structure.

[0097] The process for removing the sidewall material layer 205 from the surface of the layer to be etched 201 and the top surface of the core mold structure includes one or a combination of dry etching and wet etching processes.

[0098] The etching process has a high etching selectivity for the layer to be etched 201, the capping layer 230, and the sidewall material layer 205. That is, the etching rate of the layer to be etched 201 and the capping layer 230 is much lower than the etching rate of the sidewall material layer 205. This results in less etching damage to the layer to be etched 201 and the capping layer 230 when part of the sidewall material layer 205 is etched away. Consequently, the sacrificial layer 220 covered by the capping layer 230 suffers less etching damage, which is beneficial to improving the stability of pattern transfer and thus improving the performance of the formed semiconductor structure.

[0099] refer to Figure 12 The cover layer 230 and the sacrificial layer 220 are etched until the surface of the layer to be etched 201 is exposed, forming a first opening 206 in the remaining core structure.

[0100] In this embodiment, the etching process for part of the cover layer 230 and part of the sacrificial layer 220 is a wet etching process.

[0101] In this embodiment, a portion of the cover layer 230 is first etched using a first wet etching process until the surface of the sacrificial layer 220 is exposed; then, the exposed sacrificial layer 220 is etched using a second wet etching process.

[0102] In this embodiment, the process parameters of the first wet etching process include: the etching solution includes a diluted hydrofluoric acid solution, wherein the volume ratio of hydrofluoric acid to water in the diluted hydrofluoric acid solution is less than or equal to 1:500; the process parameters of the second wet etching process include: the etching solution includes ammonia.

[0103] In this embodiment, the first wet etching process has a high etching selectivity for the capping layer 250 and the sidewall 250, that is, the etching rate of the first wet etching process for the sidewall 250 is much lower than the etching rate for the capping layer 230. Therefore, the sidewall 250 is less damaged by etching, which ensures the integrity of the sidewall 250 pattern and helps to improve the stability of pattern transfer.

[0104] In this embodiment, the second wet etching process has a high etching selectivity for the sacrificial layer 220, the sidewall 250, and the layer 201 to be etched. That is, the etching rate of the second wet etching process for the sidewall 250 and the layer 201 to be etched is much lower than the etching rate for the sacrificial layer 220. Therefore, the sidewall 250 and the layer 201 to be etched suffer less etching damage.

[0105] In this embodiment, since the etching rates of each chip region are different, the sacrificial layer 220 located in the chip region with a fast etching rate is etched more in the same time period, while the sacrificial layer 220 located in the chip region with a slow etching rate is etched less. Therefore, the difference in etching rate is compensated by forming capping layers 230 of different thicknesses. The thickness of the capping layer 230 formed on the chip region with a fast etching rate is greater than the thickness of the capping layer 230 formed on the chip region with a slow etching rate. Under the same total etching time, the etching time of the capping layer 230 in the chip region with a fast etching rate is longer, and the etching time of the sacrificial layer 220 is shortened, thereby achieving a balance with the etching of the sacrificial layer 220 in the chip region with a slow etching rate.

[0106] In this embodiment, a wafer-to-wafer feedback method is used to reduce the negative impact of poor pattern uniformity caused by differences in etching rates among different chip regions. Specifically, data such as the etching rate of the sacrificial layer 220 of each chip region of the current wafer 200 is fed back to the control system, and then fed back to the deposition process of the capping layer of the next wafer by the control system. The specific steps include:

[0107] A control system is provided to obtain the etching rate of the sacrificial layer 220 of each chip region of the current wafer 200.

[0108] In this embodiment, the control system is the APC advanced control system.

[0109] In this embodiment, the method for obtaining the etching rate of the sacrificial layer 220 of each chip region includes: selecting m test points on each chip region, where m is a natural number greater than or equal to 1; and obtaining the etching rate v1 to v2 of the sacrificial layer 220 corresponding to each test point. m ; Calculate the average etching rate of the sacrificial layer 220 corresponding to the m test points, and obtain the etching rate of the sacrificial layer 220 in each chip region.

[0110] In this embodiment, m test points are selected in the first chip area A1, the second chip area A2, and the third chip area A3 respectively. The number of test points selected in each chip area can be the same or different. For example, 4 test points can be selected in the first chip area A1, 5 test points can be selected in the second chip area A2, and 3 test points can be selected in the third chip area A3.

[0111] The selection factors for the test points include the density of patterns on each chip area and the critical dimensions of the patterns.

[0112] In this embodiment, the method for obtaining the etching rate of the sacrificial layer 220 corresponding to the test point includes: obtaining the thickness TK1 of the sacrificial layer before etching corresponding to the test point; obtaining the thickness TK2 of the sacrificial layer after etching corresponding to the test point; obtaining the etching time t, and the etching rate of the sacrificial layer is (TK1-TK2) / t.

[0113] In this embodiment, the method for obtaining the etching rate of the sacrificial layer 220 is illustrated using the first chip region A1 as an example. Specifically, it includes: selecting four test points on the first chip region A1; and obtaining the thickness TK of the sacrificial layer 220 corresponding to each test point before etching. 11 ~TK 14 After etching is complete, the thickness TK of the etched sacrificial layer 220 is obtained. 21 ~TK 24 The etching times t1 to t4 were obtained, and the etching rates v1 to v4 corresponding to the four test points were (TK) respectively. 11 -TK 21 ) / t1、(TK 12 -TK 22 ) / t2、(TK 13 -TK 23 ) / t3、(TK 14 -TK 24 ) / t4; calculate the average value of v1 to v4 (v1+v2+v3+v4) / m, and obtain the etching rate of the sacrificial layer 220 of the first chip region A1.

[0114] The method for obtaining the etching rate of the sacrificial layer 220 in other chip areas is the same, and will not be repeated here.

[0115] It should be noted that, in this embodiment, the etching time specifically refers to the time of the second wet etching process.

[0116] After obtaining the etching rate of the sacrificial layer 220 in each chip region and feeding it back to the control system, the control system adjusts the thickness of the capping layer formed on the next wafer according to the etching rate of the sacrificial layer 220. As the etching rate of the sacrificial layer 220 increases, the thickness of the capping layer formed on the next wafer increases sequentially.

[0117] In this embodiment, specifically for the first chip region A1, the second chip region A2, and the third chip region A3, if the obtained etching rate results are that the etching rate of the first chip region A1 > the etching rate of the second chip region A2 > the etching rate of the third chip region A3, then correspondingly, the thickness of the capping layer formed in the first chip region A1 on the next wafer is greater than the thickness of the capping layer formed in the second chip region A2 > the thickness of the capping layer formed in the third chip region A3.

[0118] In this embodiment, by forming capping layers of different thicknesses on chip regions with different etching rates, the capping layer formed on chip regions with high etching rates is thicker, while the capping layer formed on chip regions with low etching rates is thinner. Since the capping layer formed on chip regions with high etching rates is thicker, the time required to etch the capping layer increases. Therefore, under the same total etching time, the time to etch the sacrificial layer is correspondingly reduced, while the etching time of the sacrificial layer in chip regions with low etching rates is relatively long. Thus, the amount of sacrificial layer etched on chip regions with high etching rates and chip regions with low etching rates can be controlled to be basically consistent, thereby making the size of the formed first opening 206 consistent and greatly improving the problem of pattern size uniformity.

[0119] Since the etching rate distribution of the same batch of products on the same production line is fixed, the etching rate distribution of the sacrificial layer 220 obtained on the current wafer 200 can be applied to the next wafer. Similarly, the thickness of the capping layer 230 formed on the current wafer 200 is also derived from the etching rate distribution of the previous wafer. However, the etching rates of different wafers are not completely equal. Therefore, the thickness of the capping layer needs to be dynamically adjusted. The thickness of the capping layer to be formed on the wafer to be etched is continuously re-determined based on the etching rate of the previous wafer, thereby further improving the dimensional uniformity of the pattern.

[0120] In this embodiment, the relationship between the thickness of the capping layer formed on the next wafer and the etching rate of the sacrificial layer on the current wafer is d = λv, where d is the thickness of the capping layer formed on the next wafer, v is the etching rate of the sacrificial layer on the current wafer, and λ is the coefficient relating the thickness of the capping layer to the etching rate of the sacrificial layer.

[0121] It should be noted that after obtaining the etching rate distribution map through optical wafer simulation, several test wafers need to be selected. By etching the test wafers, the optimal CD value of the first opening is obtained. The point corresponding to the optimal CD value is recorded as the optimal test point. Then, the etching time of the sacrificial layer corresponding to the optimal test point is recorded as the first standard time. After obtaining the first standard time, a capping layer of a certain thickness is formed on the optimal test point, which is recorded as the test thickness. The time required to etch the capping layer is recorded as the second standard time. At this time, the sum of the first standard time and the second standard time is the ideal total etching time. Under this etching time and the etching rate of the corresponding optimal test point, the optimal CD value of the first opening can be obtained.

[0122] After the wafer is formally etched, the total etching time for the capping layer and sacrificial layer remains constant. Since the etching rate varies in different regions of the wafer, the thickness of the capping layer formed in each region is adjusted accordingly based on the measured thickness due to the change in etching rate. In regions with low etching rates, the thickness of the capping layer is reduced accordingly, thereby reducing the etching time of the capping layer and increasing the etching time of the sacrificial layer. This is beneficial to maximize the CD value of the first opening to be close to the optimal CD value. Therefore, the thickness d of the capping layer is a function related to the etching rate v. The influencing factors of λ include the thickness of the capping layer formed on the current wafer, the etching time of the capping layer, and the etching time of the sacrificial layer.

[0123] In this embodiment, a temperature control method is used to adjust the thickness of the capping layer formed on the next wafer.

[0124] In this embodiment, the temperature control method specifically includes: providing a temperature control substrate (not shown), placing the next wafer on the temperature control substrate; controlling the temperature of each chip region on the next wafer through the temperature control substrate, wherein the temperature of each chip region decreases sequentially as the etching rate of the sacrificial layer increases.

[0125] In this embodiment, specifically for the first chip region A1, the second chip region A2, and the third chip region A3, if the obtained etching rate results are that the etching rate of the first chip region A1 > the etching rate of the second chip region A2 > the etching rate of the third chip region A3, then correspondingly, the temperature of the first chip region A1 on the next wafer is < the temperature of the second chip region A2 < the temperature of the third chip region A3.

[0126] It should be noted that since the cover layer is obtained through a patterning process of the cover material layer, the thickness of the cover material layer formed on the next wafer is actually controlled by temperature control methods.

[0127] Since the cover material layer is made of a temperature-sensitive material, temperature changes affect the deposition of the cover material layer. Higher temperatures result in a thinner cover material layer, while lower temperatures result in a thicker cover material layer. Therefore, cover material layers of different thicknesses can be formed in the same deposition process.

[0128] In this embodiment, after forming the second opening 206, the method further includes: using the sidewall 250 and the remaining core mold structure as a mask, etching the layer to be etched 201 to form a target pattern layer (not shown).

[0129] In this embodiment, adjusting the thickness of the capping layer according to the etching rate of the sacrificial layer is beneficial to improving the uniformity of the size of the first opening 206. During the etching of the layer to be etched 201 using the sidewall 250 and the remaining core mold structure as masks, the uniformity of the size of the first opening 206 is improved, which in turn improves the uniformity of the size of the target pattern layer, thereby improving the performance of the semiconductor structure.

[0130] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: Provide a current wafer, the current wafer including a plurality of chip regions, and a layer to be etched is formed on the current wafer; A plurality of mutually independent core mold structures are formed on the etchable layer of each of the chip regions. The core mold structure includes a sacrificial layer located on the etchable layer and a cover layer located on the surface of the sacrificial layer. The thickness of the cover layer of each of the chip regions is different. A sidewall is formed on the sidewall of the core mold structure; A wet etching process is used to etch part of the cover layer and part of the sacrificial layer until the surface of the layer to be etched is exposed, forming a first opening in the remaining core structure; The etching rate of the sacrificial layer in each chip region of the current wafer is obtained and fed back to the control system. The etching rate of the sacrificial layer in each chip region is different. The control system adjusts the thickness of the capping layer formed on the next wafer according to the etching rate of the sacrificial layer. The thickness of the capping layer formed on the chip region with a fast etching rate is greater than the thickness of the capping layer formed on the chip region with a slow etching rate. As the etching rate of the sacrificial layer on each chip region increases, the thickness of the capping layer formed on each chip region on the next wafer increases sequentially. The etching time of the sacrificial layer on the chip region with a fast etching rate is less than the etching time of the sacrificial layer on the chip region with a slow etching rate.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The relationship between the thickness of the capping layer formed on the next wafer and the etching rate of the sacrificial layer is d=λv, where d is the thickness of the capping layer formed on the next wafer, v is the etching rate of the sacrificial layer on the current wafer, and λ is the coefficient relating the thickness of the capping layer to the etching rate of the sacrificial layer.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for obtaining the etching rate of the sacrificial layer in each chip region includes: selecting m test points on each chip region, where m is a natural number greater than or equal to 1; and obtaining the etching rate v1~v2 of the sacrificial layer corresponding to each test point. m ; Calculate the average etching rate of the sacrificial layer corresponding to m test points to obtain the etching rate of the sacrificial layer in each chip region.

4. The method for forming a semiconductor structure as described in claim 3, characterized in that, The method for obtaining the etching rate of the sacrificial layer corresponding to the test point includes: obtaining the thickness TK1 of the sacrificial layer before etching; obtaining the thickness TK2 of the sacrificial layer after etching; obtaining the etching time t, and the etching rate of the sacrificial layer is (TK1-TK2) / t.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the covering layer includes silicon oxide or silicon nitride.

6. The method for forming a semiconductor structure as described in claim 5, characterized in that, The process for forming the capping layer includes chemical vapor deposition.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The thickness of the capping layer formed on the next wafer is adjusted using a temperature control method.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, The temperature control method includes: providing a temperature control substrate, placing the next wafer on the temperature control substrate; controlling the temperature of each chip region on the next wafer through the temperature control substrate, wherein the temperature of each chip region decreases sequentially as the etching rate of the sacrificial layer increases.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that, The control system is the APC advanced control system.

10. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming a capping layer with varying thickness on the current wafer includes: obtaining the etching rate of the sacrificial layer of each chip region of the previous wafer and feeding it back to the control system; the control system adjusts the thickness of the capping layer formed on the current wafer according to the etching rate of the sacrificial layer of each chip region of the previous wafer, and as the etching rate of the sacrificial layer of each chip region of the previous wafer increases, the thickness of the capping layer formed on the current wafer increases sequentially.

11. The method for forming a semiconductor structure as described in claim 1, characterized in that, The etching process for the capping layer and the sacrificial layer is a wet etching process.

12. The method for forming a semiconductor structure as described in claim 1, characterized in that, The steps of forming several mutually discrete mandrel structures include: forming a sacrificial material layer and a cover material layer on the layer to be etched; forming a patterned layer on the cover material layer, the patterned layer having a patterned opening that exposes a portion of the top surface of the cover material layer; implanting doped ions into a portion of the cover material layer and the sacrificial material layer using the patterned layer as a mask; removing the doped cover material layer and the sacrificial material layer until the surface of the layer to be etched is exposed, forming several mutually discrete mandrel structures; and removing the patterned layer.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The doped ions include carbon ions, boron ions, arsenic ions, gallium ions, or indium ions.

14. The method for forming a semiconductor structure as described in claim 12, characterized in that, The process for removing the implanted doped ions from the cover material layer and the sacrificial material layer is a dry etching process.

15. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming a sidewall on the sidewall of the mandrel structure includes: forming a sidewall material layer on the surface of the layer to be etched and on the sidewall and top surfaces of the mandrel structure; removing the sidewall material layer on the surface of the layer to be etched and on the top surface of the mandrel structure to form a sidewall on the sidewall of the mandrel structure.

16. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the sacrificial layer includes amorphous silicon, amorphous carbon, or polycrystalline silicon.

17. The method for forming a semiconductor structure as described in claim 1, characterized in that, The layer to be etched includes a single-layer material layer or multiple stacked material layers.

18. The method for forming a semiconductor structure as described in claim 1, characterized in that, The sidewall material includes titanium oxide, titanium nitride, silicon nitride, silicon oxide, or silicon oxynitride.

19. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process for forming the sidewalls includes chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

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