Storage capacitor manufacturing method and storage capacitor thereof

Abstract

The present invention provides a method for manufacturing a storage capacitor and the storage capacitor thereof, comprising: providing a semiconductor substrate; forming a first mask layer; etching the first mask layer to form a first trench; forming a second mask layer to form a second trench, removing the second mask layer above the first mask layer, the first mask layer, and the second mask layer located at the bottom of the second trench; forming a third mask layer, a fourth mask layer, and a fifth mask layer in sequence; grinding and thinning the fourth mask layer and the fifth mask layer until the second mask layer is exposed; forming a third trench and a U-shaped opening located at the boundary; etching the semiconductor substrate to form a fourth trench in the semiconductor substrate; removing the third mask layer, the fourth mask layer, and the fifth mask layer; forming an insulating layer; forming a first dielectric layer located on the insulating layer; and forming a first conductive layer, a second dielectric layer, and a second conductive layer. This method can save the number of photolithography operations and reduce production costs.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a manufacturing method of a storage capacitor and the storage capacitor thereof. Background Art

[0002] A unit cell of a storage capacitor typically consists of a storage capacitor and a MOS transistor. Increasing storage density requires integrating more storage cells per unit area and storing more information per unit cell. As semiconductor technology integration and chip performance requirements increase, chip area continues to shrink. To achieve this, the number of photolithography steps required increases, placing increasingly stringent demands on the photolithography process. This increases process complexity and increases production costs.

[0003] Therefore, it is necessary to provide a novel method for manufacturing a storage capacitor to improve the above-mentioned problems existing in the prior art. Summary of the Invention

[0004] The object of the present invention is to provide a method for manufacturing a storage capacitor and a storage capacitor thereof, so as to reduce the requirements on the photolithography accuracy of a photolithography machine while ensuring the performance of the storage capacitor, thereby reducing the process complexity and production cost.

[0005] To achieve the above object, the present invention provides a method for manufacturing a storage capacitor, comprising:

[0006] Providing a semiconductor substrate; forming a first mask layer on the semiconductor substrate; etching the first mask layer to form a first trench; forming a second mask layer at the bottom and sidewalls of the first trench and above the first mask layer, so as to form a second trench, wherein the trench width and trench depth of the second trench are both smaller than the trench width and trench depth of the first trench; removing the second mask layer above the first mask layer, the first mask layer, and the second mask layer at the bottom of the second trench; sequentially forming a third mask layer on the remaining second mask layer, a fourth mask layer on the third mask layer, and a fifth mask layer on the fourth mask layer; grinding and thinning the fourth mask layer and the fifth mask layer until the second mask layer is exposed; removing the second mask layer The method comprises the steps of: forming a first dielectric layer on the insulating layer; forming a first conductive layer on the first dielectric layer; etching the second dielectric layer on the first conductive layer; and forming a second conductive layer on the second dielectric layer.

[0007] Optionally, forming a dielectric layer and a conductive layer on the fourth trench includes:

[0008] An insulating layer is formed on the sidewalls of the fourth trench, the bottom of the fourth trench, and the semiconductor substrate; a first dielectric layer is formed on the insulating layer; a first conductive layer is formed on the first dielectric layer; a second dielectric layer is formed on the first conductive layer; and a second conductive layer is formed on the second dielectric layer.

[0009] Optionally, the method further includes: forming a third dielectric layer on the second conductive layer and performing a planarization process; and etching the third dielectric layer to form a through hole to expose the first conductive layer and the second conductive layer.

[0010] Optionally, the method further includes: filling a third conductive layer in the through hole, and etching the third conductive layer to complete metal interconnection.

[0011] Optionally, materials of the first mask layer, the second mask layer, the third mask layer, the fourth mask layer and the fifth mask layer are all silicon nitride.

[0012] Optionally, the material of the insulating layer is at least one material having a dielectric constant greater than 3.9.

[0013] Optionally, the material of the insulating layer includes at least one of zirconium dioxide, aluminum oxide, silicon nitride, hafnium dioxide, yttrium trioxide, silicon dioxide, tantalum pentoxide, lanthanum oxide, and titanium dioxide.

[0014] Optionally, the conductive layer is made of copper, aluminum or tungsten.

[0015] The beneficial effect of the manufacturing method of the storage capacitor provided by the present invention is that: the above-mentioned manufacturing method can complete etching with high lithography precision under the production conditions of using ordinary photoresist, and the width of the groove finally manufactured is narrow, which helps to increase the surface area of the capacitor and improve the capacity of the storage capacitor. While ensuring the performance of the storage capacitor, the requirements for the lithography precision of the lithography machine are reduced, thereby reducing the process complexity and production cost.

[0016] In a second aspect, an embodiment of the present invention further provides a storage capacitor, comprising: a semiconductor substrate;

[0017] An insulating layer, a first dielectric layer, a first conductive layer, a second dielectric layer, and a second conductive layer on the second dielectric layer are sequentially located on the semiconductor substrate, wherein the first conductive layer and the second conductive layer at a boundary form a U-shaped folded region; a third dielectric layer and a third conductive layer on the third dielectric layer are located on the second conductive layer, wherein the third conductive layer is electrically connected to the first conductive layer and the second conductive layer via a through hole.

[0018] The storage capacitor provided by the present invention has the beneficial effects of large capacity and low manufacturing cost. While ensuring the performance of the storage capacitor, the requirements for the photolithography accuracy of the photolithography machine are reduced, thereby reducing process complexity and production cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A flow chart of a method for manufacturing a storage capacitor provided by the present invention;

[0020] Figure 2 Schematic diagrams of intermediate structures of some embodiments of the present invention;

[0021] Figure 3 Schematic diagrams of intermediate structures of some other embodiments of the present invention;

[0022] Figures 4A to 4G Schematic diagrams of intermediate structures in some other embodiments of the present invention;

[0023] Figure 4H A schematic diagram of a storage capacitor structure provided by the present invention. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be the common meanings understood by people with ordinary skills in the field to which the present invention belongs. The words "including" and similar words used in this article mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0025] Figure 1 A schematic flow chart of a method for manufacturing a storage capacitor is shown. Figure 2 Schematic diagrams of the intermediate structure cross-sections of each process preparation stage in this example are shown respectively.

[0026] See also Figure 1 The manufacturing method of the storage capacitor provided by the embodiment of the present invention includes the following steps:

[0027] S101 , providing a semiconductor substrate 100 .

[0028] For example, Figure 2 As shown in (a) of FIG. 1 , the semiconductor substrate 100 may be an N-type or P-type silicon substrate. The material of the semiconductor substrate 100 includes one or more combinations of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, and indium gallium. The semiconductor substrate 100 may also be a silicon-on-insulator semiconductor substrate or a germanium-on-insulator semiconductor substrate.

[0029] S102 , forming a first mask layer 201 on the semiconductor substrate 100 .

[0030] For example, Figure 2 As shown in (a), the first mask layer 201 can be any one or more of silicon nitride, silicon carbide, silicon oxynitride or silicon carbonitride.

[0031] S103 , etching the first mask layer 201 to form a first trench 01 .

[0032] For example, Figure 2 As shown in (b), by coating a photoresist on the first mask layer 201 and then performing pattern etching, a first trench 01 as shown in the figure can be formed. The photoresist used in this step can be a relatively low-cost photoresist.

[0033] S104, forming a second mask layer 202 located at the bottom and sidewalls of the first trench 01 and above the first mask layer 201, so as to form a second trench 02, wherein the width and depth of the second trench 02 are both smaller than the width and depth of the first trench 01.

[0034] For example, Figure 2 As shown in (c), the photoresist coated on the first mask layer 201 is removed, and then a layer of polysilicon is deposited to form the second trench 02 as shown in the figure. The polysilicon can be any one or more of silicon nitride, silicon carbide, silicon oxynitride, or silicon carbonitride. The photoresist used in this step can still be a relatively inexpensive photoresist.

[0035] S105 , removing the second mask layer 202 above the first mask layer, the first mask layer 201 , and the second mask layer 202 located at the bottom of the second trench 02 .

[0036] For example, after one etching, the second mask layer 202 above the first mask layer 201 and the second mask layer 202 at the bottom of the second trench 02 are removed. Then, the remaining structures of the first mask layer 201 and the second mask layer 202 are as follows: Figure 2 As shown in (d) in FIG. Afterwards, the remaining first mask layer 201 is removed by further etching, and the structure of the remaining second mask layer 202 is as shown in FIG. Figure 2 As shown in (e) in .

[0037] S106 , sequentially forming a third mask layer 203 on the remaining second mask layer 202 , a fourth mask layer 204 on the third mask layer 203 , and a fifth mask layer 205 on the fourth mask layer 204 .

[0038] For example, Figure 3 As shown in (a) of FIG. 1 , a third mask layer 203 is formed on the semiconductor substrate, and then, further, as shown in FIG. Figure 3 As shown in (b), a fourth mask layer 204 is formed on the surface of the third mask layer 203; thereafter, as shown in Figure 3 As shown in (c), a fifth mask layer 205 is formed on the surface of the fourth mask layer 204. The third mask layer 203, the fourth mask layer 204 or the fifth mask layer 205 can be polysilicon or any one or more of silicon nitride, silicon carbide, silicon oxynitride or silicon carbonitride.

[0039] S107 , grinding and thinning the fourth mask layer 204 and the fifth mask layer 205 until the second mask layer 202 is exposed.

[0040] For example, Figure 3The intermediate structure shown in (c) is ground and thinned to expose the second mask layer 202, as shown in FIG. Figure 3 As shown in (d) in .

[0041] S108 , removing the second mask layer 202 and a portion of the fourth mask layer 203 to form a third trench 03 and a U-shaped opening at the boundary.

[0042] Exemplarily, by wet etching or dry etching, the Figure 3 The entire second mask layer 202 shown in (d) and a portion of the fourth mask layer 203 are formed as shown in FIG. Figure 3 The third groove 03 shown in (e).

[0043] S109 , using the third mask layer 203 around the third trench 03 , the portion of the fourth mask layer 204 , and the fifth mask layer 205 as barrier layers, the semiconductor substrate 100 is etched to form a fourth trench 04 in the semiconductor substrate 100 .

[0044] For example, the third mask layer 203, the fourth mask layer 204, and the fifth mask layer 205 around the third trench 03 are used as barrier layers. Figure 3 The third trench 03 shown in (e) is patterned and etched, thereby etching a portion of the semiconductor substrate 100, thereby forming a fourth trench 04 in the semiconductor substrate 100, as shown in FIG. Figure 3 As shown in (f) in FIG. 1 , it can be seen from the figure that the width of the fourth trench 04 is relatively narrow, which helps to increase the surface area of the capacitor and improve the capacity of the storage capacitor.

[0045] S110 , removing the third mask layer, the fourth mask layer, and the fifth mask layer serving as barrier layers above the fourth trench.

[0046] For example, after removing the third mask layer, the fourth mask layer, and the fifth mask layer serving as the barrier layer above the fourth trench, the intermediate structure is as follows: Figure 3 As shown in (g).

[0047] S111 , forming an insulating layer on the sidewalls of the fourth trench, the bottom of the fourth trench, the U-shaped opening, and the semiconductor substrate.

[0048] Optionally, the insulating layer is made of at least one material having a dielectric constant greater than 3.9. Optionally, the insulating layer is made of at least one of zirconium dioxide, aluminum oxide, silicon nitride, hafnium dioxide, yttrium trioxide, silicon dioxide, tantalum pentoxide, lanthanum oxide, and titanium dioxide. The insulating layer is used to isolate the conductive layer from the semiconductor substrate to prevent electrical leakage.

[0049] S112, forming a first dielectric layer on the insulating layer.

[0050] It is worth noting that the following Figures 4A to 4H The intermediate structure cross-section diagram does not show the insulating layer and the first dielectric layer. For ease of understanding, Figure 4A A partial enlarged view of the U-shaped opening position is shown, in which the insulating layer 3011 and the first dielectric layer 3012 are shown.

[0051] S113 , forming a first conductive layer 301 on the first dielectric layer.

[0052] For example, Figure 4A As shown, a first conductive layer 301 is formed on the first dielectric layer by deposition.

[0053] S114 , forming a second dielectric layer 302 on the first conductive layer.

[0054] For example, Figure 4B As shown, a second dielectric layer 302 is formed on the first conductive layer 301 .

[0055] S115 , forming a second conductive layer 303 on the second dielectric layer 302 .

[0056] For example, Figure 4C As shown, a second conductive layer 303 is formed on the second dielectric layer 302 .

[0057] Optionally, the method further includes the following steps: forming a third dielectric layer 304 on the second conductive layer 303 and performing a planarization process; etching the third dielectric layer 304 to form a through hole to expose the first conductive layer 301 and the second conductive layer 303; filling the through hole with a third conductive layer 305; and etching the third conductive layer 305 to form a through hole to complete the top metal interconnection.

[0058] For example, in combination Figure 4D For example, a third dielectric layer 304 is formed on the second conductive layer 303, and then a planarization process is performed to form a Figure 4E The cross-sectional diagram of the intermediate structure is shown in FIG. Figure 4F As shown, the third dielectric layer 304 is etched once to expose the first conductive layer 301 and the second conductive layer 303. The third conductive layer 305 is filled in the through hole. Figure 4G Before packaging the semiconductor structure, the third conductive layer 307 is exposed by coating photoresist and patterning the etching to complete the top metal interconnection. Figure 4H shown.

[0059] It can be seen that the above manufacturing method not only completes the self-aligned boundary, but also Figure 2 The two second grooves 02 shown in (c) are expanded to Figure 4A The nine fourth trenches 04 in the embodiment can realize the production of multiple sidewall patterns, and can also save the number of photolithography times in the stage of electrical connection of the conductive layer by forming a conductive layer folding area at the boundary, thereby achieving the purpose of saving costs.

[0060] In this embodiment, the second conductive layer 303 serves as the first plate of the capacitor. The second conductive layer 303 is isolated and insulated from the first conductive layer 301 by the second dielectric layer 302. The first conductive layer 301 and the third conductive layer 305 are electrically connected and together form the second plate of the storage capacitor. The third dielectric layer 304 and the second dielectric layer 302 together form the dielectric between the plates of the storage capacitor.

[0061] In a possible embodiment, the material of the first conductive layer 301 , the second conductive layer 303 or the third conductive layer 305 may be copper, aluminum or tungsten.

[0062] It is worth noting that after forming the second conductive layer 303 and before forming the third conductive layer 305 , more dielectric layers and conductive layers may be deposited on the semiconductor structure, which will not be shown one by one in this embodiment.

[0063] In this embodiment, the above-described manufacturing method enables etching with high photolithographic precision under production conditions using conventional photoresists. The resulting trench has a narrower width, which helps increase the surface area of the capacitor and improve the capacity of the storage capacitor. While ensuring the performance of the storage capacitor, it reduces the requirements for photolithographic precision of the photolithography machine, thereby reducing process complexity and production costs. Furthermore, by forming a conductive layer fold at the U-shaped opening at the boundary, the number of photolithography steps during the conductive layer electrical connection stage is reduced, thereby achieving cost savings.

[0064] While the embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations of these embodiments are possible. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the claims. Furthermore, the invention described herein is susceptible to other embodiments and may be practiced or implemented in a variety of ways.

Claims

1. A method for manufacturing a storage capacitor, characterized in that: include: providing a semiconductor substrate; forming a first mask layer on the semiconductor substrate; etching the first mask layer to form a first trench; forming a second mask layer located on the bottom and sidewalls of the first trench and above the first mask layer, so as to form a second trench, wherein the width and depth of the second trench are both smaller than those of the first trench; removing the second mask layer above the first mask layer, the first mask layer, and the second mask layer located at the bottom of the second trench; sequentially forming a third mask layer on the remaining second mask layer, a fourth mask layer on the third mask layer, and a fifth mask layer on the fourth mask layer; grinding and thinning the fourth mask layer and the fifth mask layer until the second mask layer is exposed; removing the second mask layer and a portion of the fourth mask layer to form a third trench and a U-shaped opening at the boundary; Using the third mask layer around the third trench, the portion of the fourth mask layer, and the fifth mask layer as barrier layers, etching the semiconductor substrate to form a fourth trench in the semiconductor substrate; removing the third mask layer, the fourth mask layer, and the fifth mask layer serving as barrier layers above the fourth trench; forming an insulating layer on the sidewalls of the fourth trench, the bottom of the fourth trench, the U-shaped opening, and the semiconductor substrate; forming a first dielectric layer on the insulating layer; forming a first conductive layer on the first dielectric layer; forming a second dielectric layer on the first conductive layer; A second conductive layer is formed on the second dielectric layer.

2. The method according to claim 1, characterized in that The method further comprises: forming a third dielectric layer on the second conductive layer and performing a planarization process on the third dielectric layer; The third dielectric layer is etched to form a through hole to expose the first conductive layer and the second conductive layer.

3. The method according to claim 2, characterized in that Also includes: The through hole is filled with a third conductive layer, and the third conductive layer is etched to complete metal interconnection.

4. The method according to any one of claims 1 to 3, characterized in that Also includes: Materials of the first mask layer, the second mask layer, the third mask layer, the fourth mask layer and the fifth mask layer are all silicon nitride.

5. The method according to any one of claims 1 to 3, characterized in that Also includes: The material of the insulating layer is at least one material having a dielectric constant greater than 3.

9.

6. The method according to any one of claims 1 to 3, characterized in that The material of the insulating layer includes at least one of zirconium dioxide, aluminum oxide, silicon nitride, hafnium dioxide, yttrium trioxide, silicon dioxide, tantalum pentoxide, lanthanum oxide, and titanium dioxide.

7. The method according to any one of claims 1 to 3, characterized in that The first conductive layer, the second conductive layer and the third conductive layer are all made of copper, aluminum or tungsten.

8. A storage capacitor, characterized in that: include: semiconductor substrates; an insulating layer on the semiconductor substrate, a first dielectric layer on the insulating layer, a first conductive layer on the first dielectric layer, a second dielectric layer on the first conductive layer, and a second conductive layer on the second dielectric layer, wherein the first conductive layer and the second conductive layer at a boundary form a U-shaped folding region; a third dielectric layer located on the second conductive layer and a third conductive layer on the third dielectric layer, wherein the third conductive layer is electrically connected to the first conductive layer and the second conductive layer through a through hole; Wherein, the storage capacitor is manufactured according to the manufacturing method according to any one of the preceding claims 1-7.

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